CN100580936C - Display device and method of manufacturing the same - Google Patents
Display device and method of manufacturing the same Download PDFInfo
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- CN100580936C CN100580936C CN200710162205A CN200710162205A CN100580936C CN 100580936 C CN100580936 C CN 100580936C CN 200710162205 A CN200710162205 A CN 200710162205A CN 200710162205 A CN200710162205 A CN 200710162205A CN 100580936 C CN100580936 C CN 100580936C
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Abstract
A display device includes a substrate, a gate insulating film provided over the substrate and disposed between a semiconductor layer and a first conductive layer including a capacitor electrode and a gate electrode, an interlayer insulating film formed over the semiconductor layer, the first conductive layer and the gate insulating film, a second conductive layer having a signal line formed over the interlayer insulating film, a protective film formed over the interlayer insulating film and the second conductive layer and a pixel electrode layer formed over the protective film. The semiconductor layer and the second conductive layer are connected via the pixel electrode layer by the pixel electrode layer penetrating the protective film to reach the second conductive layer and also penetrating the protective film, the interlayer insulating film and the gate insulating film to reach the semiconductor layer.
Description
Technical field
The present invention relates to display unit and manufacture method thereof.
Background technology
Electroluminescence) exist to adopt thin-film transistor (Thin Filmed Transistor:TFT) as active matrix (active matrix) the type liquid crystal indicator of pixel switch (switching) element and organic EL (Electroluminescence: display device (device) such as.In these display devices, adopt the mobility of polycrystalline SiTFT of polysilicon (silicon) higher as raceway groove (channel) active layer of TFT.In addition,, can carry out height and become more meticulous as under the situation of pixel switch element, and, also can be applied to drive the peripheral circuit portion that the pixel switch element is used.
In the past, as the polysilicon film of the active layer of TFT and as the conducting film of gate electrode and capacitance electrode, by being positioned at its top and conducting (for example, with reference to patent documentation 1) as the source drain metal (source drainmetal) of holding wire.In this case, generally before forming holding wire, form contact hole, form holding wire afterwards at polysilicon film and gate electrode and capacitance electrode.
Generally adopt and on holding wire, also dispose the dielectric film structure of (being called passivation (passivation) film again).And,, also need form through hole (with reference to Figure 12) in the dielectric film on holding wire for conducting to holding wire.
In addition, in the tft array portion that comprises TFT of existing display unit, be the structure that under holding wire, has contact hole (contact hole).Thus, be formed for being connected the portion of terminal of formed circuit and viewing area on the substrate that is formed with TFT simultaneously, on portion of terminal, in interlayer dielectric and diaphragm, form contact hole respectively with tft array portion.And, need by the wiring of signal wire connecting end and pixel electrode layer (with reference to Figure 13 (a) and (b)).
In existing manufacture method, for realizing as the gate electrode of the holding wire of second wiring and conduct first wiring that is positioned at its lower floor and electric capacity (capacitor) electrode or as the polysilicon film conducting of semiconductor layer, need before forming holding wire, form contact hole in the part that becomes under the holding wire.And, usually after forming holding wire, on holding wire, dispose dielectric film (being also referred to as passivating film), so, need to form through hole (through hole), realize conducting with the superiors.Therefore, mask (mask) number in man-hour is many and have a problem of cost (cost) aspect.In addition, for the part that holding wire and gate electrode and capacitance electrode utilize contact hole to carry out conducting, conductive layer overlaps.Therefore, there is the big such problem of concavo-convex change that forms the surface as the pixel electrode of topmost.In this case, display quality worsens.Like this, in existing liquid crystal indicator, there are problems such as productivity ratio is low, display quality deterioration.
In addition, the portion of terminal of TFT substrate forms simultaneously with the viewing area that is formed with the substrate of TFT.Therefore, connect up with the terminal on the layer, at first, need connect pixel electrode layer and holding wire, connect holding wire and terminal wiring by contact hole by contact hole for pixel electrode layer being connected be formed on gate electrode.That is, can not form contact hole together, the number in man-hour of TFT substrate is many.In addition, need to be provided with the contact hole in the dielectric film that is formed between holding wire and the terminal wiring and be formed on holding wire and pixel electrode between dielectric film in the Substrate Area of through hole.That is the problem that, has the area increase of portion of terminal.
Summary of the invention
The objective of the invention is in order to solve described problem, a kind of productivity ratio height, good display unit and the manufacture method thereof of display quality are provided.
The display unit of first execution mode of the present invention has: substrate; Gate insulating film is arranged on the described substrate, be configured in semiconductor layer and comprise capacitance electrode and first conductive layer of gate electrode between; Interlayer dielectric is formed on the upper strata of described semiconductor layer, described first conductive layer and described gate insulating film; Second conductive layer is formed on the described interlayer dielectric and comprises holding wire; Diaphragm is formed on described interlayer dielectric and described second conductive layer; Pixel electrode layer; be formed on the described diaphragm; described pixel electrode layer connects described diaphragm and arrives described second conductive layer; and connect described diaphragm, described interlayer dielectric and described gate insulating film and arrive described semiconductor layer; thus, described semiconductor layer is connected by described pixel electrode layer with second conductive layer.
According to the present invention, can provide a kind of productivity ratio height, good display unit and the manufacture method thereof of display quality.
Description of drawings
Fig. 1 is the plane graph of expression TFT substrat structure.
Fig. 2 (a) is the profile of structure of TFT portion, transformation component and protective circuit portion of the TFT substrate of expression embodiment 1, (b) is the plane graph of structure of protective circuit of the TFT substrate of expression embodiment 1.
Fig. 3 is the profile of the TFT substrat structure of expression embodiment 2.
Fig. 4 is the profile of the TFT substrat structure of expression embodiment 3.
Fig. 5 is the profile of the TFT substrat structure of expression embodiment 4.
Fig. 6 is the profile of the TFT substrat structure of expression embodiment 5.
Fig. 7 is the profile of the TFT substrat structure of expression embodiment 6.
Fig. 8 is the profile of the TFT substrat structure of expression embodiment 7.
Fig. 9 (a) is the profile of the TFT substrat structure of expression embodiment 8, (b) is the plane graph of the TFT substrat structure of expression embodiment 8.
Figure 10 is the profile of the TFT substrat structure of expression embodiment 9.
Figure 11 is the profile of the TFT substrat structure of expression embodiment 10.
Figure 12 is the profile of the existing TFT substrat structure of expression.
Figure 13 (a) is the profile of the existing TFT substrat structure of expression, (b) is the plane graph of the existing TFT substrat structure of expression.
Embodiment
Below, explanation can be used embodiments of the present invention.Following explanation is embodiments of the present invention, the invention is not restricted to following execution mode.
At first, use Fig. 1 that the active matrix type display of using TFT substrate of the present invention is described.Fig. 1 is the front elevation of the structure of employed TFT substrate in the expression display unit.Though what display unit of the present invention illustrated as an example is liquid crystal indicator,, this only is exemplary, also can use flat displays such as organic EL display (flat-panel monitor (flatpanel display)) etc.
Liquid crystal indicator of the present invention has TFT substrate 110.TFT substrate 110 for example is the tft array substrate.In TFT substrate 110, the frame area 112 of viewing area 111 and encirclement viewing area 111 is set.In this viewing area 111, form a plurality of grid wirings (scan signal line) 182 and a plurality of source wiring (display signal line) 153 that signal are offered TFT120 described later.A plurality of grid wirings 182 are provided with abreast.Similarly, a plurality of source wiring 153 also are provided with abreast.Grid wiring 182 and source wiring 153 form mutually across.Grid wiring 182 and source wiring 153 quadratures.And, become pixel 117 by the grid wiring 182 and source wiring 153 area surrounded of adjacency.Therefore, in TFT substrate 110, pixel 117 is configured to rectangular.
And, in the frame area 112 of TFT substrate 110, scan signal drive circuit 115 and shows signal drive circuit 116 are set.111 extensions are set to frame area 112 to grid wiring 182 from the viewing area.In the frame area 112 as the end of TFT substrate 110, grid wiring 182 is connected to scan signal drive circuit 115 by guiding wiring 121.In guiding wiring 121, the transformation component 122 that changes wiring layer (layer) is set.111 extensions are set to frame area 112 to source wiring 153 from the viewing area similarly.In the frame area 112 as TFT substrate 110 ends, source wiring 153 is connected to shows signal drive circuit 116 by guiding wiring 121.In guiding wiring 121, the transformation component 122 that changes wiring layer is set.Near scan signal drive circuit 115, connect outside wiring 118.In addition, near shows signal drive circuit 116, connect outside wiring 119.Outside wiring 118,119 for example is the wiring substrate of FPC (FlexiblePrinted Circuit) etc.And, in the frame area 112 of TFT substrate 110, have the insulation breakdown that is used to prevent between grid wiring 182 and the source wiring 153 or different layers 121 of guiding wirings insulation breakdown and protect the protective circuit 123 of each wiring.The details aftermentioned.
To offer scan signal drive circuit 115 and shows signal drive circuit 116 from the various signals of outside by outside wiring 118,119.Scan signal drive circuit 115 offers grid wiring 182 based on the control signal from the outside with signal (sweep signal).Utilize this signal, select grid wiring 182 successively.Shows signal drive circuit 116 offers source wiring 153 based on control signal or the video data from the outside with shows signal.Thus, the display voltage corresponding to video data can be offered each pixel 117.
In pixel 117, form at least one TFT 120.TFT 120 is configured near the crosspoint of source wiring 153 and grid wiring 182.For example, this TFT 120 provides display voltage to pixel electrode.That is, according to signal, as the TFT120 conducting of switch element from grid wiring 182.Thus, display voltage is applied to the pixel electrode that is connected with the drain electrode of TFT from source wiring 153.And, between pixel electrode and opposite electrode, produce the electric field corresponding with display voltage.And, form alignment films (not shown) on the surface of TFT substrate 110.
And, in TFT substrate 110, subtend configuration opposed substrate.Opposed substrate for example is colour filter (color filter) substrate, is configured in the observation side.In opposed substrate, form colour filter, black matrix (black matrix) (BM), opposite electrode and alignment films.And, also exist opposite electrode to be configured in the situation of TFT substrate 110 sides.And, clamping liquid crystal layer between TFT substrate 110 and opposed substrate.That is, between TFT substrate 110 and opposed substrate, inject liquid crystal.And, Polarizer and polarizer etc. are set at the face in the outside of TFT substrate 110 and opposed substrate.And, at the opposition side of the observation side of display panels, configuration back light unit (backlight unit) etc.
Utilize the electric field driven liquid crystal between pixel electrode and the opposite electrode.That is, the direction of orientation of the liquid crystal between substrate changes.Thus, the polarized state of light by liquid crystal layer changes.That is, for the light that becomes rectilinearly polarized light by Polarizer, polarization state changes because of liquid crystal layer.Specifically, from the light of back light unit because the Polarizer of array substrate side becomes rectilinearly polarized light.And this rectilinearly polarized light is by liquid crystal layer, and thus, polarization state changes.
Therefore, according to polarization state, the light quantity of the Polarizer by the opposed substrate side changes.That is, seeing through the light quantity change that passing through the light observed the light of lateral deviation tabula rasa that sees through of display panels from back light unit.The direction of orientation of liquid crystal changes according to the display voltage that is applied.Therefore, display voltage is controlled, thus, the light quantity by observing the lateral deviation tabula rasa is changed.That is, change display voltage, thus, can show desirable image according to each pixel.
Next, adopt Fig. 2 (a) and (b) explanation be arranged on structure and the manufacturing step of the TFT120 on the TFT substrate 110.TFT portion, transformation component and protective circuit portion in the display unit of embodiment 1 shown in Fig. 2 (a).The right zone of Fig. 2 (a) illustrates the TFT portion that is formed on the viewing area, and left zone illustrates transformation component and the protective circuit portion that is formed on outside the viewing area.And, the plane graph of the protective circuit in the frame area on the substrate of the display unit that is formed on embodiment 1 shown in Fig. 2 (b).And, be the profile shown in Fig. 2 (a) at the profile of the dotted line part shown in Fig. 2 (b).At first, mainly adopt Fig. 2 (a) that the display unit of present embodiment is described.For example, in the present embodiment, type TFT 120 describes as top grid (top gate).On glass (glass) substrate 1, be set to the basilar memebrane of dielectric film.At first, utilize the silicon nitride film 2 of plasma CVD method formation as the 50nm of basilar memebrane.This silicon nitride film 2 is to pollute and form from the Na (sodium) of glass substrate 1 in order to prevent.Then, utilize plasma CVD method to form the silicon oxide film 3 of 200nm.Silicon oxide film 3 carried out afterwards make amorphous silicon (amorphous silicon) crystallization the time play complementary effect.Silicon nitride film 2 and silicon oxide film 3 are formed on roughly whole of substrate 1.And, also can form basilar memebrane by the material outside silicon nitride film 2 or the silicon oxide film 3.And, can form basilar memebrane in individual layer ground.Like this, can be by forming the stability of characteristics that basilar memebrane makes TFT.
Next, utilize plasma (plasma) CVD method to form the amorphous silicon of 50nm.Heat-treat, the hydrogen concentration in the amorphous silicon is reduced.And, utilize laser annealing (laser anneal) method to make recrystallized amorphous siliconization, become polysilicon film 4.The laser annealing method has quasi-molecule laser annealing (excimer laser) method, YAG laser annealing method etc., still, is not limited to these.Specifically, utilize laser radiation, make the amorphous silicon fusion, afterwards, make its cooling and curing, thus, become polysilicon.And, utilize phototype to form resist figure (resist pattern).Carry out dry etching (dry etching) by the resist figure, will be used to form transistorized polysilicon film 4 and be patterned into desirable shape.Then, remove resist.Polysilicon film 4 is formed on the silicon oxide film 3 with island.Thus, in the zone that forms TFT, form polysilicon film 4 as semiconductor layer.
Next, utilize plasma CVD method on polysilicon film 4, to form gate insulating film 5.As gate insulating film 5, for example, can used thickness be the silicon oxide film of 80nm.Thus, polysilicon film 4 is covered by gate insulating film 5.Next, utilize photomechanical process to form the resist figure, and, impurity introduced on the regioselectivity ground of the capacitor lower electrode that becomes semiconductor layer.Thus, can improve the conductivity of the semiconductor layer under the capacitance electrode 6 that formed afterwards, reduce the voltage-dependent of electric capacity.
Next, utilize sputtering method to be formed for forming the metallic film of first conductive layer, this first conductive layer comprises gate electrode 15, capacitance electrode 6 and the first guiding wiring 16.As this metallic film, for example, can use Al, Cr, Mo, Ti, W etc. or in them, add alloy of other materials etc. micro-ly.After being formed for forming the metallic film of gate electrode 15, capacitance electrode 6 and the first guiding wiring 16, utilize photomechanical process to form the resist figure.And, metallic film is patterned into desirable shape by etching liquid.Thus, form gate electrode 15, capacitance electrode 6 and be arranged on the guiding of first the viewing area outside and connect up 16.Gate electrode 15 is formed on the channel region of polysilicon film 4.Capacitance electrode 6 is formed directly on the gate insulating film 5.And, remove the resist on gate electrode 15 and the capacitance electrode 6.This gate electrode 15 for example is a grid wiring 182 etc.
Next, gate electrode 15 and capacitance electrode 6 as mask, are introduced impurity in polysilicon film 4.Thus, in being configured in the source drain zone 7 of channel region both sides, introduce impurity.At this, can adopt ion (ion) injection method or ion doping (ion doping) method etc.And,, also can make LDD (Lightly Doped Drain) structure in order to improve reliability.Thus, form TFT.
Next, utilize plasma CVD method on gate insulating film 5, to form silicon oxide film as interlayer dielectric 8.Thus, cover capacitance electrode 6 and polysilicon film 4 by interlayer dielectric 8.Interlayer dielectric 8 is to make TEOS and O
2The silicon oxide film of reacted 500nm.And about the thickness of interlayer dielectric 8,500nm is sub for example, is not limited to this.And interlayer dielectric 8 is not limited to silicon oxide film, also can be silicon nitride film or organic membrane etc.
Next, in order to activate P (phosphorus) or the B (boron) that is incorporated in the polysilicon film 4, heat-treat.Heat treatment was carried out 1 hour in blanket of nitrogen, under 400 ℃.
Next, utilize sputtering method to be formed for forming the metallic film of second conductive layer, this second conductive layer comprises the holding wire 9 and the second guiding wiring 17 that is made of the source drain metal.Holding wire 9 is metal material or alloy materials such as Al, Cr, Mo, Ti, W.At this, make the laminated construction of Mo alloy/Al alloy/Mo alloy, thickness is respectively 100nm/300nm/100nm.Next, in photomechanical process, form the resist figure, holding wire 9 is patterned into desirable shape by the dry etching method.
Thus, on interlayer dielectric 8, form a plurality of holding wires 9 and be arranged on the guiding of second the viewing area outside and connect up 17.This holding wire 9 for example is a source wiring 153 etc.For the holding wire 9 and the second guiding wiring 17, be not formed on the contact hole 11 that is connected to the first guiding wiring 16 and with contact hole 11 that the source drain region 7 of polysilicon film 4 is connected in.The formation step aftermentioned of this contact hole 11.Before the contact hole of interlayer dielectric 8 forms step, form this holding wire 9 and the second guiding wiring 17.That is, form interlayer dielectric 8 after, before the composition of the contact hole 11 that carries out forming, form the holding wire 9 and the second guiding wiring 17 at interlayer dielectric 8 or gate insulating film 5.
Next, utilize plasma CVD method to form the silicon nitride film that becomes diaphragm 10 of 300nm.Next, recover, heat-treat in order to make destruction (damage).Heat treatment was carried out under 250 ℃ 1 hour in atmosphere.Diaphragm 10 is not limited to silicon nitride film, also can be dielectric films such as silicon oxide film or organic membrane.
Form after the diaphragm 10, form the contact hole 11 that connects diaphragm 10 and the arriving signal line 9 and the second guiding wiring 17.In addition, in this step, form to connect diaphragm 10 and interlayer dielectric 8 and arrive the contact hole 11 of the first guiding wiring 16.And, in this step, form the contact hole 11 that connects diaphragm 10, interlayer dielectric 8 and gate insulating film 5 and arrive the source drain zone of polysilicon film 4.Specifically, utilize photoetching (photolithography) method on diaphragm 10, to form the resist figure.And, in order diaphragm 10, interlayer dielectric 8 and gate insulating film 5 are carried out dry etching.Thus, form contact hole 11.Can form the contact hole 11 that connects diaphragm 10, interlayer dielectric 8 and gate insulating film 5 with a photomask.
After forming contact hole 11, form pixel electrode layer 12.And, pixel electrode layer 12 is carried out composition by photoetching process etc.Can utilize nesa coating formation such as ITO film as electrode layer 12.Perhaps, also can utilize metal such as Cr, Mo, Al, Ta, Ti or be that the alloy of main component forms pixel electrode layer 12 with these metals.In this pixel electrode layer 12, comprise the pixel electrode that applies the driving voltage (display voltage) that is used to drive liquid crystal.For example, under the situation of liquid crystal indicator, pixel electrode is connected with the drain electrode of TFT.This pixel electrode layer 12 is embedded in the contact hole 11.By being embedded in the pixel electrode layer 12 in the contact hole 11, in the TFT portion in the viewing area, physically and electrically connect the source region and the holding wire 9 of polysilicon film 4.In addition, grid wiring and the source wiring that is formed in the viewing area on the TFT substrate 110 is connected by the guiding wiring with drive circuit.This guiding wiring comprises the first guiding wiring, the 16 and second guiding wiring 17, and the transformation component 122 that changes wiring layer is set.And, in transformation component 122,, physically and electrically connect the first guiding wiring, the 16 and second guiding wiring 17 by being embedded in the pixel electrode layer 12 in the contact hole 11.Between polysilicon film 4 and holding wire 9, directly do not connect mutually, but only be electrically connected indirectly by pixel electrode layer 12.Similarly, between the first guiding wiring, the 16 and second guiding wiring 17, directly do not connect mutually, but only be electrically connected indirectly by pixel electrode layer 12.
That is, in the transformation component 122 outside the viewing area, the second guiding wiring 17 is connected by pixel electrode layer 12 with the first guiding wiring 16 that forms in grid layer.In addition, the TFT portion in the viewing area, holding wire 9 is connected by pixel electrode layer 12 with polysilicon film 4.Like this, holding wire 9 is connected with the polysilicon film 4 of TFT by pixel electrode layer 12.Therefore, compared with prior art, can reduce the mask step that in interlayer dielectric 8, forms contact hole, and the lip-deep flatness of pixel improves.
That is, owing under the holding wire 9 and the second guiding wiring 17, do not form contact hole, so, after forming interlayer dielectric 8, can save and before forming holding wire 9, interlayer dielectric 8 be carried out the photomechanical process step of composition.Therefore, can subdue employed mask quantity in the photomechanical process step.Thus, can improve productivity.
In this case, the signal from holding wire 9 offers polysilicon film 4 by pixel electrode layer 12.In addition, can signal directly be offered pixel electrode from polysilicon film 4.Like this, all signal line layers are not directly connected to polysilicon film 4 or grid layer.
In addition, under holding wire 9, do not remove interlayer dielectric 8.Therefore, under signal line layer, must form interlayer dielectric 8.In other words, all signal line layers are configured on the zone that is formed with interlayer dielectric 8.That is, be formed with the zone of signal line layer, configuration interlayer dielectric 8 under signal line layer at all.And, can make following structure: under the pixel electrode in being included in pixel electrode layer 12, do not have configuration signal line layer and connected contact hole.Therefore, can improve the flatness of the interlayer dielectric 8 under the pixel electrode.Thus, can improve display quality.
In addition, adopt formed protective circuit 123 on the frame area 112 on the TFT substrate 110 that Fig. 2 (b) illustrates in display unit.Protective circuit 123 has first semiconductor element and second semiconductor element.These semiconductor elements are rectifier cells of resistance value nonlinear change separately.For example, first semiconductor element is n transistor npn npn (n-Tr), and other second semiconductor element is the p transistor npn npn (p-Tr) of different conductivity types.Its conductivity type also can be opposite relation, and specifically, the ionic species during by implanted dopant in source drain zone 7 is distinguished.And even these first semiconductor elements and second semiconductor element are suitably replaced, effect also is identical.
The gate electrode of first semiconductor element and drain electrode are connected to first short-circuited conducting sleeve (not shown), and the source electrode is connected to source wiring 153 or grid wiring 182.That is, first semiconductor element is connected to the source electrode of this TFT 120 by the grid with TFT 120 or two terminal components of drain electrode constitute.In addition, the gate electrode of second semiconductor element and drain electrode are connected to second short-circuited conducting sleeve (not shown), and the source electrode is connected to source wiring 153 or grid wiring 182.That is, second semiconductor element is connected to the source electrode of this TFT 120 by the grid with TFT 120 or two terminal components of drain electrode constitute.And for example, first semiconductor element and second semiconductor element are connected in parallel.First semiconductor element is connected to first short-circuited conducting sleeve, and second semiconductor element is connected to second short-circuited conducting sleeve.
And according to the situation that produces potential difference between these short-circuited conducting sleeves (short ring), first semiconductor element and the some of second semiconductor element are opened, thus moment ground become same potential.At this, so-called open be in first semiconductor element and second semiconductor element any one for conducting, electric charge flows by the semiconductor element that becomes conducting, thus, potential difference is eliminated.In Fig. 2 (b), holding wire 9 and pixel electrode layer 12 are shown are the situation of same potential.For example, the current potential of holding wire 9 than the high situation of the current potential of pixel electrode layer 12 under, pTr is conducting, moves to pixel electrode layer 12 as the hole of charge carrier from holding wire 9.On the other hand, the current potential of holding wire 9 than the low situation of the current potential of pixel electrode layer 12 under, nTr is conducting, moves to holding wire 9 as the electronics of charge carrier from pixel electrode layer 12.And, for example,, then connect holding wire 9 and gate electrode 15 by the semiconductor element that becomes conducting if pixel electrode layer 12 is connected to gate electrode 15, can erasure signal line 9 and the potential difference of gate electrode 15.As mentioned above, the mutually different semiconductor element of combination conductivity type thus, by first short-circuited conducting sleeve or second short-circuited conducting sleeve, can bleed off the static of accumulating in source wiring 153 and grid wiring 182 etc.And protective circuit 123 is formed in the frame area 112 of TFT substrate 110, prevents the insulation breakdown between first conductive layer and second conductive layer.Thus, protection source wiring 153 and grid wiring 182.
The formation method of protective circuit 123 is identical with the TFT portion and the transformation component of described display unit.But, shown in Fig. 2 (a), form after the diaphragm 10, form perforation diaphragm 10 and interlayer dielectric 8 and the contact hole 11 of arrival gate electrode 15.In addition, in this step, form the contact hole 11 that connects diaphragm 10, interlayer dielectric 8 and gate insulating film 5 and arrive polysilicon film 4.Afterwards, on diaphragm 10, form pixel electrode layer 12.Pixel electrode layer 12 is embedded in the contact hole 11.And, be formed in the protective circuit 123 on the frame area 112 of TFT substrate 110, physically and electrically connect polysilicon film 4 and gate electrode 15 by the pixel electrode layer 12 that is embedded in the contact hole 11.
The TFT substrate that is formed as described above is fitted with the opposed substrate with opposite electrode, injects liquid crystal betwixt.To be configured in rear side as the surface light source apparatus of back light unit, make liquid crystal indicator.In addition, in the present embodiment, be not limited to liquid crystal indicator, also go in display unit such as all OLED display or the various electronic equipment.
TFT substrate with reference to the figure 3 explanation embodiment of the invention 2.Fig. 3 is the profile that the TFT substrate of present embodiment is shown.In the present embodiment, with the difference of embodiment 1 only be the structure of pixel electrode layer 12, so, omit detailed explanation.
Fig. 3 is the structure that is formed pixel electrode by the conducting film more than two layers.Pixel electrode layer 12 has metals such as nesa coatings such as ITO film and Cr, Mo, Al, Ta, Ti or is the metal film of main component with these metals.That is, in the present embodiment, pixel electrode layer 12 is the laminated construction with the conducting film 12a of lower floor and upper strata conductive layer 12b.At this, upper strata conductive layer 12b is that the alloy of main component forms by metal or with the metal, and the conductive layer 12a of lower floor is formed by nesa coating.Thus, with embodiment 1 in the same manner, can boost productivity, and, can improve display quality.And, make laminated construction, thus, can reduce the resistance of the pixel electrode layer 12 between the first guiding wiring, the 16 and second guiding wiring 17 and polysilicon film 4 and the holding wire 9.Thus, can improve display quality.Pixel electrode layer 12 is made laminated construction, thus, for example can form semitransparent liquid crystal display.That is, in pixel, in the portion of seeing through, only form pixel electrode, in reflecting part, form pixel electrode by metal or alloy by nesa coating.
In addition, illustrated that in embodiment 2 upper strata conductive layer 12b is a metal or be that alloy, the conducting film 12a of lower floor of main component is the structure of nesa coating with the metal, still, also can be and its opposite configuration.That is, also can upper strata conductive layer 12b be that nesa coating, the conducting film 12a of lower floor are metals or are the alloy of main component with the metal.And this metal can be the contour melting point metal of Cr, Mo, Ta, Ti.Adopt such structure, thus, play and remove the further effect that described productivity ratio improves or resistance reduces.Below, will describe this effect in detail.
Usually, make ITO and the so direct contacting structure of semiconductive thin film of polysilicon film in pixel electrode layer, used, come down to as the ITO of n N-type semiconductor N and contacting of semiconductive thin film.Like this, become the non-ohm contact, exist contact resistance also to be shown as the problem of high resistance.That thus, can use described structure for example has only the so little zone of the influence on device performance of pixel contact site.At this, as mentioned above, between ITO and semiconductive thin film, insert metals such as Cr, Mo, Ta, Ti, obtain the such structure of ITO/ metal/semiconductor film as nesa coating.And, obtain between ITO and semiconductive thin film for ohmic properties contact and contact resistance be low-resistance effect.That is, obtain reducing the such effect of contact resistance between pixel electrode layer 12 and the polysilicon film 4.
TFT substrate with reference to the figure 4 explanation embodiment of the invention 3.Fig. 4 is the profile that the TFT substrate of present embodiment is shown.In the present embodiment, be that pixel electrode forms barrier metal 20 when adopting nesa coating such as TIO in contact hole 11 with the difference of embodiment 1.Therefore, omit the explanation of the content identical with embodiment 1.In addition, identical about barrier metal 20 with the metal of embodiment 2, in embodiment 3, also have the contact resistance that makes ITO and semiconductive thin film and reduce such effect, also omit its explanation.At this, barrier metal 20 for example is embedded in the contact hole 11.Therefore, the source drain zone 7 that connects pixel electrode layer 12 and polysilicon film 4 by barrier metal 20.In addition, connect the pixel electrode layer 12 and the first guiding wiring 16 by barrier metal 20.And, connect pixel electrode layer 12, holding wire 9 and the second guiding wiring 17 by barrier metal 20.In this case, form barrier metal 20, thereby can reduce the contact resistance of ITO and its lower layer signal line layer, grid layer or polysilicon film 4.Therefore, can further improve display quality.
And, can make up present embodiment and embodiment 2.In addition, after forming diaphragm 10, after contact hole 11 is carried out opening, form barrier metal 20, in addition, barrier metal 20 can adopt Mo, Ti, Cr, W etc.In addition, in Fig. 4, the barrier metal 20 that is connected to holding wire 9 separates with the barrier metal 20 that is connected to source drain zone 7, but, after forming barrier metal 20, carry out composition, thus, also can connect holding wire 9 and source drain region 7 by barrier metal 20 to connect both.Thus, obtain connecting the effect that resistance reduces and characteristic improves.Between the first guiding wiring, the 16 and second guiding wiring 17 also is identical.
TFT substrate with reference to the figure 5 explanation embodiment of the invention 4.Fig. 5 is the profile that the TFT substrate of present embodiment is shown.In the present embodiment, the difference with embodiment 1 is to form silicide 21 before forming pixel electrode at least in the contact site of pixel electrode layer 12 and polysilicon film 4.Therefore, omit the explanation of the content identical with embodiment 1.Silicide 21 is formed on the surface in source drain zone 7 of polysilicon film 4.At this, pixel electrode layer 12 is made of nesa coatings such as TIO.Perhaps, lower floor's conducting film of pixel electrode layer 12 is formed by nesa coating.In this case, the source drain zone 7 that connects pixel electrode layer 12 and polysilicon film 4 by silicide 21.Therefore, can reduce to connect resistance, and display quality is improved.
TFT substrate with reference to the figure 6 explanation embodiment of the invention 5.Fig. 6 is the profile that the TFT substrate of present embodiment is shown.In the present embodiment, the difference with embodiment 1 is that compare with silicon oxide film 3 with the silicon nitride film 2 as basilar memebrane, the holding wire 9 and the second guiding wiring 17 are formed on lower floor.Therefore, omit the explanation of the content identical with embodiment 1.
At this, form the holding wire 9 and the second guiding wiring 17 for 2 times at silicon nitride film.At this, on the figure of the holding wire 9 and the second guiding wiring 17, in silicon nitride film 2, silicon oxide film 3, gate insulating film 5, interlayer dielectric 8 and diaphragm 10, form contact hole 11.By this contact hole 11, the holding wire 9 and the second guiding wiring 17 are connected with pixel electrode layer 12.After forming diaphragm 10, form perforation silicon nitride film 2 and silicon oxide film 3 and the contact hole 11 of the arriving signal line 9 and the second guiding wiring 17.Therefore, form the contact hole 11 that connects silicon nitride film 2, silicon oxide film 3, gate insulating film 5, interlayer dielectric 8 and diaphragm 10 with a photomask.Thus, can obtain the effect identical with described embodiment.And, in the present embodiment, on glass substrate 1, form the holding wire 9 and the second guiding wiring 17, silicon nitride film 2, silicon oxide film 3 successively.Because it is identical with embodiment 1 to form the step of silicon nitride film 2, so, its explanation omitted.And in the present embodiment, the holding wire 9 and the second guiding wiring 17 are formed on silicon nitride film 2 times.Therefore, between the formation step of the formation step of interlayer dielectric 8 and diaphragm 10, the step that forms the holding wire 9 and the second guiding wiring 17 need be set.In addition, basilar memebrane can adopt the material outside silicon nitride film 2 and the silicon oxide film 3, also can be single layer structure.
TFT substrate with reference to the figure 7 explanation embodiment of the invention 6.In Fig. 7, on the TFT substrate, form bottom gate type TFT.That is, the lower floor at polysilicon film 4 forms gate insulating film 5.And, form gate electrode 15, capacitance electrode 6 and the first guiding wiring 16 in the lower floor of gate insulating film 5.And gate electrode 15 is configured in polysilicon film 4 times.In this case, on glass substrate 1, form gate electrode 15, gate insulating film 5 and polysilicon film 4 successively.And the formation step after forming polysilicon film 4 is identical with embodiment 1, so omit its explanation.
TFT substrate with reference to the figure 8 explanation embodiment of the invention 7.In embodiment 7, has the structure that does not form the holding wire 9 and the second guiding wiring 17.That is, after forming interlayer dielectric 8 and before forming diaphragm 10, perhaps before forming silicon nitride film 2, do not form the holding wire 9 and the second guiding wiring 17.Therefore, between interlayer dielectric 8 and diaphragm 10 and at silicon nitride film, do not dispose the holding wire 9 and the second guiding wiring 17 for 2 times.In this step, owing to can omit the formation step of the holding wire 9 and the second guiding wiring 17, so, can further improve productivity ratio.
TFT substrate with reference to figure 9 (a) and (b) explanation embodiments of the invention 8.In embodiment 8, on the frame area 112 that is formed on substrate shown in Figure 1 110 and the structure of the portion of terminal that is connected with the pad of scan signal drive circuit 115 or shows signal drive circuit 116 describe.At this, Fig. 9 (a) is the profile of portion of terminal that the TFT substrate of embodiment 8 is shown.Fig. 9 (b) is the plane graph of portion of terminal that the TFT substrate of embodiment 8 is shown.At this, the structure of a portion of terminal in a plurality of portion of terminal is shown.In addition, in Fig. 9 (a) and the embodiment 8 that (b) illustrates, omit the explanation of the structural element identical with embodiment 1.
Shown in Fig. 9 (a), on glass substrate 1, form silicon nitride film 2 and silicon oxide film 3 as basilar memebrane with plasma CVD method.Next, in TFT 120, become the polysilicon film 4 of semiconductor layer, still,, utilize etching to remove this polysilicon film 4 in the portion of terminal of embodiment 8.And, on silicon oxide film 3, use plasma CVD method to form gate insulating film 5.Next, utilize sputtering method, the formation such as alloy of using for example Al, Cr, Mo, Ti or W etc. or add other materials micro-ly in them become the metallic film of terminal wiring 22.On this metallic film, use phototype to form the resist figure.And, by etching liquid metallic film is patterned into desirable shape, remove the resist on the metallic film.Thus, form terminal wiring 22.At this, in TFT 120, form gate electrode 15, capacitance electrode 6 and the first guiding wiring 16 with layer ground with terminal wiring 22.In addition, gate electrode 15 and capacitance electrode 6 as mask, are introduced impurity in the polysilicon film 4 on being formed on silicon oxide film 3.
Utilize plasma CVD method in terminal wiring 22, to form silicon oxide film as interlayer dielectric 8.Thus, cover terminal wiring 22 by interlayer dielectric 8.This interlayer dielectric 8 is to make TEOS and O
2The thickness that the reaction back forms is the silicon oxide film of 500nm.And,, be not limited to this though the thickness of interlayer dielectric 8 is 500nm.In addition, interlayer dielectric 8 is not limited to silicon oxide film, also can be silicon nitride film or organic membrane etc.
At this, in TFT 120, activate in order to make the P (phosphorus) or the B (boron) that are incorporated in the polysilicon film 4, heat-treat.Next, the holding wire 9 that utilizes sputtering method to form in TFT 120 to be made of the source drain metal and forms second guide and connect up 17 in transformation component etc. still, in the present embodiment as the structure of portion of terminal, does not form holding wire 9.
Next, on interlayer dielectric 8, utilize plasma CVD method to form the silicon nitride film of 300nm as diaphragm 10.This diaphragm 10 is configured in the top of terminal wiring 22.In addition, diaphragm 10 is not limited to silicon nitride film, also can be dielectric films such as silicon oxide film or organic membrane.At this,, heat-treat for the destruction of the polysilicon film 4 that recovers TFT 120.
After forming diaphragm 10, form the contact hole 11 that connects diaphragm 10 and interlayer dielectric 8 arrival terminal wirings 22.At this moment, in transformation component etc., form and connect the contact hole 11 that diaphragm 10 and interlayer dielectric 8 arrive the first guiding wiring 16.And, in TFT 120, form and connect the contact hole 11 that diaphragm 10, interlayer dielectric 8 and gate insulating film 5 arrive the source drain zone 7 of polysilicon film 4.Specifically, utilize photoetching process on diaphragm 10, to form the resist figure.And, successively diaphragm 10, interlayer dielectric 8 and gate insulating film 5 are carried out dry etching.Thus, form contact hole 11.Can form the contact hole 11 that connects diaphragm 10, interlayer dielectric 8 and gate insulating film 5 with a photomask.At this, in a portion of terminal, form four contact holes 11.
After forming contact hole 11, form pixel electrode layer 12.And, pixel electrode layer 12 is carried out composition by photoetching process etc.Pixel electrode layer 12 can be formed by nesa coatings such as ITO films.Perhaps, can be that the alloy of main component forms pixel electrode layer 12 also by metals such as Cr, Mo, Al, Ta, Ti or with these metals.This pixel electrode layer 12 can be formed by nesa coatings such as ITO films.Perhaps, can be that the alloy of main component forms pixel electrode layer 12 also by metals such as Cr, Mo, Al, Ta, Ti or with these metals.This pixel electrode layer 12 is embedded in the contact hole 11.Thus, physically and electrically splicing ear wiring 22 and pixel electrode layer 12.At this moment, in TFT 120, formation applies the pixel electrode of the driving voltage (display voltage) that is used to drive liquid crystal etc.
In embodiment 8, terminal wiring 22 can be connected by forming of contact hole with pixel electrode layer 12.That is, in the past, contact hole 11 had the formation step for each interlayer dielectric 8, diaphragm 10, and each contact hole is formed on the diverse location on the substrate surface.On the other hand, in the present embodiment, be integrally formed in the contact hole 11 that forms in each interlayer dielectric 8 and the diaphragm 10.Thus, can dwindle contact hole 11 is configured in zone on the substrate surface.Therefore, can dwindle the area of frame area 112.
The TFT substrate of the embodiment of the invention 9 is described with reference to Figure 10.In embodiment 10, the structure that is formed on the portion of terminal on the substrate identical with the TFT 120 shown in the embodiment 2 is described.Figure 10 is the profile of portion of terminal that the TFT substrate of present embodiment is shown.In addition, in the present embodiment, with the difference of the portion of terminal shown in the embodiment 8 only be the structure of pixel electrode layer 12, so omit detailed explanation.
Figure 10 is the structure that is formed pixel electrode by the conducting film more than two layers.Pixel electrode layer 12 has nesa coatings such as ITO film and is the metal film of main component by metals such as Cr, Mo, Al, Ta, Ti or with these metals.That is, in the present embodiment, pixel electrode layer 12 is the laminated construction with the conducting film 12a of lower floor and upper strata conductive layer 12b.At this, upper strata conductive layer 12b is that the alloy of main component forms by metal or with the metal, and the conductive layer 12a of lower floor is formed by nesa coating.Thus, can boost productivity, and, display quality can be improved.Described structure is applicable to transmission type liquid crystal display device and reflection-type liquid-crystal display device.
The TFT substrate of inventive embodiment 10 is described with reference to Figure 11.In embodiment 10, the structure that is formed on the portion of terminal on the substrate identical with the TFT 120 shown in the embodiment 3 is described.Figure 11 is the profile of portion of terminal that the TFT substrate of present embodiment is shown.In addition, in the present embodiment, be, when pixel electrode is nesa coating such as ITO, in contact hole 11, form barrier metal 20 with the difference of embodiment 8.Therefore, omit the explanation of the content identical with embodiment 8.
At this, barrier metal 20 for example is embedded in the contact hole 11.Therefore, connect pixel electrode layer 12 and terminal wiring 22 by barrier metal 20.In this case, for example, form barrier metal 20, thus, in TFT 120, can reduce the contact resistance of ITO and its lower layer signal line layer, grid layer or polysilicon film 4.In addition, in transformation component, can reduce the contact resistance of ITO and its lower layer signal line layer, grid layer or polysilicon film 4.Therefore, display quality is further improved.
And, present embodiment and embodiment 9 can be made up.In addition, after forming diaphragm 10, after contact hole 11 is carried out opening, form barrier metal 20, and barrier metal 20 can use Mo, Ti, Cr, W etc.
The TFT substrate of the embodiment of the invention 11 is described.Embodiment 11 explanation is formed on the structure of the portion of terminal on the substrate identical with the TFT 120 shown in the embodiment 4.In the present embodiment, be, in TFT 120, before forming pixel electrode, on the contact site at least of pixel electrode layer 12 and polysilicon film 4, form silicide 21 with the difference of embodiment 8.Therefore, having only portion of terminal is the structure identical with embodiment 8, so omit detailed explanation.That is, in embodiment 11, has the portion of terminal shown in TFT 120 shown in the embodiment 4 and the embodiment 8.
The TFT substrate of the embodiment of the invention 12 is described.Embodiment 12 explanation is formed on the structure of the portion of terminal at the end identical with the TFT 120 shown in the embodiment 5.In the present embodiment, the difference with embodiment 8 is that compare with silicon nitride film 2 and silicon oxide film 3 as basilar memebrane, the holding wire 9 and the second guiding wiring 17 are formed on lower floor.Therefore, be identical owing to have only portion of terminal with the structure of embodiment 8, so, omit detailed explanation.That is, in embodiment 12, has the portion of terminal shown in TFT 120 shown in the embodiment 3 and the embodiment 8.
The TFT substrate that is made by the manufacture method of described embodiment can form contact hole by a step, can reduce mask number in man-hour at least one time.In this case, under holding wire, do not form contact hole, thereby the flatness of the pixel electrode surface of topmost improves.And, in described embodiment 1～12, forming capacitance electrode 6 by the conductive layer identical with gate electrode 15, still, also can in the layer identical, form with holding wire 9.And, can suitably make up embodiment 1～12.
The productivity ratio height of the tft array substrate shown in the embodiments of the invention 1～12 can perform well in display unit.More particularly, can be used for having the display unit of active array type array substrate, this active array type array substrate signal routing and scan line in the viewing area of display unit, intersect and near its infall the configuration TFT constitute.
For example, go in the following liquid crystal indicator: by encapsulant applying array substrate and colour filter, liquid crystal material is enclosed by portion within it.In addition, also go for not only in the viewing area but also the TFT of the drive circuit that the periphery in the viewing area is provided with, in this case, can form simultaneously with the TFT in the viewing area.In addition, the present invention is not limited only to described execution mode, can carry out various variations in the scope that does not break away from purport of the present invention.
Claims (20)
1. a display unit is characterized in that,
Have: substrate; Semiconductor layer is arranged on the described substrate; Gate insulating film is formed on the described semiconductor layer; First conductive layer is formed on the described gate insulating film, and comprises capacitance electrode and gate electrode; Interlayer dielectric is formed on the upper strata of described semiconductor layer, described first conductive layer and described gate insulating film; Second conductive layer is formed on the described interlayer dielectric, comprises holding wire; Diaphragm is formed on described interlayer dielectric and described second conductive layer; Pixel electrode layer is formed on the described diaphragm,
Described pixel electrode layer connects described diaphragm and arrives described second conductive layer; and connect described diaphragm, described interlayer dielectric and described gate insulating film and arrive described semiconductor layer; thus, described semiconductor layer is connected by described pixel electrode layer with second conductive layer.
2. a display unit is characterized in that,
Have: substrate; First conductive layer is arranged on the described substrate, and comprises capacitance electrode and gate electrode; Gate insulating film is formed on described first conductive layer; Semiconductor layer is formed on the described gate insulating film; Interlayer dielectric is formed on the upper strata of described semiconductor layer, described first conductive layer and described gate insulating film; Second conductive layer is formed on the described interlayer dielectric, comprises holding wire; Diaphragm is formed on described interlayer dielectric and described second conductive layer; Pixel electrode layer is formed on the described diaphragm,
Described pixel electrode layer connects described diaphragm and arrives described second conductive layer, and connects described diaphragm and described interlayer dielectric arrives described semiconductor layer, and thus, described semiconductor layer is connected by described pixel electrode layer with second conductive layer.
3. according to the display unit of claim 1 or 2, it is characterized in that,
Described pixel electrode layer connects described diaphragm and arrives described second conductive layer; and; connect described diaphragm and described interlayer dielectric and arrive described first conductive layer, thus, described first conductive layer is connected by described pixel electrode layer with described second conductive layer.
4. according to the display unit of claim 1 or 2, it is characterized in that,
Described pixel electrode layer connects described diaphragm and described interlayer dielectric arrives described first conductive layer; and; connect described diaphragm and described interlayer dielectric arrives described semiconductor layer, thus, described first conductive layer is connected by described pixel electrode layer with described semiconductor layer.
5. according to the display unit of claim 3, it is characterized in that,
Have: be formed on grid wiring and source wiring in the viewing area on the described substrate; Drive circuit to described grid wiring or described source wiring supply signal; The first guiding wiring or the second guiding wiring are formed in the frame area outside the viewing area on the described substrate, connect described drive circuit, described grid wiring and described source wiring,
Described first conductive layer comprises the described first guiding wiring,
Described second conductive layer comprises the described second guiding wiring,
Described pixel electrode layer connects described diaphragm and arrives the described second guiding wiring; and; connect described diaphragm and described interlayer dielectric and arrive the described first guiding wiring, thus, the described first guiding wiring is connected by described pixel electrode layer with the described second guiding wiring.
6. according to the display unit of claim 4, it is characterized in that,
Have: be formed on grid wiring and source wiring in the viewing area on the described substrate; Drive circuit to described grid wiring or described source wiring supply signal; The first guiding wiring or the second guiding wiring are formed in the frame area outside the viewing area on the described substrate, connect described drive circuit, described grid wiring and described source wiring; Protective circuit; be formed in the frame area outside the described viewing area on the described substrate; each wiring of protection can be because of destroyed destruction of insulation between the insulation breakdown between described grid wiring and described source wiring or described first guiding wiring and the described second guiding wiring
In described protective circuit; described pixel electrode layer connects described diaphragm and described interlayer dielectric arrives described gate electrode; and; connect described diaphragm and described interlayer dielectric arrives described semiconductor layer; thus, described gate electrode is connected by described pixel electrode layer with described semiconductor layer.
7. according to the display unit of claim 1 or 2, it is characterized in that,
At the Zone Full that is provided with described second conductive layer, under described second conductive layer, do not have contact hole.
8. according to the display unit of claim 1 or 2, it is characterized in that,
Have the contact hole of the described semiconductor layer of arrival that in an etch step, forms and the contact hole of described second conductive layer of arrival.
9. according to the display unit of claim 1 or 2, it is characterized in that,
Have the described semiconductor layer of arrival that in an etch step, forms contact hole, arrive the contact hole of described first conductive layer and arrive the contact hole of described second conductive layer.
10. according to the display unit of claim 1 or 2, it is characterized in that,
Described pixel electrode layer comprises nesa coating.
11. the display unit according to claim 10 is characterized in that,
Described pixel electrode layer is connected by barrier metal with described semiconductor layer.
12. the display unit according to claim 1 or 2 is characterized in that,
Described pixel electrode layer comprises metal or alloy.
13. display unit according to claim 1 and 2 is characterized in that,
Described pixel electrode layer is the laminated construction with upper strata conducting film and lower floor's conducting film.
14. the display unit according to claim 1 or 2 is characterized in that,
Have the terminal wiring, be arranged on outside the described viewing area on the described substrate, be formed under the described interlayer dielectric,
Described pixel electrode layer connects described diaphragm and described interlayer dielectric arrives described terminal wiring, thus, connects described terminal wiring and described pixel electrode layer.
15. the manufacture method of a display unit has following steps:
On substrate, form semiconductor layer, gate insulating film successively, comprise first conductive layer of capacitance electrode and gate electrode;
Upper strata at described semiconductor layer, described first conductive layer and described gate insulating film forms interlayer dielectric;
On described interlayer dielectric, form second conductive layer that comprises holding wire;
Upper strata at described interlayer dielectric and described second conductive layer forms diaphragm;
Contact hole forms step, after forming described diaphragm, form connect described diaphragm arrive described second conductive layer contact hole, connect described diaphragm and described interlayer dielectric arrive described first conductive layer contact hole, connect the contact hole that described diaphragm, described interlayer dielectric and described gate insulating film arrive described semiconductor layer;
After forming described contact hole, on described diaphragm, form pixel electrode layer.
16. the manufacture method of a display unit has following steps:
On substrate, form first conductive layer, gate insulating film, the semiconductor layer that comprises capacitance electrode and gate electrode successively;
Upper strata at described semiconductor layer, described first conductive layer and described gate insulating film forms interlayer dielectric;
On described interlayer dielectric, form second conductive layer that comprises holding wire;
Upper strata at described interlayer dielectric and described second conductive layer forms diaphragm;
Contact hole forms step, after forming described diaphragm, form connect described diaphragm arrive described second conductive layer contact hole, connect described diaphragm and described interlayer dielectric arrive described first conductive layer contact hole, connect the contact hole that described diaphragm and described interlayer dielectric arrive described semiconductor layer;
After forming described contact hole, on described diaphragm, form pixel electrode layer.
17. the manufacture method according to the display unit of claim 15 or 16 is characterized in that,
In an etch step, form contact hole that arrives described semiconductor layer and the contact hole that arrives described second conductive layer.
18. the manufacture method according to the display unit of claim 15 or 16 is characterized in that,
In etch step, form the contact hole that arrives described semiconductor layer, arrive the contact hole of described first conductive layer and arrive the contact hole of described second conductive layer.
19. the manufacture method according to the display unit of claim 15 or 16 is characterized in that,
On described substrate, form in the step of described semiconductor layer, described first conductive layer and described gate insulating film, form described terminal wiring outside the described viewing area on described substrate,
Form in the step at described contact hole, form the contact hole that arrives described terminal wiring.
20. the manufacture method according to the display unit of claim 19 is characterized in that,
In an etch step, form the contact hole that arrives described second conductive layer and arrive the described contact hole that described terminal connects up.
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| JP2010156960A (en) * | 2008-12-03 | 2010-07-15 | Semiconductor Energy Lab Co Ltd | Liquid crystal display device |
| KR20110134685A (en) * | 2010-06-09 | 2011-12-15 | 삼성모바일디스플레이주식회사 | Display device and method for manufacturing the same |
| JP2012118199A (en) * | 2010-11-30 | 2012-06-21 | Panasonic Liquid Crystal Display Co Ltd | Liquid crystal panel, liquid crystal display device, and manufacturing method thereof |
| JP5998459B2 (en) | 2011-11-15 | 2016-09-28 | ローム株式会社 | Semiconductor device, manufacturing method thereof, and electronic component |
| WO2013105537A1 (en) * | 2012-01-11 | 2013-07-18 | シャープ株式会社 | Semiconductor device, display device, and semiconductor device manufacturing method |
| US10359871B2 (en) * | 2014-09-26 | 2019-07-23 | Lg Display Co., Ltd. | Display panel and method of manufacturing the same |
| CN105552024B (en) | 2016-03-14 | 2018-07-06 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof, display device |
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