CN100459438C - Reed-solomon decoder key equation and error value solving-optimizing circuit - Google Patents

Abstract

To solve problems of the large size of circuit board and its high cost in the design of Leed Solomon decoder circuit using the traditional technique, this invention provides an optimum solving circuit of the key equation and error value of Leed Solomon decoder. The combination of selector, multiplier, adder, 3-way selector, giving original value and 3-state function circuit, flip-flop, latch, static memory, select and reciprocating circuit and select/flip-flop circuit realizes the solving error position polynomial (x), error value polynomial (x) and final error value. It utilizes reusing the single circuit to realize the function, which needs usually two circuits. Therefore, the circuit size, complicacy and the cost are as reduced as possible.

Description

The key equation of reed-solomon decoder and error value solving-optimizing circuit

Technical field

The present invention relates to the reed-solomon decoder of the error correction device of transmission data in the digital communication, be specifically related to the key equation and the error value solving-optimizing circuit of reed-solomon decoder.

Background technology

Have a lot of coded systems in field of channel coding, the way of restraint difference according between information code element and the verification code element can be divided into block code and convolution code.Reed-solomon (Reed-Solomon) sign indicating number belongs to a kind of of block code; the characteristics of this coding method are; information is divided into the data segment of separation, is used for transmission thereby form self-contained code word at each data segment according to the redundant protection information of encryption algorithm adding simultaneously.

The unit of reed-solomon code (following abbreviation RS sign indicating number) is made up of one section byte with many bits, even mistake has all taken place in each that may single byte in the transmission, error correction capability for sign indicating number, these mistake only be can be regarded as a byte, and such structure makes it be particularly suited for handling sudden error code.

For the RS sign indicating number, select different parameters that different error correcting capabilities can be provided, also directly have influence on hard-wired complexity simultaneously.Itself can be described to (n represents the length of code word for n, form k), promptly contained byte number, k then is the number of protected information byte, has simultaneously:

n≤2 ^m-1 (1)

Wherein m is the bit number that every byte comprises, and when equation was false in (1), formed code word was called the shortening form of RS sign indicating number.According to the above, obviously redundant digit is the n-k byte, suppose every section in to t byte of multipotency correction, then have:

T=(n-k)/2 is when n-k is even number

T=(n-k-1)/2 is when n-k is odd number

We can represent a RS code word with following multinomial:

T(x)＝M(x)×x ^n-k+r(x)

＝M _k-1x ^k-1+K+M ₀x ^n-k+r _n-k-1x ^n-k-1+K+r ₀

Coefficient M _K-1... M ₁, M ₀Be k protected information byte, coefficient r _N-k-1... r ₁, r ₀Then be n-k redundancy bytes.

Reed-solomon decoder will be realized is exactly the decoding of data transmitting terminal chnnel coding, and the burst error that noise jamming in the channel is brought is corrected.The function of reed-solomon decoder realizes by four steps usually:

1) supposes that the wrong multinomial that produces in the transmission course is $E\left(x\right)=Y_1{x}^{{\mathrm{<figure-callout\; id="1"\; label="e"\; filenames="C20061009683700151.png,C20061009683700161.png"\; state="\{\{state\}\}">e</figure-callout>}}_1}+Y_2{x}^{{\mathrm{<figure-callout\; id="2"\; label="e"\; filenames="C20061009683700141.png"\; state="\{\{state\}\}">e</figure-callout>}}_2}+K{Y}_v{x}^{e_v},$ Wherein, e ₁, K e _vAs the index of x, determined the position of error code in the code word, and Y ₁, K Y _vRepresent error code values concrete on those positions.

According to the RS code word multinomial T (x) that data sending terminal sends, the reception data are R (x)=T (x)+E (x),

Can calculate associated polynomial by R (x) $S\left(x\right)=S_{b+2t-1}{x}^{2t-1}+K+S_{b+1}x+S_b.$

2) according to associated polynomial $S\left(x\right)=S_{b+2t-1}{x}^{2t-1}+K+S_{b+1}x+S_b,$ Carry out key equation Ω (x)=[S (x) Λ (x)] modx ^2tFind the solution, obtain error location polynomial Λ (x) and improper value multinomial Ω (x).

3) carry out polynomial evaluation according to Λ (x) and Ω (x), obtain concrete errors present (root of Λ (x)).

4) carry out polynomial evaluation according to Λ (x) and Ω (x), obtain improper value $Y_j=X_j^{1-b}\frac{\mathrm{\&Omega;}\left(X_j^{-1}\right)}{{\mathrm{\&Lambda;}}^{\&prime;}\left(X_j^{-1}\right)}.$

5) carry out error correction according to errors present and improper value.

Above-mentioned concrete theory can be referring to " Reed-Solomon Error Correction ", BBCResearch﹠amp; Development White Paper WHP 031, C.K.P.Clarke.The circuit design of prior art is that each realizes that with a circuit this will increase circuit area greatly with 2,4 two steps, improves circuit cost.

Summary of the invention

The objective of the invention is to address the above problem, a kind of key equation and error value solving-optimizing circuit of reed-solomon decoder is provided, it can dwindle circuit area as much as possible, reduces the complexity of circuit, reduces circuit cost.

Technical scheme of the present invention is as follows: a kind of key equation of reed-solomon decoder and error value solving-optimizing circuit, comprise selector 1, multiplier 2, selector 3, adder 4, selector 5, multiplier 6, No. three selectors 7, initialize and ternary functional circuit 8, selector 9, trigger 10, selector 11, latch 12, static memory 13, select and get reciprocal circuit 14, selection and circuits for triggering 15 and static memory 16, error value solving coefficient signal X _j ^1-bConnect an input of selector 1, the output of selector 1 connects an input of multiplier 2, simultaneously improper value polynomial solving signal Ω (X _j ^-1) connect an input of selector 3, the output of selector 3 connects another input of multiplier 2, the output of multiplier 2 connects an input of adder 4 and an input of selector 5 respectively, the output of adder 4 connects an input of selector 9, the output of selector 5 connects an input of multiplier 6, the output of multiplier 6 connects an input of initialize and ternary functional circuit 8 respectively, the input of selector 11 and the first input end of selection and circuits for triggering 15, the output of initialize and ternary functional circuit 8 connects another input of selector 9 respectively, another input of selector 3 and select and get an input of reciprocal circuit 14, the output of selector 9 connects the input of trigger 10, the output of trigger 10 connects another input of selector 11 and the input of static memory 13 respectively, the output of static memory 13 connects another input of adder 4 and another input of selector 5 respectively, error location polynomial differentiate signal Λ ' (X _j ^-1) selecting selects and get another input of reciprocal circuit 14, select to connect the input of latch 12 and second input of No. three selectors 7 respectively with the output of getting reciprocal circuit 14, the output of latch 12 connects the first input end of No. three selectors 7 and second input of selection and circuits for triggering 15 respectively, associated polynomial signal S (x) connects the 3rd input of No. three selectors 7 and another input of initialize and ternary functional circuit 8, its output connects another input of multiplier 6, select to connect the input of static memory 16 with the output of circuits for triggering 15, the output of static memory 16 connects another input of selector 1 and the 3rd input of selection and circuits for triggering 15 respectively, and selector 11 selects output error position multinomial signal or improper value multinomial signal or improper value signal to give external circuit.

The design philosophy of circuit of the present invention is as follows: key equation solving circuit adopts traditional B erlekamp algorithm, and algorithm flow is referring to Fig. 5.According to flow chart as can be seen, calculating ${\mathrm{\&Delta;}}_r=S_r+\underset{j=1}{\overset{L}{\mathrm{\&Sigma;}}}{\mathrm{\&Lambda;}}_j{S}_{r-j}$ (Λ _jCoefficient for Λ (x) the j time) and $B\left(x\right)\&LeftArrow;{\mathrm{\&Delta;}}_r^{-1}\mathrm{\&Lambda;}\left(x\right)$ The time, all will use the multiplication with Λ (x), and these two multiplication can not take place simultaneously, we can realize this two multiplication with a multiplier by time-multiplexed mode.Calculate T (x)=Λ (x)-Δ in addition _rXB (x) also will use a multiplier, $B\left(x\right){\&LeftArrow;\mathrm{\&Delta;}}_r^{-1}\mathrm{\&Lambda;}\left(x\right)$ Calculating also want one to get reciprocator, we get reciprocator with two multipliers and one and have promptly realized traditional B erlekamp algorithm.

Improper value solving circuit again, improper value passes through formula $Y_j=X_j^{1-b}\frac{\mathrm{\&Omega;}\left(X_j^{-1}\right)}{{\mathrm{\&Lambda;}}^{\&prime;}\left(X_j^{-1}\right)}$ Calculated, wherein X _j ^-1Being errors present, also is the root of Λ (x).Ω (X _j ^-1) and Λ ' (X _j ^-1) calculate by external circuit.Obviously calculate $Y_j=X_j^{1-b}\frac{\mathrm{\&Omega;}\left(X_j^{-1}\right)}{{\mathrm{\&Lambda;}}^{\&prime;}\left(X_j^{-1}\right)}$ Need two multiplication and one to get reciprocal circuit and realize, because the error value solving circuit is just in time at the further work of key equation solving circuit, so calculating $Y_j=X_j^{1-b}\frac{\mathrm{\&Omega;}\left(X_j^{-1}\right)}{{\mathrm{\&Lambda;}}^{\&prime;}\left(X_j^{-1}\right)}$ Two multipliers and a structure of getting in the equal reusable key equation solving circuit of reciprocator.

So first and last, key equation solving circuit and error value solving circuit be by multiplexing, reduced three multipliers and one and got reciprocator, reduced circuit area greatly.

Integrated circuit of the present invention comprises: selector 1, multiplier 2, selector 3, adder 4, selector 5, multiplier 6, No. three selectors 7, initialize and ternary functional circuit 8, selector 9, trigger 10, selector 11, latch 12, static memory 13 (hereinafter to be referred as SRAM), select and get reciprocal circuit 14, select and circuits for triggering 15 and static memory 16.Circuit has four external signal inputs and is respectively: X _j ^1-b, Ω (X _j ^-1), Λ ' (X _j ^-1), S (x).Error value solving coefficient signal X _j ^1-bAn input of input selector 1, selector 1 is exported to multiplier 2; While improper value polynomial solving signal Ω (X _j ^-1) being input to an input of selector 3, selector 3 is also exported to multiplier 2; Multiplier 2 is done to output signal to adder 4 after the multiplying, and selector 5; Another input signal of adder 4 is from the output of SRAM13, and this output is simultaneously also as another input of selector 5; Adder 4 is done to export to selector 9 after the add operation, and selector 5 outputs to multiplier 6, and the output of No. three selectors 7 is then as another input of multiplier 6; Multiplier 6 is done to output to initialize and ternary functional circuit 8 after the multiplying, selector 11 and selection and circuits for triggering 15; Initialize and ternary functional circuit 8 are exported to selector 9, selector 3 and select and get reciprocal circuit 14, select and get reciprocal circuit 14 another be input as Λ ' (X _j ^-1), its output is respectively as the input of No. three selectors 7 and latch 12, second of No. three selectors 7 is input as external signal S (x), and S (x) also is input to initialize and ternary functional circuit 8, and 12 of latchs are exported to and selected and circuits for triggering 15 and No. three selectors 7; Select to export to SRAM16 with circuits for triggering 15, SRAM16 exports to and selects and circuits for triggering 15 and selector 1; After selector 9 was exported to trigger 10, trigger 10 was exported to SRAM13 and selector 11 again, and the selector 11 final output error position multinomial signals or improper value multinomial signal or improper value signal selected are given external circuit.

Circuit of the present invention is realized the multiplexing of circuit by selector, after key equation solving circuit work, by selector circuit is switched to new annexation, thereby realizes the function of error value solving.When realizing key equation solving circuit, No. three selectors 7 gatings are from the input and the external signal S (x) of latch 12, selector 1 gating is from the input of SRAM16, selector 3 is with selection and get the input of reciprocal circuit 14 equal gatings from initialize and ternary functional circuit 8, selector 5 gatings are from the input of SRAM13, selector 11 gatings are from the input of trigger 10, and entire circuit realizes traditional Berlekamp algorithm by this annexation.Above-mentioned selector switches selects after other input then circuit to realize the error value solving circuit by new annexation.The analysis of physical circuit will be narrated hereinafter.

Compared with prior art, the advantage of the multiplex circuit of the present invention's proposition is:

In the key equation solving circuit part, we have saved a multiplier by the multiplexing general realization circuit than traditional B erlekamp algorithm of multiplier, and two multipliers of error value solving circuit and one get reciprocator all multiplexing structure in the key equation solving circuit, entire circuit has just been saved three multipliers and one and has been got reciprocator like this, has reduced the complexity of hardware greatly.According to statistics, can save about 35% circuit scale behind the circuit optimization, and at the code word of RS (204,188), circuit speed still can reach 28.8Mbps, enough satisfies the requirement of reed-solomon decoder.

Description of drawings

Fig. 1 is the circuit block diagram of the multiplex circuit of the present invention's proposition.

Fig. 2 is the physical circuit figure of the multiplex circuit of the present invention's proposition.

Fig. 3 is the algorithm flow chart of traditional B erlekamp algorithm.

Embodiment

As shown in Figure 1, a kind of key equation of reed-solomon decoder and error value solving-optimizing circuit, comprise selector 1, multiplier 2, selector 3, adder 4, selector 5, multiplier 6, No. three selectors 7, initialize and ternary functional circuit 8, selector 9, trigger 10, selector 11, latch 12, static memory 13, select and get reciprocal circuit 14, selection and circuits for triggering 15 and static memory 16, error value solving coefficient signal X _j ^1-bConnect an input of selector 1, the output of selector 1 connects an input of multiplier 2, simultaneously improper value polynomial solving signal Ω (X _j ^-1) connect an input of selector 3, the output of selector 3 connects another input of multiplier 2, the output of multiplier 2 connects an input of adder 4 and an input of selector 5 respectively, the output of adder 4 connects an input of selector 9, the output of selector 5 connects an input of multiplier 6, the output of multiplier 6 connects an input of initialize and ternary functional circuit 8 respectively, the input of selector 11 and the first input end of selection and circuits for triggering 15, the output of initialize and ternary functional circuit 8 connects another input of selector 9 respectively, another input of selector 3 and select and get an input of reciprocal circuit 14, the output of selector 9 connects the input of trigger 10, the output of trigger 10 connects another input of selector 11 and the input of static memory 13 respectively, the output of static memory 13 connects another input of adder 4 and another input of selector 5 respectively, error location polynomial differentiate signal Λ ' (X _j ^-1) selecting selects and get another input of reciprocal circuit 14, select to connect the input of latch 12 and second input of No. three selectors 7 respectively with the output of getting reciprocal circuit 14, the output of latch 12 connects the first input end of No. three selectors 7 and second input of selection and circuits for triggering 15 respectively, associated polynomial signal S (x) connects the 3rd input of No. three selectors 7 and another input of initialize and ternary functional circuit 8, its output connects another input of multiplier 6, select to connect the input of static memory 16 with the output of circuits for triggering 15, the output of static memory 16 connects another input of selector 1 and the 3rd input of selection and circuits for triggering 15 respectively, and selector 11 selects output error position multinomial signal or improper value multinomial signal or improper value signal to give external circuit.

As shown in Figure 2, above-mentioned selection with get reciprocal circuit 14 by selector 141 with get reciprocator 142 and form above-mentioned error location polynomial differentiate signal Λ ' (X _j ^-1) connecing an input of selector 141, the output of selector 141 accesses the input of reciprocator 142, and another input of selector 141 is got the above-mentioned latch 12 of exporting to of reciprocator 142 from the output of initialize and ternary functional circuit 8.

Above-mentioned selection and circuits for triggering 15 are made up of selector 151, trigger 152, selector 153 and trigger 154, an input of selector 151 is from the output of multiplier 6, another input is from the output of static memory 16, its output connects the input of trigger 152, the output of trigger 152 connects an input of selector 153, another input of selector 153 is from the output of latch 12, the output of selector 153 connects the output of trigger 154, and the output of trigger 154 connects static memory 16.

Circuit of the present invention is realized the multiplexing of circuit by selector, and the connection by solid arrow among Fig. 2 has indicated key equation solving circuit, and the connection of arrow has by a dotted line indicated the error value solving circuit.After key equation solving circuit work, by selector circuit is switched to the annexation of dotted line, thereby realize the function of error value solving.

(embodiment)

Following circuit all describes with the form of codewords of RS (204,188).

1, key equation solving circuit:

This part adopts the Berlekamp traditional algorithm, but less change is arranged.Be mainly the setting of initial value, the result that we can directly calculate the traditional B erlekamp algorithm iteration first time is: A (x)=1+S ₀X; B (x)=1/S ₀(S _iAssociated polynomial S (x) coefficient that calculates for previous circuit), so we can directly be set at iteration result for the first time to initial value, and consider 0 item 1 for Λ (x), can not participate in computing and final iteration result that we are required in the iteration afterwards for the coefficient of Λ (x), need not item 0 time from 1 item to 8 time item.Then our iterative initial value that can provide is Λ (x)=S ₀B (x)=1/S ₀, only need 15 iteration can obtain the result afterwards.When we find to calculate middle multinomial T (x) in iterative process in addition, following formula: T (x)=Λ (x)-Δ is arranged _rXB (x) is because we are made as S with Λ (x) initial value ₀First power has fallen, so formula should be made following corrigendum: T (x)=Λ (x)-Δ _rB (x), Δ to B (x) assignment the time simultaneously _r ^-1Λ (x) will change Δ into _r ^-1X Λ (x), lucky so just saved hardware realize in to the shifting function of B (x).Simultaneously by directly importing S by S (x) _iValue has guaranteed Δ as the initial value that adds up _rThat calculates is correct.Analysis conventional Berlekamp algorithm, we also can find following rule: two branches of traditional B erlekamp algorithm alternately occur, and promptly the assignment of B (x) alternately is Δ _r ^-1X Λ (x) or xB (x) (i.e. displacement).Can obtain end value Λ (x) after 15 iteration.

0～7 address correspondence of SRAM13 is deposited Λ (x) in the physical circuit (as Fig. 2), and B (x) is deposited in 0～7 address of SRAM16.Initialize and ternary functional circuit 8 show with empty collimation mark among Fig. 2, and this circuit has three functional statuses: the one, and accumulation state realizes accumulation function, at this moment ABCD=1100; The 2nd, initialize (comprises Λ (x), B (x) initial value and calculating Δ _rThe initial value that adds up) state, this moment ABCD=0001; The 3rd, latch mode, ABCD=0010 at this moment.

Corresponding diagram 2 now is described below circuit:

1. external signal S (x) at first exports S ₀, initialize and ternary functional circuit 8 are in the initialize state, and since ABC=000, a of selector 81, the b end is 1, and its output also is 1, and D also is 1, S ₀Export to selector 9 and selector 141 respectively through two NAND gate and trigger 82.S ₀Select output by selector 9 and give Λ (x) initialize after trigger 10 is input to SRAM13 at last; And S ₀Selected after the output then to become 1/S0 and pass through latch 12 again through getting reciprocator 142 by selector 141, selector 153 and trigger 154 are input to SRAM16 and give B (x) initialize.

2. S (x) export successively Sr, Sr-1 ..., Sr-L.Initialize and ternary functional circuit 8 are in the initialize state during output Sr, because ABCD=0001, trigger 82 outputs at first are Sr; S (x) export successively Sr-1 ..., initialize and ternary functional circuit 8 are in accumulation state during Sr-L because ABC=110, a input of selector 81 is the output of multiplier 6, the b input then be multiplier 6 export anti-phase; And D=0 makes selector 81 export the anti-phase selecting side of being exported to selector 81 again for by trigger 82 trigger 82.So just realized the function that the output to multiplier 6 constantly adds up.S (x) export successively Sr-1 ..., during Sr-L, the c of No. three selectors 7 end gating, S (x) outputs to multiplier 6; SRAM13 export successively Λ 1 ..., Λ L is input to multiplier 6 by selector 5 gatings.Through after multiplier multiplies each other, add up through initialize and ternary functional circuit 8 again and finally obtain Δ _r

3. calculate Δ _rAfter, initialize and ternary functional circuit 8 enter latch mode, this moment ABCD=0010, then a input of selector 81 is 1, the b input is 0, output is then sent into trigger 82 through NAND gate; If trigger 82 is output as 0, then select a end 1 input of selector 81, be 0 after NAND gate, then trigger 82 is output as 0 constant; If trigger 82 is output as 1, then select b end 0 input of selector 81, be 1 after NAND gate, then trigger 82 is output as 1 constantly, realizes latch function thus.Trigger 82 output Δs _rAfter being latched by initialize and ternary functional circuit 8, by selector 3 gatings input multiplier 2, selector 1 selects SRAM16 output B (x) to multiplier 2, Δ _rObtain T (x) through output Λ (x) addition of adder 4 and SRAM13 with SRAM16 output B (x) again after multiplier 2 multiplies each other, adder 4 output T (x) output to trigger 10 through selector 9, export to SRAM13 at last again, finish the renewal to Λ (x).

4. the output Δ of trigger 82 _rAfter latching by initialize and ternary functional circuit 8, also select to enter simultaneously and get reciprocator 142 and obtain Δ by selector 141 _r ^-1, being strobed into multiplier 6 through latch 12 by No. three selectors 7 again, SRAM13 output Λ (x) also is strobed into multiplier 6, Δ by selector 5 _r ^-1Multiply each other with Λ (x) and to obtain Δ _r ^-1Λ (x), Δ _r ^-1Λ (x) outputs to selector 151, and the output B (x) of SRAM16 also is input to selector 151 simultaneously, is input Δs by selector 151 alternate selection _r ^-1Λ (x) is B (x) still, and the output of selector 151 is input to selector 153 through trigger 152 again, is strobed into trigger 154 through it, then outputs to SRAM16 again, but the Input Address of SRAM16 has biased moving, original Δ at this moment _r ^-1Λ (x) and B (x) will be stored as Δ if be strobed into SRAM16 _r ^-1X Λ (x) and xB (x).

5. after 1. step, 2.～4. step is with loop iteration 15 times, and end product error location polynomial Λ (x) will calculate in the 3. step of the 15th iteration, promptly exports to selector 11 by trigger 10 and by selector 11 final gatings outputs.

This circuit is also wanted the value of mistake in computation simultaneously multinomial (Ω (x)=[S (x) Λ (x)] mod x ²ⁱ), with SRAM13, the SRAM16 expansion is twice, and 8～15 address correspondences of SRAM1 are deposited Ω (x), multinomial A (x) in the middle of deposit 8～15 addresses of SRAM2.Iterative process and above-mentioned 4 steps are identical, are the initial value design difference of first step, Ω (x)=S ₀, A (x)=0.Circuit of the present invention only needs to use earlier SRAM13, after the value in 0～7 address of SRAM16 is calculated Λ (x), uses value in 8～15 addresses again and calculates Ω (x) and get final product, finally exports and is followed successively by Λ (x) and Ω (x) through trigger 10.

2, error value solving circuit

This circuit promptly will calculate $Y_j=X_j^{1-b}\frac{\mathrm{\&Omega;}\left(X_j^{-1}\right)}{{\mathrm{\&Lambda;}}^{\&prime;}\left(X_j^{-1}\right)},$ X _j ^1-b, Ω (X _j ^-1) and Λ ' (X _j ^-1) be external input signal.Shown in Fig. 2 dotted line connects, Λ ' (X _j ^-1) be input to through selector 141 gatings and get reciprocator 142, get back reciprocal and be strobed into multiplier 6, X by No. three selectors _j ^1-bOutput to multiplier 2 via selector 1, Ω (X _j ^-1) also output to multiplier 2 and and X through selector 3 _j ^1-bMultiply each other multiplied result and after selector 5 is strobed into multiplier 6 and Λ ' (X _j ^-1) reciprocal multiplication, finally obtain a result $Y_j=X_j^{1-b}\frac{\mathrm{\&Omega;}\left(X_j^{-1}\right)}{{\mathrm{\&Lambda;}}^{\&prime;}\left(X_j^{-1}\right)}.$ It is used that all circuit modules that this circuit is used are in the key equation solving circuit institute, that is to say that circuit of the present invention realized the function of two circuit with the resource of key equation solving circuit, therefore circuit of the present invention is at the cost of circuit, on the area with advantageous.

SRAM in this circuit, latch all adopt known structure, for example can adopt " Computer Structure and Logic Design ", Higher Education Publishing House, June calendar year 2001 the 1st edition, the structure of p196～p197 and p107.

The circuit structure of getting reciprocator in the circuit, we adopt circulative shift operation to realize, and the data in the RS decoder are the element in GF territory.Arbitrary element β in the GF territory there are following characteristics:

${\mathrm{\&beta;}}^{-1}={\mathrm{\&beta;}}^{2^m-2}={\mathrm{\&beta;}}^{2^1}{\mathrm{\&beta;}}^{2^2}\mathrm{\&Lambda;}{\mathrm{\&beta;}}^{2^{m-2}}$

Arbitrary element β can be expressed as: $\mathrm{\&beta;}={\mathrm{<figure-callout\; id="0"\; label="b"\; filenames="C20061009683700161.png"\; state="\{\{state\}\}">b</figure-callout>}}_0{\mathrm{\&alpha;}}^{2^0}+{\mathrm{<figure-callout\; id="1"\; label="b"\; filenames="C20061009683700151.png,C20061009683700161.png"\; state="\{\{state\}\}">b</figure-callout>}}_1{\mathrm{\&alpha;}}^{2^1}+L+b_{m-1}{\mathrm{\&alpha;}}^{2^{m-1}},$ b ₀, b ₁L b _M-1The data of just representing a byte m position, β clearly square can be expressed as ${\mathrm{\&beta;}}^2=b_{m-1}{\mathrm{\&alpha;}}^{2^0}+{\mathrm{<figure-callout\; id="0"\; label="b"\; filenames="C20061009683700161.png"\; state="\{\{state\}\}">b</figure-callout>}}_0{\mathrm{\&alpha;}}^{2^1}+L+b_{m-2}{\mathrm{\&alpha;}}^{2^{m-1}}.$ So a circulative shift operation can realize the square operation of β, the inverse of β is as long as m-1 circulative shift operation and m-2 multiplication can be realized.Concrete structure can be referring to Feng G L.A VLSIarchitecture for fast inversion in GF (2m) [J] .IEEE Trans Computers, 1989; 38 (10): 1383-1386.

Claims (3)

1, a kind of key equation of reed-solomon decoder and error value solving-optimizing circuit is characterized in that,

Comprise selector (1), multiplier (2), selector (3), adder (4), selector (5), multiplier (6), No. three selectors (7), initialize and ternary functional circuit (8), selector (9), trigger (10), selector (11), latch (12), static memory (13), select and get reciprocal circuit (14), selection and circuits for triggering (15) and static memory (16), error value solving coefficient signal X _j ^1-bConnect an input of selector (1), the output of selector (1) connects an input of multiplier (2), simultaneously improper value polynomial solving signal Ω (X _j ^-1) connect an input of selector (3), the output of selector (3) connects another input of multiplier (2), the output of multiplier (2) connects an input of adder (4) and an input of selector (5) respectively, the output of adder (4) connects an input of selector (9), the output of selector (5) connects an input of multiplier (6), the output of multiplier (6) connects an input of initialize and ternary functional circuit (8) respectively, the input of selector (11) and the first input end of selection and circuits for triggering (15), the output of initialize and ternary functional circuit (8) connects another input of selector (9) respectively, another input of selector (3) and select and get an input of reciprocal circuit (14), the output of selector (9) connects the input of trigger (10), the output of trigger (10) connects another input of selector (11) and the input of static memory (13) respectively, the output of static memory (13) connects another input of adder (4) and another input of selector (5) respectively, error location polynomial differentiate signal Λ ' (X _j ^-1) selecting selects and get another input of reciprocal circuit (14), select to connect the input of latch (12) and second input of No. three selectors (7) respectively with the output of getting reciprocal circuit (14), the output of latch (12) connects the first input end of No. three selectors (7) and second input of selection and circuits for triggering (15) respectively, associated polynomial signal S (x) connects the 3rd input of No. three selectors (7) and another input of initialize and ternary functional circuit (8), the output of No. three selectors (7) connects another input of multiplier (6), select to connect the input of static memory (16) with the output of circuits for triggering (15), the output of static memory (16) connects another input of selector (1) and the 3rd input of selection and circuits for triggering (15) respectively, and selector (11) selects output error position multinomial signal or improper value multinomial signal or improper value signal to give external circuit.

2, the key equation of reed-solomon decoder according to claim 1 and error value solving-optimizing circuit is characterized in that,

Above-mentioned selection with get reciprocal circuit (14) by selector (141) with get reciprocator (142) and form, above-mentioned error location polynomial differentiate signal Λ ' (X _j ^-1) connect an input of selector (141), the output of selector (141) accesses the input of reciprocator (142), another input of selector (141) is from the output of initialize and ternary functional circuit (8), and that gets reciprocator (142) exports to above-mentioned latch (12).

3, the key equation of reed-solomon decoder according to claim 1 and error value solving-optimizing circuit is characterized in that,

Above-mentioned selection and circuits for triggering (15) are by selector (151), trigger (152), selector (153) and trigger (154) are formed, an input of selector (151) is from the output of multiplier (6), another input is from the output of static memory (16), its output connects the input of trigger (152), the output of trigger (152) connects an input of selector (153), another input of selector (153) is from the output of latch (12), the output of selector (153) connects the input of trigger (154), and the output of trigger (154) connects static memory (16).

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