CN100442070C

CN100442070C - Method for parallelly detecting synchronous communication chips

Info

Publication number: CN100442070C
Application number: CNB2005101112912A
Authority: CN
Inventors: 武建宏
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2005-12-08
Filing date: 2005-12-08
Publication date: 2008-12-10
Anticipated expiration: 2025-12-08
Also published as: CN1979201A

Abstract

The invention discloses a method to take multi-chip parallel testing by using synchronous communication chip. It includes the following steps: taking division to the different test vectors according to time cycle, and restoring into memory of tester; outputting the data according to time cycle to gain paralleling testing and taking qualified/error judgment. The invention could improve testing efficiency of testing chip and lower testing time and cost.

Description

The method of parallelly detecting synchronous communication chips

Technical field

The present invention relates to a kind of method of testing of large scale integrated circuit synchronous communication chip, particularly relate to the method that a kind of synchronous communication chip is realized multicore sheet concurrent testing.

Background technology

For existing test macro, promptly allow to carry out a plurality of synchronous communication chip simultaneous tests, also be on all four (as Fig. 1) to the employed test vector of each measured device (DUT, device under test).When using different test vectors to different measured devices, when perhaps each measured device being write different data, because the restriction of the design specification of existing tester and existing measuring technology can't realize simultaneously a plurality of chips being carried out the test of different test vectors.

Summary of the invention

The technical problem to be solved in the present invention provides a kind of method of parallelly detecting synchronous communication chips, and it can realize that a plurality of chips carry out the test of different test vectors simultaneously to the synchronous communication chip, shortens the test duration of chip, reduces the testing cost of chip.

For solving the problems of the technologies described above, the method of parallelly detecting synchronous communication chips of the present invention is to adopt following technical scheme to realize, earlier cut apart in the Data Buffer Memory that stores tester into by the clock cycle to the different test vector of all measured devices, again all are stored data based clock period and line output, thereby obtain the concurrent testing of the multiple test vector of a plurality of detected element, and simultaneously it is carried out pass/fail and judge.

Adopt method of the present invention can obviously shorten the test duration of chip.For example adopt general tester to use identical test vector to test simultaneously to 16 chips.If the required test vector difference of each chip so just needs test 16 times.And adopt 16 different test vectors with after surveying, and testing efficiency has reached about 16 times of the different vectors of single test successively, and it is about about 93% that this means that also test duration to one piece of fecund product chip has shortened, and greatly reduces the testing cost of chip.

Description of drawings

The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:

Fig. 1 is the test vector synoptic diagram that uses by existing method each detected element when surveying;

Fig. 2 can realize that by method of the present invention multidirectional amount is parallel with the synoptic diagram of surveying;

Fig. 3 is cut apart the storage synoptic diagram by a plurality of test vector data of method of the present invention;

Fig. 4 is by a plurality of test vectors of method of the present invention and line output test synoptic diagram.

Embodiment

The method of parallelly detecting synchronous communication chips of the present invention, at first cut apart in the internal memory that stores tester into by the clock cycle to the different test vector of all detected element, again all are stored data based clock period and line output, thereby obtain the concurrent testing of the multiple test vector of a plurality of detected element, and simultaneously it is carried out pass/fail and judge.The test (referring to Fig. 2) of different test vectors is carried out in realization simultaneously to the multicore sheet of synchronous communication chip.

The described process of cutting apart storage is: the coordinate of first DUT when survey is together got at every turn in communication to probe station by tester, the relative position of each DUT when basis is with survey then, the concrete coordinate of each DUT in the time of can calculating at every turn survey together.Then, select different test vectors for use according to the concrete coordinate of each DUT.At last selected test vector is carried out cutting apart by the minimum period in real time, the data that each test vector is partitioned into are formed a byte, then these data are deposited in the DBM (data buffer memory Data Buffer Memory) of tester, by that analogy, all test vectors are all cut apart changed in order that the address deposits DBM in.When test, press the clock signal, read the data parallel output among the DBM successively, use the test of multiple vector when realizing with survey with this.

Fig. 3 shows the described process of cutting apart storage: at first be that test vector to the required use of a plurality of measured devices carries out data according to the minimum period and cuts apart.Then, will cut apart good data stores in the internal memory of tester by the address.

As shown in Figure 4, according to clock signal the data in the tester internal memory are read successively by the address, each of data is as the input signal of each measured device.Concurrent testing when realizing that with this a plurality of measured devices use multiple test vector.

Tested object is the synchronous communication chip; The number of concurrent testing can be 4/8,16/32, for example, can stick into row test simultaneously to the CPU of nearly 16 SIM (subscriber identification module subscriber identification module) card or other synchronous communications.

The present invention has adopted all I/O terminals (chip input and output terminal) has been carried out the independently mode of output test vector, and the test vector of various chips is reconfigured output simultaneously.Therefore, it can be to various chips on a slice silicon chip, or the multiple input content of chip of the same race is carried out concurrent testing.And adopted the mode of production of seriation, promptly to similar different series product, test procedure has very high transplantability.Described test vector has adopted the mode of production of hardware and software platform, promptly can produce the special test vector of standard according to different instructions automatically.For example can make standard special test subvector to some general operations, when test, call corresponding test subvector automatically according to the position and the different instructions of chip to certain series of products.

The present invention can shorten the test duration of chip, reduces the testing cost of chip, realizes to greatest extent the multiple test vector of a plurality of chips of synchronous communication chip is tested simultaneously.

Claims

1, a kind of method of parallelly detecting synchronous communication chips, it is characterized in that: cut apart in the Data Buffer Memory that stores tester into by the clock cycle to the different test vector of all detected element earlier, again all are stored data based clock period and line output, thereby obtain the concurrent testing of the multiple test vector of a plurality of detected element, and simultaneously it is carried out pass/fail and judge.

2, the method for parallelly detecting synchronous communication chips as claimed in claim 1 is characterized in that: the chip of concurrent testing is 4,8,16 or 32.

3, the method for parallelly detecting synchronous communication chips as claimed in claim 1 is characterized in that: described test vector can produce the special test vector of standard automatically according to different instructions.

4, as the method for any one described parallelly detecting synchronous communication chips in the claim 1 to 3, it is characterized in that: the described process of cutting apart storage is: tester to probe station communication get each when surveying the coordinate of first DUT, the relative position of each DUT when basis is with survey then, the concrete coordinate of each DUT when calculating at every turn with survey; Then, select different test vectors for use according to the concrete coordinate of each DUT; At last selected test vector is carried out cutting apart by the minimum period in real time, the data that each test vector is partitioned into are formed a byte, then these data are deposited in the Data Buffer Memory of tester, by that analogy, all test vectors are all cut apart changed in order that the address deposits Data Buffer Memory in.

5, as the method for any one described parallelly detecting synchronous communication chips in the claim 1 to 3, it is characterized in that: described clock cycle and the line output of pressing, be meant by the clock cycle and read data parallel output in the Data Buffer Memory of tester successively, each of data is as the input signal of each detected element.