CN101165502B - Tester simultaneous test method - Google Patents
Tester simultaneous test method Download PDFInfo
- Publication number
- CN101165502B CN101165502B CN2006101172496A CN200610117249A CN101165502B CN 101165502 B CN101165502 B CN 101165502B CN 2006101172496 A CN2006101172496 A CN 2006101172496A CN 200610117249 A CN200610117249 A CN 200610117249A CN 101165502 B CN101165502 B CN 101165502B
- Authority
- CN
- China
- Prior art keywords
- test
- channel
- chip
- vector
- vector generator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
The method comprises: 1) error processing program, setting multi chips synchronous test as one chip to make test; 2) algorithm vector generator, allocating a generated signal to the test channels of multi chips through a programmable data selector; 3) sequential vector generator, using a preset program to expand the test vector of one chip to the test channel of multi chips; 4) getting the testresult of all tested channels.
Description
Technical field
The present invention relates to a kind of integrated circuit (IC) testing method, be meant a kind of tester simultaneous test method especially.
Background technology
In the semiconductor test industry, existing logic test equipment is generally all fixed with quantitation and is fewer, general logic tester can only can be tested simultaneously to 2 to 4 chips, and owing to adopt the simultaneous test method of system default, the test vector of each chip must be identical, the test underaction.
Test macro has the two large divisions to produce by test vector, i.e. algorithm vector generator (ALPG) and order vector generator (SQPG).When writing test procedure,, produce logical value jointly by two generators and be passed to Frame Handler generation resolution chart as long as above-mentioned two generators are write test vector at a chip.As long as when needs carry out with survey, tell system several with surveying, need not special in addition the programming, system just can carry out 2 to 4 with surveying on the test channel of appointment.But this technical disadvantages is few with surveying number, and test vector is dumb.
Therefore, in this technical field, need a kind of tester simultaneous test method, improve same quantitation, and can adjust arbitrarily as required with measuring.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of tester simultaneous test method, and it can improve homonymy quantity, and can adjust arbitrarily as required with measuring.
For solving the problems of the technologies described above, tester simultaneous test method of the present invention, the first step: error handler, set a plurality of chip simultaneous tests and test as a chip; Second step: the algorithm vector generator is assigned to a signal that produces the test channel of a plurality of chips by the programmable data selector switch; The 3rd step: the order vector generator expands to the test vector of a chip by setting program the test channel of a plurality of chips; The 4th step: obtain the test result of all test channel, described test channel is divided into groups according to different channel address, judges that according to the result of described channel packet whether qualified each chip is.
The present invention breaks the very few restriction of the tester simultaneous quantitation of original higher-order logic, make and have only 2 logic testers of surveying together can bring up to 64 with surveying originally with quantitation, and can adjust same quantitation arbitrarily as required, simultaneously, it is many to give full play to higher-order logic tester test channel, the measuring accuracy height, the advantage that test frequency is high.
In addition, the test to each chip can control to the vectorial different, more convenient of each test channel output.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment.
Accompanying drawing is a tester simultaneous test connection diagram of the present invention.
Embodiment
When the test frequency high product, the tester of general low side can't be realized, simultaneously, product has complicated logic function test must need powerful SQPG test function again, at this moment also can't be competent at the more memory test instrument of quantitation, therefore, must use some high-end logic testers, but this type of logic tester is general fewer with surveying number, has only 2 to 4 with surveying.
Can realize that by the present invention this series products is carried out the greater number chip to be tested simultaneously, its method is as follows:
The first step: at first, need make amendment to error handler, needs are tested as a chip with all chips of surveying, can directly obtain the test result of all test channel through test, as long as all are no more than the total test channel number of tester with the pin of surveying chip, can increase same quantitation as much as possible.
Second step:, realize many chip simultaneous tests of ALPG to need by PDS (programmable data selector switch) linking functions the logical value that ALPG produces being connected on the test channel of a plurality of chips by the test channel of ALPG generation in the test vector.As shown in drawings, on the test channel of PDS with signal allocation to two chip of ALPG generation.
The 3rd step: to the test channel that need produce by SQPG (sequential vector generator) in the test vector, by software the test vector of an original chip is expanded to a plurality of chip testing passages, as shown in drawings, the SQPG test signal that directly produces two chips is connected respectively on the corresponding test channel.Then with all passages defining by a chip.
The 4th step: all passages are divided into groups according to different channel address, according to not on the same group in the test result of test channel judge that each chip is qualified and defective.
Claims (1)
1. tester simultaneous test method is characterized in that: the first step: at first, need make amendment to error handler, set a plurality of chip simultaneous tests and test as a chip, all are no more than the total test channel number of tester with pins of surveying chips; Second step: the algorithm vector generator, to the test channel that need be produced by the algorithm vector generator in the test vector, the signal that the algorithm vector generator is produced is assigned to the test channel of a plurality of chips by the programmable data selector switch; The 3rd step: the order vector generator to the test channel that need be produced by the order vector generator in the test vector, expands to the test vector of an original chip by setting program the test channel of a plurality of chips; The 4th step: obtain the test result of all test channel, described test channel is divided into groups according to different channel address, judges that according to the result of described channel packet whether qualified each chip is.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2006101172496A CN101165502B (en) | 2006-10-18 | 2006-10-18 | Tester simultaneous test method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2006101172496A CN101165502B (en) | 2006-10-18 | 2006-10-18 | Tester simultaneous test method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101165502A CN101165502A (en) | 2008-04-23 |
| CN101165502B true CN101165502B (en) | 2011-06-22 |
Family
ID=39334272
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2006101172496A Active CN101165502B (en) | 2006-10-18 | 2006-10-18 | Tester simultaneous test method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101165502B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102540059B (en) * | 2010-12-27 | 2014-07-09 | 上海华虹宏力半导体制造有限公司 | Testing device and method for digital semiconductor device |
| CN102426335B (en) * | 2011-08-24 | 2013-07-10 | 湖北航天技术研究院计量测试技术研究所 | Method for automatically generating test pattern vector of DSP (Digital Signal Processor) device |
| CN104215843B (en) * | 2013-06-05 | 2017-08-08 | 上海华虹宏力半导体制造有限公司 | Improve the chip array method of chip simultaneous test |
| CN104808134A (en) * | 2015-04-18 | 2015-07-29 | 南通金泰科技有限公司 | Multi-channel chip test system |
| CN105139893B (en) * | 2015-09-27 | 2018-10-16 | 上海华力微电子有限公司 | A kind of memorizer test device and a kind of storage core chip test method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19633711A1 (en) * | 1996-08-21 | 1997-09-11 | Siemens Components | Semiconductor component testing system |
| CN1211737A (en) * | 1997-08-26 | 1999-03-24 | 三星电子株式会社 | IC chip tester and method for testing IC chip using the tester |
| CN1450357A (en) * | 2003-05-21 | 2003-10-22 | 中国科学院计算技术研究所 | Full speed current test method for IC |
-
2006
- 2006-10-18 CN CN2006101172496A patent/CN101165502B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19633711A1 (en) * | 1996-08-21 | 1997-09-11 | Siemens Components | Semiconductor component testing system |
| CN1211737A (en) * | 1997-08-26 | 1999-03-24 | 三星电子株式会社 | IC chip tester and method for testing IC chip using the tester |
| CN1450357A (en) * | 2003-05-21 | 2003-10-22 | 中国科学院计算技术研究所 | Full speed current test method for IC |
Non-Patent Citations (3)
| Title |
|---|
| 周蓓蓓等.WXC-1向量测试仪的设计与实现.《苏州科技学院学报(工程技术版)》.2002,第15卷(第4期),71-75. * |
| 李玉等.便携式逻辑芯片功能检测仪.《舰船电子工程》.2005,(第5期),73-75. * |
| 高蒙等.基于DSP芯片的液晶特性专用测试仪研制.《现代电子技术(半月刊)》.2006,(第1期),86-88,91. * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101165502A (en) | 2008-04-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8650524B1 (en) | Method and apparatus for low-pin count testing of integrated circuits | |
| US8904256B1 (en) | Method and apparatus for low-pin count testing of integrated circuits | |
| US6359818B2 (en) | Apparatus for analyzing failure for semiconductor memory device | |
| US20020184582A1 (en) | Test access mechanism for supporting a configurable built-in self-test circuit and method thereof | |
| US7114110B2 (en) | Semiconductor device, and the method of testing or making of the semiconductor device | |
| CN101165502B (en) | Tester simultaneous test method | |
| US9455050B2 (en) | Failure diagnosis circuit | |
| US7003697B2 (en) | Apparatus having pattern scrambler for testing a semiconductor device and method for operating same | |
| WO2008044391A1 (en) | Testing device, testing method, and manufacturing method | |
| US8799731B2 (en) | Clock control for reducing timing exceptions in scan testing of an integrated circuit | |
| US7257753B2 (en) | Semiconductor testing apparatus | |
| US20030011396A1 (en) | Semiconductor device and test system therefor | |
| US8341477B2 (en) | Test board having a plurality of test modules and a test system having the same | |
| CN112100010B (en) | DFT test port distribution method, chip and test method suitable for multi-package | |
| US9293226B2 (en) | Memory test device and operating method thereof | |
| CN103366827A (en) | Storage device and method for testing storage device through testing machine | |
| US8441277B2 (en) | Semiconductor testing device, semiconductor device, and testing method | |
| US6647522B1 (en) | Semiconductor devices having multiple memories | |
| US7065693B2 (en) | Implementation of test patterns in automated test equipment | |
| US7433252B2 (en) | Semiconductor memory device capable of storing data of various patterns and method of electrically testing the semiconductor memory device | |
| US6374376B1 (en) | Circuit, system and method for arranging data output by semiconductor testers to packet-based devices under test | |
| CN108335720B (en) | Method for compiling personalized data by using memory tester | |
| KR101184312B1 (en) | Testing apparatus | |
| US6507801B1 (en) | Semiconductor device testing system | |
| US20020049942A1 (en) | Analog/digital characteristics testing device and IC testing apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140110 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20140110 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |