CN100357870C - Method of proceeding access multikind storage on chip select outer unibus - Google Patents
Method of proceeding access multikind storage on chip select outer unibus Download PDFInfo
- Publication number
- CN100357870C CN100357870C CNB2005100323070A CN200510032307A CN100357870C CN 100357870 C CN100357870 C CN 100357870C CN B2005100323070 A CNB2005100323070 A CN B2005100323070A CN 200510032307 A CN200510032307 A CN 200510032307A CN 100357870 C CN100357870 C CN 100357870C
- Authority
- CN
- China
- Prior art keywords
- signal
- memory
- read
- write
- storer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The present invention discloses a method for accessing multi-kind memories hung on a single unibus outside a chip, which aims at providing a method for accessing multi-kind memories hung on a single unibus outside a chip. The present invention has the technical scheme that the range of an accessing memory address is divided into M subspace, and each subspace corresponds to one kind of memory; a single unibus memory interface which is provided with M chip-selected signals is arranged, and each chip-selected signal is connected with one kind of memory; a decoding element, a control register group, M storage controllers and a cross switch are integrated in the memory interface to realize configuration to the parameters of the memories, decoding to the chip-selected signals and the generation of unibus signals, and simultaneous accessing to M memories hung on the single unibus can be realized through selection to the unibus signals. After the present invention is adopted, an embedded microprocessor can adopt the single unibus to access multi-kind memories hung outside a chip, the power consumption and the area of the microprocessor can be reduced, and the number of pins can be reduced.
Description
Technical field: the present invention relates among embedded microprocessor and the SoC (System on Chip, SOC (system on a chip)), to being articulated in the method that the multiple storer on the unibus conducts interviews outside the sheet.
Background technology: in universal cpu, be responsible for all realizing by the bridging chip on the mainboard with the control parts of depositing of external memory storage swap data.And at embedded microprocessor, DSP (Digital Signal Processor for example, digital signal processor), ASIC (Appl ication Specific Integrated Circuit, special IC), and among some SoC, deposit the control parts and usually be integrated on the chip piece, direct and memory transactions data by external bus with CPU nuclear, DMA parts such as (Direct Memory Access, direct memory access (DMA)).The control parts of depositing of this responsible visit chip external memory are also referred to as memory interface.Memory interface and CPU nuclear is integrated in the mode on the chip piece can effectively improves the data throughput bandwidth, reduce system power dissipation, reduce on the plate wiring the interference of high speed transmission of signals.But in Embedded Application, system often needs to articulate simultaneously multiple storer, for example is used for the SDRAM or the SBSRAM of fast data buffer, is used to store the Flash or the ROM of user program, is used for the FIFO of exchanges data etc.Different storeies is externally visited in the memory access request of the internal responding DMA of memory interface.The read-write mode of these storeies has nothing in common with each other, and the address realm of every kind of storer is also inequality.Conventional implementation method is to design a scu respectively in chip every kind of storer, for every kind of storer one cover read-write bus is set simultaneously in chip pin.But this method can increase power consumption, area and the pin number of chip greatly, and Embedded Application often requires microprocessor to have lower power consumption, less area and less pin number.How the multiple storer that articulates simultaneously on the unibus being conducted interviews is the major issue that needs to be resolved hurrily in this class microprocessor Design.Here said " unibus " is meant a unique cover memory access bus that comprises storer control signals such as address, data, read/write enable.
Summary of the invention:
The technical problem to be solved in the present invention is: at the needs that need to articulate and visit multiple storer in the built-in applied system, a kind of method that the multiple storer that is articulated on the outer unibus of sheet is conducted interviews is proposed, embedded microprocessor can be conducted interviews to being articulated in the outer multiple storer of sheet by unibus, overcome traditional employing multibus and visit the deficiency of multiple memory approach, reduce the power consumption and the area of this class microprocessor, reduce the pin number.
Technical scheme is that the memory access address realm is divided into the M sub spaces, the corresponding a kind of storer in each subspace.A kind of unibus memory interface of design is provided with the M silver and selects signal on interface in embedded microprocessor, and each chip selection signal connects a kind of storer.The inner integrated decoding unit of memory interface, control register group, M kind memory controller and a cross bar switch, realization is to the configuration of each memory parameter, the decoding of chip selection signal and the generation of bus signals, realizes the target that the M kind storer that articulates simultaneously on the unibus is conducted interviews by the selection to bus signals.
Concrete technical scheme is:
At first the memory access address realm is divided.If external bus articulates M kind storer simultaneously, then whole memory access address realm is divided into the M sub spaces, the corresponding storer in each subspace.When dividing the subspace, address, begin to divide from the MSB (Most Significant Bit, highest significant position) of address.If the capacity difference of each storer, each sub spaces of being divided varies in size, and promptly carries out inhomogeneous division; If total address realm is enough big, after evenly being divided into the M sub spaces, the size of each subspace can both satisfy the capacity of respective memory, then evenly divides, be about to total address realm and evenly be divided into the M sub spaces, be convenient to decoding unit like this and decipher.Wherein M is the integer more than or equal to 1.
The method for designing of unibus memory interface is: it is made up of decoding unit, control register group, M kind memory controller, cross bar switch.Decoding unit links to each other with cross bar switch with DMA, control register group, memory controller, receive the controlled variable of memory access request signal, address signal and the control register group of DMA, the memory access solicited message is deciphered, produce M chip selection signal and export to cross bar switch, the read/write start up command signals of generation and read-write number of times signal are exported to memory controller; The control register group connects by configuration bus and the CPU nuclear phase of CPU, accepts the configuration that CPU checks various memory parameter, and sends controlled variable to decoding unit and memory controller; The controlled variable signal of read/write command that data-signal, address signal, the decoding unit of memory controller reception DMA memory access produces and read/write number of times signal, control register group, produce required data of read/write respective memory and control signal (address, read/write enable, output enable etc.), and these signals are delivered to cross bar switch, the number of memory controller is consistent with the storer kind, if the storer kind is M, then the number of memory controller also is M.Cross bar switch internally connects the M silver and selects signal and M the bus signals that memory controller produces, and externally articulates M kind storer by the outer unibus of sheet.
Decoding unit is made of chip selection signal decoding module, read/write signal decoding module and read-write number of times decoding module.Select signal owing to comprise the M silver on the memory interface, each chip selection signal connects a kind of storer, therefore when the chip selection signal decoding module is deciphered the high position of DMA memory access address, judge the subspace that this address is affiliated, activate in the corresponding M chip selection signal then, be used to choose corresponding memory on the outer unibus of sheet; The read/write signal decoding module is deciphered according to a high position and the memory access request of memory access address, judges the storer that will read and write, sends corresponding read/write start up command signals and gives corresponding memory controller, starts the read/write processes of memory controller.The memory width parameter that read-write number of times decoding module is sent here according to memory access data width and control register group is deciphered, and produces read/write number of times signal.If the data width of memory access is greater than the memory width that has disposed in the corresponding control register, read/write number of times signal will be used to indicate the operation of respective stored controller greater than 1.For example, the data width of certain read request is 32, and the width of corresponding stored device has only 16, so decoding unit will decipher produce size be 2 read the number of times signal, memory controller will be according to this signal, from 2 continuous addresses of respective memory, respectively read 16 bit data, be merged into 32 data, return to DMA.If the maximal value of memory access data width is S times of minimum widith in M the memory width, S is 2 integral number power, and the width of read/write number of times signal should be made as log so
2The S position.
The control register group comprises decoding scheme and M group control register, comprise several registers in every group of control register, be used to dispose a kind of controlled variable of storer, foundation/triggering/retention time of the width of storer and type, asynchronous memory for example, the row/row of SDRAM storer/parameters such as body number of addresses.The type of parameter and number are according to the needs increase and decrease of actual storage.If the required controlled variable of certain storer is less, use a control register can represent all parameters, only a control register need be set in the control corresponding registers group so.If must use a plurality of control registers could represent all controlled variable, need to be provided with a plurality of control registers in the control corresponding registers group so.The bit wide of each control register is traditionally arranged to be the word length of microprocessor, simultaneously corresponding global logic address.CPU carries out read/write by configuration bus to the controlled variable of each control register.When read/write, decoding scheme is deciphered read/write address, the read/write command sent here on the configuration bus, produces the command signal of the corresponding control register of read/write.Control register is accepted the command signal of decoding scheme: if the write parameters order, then the data of sending here on the configuration bus are write the respective field of register; If read parameter command, then the data of own respective field are outputed on the configuration bus, provide ready for data signal simultaneously.Every kind of memory controller adopts disclosed standard design method in the memory interface.The read/write startup command that decoding unit produces only activates a kind of controller of storer at every turn, and remaining memory controller can not respond.The memory controller that is activated produces required valid data and the control signal of read/write respective memory, and data and control signal that remaining memory controller produces are invalid.
Cross bar switch is a group selection logical circuit, is made of M road multi-selection device.Data and control signal that it is sent here each memory controller according to M chip selection signal are carried out multiselect one operation.If (1≤i≤M) individual chip selection signal is effective, and data and the control signal of then selecting i memory controller (memory controller that promptly is activated) to produce output on the external bus, also export M chip selection signal simultaneously for i.
Utilize above-mentioned memory interface to the method that a plurality of storeies that are articulated on the outer unibus of sheet conduct interviews to be: before the beginning memory access, CPU writes the control register group by configuration bus with the controlled variable of various storeies.When memory access, decoding unit is deciphered memory access address, memory access request and memory access data width according to the controlled variable that the control register group provides, activation M silver selects in the signal, produces effective read/write start up command signals and read/write number of times signal simultaneously, exports to memory controller.Because wherein a kind of storer is only visited in each memory access, therefore have only the read/write startup command of a corresponding decoded unit of memory controller to activate, remaining memory controller does not respond.The memory controller that is activated produces the data and the control signal that meet the requirement of respective memory sequential according to memory access data, address and controlled variable, exports to cross bar switch.Cross bar switch selects signal according to the M silver, and data and the control signal of selecting the respective stored controller to produce output on the external bus.Signal on the memory response external bus that the effective chip selection signal of quilt is chosen is finished accessing operation.Other storeies of not chosen by chip selection signal are the response external bus signals not.So just realized target that the multiple storer that articulates simultaneously on the unibus is conducted interviews.
The kind of increase/minimizing storer needs only increase/minimizing control corresponding register, chip selection signal, memory controller and switch and selects logic if desired.
Adopt the present invention can produce following beneficial technical effects:
1. the multiplexing cover external bus of all storeies reduces the chip pin number under the original multibus mode, has reduced chip power-consumption and area;
2. according to the needs of different application to the storer kind, the present invention is with good expansibility and tailorability:
3. the present invention adopts the module interface of standard, has module reuse preferably.
Description of drawings:
Fig. 1 is a general embedded microprocessor application system building-block of logic.
Fig. 2 is the building-block of logic of unibus memory interface of the present invention.
Fig. 3 is the building-block of logic of decoding unit of the present invention.
Fig. 4 is the composition structural drawing of control register group of the present invention.
Fig. 5 is the interconnection example that memory interface of the present invention articulates the Flash of 16 of the SDRAM of a slice 32 bit wides and a slices simultaneously.
Embodiment:
Fig. 1 is a general embedded microprocessor application system.Microprocessor internal is integrated a kind of memory interface of the present invention.In this example, SDRAM, SBSRAM, FIFO, Flash totally 4 kinds of different storeies have been articulated on the memory interface external bus simultaneously.
Fig. 2 is the building-block of logic that articulates the unibus memory interface of SDRAM commonly used, SBSRAM, FIFO, four kinds of storeies of Flash.This unibus memory interface is made up of decoding unit, control register group, 4 memory controllers, cross bar switches.Decoding unit receives the memory access request signal of DMA, and the control register group connects the configuration bus of CPU, and cross bar switch connects four kinds of storeies by the outer unibus of sheet.Before the beginning memory access, CPU writes the control register group by configuration bus with the controlled variable of four kinds of storeies.When memory access, decoding unit is deciphered memory access address, memory access request and memory access data width according to the controlled variable that the control register group provides, activate 4 silvers and select in the signal one, produce effective read/write start up command signals and read/write number of times indicator signal simultaneously, export to memory controller.Because wherein a kind of storer is only visited in each memory access, therefore have only the read/write startup command of a corresponding decoded unit of memory controller to activate, remaining memory controller does not respond.The memory controller that is activated produces the data and the control signal that meet the requirement of respective memory sequential according to memory access data, address and controlled variable, exports to cross bar switch.Cross bar switch is four to select a logic, and it selects signal according to 4 silvers, and data and the control signal of selecting one of them memory controller to produce output on the external bus.Signal on the memory response external bus that the effective chip selection signal of quilt is chosen is finished accessing operation.
Fig. 3 has provided the composition structure of decoding unit of the present invention.This figure is an example with four kinds of storeies of SDRAM, SBSRAM, FIFO, Flash commonly used still.Suppose that the memory access address size is the n position, and after being divided into 4 sub spaces, just can distinguish 4 sub spaces according to n position and n-1 bit address, " chip selection signal decoding " module can realize with a 2-4 code translator, the chip selection signal of 4 storages of decoding output." read-write decoding " module through decoding, produces the read/write start up command signals of 4 storeies according to n position and n-1 bit address and read signal.The memory width parameter that " read-write number of times decoding " module is sent here according to memory access data width signal and 4 control registers is deciphered, and produces read/write number of times signal, is used to indicate the read-write process of memory controller.The maximal value of supposing the memory access data width is S times (S generally is 2 integral number power) of minimum widith in 4 memory widths, and the width of read/write number of times signal should be made as log so
2The S position.The maximal value of for example memory access data width is 64, and external storer minimum widith is 8 bit wides, and S equals 8 so, and the width of read/write number of times signal should be made as 3.
Fig. 4 has provided the building-block of logic of control register group of the present invention.Be example with four kinds of storeies of SDRAM, SBSRAM, FIFO, Flash commonly used still, the control register group is made of decoding scheme and four groups of control registers.Example among the figure comprises four groups of control registers, and provided respectively organize control register the specific field structure, be respectively applied for the configuration SDRAM, SBSRAM, FIFO and Flash controlled variable.Wherein R1 is the control register group of configuration SDRAM controlled variable, wherein comprises 2 32 register, be respectively applied for configuration burst mode, CAS response beat, refresh enable, controlled variable such as refresh cycle.R2 is the control register group of SBSRAM, wherein only comprises 1 32 register.R3 is the control register group of FIFO, and R4 is the control register group of Flash, all has only one 32 control register respectively.Control register is divided into a plurality of fields, and each field is used to be provided with a parameter, and the length of field is decided according to the complex situations of parameter.If this parameter has n kind situation, the required figure place B of this field should satisfy so
If the controlled variable of certain storer is more, use the control register can't perfect representation, can dispose a kind of parameter of storer so with a plurality of control registers.The R1 group that is used for disposing the SDRAM parameter among Fig. 4 has just been used 2 control registers.Each control register all has a global address, and CPU can carry out read/write to the controlled variable of each control register by configuration bus.When read/write, decoding scheme is deciphered read/write address, the read/write command sent here on the configuration bus, produces the command signal of the corresponding control register of read/write.Control register is accepted the command signal of decoding scheme: if the write parameters order, then the data of sending here on the configuration bus are write the respective field of register; If read parameter command, then the data of own respective field are outputed on the configuration bus, provide ready for data signal simultaneously.
Fig. 5 has provided memory interface of the present invention articulates the Flash of the SDRAM of one 32 bit wide and one 16 bit wide simultaneously by external bus synoptic diagram.
The present invention at present adopts in 32 high performance float-point DSP " milky way is soared-DSP700 " that University of Science and Technology for National Defence develops voluntarily, and this DSP can articulate 4 kinds of different storeies on the unibus simultaneously outside sheet.
Claims (6)
1. the method that the multiple storer that is articulated on the outer unibus of sheet is conducted interviews is characterized in that the memory access address realm is divided into the M sub spaces, the corresponding a kind of storer in each subspace; A kind of unibus memory interface of design is provided with the M silver and selects signal on interface in embedded microprocessor, and each chip selection signal connects a kind of storer; The inner integrated decoding unit of memory interface, control register group, M kind memory controller and a cross bar switch, decoding unit links to each other with DMA, receive the controlled variable of memory access request signal, address signal and the control register group of DMA, the memory access solicited message is deciphered, produce M chip selection signal and export to cross bar switch, the read/write start up command signals of generation and read-write number of times signal are exported to memory controller; The control register group connects by configuration bus and the CPU nuclear phase of CPU, accepts the configuration that CPU checks various memory parameter, and sends controlled variable to decoding unit and memory controller; The controlled variable signal of read/write command that data-signal, address signal, the decoding unit of memory controller reception DMA memory access produces and read/write number of times signal, control register group, produce required data and the control signal of read/write respective memory, and these signals are delivered to cross bar switch, the number of memory controller is consistent with the storer kind, if the storer kind is M, then the number of memory controller also is M; Cross bar switch internally connects the M silver and selects signal and M the bus signals that memory controller produces, and externally articulates M kind storer by the outer unibus of sheet; Realize the configuration of each memory parameter, the decoding of chip selection signal and the generation of bus signals by memory interface, realize the target that the M kind storer that articulates simultaneously on the unibus is conducted interviews by selection bus signals; Wherein M is the integer more than or equal to 1.
2. the method that the multiple storer that is articulated on the outer unibus of sheet is conducted interviews as claimed in claim 1, it is characterized in that the method that the memory access address realm is divided being: if external bus articulates M kind storer simultaneously, then whole memory access address realm is divided into the M sub spaces, the corresponding storer in each subspace, begin to divide from the highest significant position MSB of address, if the capacity difference of each storer, each sub spaces of being divided varies in size, and promptly carries out inhomogeneous division; If total address realm is enough big, evenly be divided into the M sub spaces after, the size of each subspace can both satisfy the capacity of respective memory, then evenly divides, and is about to total address realm and evenly is divided into the M sub spaces.
3. the method that the multiple storer that is articulated on the outer unibus of sheet is conducted interviews as claimed in claim 1 is characterized in that described decoding unit is made of chip selection signal decoding module, read/write signal decoding module and read-write number of times decoding module; When the chip selection signal decoding module is deciphered the high position of DMA memory access address, judge the subspace that this address is affiliated, activate in the corresponding M chip selection signal then, be used to choose corresponding memory on the outer unibus of sheet; The read/write signal decoding module is deciphered according to a high position and the memory access request of memory access address, judges the storer that will read and write, sends corresponding read/write start up command signals and gives corresponding memory controller, starts the read/write processes of memory controller; The memory width parameter that read-write number of times decoding module is sent here according to memory access data width and control register group is deciphered, and produces read/write number of times signal; If the data width of memory access is greater than the memory width that has disposed in the corresponding control register, read/write number of times signal will be used to indicate the operation of respective stored controller greater than 1; If the maximal value of memory access data width is S times of minimum widith in M the memory width, S is 2 integral number power, and the width of read/write number of times signal should be made as log so
2The S position.
4. the method that the multiple storer that is articulated on the outer unibus of sheet is conducted interviews as claimed in claim 1, it is characterized in that described control register group comprises decoding scheme and M group control register, comprise several registers in every group of control register, be used to dispose a kind of controlled variable of storer, the type of parameter and number are according to the needs increase and decrease of actual storage; The bit wide of each control register is traditionally arranged to be the word length of microprocessor, simultaneously corresponding global logic address; CPU carries out read/write by configuration bus to the controlled variable of each control register; When read/write, decoding scheme is deciphered read/write address, the read/write command sent here on the configuration bus, produces the command signal of the corresponding control register of read/write; Control register is accepted the command signal of decoding scheme: if the write parameters order, then the data of sending here on the configuration bus are write the respective field of register; If read parameter command, then the data of own respective field are outputed on the configuration bus, provide ready for data signal simultaneously.
5. the method that the multiple storer that is articulated on the outer unibus of sheet is conducted interviews as claimed in claim 1, it is characterized in that described cross bar switch is a group selection logical circuit, constitute by M road multi-selection device, data and control signal that it is sent here each memory controller according to M chip selection signal are carried out multiselect one operation, if i chip selection signal is effective, data and control signal that the memory controller of then selecting i memory controller promptly to be activated produces, output on the external bus, also export M chip selection signal simultaneously, wherein 1≤i≤M.
6. the method that the multiple storer that is articulated on the outer unibus of sheet is conducted interviews as claimed in claim 1, it is characterized in that utilizing described memory interface to the method that a plurality of storeies that are articulated on the outer unibus of sheet conduct interviews to be: before the beginning memory access, CPU writes the control register group by configuration bus with the controlled variable of various storeies; When memory access, decoding unit is deciphered memory access address, memory access request and memory access data width according to the controlled variable that the control register group provides, activation M silver selects in the signal, produces effective read/write start up command signals and read/write number of times signal simultaneously, exports to memory controller; Because wherein a kind of storer is only visited in each memory access, therefore have only the read/write startup command of a corresponding decoded unit of memory controller to activate, remaining memory controller does not respond; The memory controller that is activated produces the data and the control signal that meet the requirement of respective memory sequential according to memory access data, address and controlled variable, exports to cross bar switch; Cross bar switch selects signal according to the M silver, and data and the control signal of selecting the respective stored controller to produce output on the external bus; Signal on the memory response external bus that the effective chip selection signal of quilt is chosen is finished accessing operation; Other storeies of not chosen by chip selection signal are the response external bus signals not.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100323070A CN100357870C (en) | 2005-10-28 | 2005-10-28 | Method of proceeding access multikind storage on chip select outer unibus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100323070A CN100357870C (en) | 2005-10-28 | 2005-10-28 | Method of proceeding access multikind storage on chip select outer unibus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1758208A CN1758208A (en) | 2006-04-12 |
| CN100357870C true CN100357870C (en) | 2007-12-26 |
Family
ID=36703607
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100323070A Expired - Fee Related CN100357870C (en) | 2005-10-28 | 2005-10-28 | Method of proceeding access multikind storage on chip select outer unibus |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100357870C (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4497184B2 (en) * | 2007-09-13 | 2010-07-07 | ソニー株式会社 | Integrated device, layout method thereof, and program |
| CN102087874B (en) * | 2009-12-07 | 2013-02-27 | 晨星软件研发(深圳)有限公司 | General memory input and output generating device and method |
| US10628373B2 (en) * | 2015-12-01 | 2020-04-21 | Marvell International Ltd. | Systems and methods for transmitting an access request via a flexible register access bus |
| CN105701026A (en) * | 2016-01-04 | 2016-06-22 | 上海斐讯数据通信技术有限公司 | Data collector and method for collecting data by utilizing system redundant resources |
| CN109842409B (en) * | 2017-11-27 | 2023-01-13 | 中国航空工业集团公司西安航空计算技术研究所 | Control circuit supporting PROM and processor to configure eFPGA on line |
| CN111045955B (en) * | 2019-12-16 | 2023-09-22 | 瓴盛科技有限公司 | Storage device with dynamic configuration architecture, operation method thereof and electronic equipment |
| CN114328309A (en) * | 2021-12-03 | 2022-04-12 | 南京风兴科技有限公司 | Memory management circuit and memory sharing method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6438638B1 (en) * | 2000-07-06 | 2002-08-20 | Onspec Electronic, Inc. | Flashtoaster for reading several types of flash-memory cards with or without a PC |
| CN1475013A (en) * | 2000-09-18 | 2004-02-11 | 英特尔公司 | Buffer to multiple memory interface |
| US6832281B2 (en) * | 2000-07-06 | 2004-12-14 | Onspec Electronic Inc. | Flashtoaster for reading several types of flash memory cards with or without a PC |
-
2005
- 2005-10-28 CN CNB2005100323070A patent/CN100357870C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6438638B1 (en) * | 2000-07-06 | 2002-08-20 | Onspec Electronic, Inc. | Flashtoaster for reading several types of flash-memory cards with or without a PC |
| US6832281B2 (en) * | 2000-07-06 | 2004-12-14 | Onspec Electronic Inc. | Flashtoaster for reading several types of flash memory cards with or without a PC |
| CN1475013A (en) * | 2000-09-18 | 2004-02-11 | 英特尔公司 | Buffer to multiple memory interface |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1758208A (en) | 2006-04-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100357870C (en) | Method of proceeding access multikind storage on chip select outer unibus | |
| US8195856B2 (en) | I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures | |
| KR100244841B1 (en) | High-speed, multiple-port, interleaved cache with arbitration of multiple access addresses | |
| EP1488323B1 (en) | Memory system with burst length shorter than prefetch length | |
| US20070255882A1 (en) | I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures | |
| EP1422722A1 (en) | Synchronous semiconductor storage device module and its control method, information device | |
| CN101038783B (en) | Semiconductor memory, memory system, and operation method of memory system | |
| CN104981872A (en) | A memory system | |
| US5329489A (en) | DRAM having exclusively enabled column buffer blocks | |
| KR20190022428A (en) | Command arbitration for high-speed memory interfaces | |
| WO2018013159A1 (en) | Memory controller with virtual controller mode | |
| JP3039557B2 (en) | Storage device | |
| JP2023539737A (en) | Memory controller with multiple command subqueues and corresponding arbiters | |
| JP2002109884A (en) | Memory device | |
| CN111916120B (en) | Bandwidth boosted stacked memory | |
| US9275692B2 (en) | Memory, memory controllers, and methods for dynamically switching a data masking/data bus inversion input | |
| US20050182908A1 (en) | Method and apparatus of interleaving memory bank in multi-layer bus system | |
| CN103412848B (en) | A kind of four core processor systems are shared the method for single program storage | |
| KR20100127317A (en) | Integrated circuit with multiported memory supercell and data path switching circuitry | |
| CN100422955C (en) | Semiconductor memory device, controller, and read/write control method thereof | |
| JP2009104682A (en) | Semiconductor memory device and kind development method | |
| US20060248247A1 (en) | Apparatus and method for controlling access to a memory | |
| CN111241007B (en) | Data reading and writing method and device and dynamic random access memory | |
| CN111158753A (en) | Flash controller structure with data prefetching function and implementation method thereof | |
| US7729198B2 (en) | Synchronous memory circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Assignee: Hunan Aerospace Electromechanical Equipment and Special Material Institute Assignor: National University of Defense Technology of People's Liberation Army of China Contract fulfillment period: 2009.12.10 to 2015.12.10 Contract record no.: 2009430000272 Denomination of invention: Method of proceeding access multikind storage on chip select outer unibus Granted publication date: 20071226 License type: Exclusive license Record date: 20091230 |
|
| LIC | Patent licence contract for exploitation submitted for record |
Free format text: EXCLUSIVE LICENSE; TIME LIMIT OF IMPLEMENTING CONTACT: 2009.12.10 TO 2015.12.10; CHANGE OF CONTRACT Name of requester: HUNAN AEROSPACE ELECTRICAL AND MECHANICAL EQUIPMEN Effective date: 20091230 |
|
| EC01 | Cancellation of recordation of patent licensing contract |
Assignee: Hunan Aerospace Electromechanical Equipment and Special Material Institute Assignor: National University of Defense Technology of People's Liberation Army of China Contract record no.: 2009430000272 Date of cancellation: 20120117 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20071226 Termination date: 20191028 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |