CH628764A5 - Method of remote synchronisation of a colour television clock generator according to the CCIR PAL standard - Google Patents

Description

The invention relates to a method for external control voltage to readjust a first reference oscillator 4, synchronization of a color television clock generator according to CCIR. In addition, the amplitude standard 5 is used in the PAL standard. CVBS signal contained synchronization signal 6 derived and

If different CVBS signals are to be mixed with one another by separators 7 and 10 in their vertical and horizontal positions, then it is necessary to split the CVBS signal sources in a synchronous manner. To operate by means of the H separator. The synchronization of these image signal sources 10 is obtained with a horizontal pulse 11 obtained from an internal horizontal pulse 14, which is generally taken from a clock generator, from divider 17, and outputs the corresponding synchronization signals. Are compared as a second phase comparison circuit 12. The CVBS signal sources but also semi-professional video recorder control voltage obtained thereby controls one of the two (which due to their large time errors cannot be synchronized due to their large time errors, the second reference oscillating frequency oscillating 65 horizontal frequency 2 fH) or the public lator 13, the clock pulse for the Divider 17 delivers.

TV network used, the clock center itself must be in the divider 17 by frequency division and logical external synchronization. The synchronization of the clock link all for the synchronization of image signal sources

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required impulses generated. The synchronization pulse obtained in this way is compared to a vertical-frequency pulse 23, which is then obtained by integrating pulses by means of a time-of-flight compensation 18, the synchronization signal 6 and pulse shaping via a different multivibrator 30 that is monostable to be synchronized with different image signal sources. By the way leads. the logical link is coincidence only after every four

The different sub-images are possible with this runtime compensation 18 (FIG. 3). This means that the running times of the sync coincidence gates 25, which are dependent on the cable lengths, only compensate for output chronizing and composite signals in the sub-picture 1, 5, 9, etc., and emit such a pulse.

that all synchronization signals for image signal sources with short- Since the divider 17 with the pulse count at time t2

Ren cable lengths according to the term for the largest of the sub-picture 2, it must also be set with a pulse

Cable length can be delayed. All FBAS signals of the synchro- "> are, which corresponds to this field. With the output-imized image signal sources, therefore, compared to the sync of the coincidence gate 25, the time difference at the time ti of the partial bilizing FBAS signal shows that the 1 is generated, a flip-flop 26 is therefore clocked, which, by delaying the synchronizing composite signal, then releases a 1: 155 divider 28. After 155 pulses, hal must be equalized in order to ensure a perfect mixture of all composite signals Horizontal frequency, this divider 28 signals to ensure at time t 2. Is an output pulse that the pulse generator 29

The circuit outlay for delaying a video signal reset pulse 15 with a quarter of the vertical frequency nals is not insignificant, however, and can only be output via. The 1: 155 divider 28 is blocked via the flip-flop 26, and broadband delay lines are speaking. In order to prevent interference in the synchronizing from circumventing this, a runtime compensation 19 is inserted into the supply line FBAS signal, e.g. Drop-outs in video recorders, leading to a fal-des internal horizontal im taken from the divider 17-20 selection of the reset pulse 15, the puises 14 is inserted to the second phase comparison circuit 12. Coincidence gate 25 with a taken from the divider 17-This can be blocked with the aid of integrated circuits on simple NEN vertical pulse 16. A reset pulse 15 will

Way. thus only generated when the vertical pulses of the synchronous

With a correspondingly delayed pulse, the nascent CVBS signal and the divider 17 do not phase-that the clock frequency 2 fH and thus all output signals 25 are the same.

of the divider 17 compared to the horizontal pulse 11 or FIG. 4 finally shows a circuit arrangement for compared to the synchronizing CVBS signal by a one-time compensation, in which the internal horizontal pulse 14 leads by a settable value. a capacitor 31 or an inverter 39 and a capacitor

In order to ensure the correct field assignment and the correct PAL capacitor 32 differentiated and supplied to an AND gate 33 switching phase, the divider 17 is supplied with a 30. With the target reset pulse 15 present at the output of the AND gate 33, which is triggered in a reset pulse pulse 34, a monostable multivibrator 35 is triggered. Circuit 9 is won. An embodiment of such an output pulse 36 clocks a flip-flop 38, which can be set with the reset pulse circuit 9 in accordance with FIG. 2 with an integrally negative flank of the input signal, so that it is constructed on integrated circuits. a correspondingly delayed output Q of this flip-flop 38

To select the reset pulse 15, 35 device signal is first removable. By adjusting a time-related division of the frequency of the horizontal pulse 11 with a 1: 2 divider 21 to the monostable multivibrator 35, the 1: 2 divider 21 due to the resistance 37 coming from the burst 40 being the achievable delay changed-led PAL switching voltage 3 is set. The exit imbar. The temporal assignment of the individual pulses is shown in pulse with half the horizontal frequency using a FIG. 5.

Pulse shaper 22 fed to a coincidence gate 25 and with 40

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3 sheets of drawings

Claims (5)

628764 2 PATENT CLAIMS central office in this case takes place through the public long-distance 1. Method for external synchronization of a color television network or the video recorder, while the image signal source clock according to the CCIR-PAL standard, characterized thereby, are synchronized via the clock center. net that-an FBAS signal of a color television camera, the remote- In known arrangements for black and white television Veryundfunks or a video recorder for synchronization s systems, the incoming synchronization signal is used for this purpose, such that an internally derived, horizontally-frequency pulse sequence in tal (11) and vertical (8) and burst (40) separated from such a composite signal Horizon The phase discriminator is compared and the control voltage is compared so that burst (40) and horizontal pulses (11) use reference oscillators (4,12) for comparing the internal clock frequency oscillator (2, 12) reference oscillators (4, 13). This results in a phase equality of the horizontalfre-controls, which reaches the ink carrier (F) and the double horizontalfre-10 quent impulses. For vertical synchronization quenz (2 fH) or via a frequency divider (17) horizontal - either generate a phase comparison of the vertical-frequency pulses and vertical pulses and that the frequency divider (17) is set with a corresponding influence on the clock frequency by a specially obtained reset pulse (15) leads or the vertical counter is set by one of the synchronisers, which sets the information for the correct field assignment such as the vertical signal pulse. also included for PAL switching phase. 15 However, these processes are not 2. The method according to claim 1, characterized in that television systems can be transmitted, since here the correct phase-that for the selection of the special reset pulse (15) would be given for color carriers and PAL switching voltage, must first be derived from the synchronizing CVBS signal. teten horizontal pulses (11) with a 1: 2 divider (21) The object of the invention is a simple, that this 1: 2 divider (21) by a burst of 20 methods for synchronizing a PAL color television clock - (40) derived switching voltage is set, that the output is to be created, in which the correct timing for this 1: 2 divider (21) via a horizontal and vertical frequency working as a pulse shaper as well as for color carriers and monostable multivibrator (22 ) is guaranteed with an input of a Koin-PAL switching phase. zidenzgatters (25) is connected, the second input is a. This object is achieved according to the invention by vertical frequency pulse (23), which by integer 25 specified in the characterizing part of claim 1 gration of the measures taken from the synchronizing CVBS signal . separated synchronization signal (6) after pulse formation via advantageous developments of the inventive Ver a monostable multivibrator (30) is obtained that the driving result from the dependent claims. Output of this coincidence gate (25) to the clock input The particular advantage of the subject matter of a flip-flop (26), which has a 155 counter 30 over the prior art, is that (28) sets the clock input of this Counter is connected to the output by suitable formation of the horizontal phase comparison of the 1: 2 divider (21) mentioned and that the and the circuit arrangement for obtaining the reset output of the 155 counter (28) with the reset input (R) des puises the color television clock center synonymous of semipro flip-flops (26) and the clock input of a pulse shaper (29) professional video recorders who are properly synchronized (Fig. 2). 35 den, which is usually due to timing errors and drop 3. The method according to claim 2, characterized, outs only leads to unsatisfactory results. Another advantage of the subject matter of the invention is the short synthetic-frequency blocking pulse (16) that is fed to a third input of the coincidence gate (25). chronization time. 4. The method according to claim 1, characterized in that the invention is explained in more detail below with the aid of the drawing fi that for the runtime compensation of the synchronizing FBAS 40 guren. Show it: 1 is a block diagram of a circuit arrangement for the internally generated horizontal pulses (14) in accordance with the implementation of the method according to the invention, be hesitated. Fig. 2 shows an embodiment of a circuit arrangement 5. The method according to claim 4, characterized for obtaining a special reset pulse, that from the leading and trailing edge of the pulses 45 to be delayed, FIG. 3 pulse diagrams for explaining the circuitry are generated by differentiation, needle pulses which have an order according to FIG. 2, monostable multivibrator (35) trigger that its output Fig. 4 an embodiment of a circuit arrangement is connected to the clock input of a flip-flop (38) and to balance the runtime of the central synchronizing that this flip-flop (38) with the negative edge of the VER FBAS signal and hesitating pulses is set (Fig. 4). 50 Fig. 5 pulse diagrams for the circuit arrangement according to Fig. 4. 1 ..: H 3ns an FBAS signal via a burst sampling 1, the burst separated from the FBAS signal 55 and fed to a first phase comparison circuit 2, the