CA2583708C - Stable driving scheme for active matrix displays - Google Patents
Stable driving scheme for active matrix displays Download PDFInfo
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- CA2583708C CA2583708C CA2583708A CA2583708A CA2583708C CA 2583708 C CA2583708 C CA 2583708C CA 2583708 A CA2583708 A CA 2583708A CA 2583708 A CA2583708 A CA 2583708A CA 2583708 C CA2583708 C CA 2583708C
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
- G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
- G09G2300/0866—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes by means of changes in the pixel supply voltage
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/04—Maintaining the quality of display appearance
- G09G2320/043—Preventing or counteracting the effects of ageing
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- Engineering & Computer Science (AREA)
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- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
A method and system for operating a pixel array having at least one pixel circuit is provided.
The method includes repeating an operation cycle defining a frame period for a pixel circuit, including at each frame period, programming the pixel circuit, driving the pixel circuit, and relaxing a stress effect on the pixel circuit, prior to a next frame period.
The system includes a pixel array including a plurality of pixel circuits and a plurality of lines for operation of the plurality of pixel circuits. Each of the pixel circuits includes a light emitting device, a storage capacitor, and a drive circuit connected to the light emitting device and the storage capacitor.
The system includes a drive for operating the plurality of lines to repeat an operation cycle having a frame period so that each of the operation cycles comprises a programming cycle, a driving cycle and a relaxing cycle for relaxing a stress on a pixel circuit, prior to a next frame period.
The method includes repeating an operation cycle defining a frame period for a pixel circuit, including at each frame period, programming the pixel circuit, driving the pixel circuit, and relaxing a stress effect on the pixel circuit, prior to a next frame period.
The system includes a pixel array including a plurality of pixel circuits and a plurality of lines for operation of the plurality of pixel circuits. Each of the pixel circuits includes a light emitting device, a storage capacitor, and a drive circuit connected to the light emitting device and the storage capacitor.
The system includes a drive for operating the plurality of lines to repeat an operation cycle having a frame period so that each of the operation cycles comprises a programming cycle, a driving cycle and a relaxing cycle for relaxing a stress on a pixel circuit, prior to a next frame period.
Description
STABLE DRIVING SCHEME For ACTIVE MATRIX DISPLAYS
FIELD OF INVENTION
[0001 ] The present invention relates to light emitting device displays, and more specifically to a method and system for driving a pixel circuit.
BACKGROUND OF THE INVENTION
FIELD OF INVENTION
[0001 ] The present invention relates to light emitting device displays, and more specifically to a method and system for driving a pixel circuit.
BACKGROUND OF THE INVENTION
[0002] Electro-luminance displays have been developed for a wide variety of devices, such as cell phones. In particular, active-matrix organic light emitting diode (AMOLED) displays with amorphous silicon (a-Si), poly-silicon, organic, or other driving backplane have become more attractive due to advantages, such as feasible flexible displays, its low cost fabrication, high resolution, and a wide viewing angle.
[0003] An AMOLED display includes an array of rows and columns of pixels, each having an organic light emitting diode (OLED) and backplane electronics arranged in the array of rows and columns. Since the OLED is a current driven device, the pixel circuit of the AMOLED
should be capable of providing an accurate and constant drive current.
should be capable of providing an accurate and constant drive current.
[0004] However, the AMOLED displays exhibit non-uniformities in luminance on a pixel-to-pixel basis, as a result of pixel degradation, i.e., aging caused by operational use over time (e.g., threshold shift, OLED aging). Depending on the usage of the display, different pixels may have different amounts of the degradation. There may be an ever-increasing error between the required brightness of some pixels as specified by luminance data and the actual brightness of the pixels. The result is that the desired image will not show properly on the display.
[0005] Therefore, there is a need to provide a method and system that is capable of suppressing the aging of the pixel circuit.
SUMMARY OF THE INVENTION
SUMMARY OF THE INVENTION
[0006] It is an object of the invention to provide a method and system that obviates or mitigates at least one of the disadvantages of existing systems.
-I-[0007] In accordance with an aspect of the present invention there is provided a method of operating a pixel array having at least one pixel circuit. The method includes the steps of:
repeating an operation cycle defining a frame period for a pixel circuit, including at each frame period, programming the pixel circuit, driving the pixel circuit; and relaxing a stress effect on the pixel circuit, prior to a next frame period.
-I-[0007] In accordance with an aspect of the present invention there is provided a method of operating a pixel array having at least one pixel circuit. The method includes the steps of:
repeating an operation cycle defining a frame period for a pixel circuit, including at each frame period, programming the pixel circuit, driving the pixel circuit; and relaxing a stress effect on the pixel circuit, prior to a next frame period.
[0008] In accordance with another aspect of the present invention there is provided a display system. The display system includes a pixel array including a plurality of pixel circuits and a plurality of lines for operation of the plurality of pixel circuits. Each of the pixel circuits includes a light emitting device, a storage capacitor, and a drive circuit connected to the light emitting device and the storage capacitor. The display system includes a drive for operating the plurality of lines to repeat an operation cycle having a frame period so that each of the operation cycle comprises a programming cycle, a driving cycle and a relaxing cycle for relaxing a stress on a pixel circuit, prior to a next frame period.
[0009] This summary of the invention does not necessarily describe all features of the invention.
BRIEF DESCRIPTION OF THE DRAWINGS
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] These and other features of the invention will become more apparent from the following description in which reference is made to the appended drawings wherein:
FIGURE 1 is a timing chart for suppressing aging of a pixel circuit, in accordance with an embodiment of the present invention FIGURE 2 is a diagram illustrating an example of a pixel circuit to which the timing schedule of Figure 1 is suitably applied;
FIGURE 3 is an exemplary timing chart for a compensating driving scheme in accordance with an embodiment of the present invention;
FIGURE 4 is a diagram illustrating an example of a display system for implementing the timing schedule of Figure 1 and the compensating driving scheme of Figure 3;
FIGURE 5 is a graph illustrating measurement results for a conventional driving scheme and the compensating driving scheme of Figure 3;
FIGURE 6 is a timing chart illustrating an example of frames based on the timing schedule of Figure 1 and the compensating driving scheme of Figure 3;
FIGURE 7 is a graph illustrating the measurement result of threshold voltage shift based on the compensating driving scheme of Figure 6;
FIGURE 8 is a graph illustrating the measurement result of OLED current based on the compensating driving scheme of Figure 6;
FIGURE 9 is a diagram illustrating an example of a driving scheme applied to a pixel array, in accordance with an embodiment of the present invention;
FIGURE 10(a) is a diagram illustrating an example of array structure having top emission pixels applicable to the display system of Figure 4; and FIGURE 10(b) is a diagram illustrating an example of array structure having bottom emission pixels applicable to the display system of Figure 4.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0011 ] Embodiments of the present invention are described using a pixel circuit having an organic light emitting diode (OLED) and a plurality of thin film transistors (TFTs). The pixel circuit may contain a light emitting device other than the OLED. The transistors in the pixel circuit may be n-type transistors, p-type transistors or combinations thereof.
The transistors in the pixel circuit may be fabricated using amorphous silicon, nano/micro crystalline silicon, poly silicon, organic semiconductors technologies (e.g., organic TFT), NMOS/PMOS
technology, CMOS technology (e.g., MOSFET) or combinations thereof. A display having the pixel circuit may be a single color, multi-color or a fully color display, and may include one or more than one electroluminescence (EL) element (e.g., organic EL). The display may be an active matrix light emitting display (e.g., AMOLED). The display may be used in DVDs, personal digital assistants (PDAs), computer displays, or cellular phones. The display may be a flat panel.
[0012] In the description below, "pixel circuit" and "pixel" are used interchangeably. In the description below, "signal" and "line" may be used interchangeably. In the description below, the terms "line" and "node" may be used interchangeably. In the description below, the terms "select line" and "address line" may be used interchangeably. In the description below, "connect (or connected)"and "couple (or coupled)" may be used interchangeably, and may be used to indicate that two or more elements are directly or indirectly in physical or electrical contact with each other.
[0013] Figure 1 illustrates a timing schedule for suppressing aging for a pixel circuit, in accordance with an embodiment of the present invention. The pixel circuit, which is operated using the timing schedule of Figure 1, includes a plurality of transistors and an OLED (e.g., 22, 24, 26 of Figure 2). In Figure 1, a frame 10 is divided into three phases:
a programming cycle 12, a driving (i.e., emitting) cycle 14, and a relaxing cycle 16. The frame 10 is a time interval or period in which a display shows a frame of a video signal. During the programming cycle 12, a pixel circuit is programmed with required data to provide the wanted brightness. During the driving cycle 14, the OLED of the pixel circuit emits required brightness based on the programming data. Finally, during the relaxing cycle 16, the pixel circuit is OFF or biased with reverse polarity of the driving cycle 14.
Consequently, the aging effect caused by the driving cycle 14 is annealed. This prevents aging accumulation effect from one frame to the other frame, and so the pixel life time increases significantly.
[0014] To obtain the wanted average brightness, the pixel circuit is programmed for a higher brightness since it is OFF for a fraction of frame time (i.e., relaxing cycle 16). The programming brightness based on wanted one is given by:
rf Lcp rt -- re , ... (1) where "Lcp" is a compensating luminance, "LN" is a normal luminance, "TR" is a relaxation time (16 of Figure 1), and "TF" is a frame time (10 of Figure 1).
[0015] As described below, letting the pixel circuit relax for a fraction of each frame can control the aging of the pixel, which includes the aging of driving devices (i.e., TFTs 24 and 26 of Figure 2), the OLED (e.g., 22 of Figure 1), or combinations thereof.
[0016] Figure 2 illustrates an example of a pixel circuit to which the timing schedule of Figure 1 is applicable. The pixel circuit 20 of Figure 2 is a 2-TFT pixel circuit. The pixel circuit 20 includes an OLED 22, a drive TFT 24, a switch TFT 26, and a storage capacitor 28.
Each of the TFTs 24 and 26 have a source terminal, a drain terminal and a gate terminal. In Figure 2, CLD represents OLED capacitance. The TFTs 24 and 26 are n-type TFTs.
However, it would be appreciated by one of ordinary skill in the art that the driving schemed of Figure 1 is applicable to a complementary pixel circuit having p-type transistors or the combination of n-type and p-type transistors.
[0017] One terminal of the drive TFT 24 is connected to a power supply line VDD, and the other terminal of the drive TFT 24 is connected to one terminal of the OLED 22 (node B 1).
One terminal of the switch TFT 26 is connected to a data line VDATA, and the other terminal of the switch TFT 26 is connected to the gate terminal of the drive TFT 24 (node Al). The gate terminal of the switch TFT 26 is connected to a select line SEL. One terminal of the storage capacitor 28 is connected to node Al, and the other terminal of the storage capacitor 28 is connected to node B 1.
[0018] Figure 3 illustrates an exemplary time schedule for a compensating driving scheme in accordance with an embodiment of the present invention, which is applicable to the pixel of Figure 2. In Figure 3, "32" represents "Vcp-Gen cycle", "34" represents "VT-Gen cycle", "36"
represents "programming cycle" and associated with the programming cycle 12 of Figure 1, and "38" represents "driving cycle" and associated with the driving cycle 14 of Figure 1.
[0019] The waveforms of Figure 3 are used, for example, in the cycles 12 and 14 of Figure 1.
During the Vcp-Gen cycle 32, a voltage is developed across the gate-source voltage of a drive TFT (e.g., 24 of Figure 2). During the VT-Gen cycle 34, voltage at node Bl becomes -VT of the drive TFT (e.g., 24 of Figure 2) where VT is the threshold voltage of the drive TFT (e.g., 24 of Figure 2). During the programming cycle 36, node Al is charged to Vp which is related to Lcp of (1).
[0020] Referring to Figures 2 and 3, during the first operating cycle 32 ("Vcp-Gen"), VDD
changes to a negative voltage (-VCPB) while VDATA has a positive voltage (VcpA). Thus, node Al is charged to VCPA, and node Bi is discharged to -VcpB. VCPA is smaller than VTO+VOLEDO, where the VTO is the threshold voltage of the unstressed drive TFT
24 and the VOLEDO is the ON voltage of the unstressed OLED 22 .
[0021] During the second operating cycle 34 ("VT-Gen"), VDD changes to Vdd2 that is a voltage during the driving cycle 38. As a result, node B1 is charged to the point at which the drive TFT 24 turns off. At this point, the voltage at node B 1 is (VCPA-VT) where VT is the threshold of the drive TFT 24, and the voltage stored in the storage capacitor 28 is the VT of the drive TFT 24.
[0022] During the third operating cycle 36 ("programming cycle"), VDATA
changes to a programming voltage, VCPA+VP. VDD goes to Vddl which is a positive voltage.
Assuming that the OLED capacitance (CLD) is large, the voltage at node B1 remains at VCPA-VT.
Therefore, the gate-source voltage of the drive TFT 24 ideally becomes Vp+VT.
Consequently, the pixel current becomes independent of (AVT +AVOLED) where AVT
is a shift of the threshold voltage of the drive TFT 24 and AVOLED is a shift of the ON
voltage of the OLED 22.
[0023] Figure 4 illustrates an example of a display system for implementing the timing schedule of Figure 1 and the compensating driving scheme of Figure 3. The display system 1000 includes a pixel array 1002 having a plurality of pixels 1004. The pixel corresponds to the pixel 20 of Figure 2. However, the pixel 1004 may have structure different from that of the pixel 20. The pixels 1004 are arranged in row and column. In Figure 4, the pixels 1004 are arranged in two rows and two columns. The number of the pixels 1004 may vary in dependence upon the system design, and does not limited to four. The pixel array 1002 is an active matrix light emitting display, and may form an AMOLED
display.
[0024] "SEL[i]" is an address line for the ith row (i= ... k, k+1...) and corresponds to SEL of Figure 2. "VDD[i]" is a power supply line for the ith row (i= ... k, k+l...) and corresponds to VDD of Figure 2. "VDATA[j]" is a data line for the jth row (i= ... 1, 1+1...) and corresponds to VDATA of Figure 2.
[0025] A gate driver 1006 drives SEL[i] and VDD[i]. The gate driver 1006 includes an address driver for providing address signals to SEL[i]. A data driver 1008 generates a programming data and drives VDATA(j]. The controller 1010 controls the drivers 1006 and 1008 to drive the pixels 1004 based on the timing schedule of Figure 1 and the compensating driving scheme of Figure 3.
[0026] Figure 5 illustrates lifetime results for a conventional driving scheme and the compensating driving scheme. Pixel circuits of Figure 2 are programmed for 2 A at a frame rate of -60 IHIz by using the conventional driving scheme (40) and the compensating driving scheme (42). The compensating driving scheme (42) is highly stable, reducing the total aging error to less than 10%. By contrast, in the conventional driving scheme (40), while the pixel current becomes half of its initial value after about 360 hours, the aging effects result in a 50% error in the pixel current over the measurement period. The total shift in the OLED
voltage and threshold voltage of the drive TFT (i.e., 24 of Figure 2), L.(VOLED+ VT), is -4 V.
[0027] Figure 6 illustrates an example of frames using the timing schedule of Figure 1 and the compensating driving scheme of Figure 3.
[0028] In Figure 6, "i" represents the ith row in a pixel array, "k"
represents the kth row in the pixel array, "m" represents the mth column in the pixel array, and "1"
represents the I th column in the pixel array. The waveforms of Figure 6 are applicable to the display system 1000 of Figure 4 to operate the pixel array 1002 of Figure 4. It is assumed that the pixel array includes more than one pixel circuit 20 of Figure 2.
[0029] In Figure 6, "50" represents a frame for the ith row and corresponds to "10" of Figure 1, "52" represents "Vcp-Gen cycle" and corresponds to "32" of Figure 3, "54"
represents "VT-Gen cycle" and corresponds to "34" of Figure 3, and "56" represents "programming cycle"
and corresponds to "36" of Figure 3. In Figure 6, "58" represents "driving cycle" and corresponds to "38" of Figure 3. In Figure 6, "66" represents the values of the corresponding VDATA lines during the operating cycle 56.
[0030] In Figure 6, "60" represents a relaxing cycle for the ith row and corresponds to "16" of Figure 1. The relaxing cycle 60 includes a first operating cycle "62" and a second operating cycle "64". During the relaxing cycle 60 for the ith row, SEL[i] is high at the first operating cycle 62 and then is low at the second operating cycle 64. During the frame cycle 62, node Al of each pixel at the ith row is charged to a certain voltage, such as, zero.
Thus, the pixels are OFF during the frame cycle 64. "Vcp-Gen cycle" 52 for the kth row occurs at the same timing of the first operating cycle 62 for the ith row.
[0031 ] During the first operating cycle 52 for the kth row, which is the same as the first operating cycle 62 for the ith row, SEL[i] is high, and so the storage capacitors of the pixel circuits at the ith row are charged to VCPA. VDATA lines have VCPA.
Considering that VCPA
is smaller than VOLEDO+VTO, the pixel circuits at the ith row are OFF at the second operating cycle 64 and also the corresponding drive TFTs (24 of Figure 2) are negatively biased resulting in partial annealing of the VT-shift at the cycle 64.
[0032] Figures 7 and 9 illustrate results of a longer lifetime test for a pixel circuit employing the timing cycles of Figure 6. To obtain data of Figures 7 and 8, a pixel array having more than one pixel 20 of Figure 2 was used.
[0033] In Figure 7, "80" represents the measurement result of the shift in the threshold voltage of the drive transistor (i.e., 24 of Figure 2). The result signifies that the above method results in a highly stable pixel current even after 90 days of operation.
Here, the pixel of Figure 2 is programmed for 2.5 to to compensate for the luminance lost during the relaxing cycle. The A (Vc,LFD+ VT) is extracted once after a long tinning interval (few days) to not disturb pixel operation. It is clear that the OLED current is significantly stable after 1500 hours of operation which is the results of suppression in the aging of the drive TFT (i.e., 24 of Figure 2) as shown in Figure 7.
[0034] In Figure 8, "90" represents the measurement result of OLED current of the pixel (i.e., 20 of Figure 2) over time. The result depicted in Figure 8 confirms that the enhanced timing diagram suppresses aging significantly, resulting in longer lifetime. Here, A(VOLED+ VT) is 1.8 V after a 90 days of operation, whereas it is 3.6 V for the compensating driving scheme without the relaxing cycle after a shorter time.
[0035] Figure 9 is a diagram illustrating an example of the driving scheme applied to a pixel array, in accordance with an embodiment of the present invention. In Figure 9, each of ROW
(i), ROW(k) and ROW (n) represents a row of the pixel array. The pixel array may be the pixel array 1002 of Figure 4. The frame 100 of Figure 9 includes a programming cycle 102, a driving cycle 104, and a relaxing cycle 106, and has a frame time "zF". The programming cycle 102, the driving cycle 104, and the relaxing cycle 106 may correspond to the operation cycles 12, 14, and 16 of Figure 1, respectively. The programming cycle 102 may include the operating cycles 32, 34 and 36 of Figure 3. The relaxing cycle 106 may be similar to the relaxing cycle 60 of Figure 6.
[0036] The programming cycle 102 for the kth row occurs at the same timing of the relaxing cycle 106 for the ith row. The programming cycle 102 for the nth row occurs at the same timing of the relaxing cycle 106 for the kth row.
[0037] Figure 10(a) illustrates an example of array structure having top emission pixels.
Figure 10(b) illustrates an example of array structure having bottom emission pixels. The pixel array of Figure 4 may have the array structure of Figure 10(a) or 10(b).
In Figure 10(a), 200 represents a substrate, 202 represents a pixel contact, 203 represents a (top emission) pixel circuit, and 204 represents a transparent top electrode on the OLEDs. In Figure 10(b), 210 represents a transparent substrate, 211 represents a (bottom emission) pixel circuit, and 212 represents a top electrode. All of the pixel circuits including the TFTs, the storage capacitor, the SEL, VDATA, and VDD lines are fabricated together. After that, the OLEDs are fabricated for all pixel circuits. The OLED is connected to the corresponding driving transistor using a via (e.g., BI of Figure 2) as shown in Figures 10(a) and 10(b). The panel is finished by deposition of the top electrode on the OLEDs which can be a continuous layer, reducing the complexity of the design and can be used to turn the entire display ON/OFF or control the brightness.
[0038] In the above description, the pixel circuit 20 of Figure 2 is used as an example of a pixel circuit for implementing the timing schedule of Figure 1, the compensating driving schedule of Figure 3, and the timing schedule of Figure 6. However, it is appreciated that the above timing schedules of Figures 1, 3 and 6 are applicable to pixel circuits other than that of Figure 2, despite its configuration and type.
[0039] Examples of the driving scheme, compensating and driving scheme, and pixel/pixel arrays are described in G.R. Chaji and A. Nathan, "Stable voltage-programmed pixel circuit for AMOLED displays," IEEE J. of Display Technology, vol. 2, no. 4, pp. 347-358, Dec.
2006, [0040] One or more currently preferred embodiments have been described by way of example.
It will be apparent to persons skilled in the art that a number of variations and modifications can be made without departing from the scope of the invention as defined in the claims.
FIGURE 1 is a timing chart for suppressing aging of a pixel circuit, in accordance with an embodiment of the present invention FIGURE 2 is a diagram illustrating an example of a pixel circuit to which the timing schedule of Figure 1 is suitably applied;
FIGURE 3 is an exemplary timing chart for a compensating driving scheme in accordance with an embodiment of the present invention;
FIGURE 4 is a diagram illustrating an example of a display system for implementing the timing schedule of Figure 1 and the compensating driving scheme of Figure 3;
FIGURE 5 is a graph illustrating measurement results for a conventional driving scheme and the compensating driving scheme of Figure 3;
FIGURE 6 is a timing chart illustrating an example of frames based on the timing schedule of Figure 1 and the compensating driving scheme of Figure 3;
FIGURE 7 is a graph illustrating the measurement result of threshold voltage shift based on the compensating driving scheme of Figure 6;
FIGURE 8 is a graph illustrating the measurement result of OLED current based on the compensating driving scheme of Figure 6;
FIGURE 9 is a diagram illustrating an example of a driving scheme applied to a pixel array, in accordance with an embodiment of the present invention;
FIGURE 10(a) is a diagram illustrating an example of array structure having top emission pixels applicable to the display system of Figure 4; and FIGURE 10(b) is a diagram illustrating an example of array structure having bottom emission pixels applicable to the display system of Figure 4.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0011 ] Embodiments of the present invention are described using a pixel circuit having an organic light emitting diode (OLED) and a plurality of thin film transistors (TFTs). The pixel circuit may contain a light emitting device other than the OLED. The transistors in the pixel circuit may be n-type transistors, p-type transistors or combinations thereof.
The transistors in the pixel circuit may be fabricated using amorphous silicon, nano/micro crystalline silicon, poly silicon, organic semiconductors technologies (e.g., organic TFT), NMOS/PMOS
technology, CMOS technology (e.g., MOSFET) or combinations thereof. A display having the pixel circuit may be a single color, multi-color or a fully color display, and may include one or more than one electroluminescence (EL) element (e.g., organic EL). The display may be an active matrix light emitting display (e.g., AMOLED). The display may be used in DVDs, personal digital assistants (PDAs), computer displays, or cellular phones. The display may be a flat panel.
[0012] In the description below, "pixel circuit" and "pixel" are used interchangeably. In the description below, "signal" and "line" may be used interchangeably. In the description below, the terms "line" and "node" may be used interchangeably. In the description below, the terms "select line" and "address line" may be used interchangeably. In the description below, "connect (or connected)"and "couple (or coupled)" may be used interchangeably, and may be used to indicate that two or more elements are directly or indirectly in physical or electrical contact with each other.
[0013] Figure 1 illustrates a timing schedule for suppressing aging for a pixel circuit, in accordance with an embodiment of the present invention. The pixel circuit, which is operated using the timing schedule of Figure 1, includes a plurality of transistors and an OLED (e.g., 22, 24, 26 of Figure 2). In Figure 1, a frame 10 is divided into three phases:
a programming cycle 12, a driving (i.e., emitting) cycle 14, and a relaxing cycle 16. The frame 10 is a time interval or period in which a display shows a frame of a video signal. During the programming cycle 12, a pixel circuit is programmed with required data to provide the wanted brightness. During the driving cycle 14, the OLED of the pixel circuit emits required brightness based on the programming data. Finally, during the relaxing cycle 16, the pixel circuit is OFF or biased with reverse polarity of the driving cycle 14.
Consequently, the aging effect caused by the driving cycle 14 is annealed. This prevents aging accumulation effect from one frame to the other frame, and so the pixel life time increases significantly.
[0014] To obtain the wanted average brightness, the pixel circuit is programmed for a higher brightness since it is OFF for a fraction of frame time (i.e., relaxing cycle 16). The programming brightness based on wanted one is given by:
rf Lcp rt -- re , ... (1) where "Lcp" is a compensating luminance, "LN" is a normal luminance, "TR" is a relaxation time (16 of Figure 1), and "TF" is a frame time (10 of Figure 1).
[0015] As described below, letting the pixel circuit relax for a fraction of each frame can control the aging of the pixel, which includes the aging of driving devices (i.e., TFTs 24 and 26 of Figure 2), the OLED (e.g., 22 of Figure 1), or combinations thereof.
[0016] Figure 2 illustrates an example of a pixel circuit to which the timing schedule of Figure 1 is applicable. The pixel circuit 20 of Figure 2 is a 2-TFT pixel circuit. The pixel circuit 20 includes an OLED 22, a drive TFT 24, a switch TFT 26, and a storage capacitor 28.
Each of the TFTs 24 and 26 have a source terminal, a drain terminal and a gate terminal. In Figure 2, CLD represents OLED capacitance. The TFTs 24 and 26 are n-type TFTs.
However, it would be appreciated by one of ordinary skill in the art that the driving schemed of Figure 1 is applicable to a complementary pixel circuit having p-type transistors or the combination of n-type and p-type transistors.
[0017] One terminal of the drive TFT 24 is connected to a power supply line VDD, and the other terminal of the drive TFT 24 is connected to one terminal of the OLED 22 (node B 1).
One terminal of the switch TFT 26 is connected to a data line VDATA, and the other terminal of the switch TFT 26 is connected to the gate terminal of the drive TFT 24 (node Al). The gate terminal of the switch TFT 26 is connected to a select line SEL. One terminal of the storage capacitor 28 is connected to node Al, and the other terminal of the storage capacitor 28 is connected to node B 1.
[0018] Figure 3 illustrates an exemplary time schedule for a compensating driving scheme in accordance with an embodiment of the present invention, which is applicable to the pixel of Figure 2. In Figure 3, "32" represents "Vcp-Gen cycle", "34" represents "VT-Gen cycle", "36"
represents "programming cycle" and associated with the programming cycle 12 of Figure 1, and "38" represents "driving cycle" and associated with the driving cycle 14 of Figure 1.
[0019] The waveforms of Figure 3 are used, for example, in the cycles 12 and 14 of Figure 1.
During the Vcp-Gen cycle 32, a voltage is developed across the gate-source voltage of a drive TFT (e.g., 24 of Figure 2). During the VT-Gen cycle 34, voltage at node Bl becomes -VT of the drive TFT (e.g., 24 of Figure 2) where VT is the threshold voltage of the drive TFT (e.g., 24 of Figure 2). During the programming cycle 36, node Al is charged to Vp which is related to Lcp of (1).
[0020] Referring to Figures 2 and 3, during the first operating cycle 32 ("Vcp-Gen"), VDD
changes to a negative voltage (-VCPB) while VDATA has a positive voltage (VcpA). Thus, node Al is charged to VCPA, and node Bi is discharged to -VcpB. VCPA is smaller than VTO+VOLEDO, where the VTO is the threshold voltage of the unstressed drive TFT
24 and the VOLEDO is the ON voltage of the unstressed OLED 22 .
[0021] During the second operating cycle 34 ("VT-Gen"), VDD changes to Vdd2 that is a voltage during the driving cycle 38. As a result, node B1 is charged to the point at which the drive TFT 24 turns off. At this point, the voltage at node B 1 is (VCPA-VT) where VT is the threshold of the drive TFT 24, and the voltage stored in the storage capacitor 28 is the VT of the drive TFT 24.
[0022] During the third operating cycle 36 ("programming cycle"), VDATA
changes to a programming voltage, VCPA+VP. VDD goes to Vddl which is a positive voltage.
Assuming that the OLED capacitance (CLD) is large, the voltage at node B1 remains at VCPA-VT.
Therefore, the gate-source voltage of the drive TFT 24 ideally becomes Vp+VT.
Consequently, the pixel current becomes independent of (AVT +AVOLED) where AVT
is a shift of the threshold voltage of the drive TFT 24 and AVOLED is a shift of the ON
voltage of the OLED 22.
[0023] Figure 4 illustrates an example of a display system for implementing the timing schedule of Figure 1 and the compensating driving scheme of Figure 3. The display system 1000 includes a pixel array 1002 having a plurality of pixels 1004. The pixel corresponds to the pixel 20 of Figure 2. However, the pixel 1004 may have structure different from that of the pixel 20. The pixels 1004 are arranged in row and column. In Figure 4, the pixels 1004 are arranged in two rows and two columns. The number of the pixels 1004 may vary in dependence upon the system design, and does not limited to four. The pixel array 1002 is an active matrix light emitting display, and may form an AMOLED
display.
[0024] "SEL[i]" is an address line for the ith row (i= ... k, k+1...) and corresponds to SEL of Figure 2. "VDD[i]" is a power supply line for the ith row (i= ... k, k+l...) and corresponds to VDD of Figure 2. "VDATA[j]" is a data line for the jth row (i= ... 1, 1+1...) and corresponds to VDATA of Figure 2.
[0025] A gate driver 1006 drives SEL[i] and VDD[i]. The gate driver 1006 includes an address driver for providing address signals to SEL[i]. A data driver 1008 generates a programming data and drives VDATA(j]. The controller 1010 controls the drivers 1006 and 1008 to drive the pixels 1004 based on the timing schedule of Figure 1 and the compensating driving scheme of Figure 3.
[0026] Figure 5 illustrates lifetime results for a conventional driving scheme and the compensating driving scheme. Pixel circuits of Figure 2 are programmed for 2 A at a frame rate of -60 IHIz by using the conventional driving scheme (40) and the compensating driving scheme (42). The compensating driving scheme (42) is highly stable, reducing the total aging error to less than 10%. By contrast, in the conventional driving scheme (40), while the pixel current becomes half of its initial value after about 360 hours, the aging effects result in a 50% error in the pixel current over the measurement period. The total shift in the OLED
voltage and threshold voltage of the drive TFT (i.e., 24 of Figure 2), L.(VOLED+ VT), is -4 V.
[0027] Figure 6 illustrates an example of frames using the timing schedule of Figure 1 and the compensating driving scheme of Figure 3.
[0028] In Figure 6, "i" represents the ith row in a pixel array, "k"
represents the kth row in the pixel array, "m" represents the mth column in the pixel array, and "1"
represents the I th column in the pixel array. The waveforms of Figure 6 are applicable to the display system 1000 of Figure 4 to operate the pixel array 1002 of Figure 4. It is assumed that the pixel array includes more than one pixel circuit 20 of Figure 2.
[0029] In Figure 6, "50" represents a frame for the ith row and corresponds to "10" of Figure 1, "52" represents "Vcp-Gen cycle" and corresponds to "32" of Figure 3, "54"
represents "VT-Gen cycle" and corresponds to "34" of Figure 3, and "56" represents "programming cycle"
and corresponds to "36" of Figure 3. In Figure 6, "58" represents "driving cycle" and corresponds to "38" of Figure 3. In Figure 6, "66" represents the values of the corresponding VDATA lines during the operating cycle 56.
[0030] In Figure 6, "60" represents a relaxing cycle for the ith row and corresponds to "16" of Figure 1. The relaxing cycle 60 includes a first operating cycle "62" and a second operating cycle "64". During the relaxing cycle 60 for the ith row, SEL[i] is high at the first operating cycle 62 and then is low at the second operating cycle 64. During the frame cycle 62, node Al of each pixel at the ith row is charged to a certain voltage, such as, zero.
Thus, the pixels are OFF during the frame cycle 64. "Vcp-Gen cycle" 52 for the kth row occurs at the same timing of the first operating cycle 62 for the ith row.
[0031 ] During the first operating cycle 52 for the kth row, which is the same as the first operating cycle 62 for the ith row, SEL[i] is high, and so the storage capacitors of the pixel circuits at the ith row are charged to VCPA. VDATA lines have VCPA.
Considering that VCPA
is smaller than VOLEDO+VTO, the pixel circuits at the ith row are OFF at the second operating cycle 64 and also the corresponding drive TFTs (24 of Figure 2) are negatively biased resulting in partial annealing of the VT-shift at the cycle 64.
[0032] Figures 7 and 9 illustrate results of a longer lifetime test for a pixel circuit employing the timing cycles of Figure 6. To obtain data of Figures 7 and 8, a pixel array having more than one pixel 20 of Figure 2 was used.
[0033] In Figure 7, "80" represents the measurement result of the shift in the threshold voltage of the drive transistor (i.e., 24 of Figure 2). The result signifies that the above method results in a highly stable pixel current even after 90 days of operation.
Here, the pixel of Figure 2 is programmed for 2.5 to to compensate for the luminance lost during the relaxing cycle. The A (Vc,LFD+ VT) is extracted once after a long tinning interval (few days) to not disturb pixel operation. It is clear that the OLED current is significantly stable after 1500 hours of operation which is the results of suppression in the aging of the drive TFT (i.e., 24 of Figure 2) as shown in Figure 7.
[0034] In Figure 8, "90" represents the measurement result of OLED current of the pixel (i.e., 20 of Figure 2) over time. The result depicted in Figure 8 confirms that the enhanced timing diagram suppresses aging significantly, resulting in longer lifetime. Here, A(VOLED+ VT) is 1.8 V after a 90 days of operation, whereas it is 3.6 V for the compensating driving scheme without the relaxing cycle after a shorter time.
[0035] Figure 9 is a diagram illustrating an example of the driving scheme applied to a pixel array, in accordance with an embodiment of the present invention. In Figure 9, each of ROW
(i), ROW(k) and ROW (n) represents a row of the pixel array. The pixel array may be the pixel array 1002 of Figure 4. The frame 100 of Figure 9 includes a programming cycle 102, a driving cycle 104, and a relaxing cycle 106, and has a frame time "zF". The programming cycle 102, the driving cycle 104, and the relaxing cycle 106 may correspond to the operation cycles 12, 14, and 16 of Figure 1, respectively. The programming cycle 102 may include the operating cycles 32, 34 and 36 of Figure 3. The relaxing cycle 106 may be similar to the relaxing cycle 60 of Figure 6.
[0036] The programming cycle 102 for the kth row occurs at the same timing of the relaxing cycle 106 for the ith row. The programming cycle 102 for the nth row occurs at the same timing of the relaxing cycle 106 for the kth row.
[0037] Figure 10(a) illustrates an example of array structure having top emission pixels.
Figure 10(b) illustrates an example of array structure having bottom emission pixels. The pixel array of Figure 4 may have the array structure of Figure 10(a) or 10(b).
In Figure 10(a), 200 represents a substrate, 202 represents a pixel contact, 203 represents a (top emission) pixel circuit, and 204 represents a transparent top electrode on the OLEDs. In Figure 10(b), 210 represents a transparent substrate, 211 represents a (bottom emission) pixel circuit, and 212 represents a top electrode. All of the pixel circuits including the TFTs, the storage capacitor, the SEL, VDATA, and VDD lines are fabricated together. After that, the OLEDs are fabricated for all pixel circuits. The OLED is connected to the corresponding driving transistor using a via (e.g., BI of Figure 2) as shown in Figures 10(a) and 10(b). The panel is finished by deposition of the top electrode on the OLEDs which can be a continuous layer, reducing the complexity of the design and can be used to turn the entire display ON/OFF or control the brightness.
[0038] In the above description, the pixel circuit 20 of Figure 2 is used as an example of a pixel circuit for implementing the timing schedule of Figure 1, the compensating driving schedule of Figure 3, and the timing schedule of Figure 6. However, it is appreciated that the above timing schedules of Figures 1, 3 and 6 are applicable to pixel circuits other than that of Figure 2, despite its configuration and type.
[0039] Examples of the driving scheme, compensating and driving scheme, and pixel/pixel arrays are described in G.R. Chaji and A. Nathan, "Stable voltage-programmed pixel circuit for AMOLED displays," IEEE J. of Display Technology, vol. 2, no. 4, pp. 347-358, Dec.
2006, [0040] One or more currently preferred embodiments have been described by way of example.
It will be apparent to persons skilled in the art that a number of variations and modifications can be made without departing from the scope of the invention as defined in the claims.
Claims (46)
1. A method of operating a pixel array having at least one pixel circuit, wherein the pixel circuit comprises a switch, a drive transistor, a light emitting device, and a storage capacitor connected to the drive transistor and the light emitting device, the drive transistor having a gate terminal, a source terminal and a drain terminal, the gate terminal of the drive transistor being connected to a data line via the switch, one of the source and drain terminals of the drive transistor being connected to a power supply line, the method comprising the steps of:
repeating an operation cycle defining a frame period for a pixel circuit, including at each frame period, programming the pixel circuit having:
at a first cycle, charging the power supply line to a first voltage and charging the data line to a second voltage with a reverse polarity of the first voltage to develop a voltage across the gate-source voltage of the drive transistor;
driving the pixel circuit; and relaxing a stress effect on the pixel circuit, prior to a next frame period.
repeating an operation cycle defining a frame period for a pixel circuit, including at each frame period, programming the pixel circuit having:
at a first cycle, charging the power supply line to a first voltage and charging the data line to a second voltage with a reverse polarity of the first voltage to develop a voltage across the gate-source voltage of the drive transistor;
driving the pixel circuit; and relaxing a stress effect on the pixel circuit, prior to a next frame period.
2. The method as claimed in claim 1, wherein the step of programming comprises:
programming the pixel circuit by a voltage defined by:
where "L CP" is a compensating luminance, "L N" is a normal luminance, ".TAU.R" is a relaxation time at the step of relaxing, and ".TAU.F" is the frame period.
programming the pixel circuit by a voltage defined by:
where "L CP" is a compensating luminance, "L N" is a normal luminance, ".TAU.R" is a relaxation time at the step of relaxing, and ".TAU.F" is the frame period.
3. The method as claimed in claim 1 or 2, wherein the step of relaxing comprises:
at a first relaxing cycle, selecting the pixel circuit and charging the gate and source terminals of the drive transistor to a predetermined voltage, at a second relaxing cycle, deselecting the pixel circuit, the predetermined voltage being selected so that the pixel circuit turns off at the second relaxing cycle.
at a first relaxing cycle, selecting the pixel circuit and charging the gate and source terminals of the drive transistor to a predetermined voltage, at a second relaxing cycle, deselecting the pixel circuit, the predetermined voltage being selected so that the pixel circuit turns off at the second relaxing cycle.
4. The method as claimed in any one of claims 1 to 3, wherein the step of programming is applied to a kth row of the pixel array when the step of relaxing is applied to an ith row of the pixel array.
5. The method as claimed in any one of claims 1 to 4, wherein the step of programming comprises:
at a second cycle subsequent to the first cycle, operating on the pixel circuit so that a connection point between the light emitting device and the drive transistor and the storage capacitor is charged to a threshold voltage of the drive transistor.
at a second cycle subsequent to the first cycle, operating on the pixel circuit so that a connection point between the light emitting device and the drive transistor and the storage capacitor is charged to a threshold voltage of the drive transistor.
6. The method as claimed in any one of claims 1 to 4, wherein the step of programming comprises:
at a second cycle subsequent to the first cycle, operating on the pixel circuit so that a voltage stored in the storage capacitor is a threshold voltage of the drive transistor.
at a second cycle subsequent to the first cycle, operating on the pixel circuit so that a voltage stored in the storage capacitor is a threshold voltage of the drive transistor.
7. The method as claimed in claim 5 or 6, wherein the step of programming comprises:
at a third cycle subsequent to the second cycle, charging the data line to a voltage associated with a programming data.
at a third cycle subsequent to the second cycle, charging the data line to a voltage associated with a programming data.
8. The method as claimed in any one of claims 1 to 7, wherein a first terminal of the storage capacitor is connected to the gate terminal of the drive transistor, a second terminal of the storage capacitor being connected to a connection node between the drive transistor and the light emitting device.
9. A method of operating a pixel array having at least one pixel circuit, wherein the pixel circuit comprises a switch, a drive transistor, a light emitting device, and a storage capacitor connected to the drive transistor and the light emitting device, the drive transistor having a gate terminal, a source terminal and a drain terminal, the gate terminal of the drive transistor being connected to a data line via the switch transistor, one of the source and drain terminals of the drive transistor being connected to a power supply line, the method comprising the steps of:
repeating an operation cycle defining a frame period for a pixel circuit, including at each frame period, programming the pixel circuit having:
at a first cycle, developing a voltage across the gate-source voltage of the drive transistor; and at a second cycle subsequent to the first cycle, charging the power supply line to a voltage that is substantially identical to a voltage used for driving the pixel circuit;
driving the pixel circuit; and relaxing a stress effect on the pixel circuit, prior to a next frame period.
repeating an operation cycle defining a frame period for a pixel circuit, including at each frame period, programming the pixel circuit having:
at a first cycle, developing a voltage across the gate-source voltage of the drive transistor; and at a second cycle subsequent to the first cycle, charging the power supply line to a voltage that is substantially identical to a voltage used for driving the pixel circuit;
driving the pixel circuit; and relaxing a stress effect on the pixel circuit, prior to a next frame period.
10. The method as claimed in claim 9, wherein the step of programming comprises:
at a third cycle subsequent to the second cycle, programming the pixel circuit by a voltage defined by:
where "L CP" is a compensating luminance, "L N" is a normal luminance, ".TAU.R" is a relaxation time at the step of relaxing, and ".TAU.F" is the frame period.
at a third cycle subsequent to the second cycle, programming the pixel circuit by a voltage defined by:
where "L CP" is a compensating luminance, "L N" is a normal luminance, ".TAU.R" is a relaxation time at the step of relaxing, and ".TAU.F" is the frame period.
11. The method as claimed in claim 9 or 10, wherein the step of relaxing comprises:
at a first relaxing cycle, selecting the pixel circuit and charging the gate and source terminals of the drive transistor to a predetermined voltage, at a second relaxing cycle, deselecting the pixel circuit, the predetermined voltage being selected so that the pixel circuit turns off at the second relaxing cycle.
at a first relaxing cycle, selecting the pixel circuit and charging the gate and source terminals of the drive transistor to a predetermined voltage, at a second relaxing cycle, deselecting the pixel circuit, the predetermined voltage being selected so that the pixel circuit turns off at the second relaxing cycle.
12. The method as claimed in any one of claims 9 to 11, wherein the step of programming is applied to a kth row of the pixel array when the step of relaxing is applied to an ith row of the pixel array.
13. The method as claimed in any one of claims 9 to 12, wherein the step of programming comprises:
at a third cycle subsequent to the second cycle, charging the data line to a voltage associated with a programming data.
at a third cycle subsequent to the second cycle, charging the data line to a voltage associated with a programming data.
14. The method as claimed in any one of claims 9 to 13, wherein a first terminal of the storage capacitor is connected to the gate terminal of the drive transistor, a second terminal of the storage capacitor being connected to a connection node between the drive transistor and the light emitting device.
15. A method of operating a pixel array having at least one pixel circuit, wherein the pixel circuit comprises a switch, a drive transistor, a light emitting device, and a storage capacitor connected to the drive transistor and the light emitting device, the drive transistor having a gate terminal, a source terminal and a drain terminal, the gate terminal of the drive transistor being connected to a data line via the switch, one of the source and drain terminals of the drive transistor being connected to a power supply line, the method comprising the steps of:
repeating an operation cycle defining a frame period for a pixel circuit, including at each frame period, programming the pixel circuit having:
at a first cycle, developing a voltage across the gate-source voltage of the drive transistor; and at a second cycle subsequent to the first cycle, charging one of the source and drain terminals of the drive transistor to a point at which the drive transistor turns off, driving the pixel circuit; and relaxing a stress effect on the pixel circuit, prior to a next frame period.
repeating an operation cycle defining a frame period for a pixel circuit, including at each frame period, programming the pixel circuit having:
at a first cycle, developing a voltage across the gate-source voltage of the drive transistor; and at a second cycle subsequent to the first cycle, charging one of the source and drain terminals of the drive transistor to a point at which the drive transistor turns off, driving the pixel circuit; and relaxing a stress effect on the pixel circuit, prior to a next frame period.
16. The method as claimed in claim 15, wherein the step of programming comprises:
programming the pixel circuit by a voltage defined by:
where "L CP" is a compensating luminance, "L N" is a normal luminance, ".tau.
R" is a relaxation time at the step of relaxing, and ".tau. F" is the frame period.
programming the pixel circuit by a voltage defined by:
where "L CP" is a compensating luminance, "L N" is a normal luminance, ".tau.
R" is a relaxation time at the step of relaxing, and ".tau. F" is the frame period.
17. The method as claimed in claim 15 or 16, wherein the step of relaxing comprises:
at a first relaxing cycle, selecting the pixel circuit and charging the gate and source terminals of the drive transistor to a predetermined voltage, at a second relaxing cycle, deselecting the pixel circuit, the predetermined voltage being selected so that the pixel circuit turns off at the second relaxing cycle.
at a first relaxing cycle, selecting the pixel circuit and charging the gate and source terminals of the drive transistor to a predetermined voltage, at a second relaxing cycle, deselecting the pixel circuit, the predetermined voltage being selected so that the pixel circuit turns off at the second relaxing cycle.
18. The method as claimed in any one of claims 15 to 17, wherein the step of programming is applied to a kth row of the pixel array when the step of relaxing is applied to an ith row of the pixel array.
19. The method as claimed in any one of claims 15 to 18, wherein the step of programming comprises:
at a third cycle subsequent to the second cycle, charging the data line to a voltage associated with a programming data.
at a third cycle subsequent to the second cycle, charging the data line to a voltage associated with a programming data.
20. The method as claimed in any one of claims 15 to 19, wherein a first terminal of the storage capacitor is connected to the gate terminal of the drive transistor, a second terminal of the storage capacitor being connected to a connection node between the drive transistor and the light emitting device.
21. A method of operating a pixel array having at least one pixel circuit, wherein the pixel circuit comprises a switch transistor, a drive transistor, a light emitting device, and a storage capacitor connected to the drive transistor and the light emitting device, each transistor having a gate terminal, a first terminal and a second terminal, the gate terminal of the drive transistor being connected to a data line via the switch transistor, one of the first and second terminals of the drive transistor being connected to a power supply line, the gate terminal of the switch transistor being connected to a select line, the method comprising the steps of:
repeating an operation cycle defining a frame period for a pixel circuit, including at each frame period, programming the pixel circuit including:
changing a voltage of the select line and a voltage of the power supply line and providing programming data on the data line;
driving the pixel circuit; and relaxing a stress effect on the pixel circuit, prior to a next frame period, including:
changing the voltage of the select line to turn off the pixel circuit or bias the pixel circuit with reverse polarity of the step of driving.
repeating an operation cycle defining a frame period for a pixel circuit, including at each frame period, programming the pixel circuit including:
changing a voltage of the select line and a voltage of the power supply line and providing programming data on the data line;
driving the pixel circuit; and relaxing a stress effect on the pixel circuit, prior to a next frame period, including:
changing the voltage of the select line to turn off the pixel circuit or bias the pixel circuit with reverse polarity of the step of driving.
22. The method as claimed in claim 21, wherein the step of programming comprises:
programming the pixel circuit by a voltage defined by:
where "L CP" is a compensating luminance, "L N" is a normal luminance, ".tau.
R" is a relaxation time at the step of relaxing, and ".tau. F" is the frame period.
programming the pixel circuit by a voltage defined by:
where "L CP" is a compensating luminance, "L N" is a normal luminance, ".tau.
R" is a relaxation time at the step of relaxing, and ".tau. F" is the frame period.
23. The method as claimed in claim 21 or 22, wherein the step of relaxing comprises:
at a first relaxing cycle, selecting the pixel circuit and charging the gate and source terminals of the drive transistor to a predetermined voltage, at a second relaxing cycle, deselecting the pixel circuit, the predetermined voltage being selected so that the pixel circuit turns off at the second relaxing cycle.
at a first relaxing cycle, selecting the pixel circuit and charging the gate and source terminals of the drive transistor to a predetermined voltage, at a second relaxing cycle, deselecting the pixel circuit, the predetermined voltage being selected so that the pixel circuit turns off at the second relaxing cycle.
24. The method as claimed in any one of claims 21 to 23, wherein the step of programming is applied to a kth row of the pixel array when the step of relaxing is applied to an ith row of the pixel array.
25. The method as claimed in any one of claims 21 to 24, wherein the step of changing at the step of relaxing comprising:
turning on the switch transistor and subsequently turning off the switch transistor.
turning on the switch transistor and subsequently turning off the switch transistor.
26. The method as claimed in any one of claims 21 to 25, wherein one of the first and second terminals is a source terminal, and wherein the step of changing at the step of programming step comprises:
at a first cycle, developing a voltage across the gate-source voltage of the drive transistor.
at a first cycle, developing a voltage across the gate-source voltage of the drive transistor.
27. The method as claimed in claim 26, wherein the step of developing comprises:
charging the power supply line to a first voltage and charging the data line to a second voltage with a reverse polarity of the first voltage.
charging the power supply line to a first voltage and charging the data line to a second voltage with a reverse polarity of the first voltage.
28. The method as claimed in claim 26, wherein the step of changing at the step of changing at the step of programming comprises:
at a second cycle subsequent to the first cycle, operating on the pixel circuit so that a connection point between the light emitting device and the drive transistor and the storage capacitor is charged to a threshold voltage of the drive transistor.
at a second cycle subsequent to the first cycle, operating on the pixel circuit so that a connection point between the light emitting device and the drive transistor and the storage capacitor is charged to a threshold voltage of the drive transistor.
29. The method as claimed in claim 26, wherein the step of changing at the step of programming comprises:
at a second cycle subsequent to the first cycle, operating on the pixel circuit so that a voltage stored in the storage capacitor is a threshold voltage of the drive transistor.
at a second cycle subsequent to the first cycle, operating on the pixel circuit so that a voltage stored in the storage capacitor is a threshold voltage of the drive transistor.
30. The method as claimed in claim 26, wherein the step of changing at the step of programming comprises:
at a second cycle subsequent to the first cycle, charging the power supply line to a third voltage, the third voltage being identical to a voltage for driving the pixel circuit.
at a second cycle subsequent to the first cycle, charging the power supply line to a third voltage, the third voltage being identical to a voltage for driving the pixel circuit.
31. The method as claimed in claim 26, wherein the step of changing at the step of programming comprises:
at a second cycle subsequent to the first cycle, charging one of the first and second terminals of the drive transistor to a point at which the drive transistor turns off.
at a second cycle subsequent to the first cycle, charging one of the first and second terminals of the drive transistor to a point at which the drive transistor turns off.
32. The method as claimed in any one of claims 21 to 31, wherein the step of programming comprises:
at a third cycle subsequent to the second cycle, charging the data line to a voltage associated with a programming data.
at a third cycle subsequent to the second cycle, charging the data line to a voltage associated with a programming data.
33. The method as claimed in any one of claims 21 to 32, wherein the first terminal of the drive transistor is connected to the power supply line and the second terminal of the drive transistor is connected to the light emitting device, a first terminal of the storage capacitor being connected to the gate terminal of the drive transistor, a second terminal of the storage capacitor being connected to the second terminal of the drive transistor and the light emitting device.
34. A display system comprising:
a pixel array including a plurality of pixel circuits and a plurality of lines for operation of the plurality of pixel circuits, each of the pixel circuits having:
a light emitting device;
a storage capacitor;
a switch transistor; and a drive transistor connected to the light emitting device and the storage capacitor;
a driver for operating the plurality of lines to repeat an operation cycle having a frame period so that each operation cycle comprises a programming cycle, a driving cycle and a relaxing cycle for relaxing a stress on a pixel circuit, prior to a next frame period; and a controller for controlling the driver so that the programming cycle for an ith row occurs during the relaxing cycle for a kth row (i .noteq. k).
a pixel array including a plurality of pixel circuits and a plurality of lines for operation of the plurality of pixel circuits, each of the pixel circuits having:
a light emitting device;
a storage capacitor;
a switch transistor; and a drive transistor connected to the light emitting device and the storage capacitor;
a driver for operating the plurality of lines to repeat an operation cycle having a frame period so that each operation cycle comprises a programming cycle, a driving cycle and a relaxing cycle for relaxing a stress on a pixel circuit, prior to a next frame period; and a controller for controlling the driver so that the programming cycle for an ith row occurs during the relaxing cycle for a kth row (i .noteq. k).
35. The display system as claimed in claim 34, wherein the light emitting device is an organic light emitting diode.
36. The display system as claimed in claim 34 or 35, wherein the transistors are fabricated using amorphous silicon, nano/micro crystalline silicon, poly silicon, organic semiconductors technology, NMOS/PMOS technology, CMOS technology, or combinations thereof.
37. The display system as claimed in any one of claims 34 to 36, wherein at the programming cycle, the pixel circuit is programmed by a voltage defined by:
where "L CP" is a compensating luminance, "L N" is a normal luminance, ".tau.
R" is a relaxation time at the step of relaxing, and ".tau. F" is the frame period.
where "L CP" is a compensating luminance, "L N" is a normal luminance, ".tau.
R" is a relaxation time at the step of relaxing, and ".tau. F" is the frame period.
38. The display system as claimed in any one of claims 34 to 37, wherein at the relaxing cycle comprises:
a first relaxing cycle for selecting the pixel circuit and charging the gate and source terminals of the drive transistor to a predetermined voltage; and a second relaxing cycle for deselecting the pixel circuit, the predetermined voltage being selected so that the pixel circuit turns off at the second relaxing cycle.
a first relaxing cycle for selecting the pixel circuit and charging the gate and source terminals of the drive transistor to a predetermined voltage; and a second relaxing cycle for deselecting the pixel circuit, the predetermined voltage being selected so that the pixel circuit turns off at the second relaxing cycle.
39. The display system as claimed in any one of claims 34 to 38, wherein the programming cycle is applied to a kth row of the pixel array when the relaxing cycle is applied to an ith row of the pixel array.
40. A display system comprising:
a pixel array including a plurality of pixel circuits, each of the pixel circuits having:
a light emitting device;
a storage capacitor;
a drive transistor having a gate terminal, a first terminal and a second terminal, the first terminal of the drive transistor being connected to a power supply line, the second terminal of the drive transistor being connected to the light emitting device;
and a switch transistor having a gate terminal, a first terminal and a second terminal, a gate terminal of the switch transistor being connected to a select line, the first terminal of the switch transistor being connected a data line, the second terminal of the switch transistor being connected to the gate terminal of the drive transistor;
a controlling circuit for controlling an operation cycle having a frame period for the pixel array so that each operation cycle comprises a preparation and programming cycle, a driving cycle and a relaxing cycle for relaxing a stress on a pixel circuit, prior to a next frame period, including:
means for changing a voltage of the select line and a voltage of the power supply line at the preparation and programming cycle to control a voltage stored in the storage capacitor, and means for changing the voltage of the select line at the relaxing cycle to turn off the pixel circuit or biasing the pixel circuit with reverse polarity of the driving.
a pixel array including a plurality of pixel circuits, each of the pixel circuits having:
a light emitting device;
a storage capacitor;
a drive transistor having a gate terminal, a first terminal and a second terminal, the first terminal of the drive transistor being connected to a power supply line, the second terminal of the drive transistor being connected to the light emitting device;
and a switch transistor having a gate terminal, a first terminal and a second terminal, a gate terminal of the switch transistor being connected to a select line, the first terminal of the switch transistor being connected a data line, the second terminal of the switch transistor being connected to the gate terminal of the drive transistor;
a controlling circuit for controlling an operation cycle having a frame period for the pixel array so that each operation cycle comprises a preparation and programming cycle, a driving cycle and a relaxing cycle for relaxing a stress on a pixel circuit, prior to a next frame period, including:
means for changing a voltage of the select line and a voltage of the power supply line at the preparation and programming cycle to control a voltage stored in the storage capacitor, and means for changing the voltage of the select line at the relaxing cycle to turn off the pixel circuit or biasing the pixel circuit with reverse polarity of the driving.
41. The display system as claimed in claim 40, wherein the controlling circuit comprises:
means for turning on the switch transistor and subsequently turning off the switch transistor.
means for turning on the switch transistor and subsequently turning off the switch transistor.
42. The display system as claimed in claim 40, wherein the light emitting device is an organic light emitting diode.
43. The display system as claimed in claim 40, wherein the transistors are fabricated using fabricated using amorphous silicon, nano/micro crystalline silicon, poly silicon, organic semiconductors technology, NMOS/PMOS technology, CMOS technology, or combinations thereof.
44. The display system as claimed in any one of claims 40 to 43, wherein at the programming cycle, the pixel circuit is programmed by a voltage defined by:
where "L CP" is a compensating luminance, "L N" is a normal luminance, ".tau.
R" is a relaxation time at the step of relaxing, and ".tau. F" is the frame period.
where "L CP" is a compensating luminance, "L N" is a normal luminance, ".tau.
R" is a relaxation time at the step of relaxing, and ".tau. F" is the frame period.
45. The display system as claimed in any one of claims 40 to 44, wherein at the relaxing cycle comprises:
a first relaxing cycle for selecting the pixel circuit and charging the gate and source terminals of the drive transistor to a predetermined voltage; and a second relaxing cycle for deselecting the pixel circuit, the predetermined voltage being selected so that the pixel circuit turns off at the second relaxing cycle.
a first relaxing cycle for selecting the pixel circuit and charging the gate and source terminals of the drive transistor to a predetermined voltage; and a second relaxing cycle for deselecting the pixel circuit, the predetermined voltage being selected so that the pixel circuit turns off at the second relaxing cycle.
46. The display system as claimed in any one of claims 40 to 45, wherein the programming cycle is applied to a kth row of the pixel array when the relaxing cycle is applied to an ith row of the pixel array.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA2583708A CA2583708C (en) | 2006-04-19 | 2007-04-18 | Stable driving scheme for active matrix displays |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA002544090A CA2544090A1 (en) | 2005-12-06 | 2006-04-19 | Stable driving scheme preventing the accumulative aging in active matrix displays |
| CA2,544,090 | 2006-04-19 | ||
| CA2583708A CA2583708C (en) | 2006-04-19 | 2007-04-18 | Stable driving scheme for active matrix displays |
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| Publication Number | Publication Date |
|---|---|
| CA2583708A1 CA2583708A1 (en) | 2007-07-07 |
| CA2583708C true CA2583708C (en) | 2011-03-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA2583708A Expired - Fee Related CA2583708C (en) | 2006-04-19 | 2007-04-18 | Stable driving scheme for active matrix displays |
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| Country | Link |
|---|---|
| CA (1) | CA2583708C (en) |
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- 2007-04-18 CA CA2583708A patent/CA2583708C/en not_active Expired - Fee Related
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| Publication number | Publication date |
|---|---|
| CA2583708A1 (en) | 2007-07-07 |
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