CA2415491A1 - Embeddable single board computer - Google Patents

Abstract

An embeddable single board computer includes a microprocessor, memory and a PCI interface all operatively connected on a DIMM standard form factor.

Description

SPECIFICATION
[Electronic Version 1.2.8]
EMBEDDABLE SINGLE BOARD COMPUTER
Background of Invention [0001 ] This invention relates to embeddable single board computers.

[0002] Embedded computer systems are those without the typical front-end of desktop or personal computers. Embedded computers are computers that are integrated into their environment such that a user may be unaware that a computer is providing functionality to the apparatus or system which includes the embedded computer.

[0003] Microcomputers typically consist of many circuit boards plugged into a backplane. A backplane operates much like an electrical junction box, and, more particularly, is an electronic circuit board containing circuitry and sockets into which additional electronic devices on other circuit boards or cards can be plugged.
A
backplane typically operates only as an intermediary board to provide pathways between the various ports, and the backplane is typically itself placed in data communication, via another plug, slot or socket on the backplane with another electronic circuit board, which in fact operates as the CPU for the device.

[0004] Embeddable single board computers (SBC) resulted from advances in integrated circuit technology which allowed functions which had previously occupied entire circuit boards to be crammed into single "large-scale integration" or "LSI" logic chips. LSI chips for CPU, memory, storage and various ports or interfaces made it possible to implement complete microcomputer systems onto a single board without a backplane.

(0005] There are many well-known form factors in the case of embeddable SBC's such as Little BoardT"' (Ampro), ISA "slot boards", PC/104 modules, CompactPCl, PC/104 Plus and EBX (Embedded Board, Expandable). The latter three added the well-known Peripheral Component Interconnect (PCI) bus standard to the SBC. However, these solutions suffer from the disadvantage of being very expensive because they are typically used in industrial niche applications.

[0006] There is a need in the art for a compact embeddable single board computer which is inexpensive and permits rapid and efficient application development.
Summary of Invention [0007) The present invention provides a single board computer implemented in a standard commercially available form factor the Dual In-Line Memory Module (DIMM) form factor. In one aspect, the invention may comprise a single board computer wherein the board comprises a DIMM form factor, the computer comprising: (a) a microprocessor; (b) memory; and (c) a PCI interface port; wherein the memory and the PCI interface port are operatively connected to the microprocessor.

[0008] PCI refers to peripheral component interconnect. PCI is a standardized data transfer mechanism developed by a consortium of several companies and administered by a group known as the PCI SIG or PCI Special Interest Group to ensure widespread compatibility between different peripheral devices, and avoid permutations of local bus architectures which varied, or which were peculiar to a specific processor bus. Currently, the PCI standard calls for the ability to support up to 66 MHz operating speed. PCI
specifications are well known in the art and may be obtained from PCI SIG.

[0009] By using PCI, a myriad of options are available to the embedded systems developer. The developer now may select from a range of high-volume PCI
components used in desktop applications. This brings low-cost, high-performance, system-level solutions within reach of the embedded marketplace. Use of standard PCI
technology enables a significant reduction in development effort. Using existing proven technology reduces time-to-market of both the hardware and software components.
Brief Description of Drawings [0010] Figure 1. A schematic representation of one embodiment of an embeddable single board computer.
[001 1 ] Figure 2. A schematic representation of a passive backplane for use in developing applications for a SBC of the present invention.
[0012] Figure 3. A schematic representation of the PCI interface architecture.
Detailed Description [001 3] The exemplary implementation of the present invention combines a superset of the 32-bit, 33MHz desktop PCI standard with a dual in-line memory module (DIMM) form factor. This form factor uses a high-volume, commercially available 168 pin DIMM
interconnect component as specified by~EDEC Solid State Technology Association. The use of a high-volume interconnect reduces system cost considerably, as can be seen when a comparison is done between the desktop market and other PCI
technologies.The acceptable sizes defined by the DIMM standard may improve reliability by reducing the mass of the circuit card considerably. Reliability is enhanced further by the presence of card locks at both ends of the DIMM connector. Easily manufactured and inexpensive braces also may be added to the middle of the circuit cards for additional support.
[0014] The following description of a single preferred embodiment is not intended to be limiting of the invention as claimed herein.
[001 5] System Architecture The hardware implementation of the present invention may address the needs of the embedded marketplace by focusing on scalability, physical size, flexibility, development costs and product cost. Figure 1 schematically illustrates one embodiment of the invention as a single board computer (10), which may be referred to herein as the SBC-CPU module. Figure 2 illustrates a passive developers' backplane (100) and the SBC-CPU module (10). The developers' backplane is intended to be used by other embedded system developers for quick application development.
The backplane may include a standard desktop PCI slot to facilitate software development earlier in the cycle using standard PCI peripheral cards, as is shown in Figure 2.
[0016] The architecture of a single board computer (10) of the present invention comprises four main functional regions: an Ethernet controller, a PCI
interface, a microprocessor and system memory. Therefore, in one embodiment shown in Figure 1, the SBC-CPU comprises a microprocessor (12), memory (14), an Ethernet network interface (16), a PCI interface (18) and both RS 232 (20) and RS 485 (22) serial communication ports.
[0017] The microprocessor may be any microprocessor suitable for a single board computer. In a preferred embodiment, the microprocessor (12) comprises a Motorola DragonbaIIT"' VZ microcontroller and the MC68VZ328 in particular. This microprocessor is preferred because it is based on a 68K core and runs at higher speeds and lower power than previous components. The VZ328 is used in many of the most popular PDAs on the market and has many features integrated into the device including: ~

CPU chip-select logic and 8-16-bit bus interface clock generation module (CGM) and power control interrupt controller ~76 GPIO lines grouped into ten ports two pulse-width modulators (PWM 1 and PWM 2) two general-purpose timers two serial peripheral interfaces (SPI 1 and SPI 2) two UARTs (DART 1 and UART 2) and infrared communication support ~ LCD controller ~ real-time clock ~ DRAM controller that supports EDO RAM, Fast Page Mode and SDRAM ~ in-circuit emulation module bootstrap mode [0018] Operating System The choice of an operating system may be made to preferably meet the following requirements: widely used, easily supported, ease of development, low-development costs, low per-unit licensing fees, support for wide range of hardware platforms and devices, code maintenance, qualified developers and maximized exploitation of the technology platform. In a preferred embodiment, the operating system comprises a Linux system and more preferably comprises a NClinux system.
[0019] Linux has existed in the desktop domain for a considerable length of time, and thus it has accumulated a significant knowledge base related to PCI
development.
[0020] It is known in the art that the use of closed-source operating systems for embedded projects has created problems with code debug and trace during development. Another important consideration is off-the-shelf support for different filesystems, network stacks and peripheral devices. Finally, support for a wide range of hardware platforms is important for future development projects that require application migration to higher levels of performance.
[0021 ] The hardware platform of the preferred embodiment includes the Motorola DragonballT"~VZ microcontroller. The Motorola DragonballT"'family devices use a large-endian memory format and alignment that is different from x86-based devices.
The DragonbaIIT"'also lacks a memory management unit (MMU) unlike microprocessors typically used in desktop computers. Typically, lower-cost processors lack an MMU, and many embedded applications are driven by cost. The software for these embedded applications does not require the benefits that an MMU would provide.
[0022] It is known that a full Linux kernel requires the presence of an MMU in the hardware system. Due to the absence of the MMU in the DragonbaIITMprocessor, a process of porting a Linux kernel to this microprocessor architecture is required.
NClinux is a Linux 2.0 kernel that has been ported to a Motorola 68k family device that does not have an MMU. Same kernel services need to be adapted to work in an environment without an MMU. For example, services normally provided by the function fork() may be accomplished with vfork(), given that care is used. Note that uClinux originally was ported to the DragonbaIIT"" EZ processor. Implementation of one embodiment uses the DragonbaIIT"'VZ and so requires some additional kernel modifications.
[0023] A major factor to consider for selection of an OS is a wide range of support for hardware platforms and peripheral components. It is preferred to have full software support for as many devices as possible. Thus, migrating an application to the architecture of the present invention mainly would involve a hardware form-factor change, with only minimal changes to the hardware design and application software.
Device-driver design is one of the most substantial costs during software development.

A large support base for peripheral devices and components, such as network interfaces, RAM, ROM, serial communications and displays, is essential for cost savings during the development phase. Linux is a preferred choice since the supported knowledge base includes source code.
[0024] Performance is also a significant consideration. Linux is a multitasking operating system and provides a rich application development environment. Many practical embedded applications can be developed within this operating system environment. We have found that with properly written drivers, one can respond to hard real-time interrupts without having to preempt the kernel. For most applications, this is sufficient--especially given that the gcc tools compile C code into efficient code, and embedded assembly code can be written if response times are critical.
[0025] Certain applications may require a more deterministic response. Real-time extensions for Linux are known to those skilled in the art. Projects such as RTLinux and RTAI provide the necessary framework for providing real-time response within Linux.
They operate on the principle that an RT kernel runs at the core with the Linux kernel scheduled as a low-priority task. Filesystems for embedded applications require a level of robustness that exceeds that of normal desktop systems. In addition, they must support diskless storage and embedded devices. Achieving these requirements generally involves a sacrifice in efficiency and performance.
[0026] In one preferred embodiment, the filesystem comprises the journaling Flash Filesystem (jFFS). ~FFS is specifically designed to minimize the risk of data loss from a system crash or uncontrolled shutdown for industry-standard Flash memories. It is included in the standard Linux 2.4 kernel and is available as an open-source patch for the Linux 2.0 kernel. jFFS is a log-structured list of nodes on the Flash media. Each node contains information about the associated file and possible file data. If data is present, the node will contain a field that indicates the location in the file where data should appear. This allows newer data to overwrite older data. The node also contains information about the amount and location of data to delete from the file.
This information is used for truncating files or overwriting selected data within a file. In addition, each node contains information that is used to indicate the relative age of the node. In order to recreate a file, the entire media must be scanned, the individual nodes must be sorted in order of increasing version number and the data must be processed according to the instructions in each node: This is required only once when the filesystem is mounted.
[0027] ~FFS writes to the Flash media in a cyclic manner. New nodes simply are appended until the end of the media is reached. Before reaching the end of the media, the first block of media must be freed for use. This is accomplished by copying all valid nodes (nodes that have not been made obsolete by later nodes) and then erasing the block. This inherent cyclic nature ensures wear-leveling of the Flash media.

[0028] As evident, ,JFFS is not an efficient means of storing and retrieving data. The number of bytes required to store a file can be more significant than the actual file size.
However, this lack of efficiency is compensated for in terms of robustness and crash recovery, where JFFS rates highly. If the system crashes or experiences an unexpected loss of power, only the last node written might be affected. Thus, the file still can be recreated excluding the changes described by the last corrupted node.
[0029] Memory In one embodiment, the total memory capacity of the SBC-CPU is 40MB which may comrpise both volatile and nonvolatile parts. The volatile memory capacity is 32MB Synchronous Dynamic RAM (SDRAM). When Linux was considered in the design process, one of the requirements that contributed to an early design iteration was the memory footprint. This requirement influenced the microprocessor selection because of the need for an integrated SDRAM controller. The SDRAM is preferably a MT48LC4M16A2 or compatible 3.0V SDRAM.
[0030] In one embodiment, the nonvolatile memory storage is limited to 8MB and is made up using Flash-based memory which is preferably AMD29DL322D or compatible 3.0V Flash ROM. Flash ROM is located at 0x100000000 in memory. The operating system kernel is located at the beginning of flash, the read-only root file system is located immediately after the kernel and the,]FFS starts on the first sector boundary after the root file system. Total kernel requirements are 450KB, and the root file system and ~FFS requirement is 1 50-400KB, depending on which standard Linux components are required for the application. This leaves approximately 7MB of RAM free for user application and data.
[0031 ] A DragonbaIIT"'VZ has four pairs of chip selects which are configurable as pairs: CSAO and CSA1 , CSBO and CSB1, CSCO and CSC1, and CSDO and CSD1. Chip select pairs share a base address, the size of the addressable area, the number of wait states, and whether it is an 8-bit or a 16-bit chip select. When SDRAM is enabled, the DragonbaIIT"' VZ consumes five of the chip seleets. The 16-bit flash is assigned to CSAO
because that is the only chip select active after reset. The wait states are set for internal timing.
[0032] The 16-bit PCI interface is preferably a synchronous interface and must be attached to CSBO, which is configured for external timing.
[0033] The Ethernet chip supports either 8 or 16 bit interface, however, because most NE2000 compatible drivers have been written for an 8-bit interface, the device has been interfaced as an 8 bit device attached to CSAI . Because the chip select pair must be configured as 16-bit to support the 16-bit flash, the registers of the ethernet chip will appear at every other byte address rather than a block of contiguous bytes.

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:~',i.~:,6=~:.~'a a ... °f , i : s ~ G'> ;_°. tw . .r . ,i~ ~. Y..,., [0040] The PCI architecture used in the embodiment described herein is dictated principally by the Motorola DragonbaIIT"''s (VZ328) inability to support multiple masters on the address and control buses. It is possible to insert buffers to isolate the VZ328 address and control signals. Such an implementation would suffer however, because another external device that gains control of the bus would not have access to the peripherals internal to the VZ328. These include functions such as chip-select logic and, most importantly, the SDRAM memory interface. Therefore, little is to be gained by adding the external buffer logic.
[0041 ] A solution exists where a dual-ported memory is used to interface the PCI
bus with the DragonbaIIT"" microprocessor, as shown schematically in Figure 3.
Cypress Semiconductor offers a component with a dual-ported memory and PCI
Master/Target interface combined into one integrated circuit. The Cypress Cy7C09449 acts as a bridge in this implementation. This results in two distinct address spaces: one for the VZ328 and one for the PCI.
[0042] The preferred embodiment implements a modified version of the PCI
Specification 2.1 for embedded applications.
[0043] Linux Support for PCI In the 2Ø38 kernel used as a starting point for the embodiment described herein, Linux support for PCI peripherals is extensive but is completely dependent on BIOS calls for PCI configuration. This works well for PCs but is not so well suited for implementing PCI for an embedded system. It appears that all Linux implementations of PCI use the BIOS. Therefore, in one embodiment, the starting point was to give the PCI BIOS functionality in order to make use of the base Linux PCI
driver.
[0044] Most developers are familiar with PCI in the Intel x86 environment. It is important to note that such an implementation is a special case. In the special case, the PCI memory address space and the host processor (386, 486, Pentium, Athlon), physical address space are one and the same. The bridge arrangement required by the architecture described above is the more general case.
[0045] There are other significant development issues as well. These stem from the reality that most PCI development is for products intended for the desktop. In addition to the above problem, other problems involved in porting PC drivers to our embedded platform include: 1 ) byte order is generally ignored as x86s and PCI are the same; 2) word alignment is generally poor on x86s as these processors automatically generate multiple bus cycles; 3) new hardware still reflects ISAs (industry-standard architectures, i.e., AT) by using the same I/O register maps, rather than introducing improved memory space register maps; and 4) drivers, especially video drivers, sometimes rely on expansion ROMs that contain x86 binary code, which assumes the existence of PC
peripheral devices and specific x86 PC BIOS software interrupt vectors.

[0046] One consequence of using the Motorola VZ328 microprocessor is that placing the memory onto the PCI bus would transform the architecture into the special case of the PC, at increased cost and complexity.
[0047] PCI BIOS Development The PCI BIOS must do two things. It must allocate memory space, I/O space and interrupts. It also must allow a device driver access to PCI
configuration cycles that allow the device driver to find the card, read the card resources and be able to configure the card as necessary.
[0048] The PCI BIOS calls have been extended to provide a hardware abstraction layer to compensate for having a split memory address space. These functions are summarized as follows: ~ pcibios_read_memory_byte(); ~ pcibios write_memory_byte();
pcibios_read_memory_word0; ~ pcibios_write_memory_wordQ;
~pcibios_read_memory_dword(); ~pcibios_write_memory_dword().
[0049] he VZ328, unlike x86 processors, does not have both a memory address space and an I/O address space. The VZ328 itself cannot generate an I/O cycle, nor does it need to. The VZ328 must communicate the PCI I/O address to the bridge, as required for PCI memory addresses, and must communicate a request to the bridge for a PCI I/0 cycle. The PCI BIOS calls have been extended with the addition of the following functions to support I/O cycles: ~ pcibios_read_io_bytep ; ~ pcibios write_io_byte() pcibios_read_io_word0 ; ~ pcibios write_io_word() ; ~ pcibios_read_io_dword() pcibios write_io_dwordQ
[0050] The VZ328, unlike x86 processors, is a large-endian device. PCI has been defined to work well with x86 devices, which are small-endian. Since most PCI
data transfers are word or dword (i.e., few byte transfers), it is advantageous to avoid byte swapping on every word or dword access, so the data bus between the bridge and the VZ328 has been swapped in hardware. A side-effect result is that byte accesses now must be corrected by inverting the least significant address bit (AO).
Fortunately, this is handled in the supplied PCI BIOS calls (and in the above extensions), so the details largely are hidden by the PC1 BIOS: ~ pcibios_read_config_byte();
pcibios write_config_bytep; ~ pcibios_read_config_wordp; ~
pcibios_write_config word();
pcibios_read_config_dwordQ; ~ pcibios_write_config_dwordQ.
[0051 ] Most transfers on the PCI bus are accomplished using direct memory access (DMA) bus cycles. These transfers can be initiated by any PCI device to any memory address reachable on the PCI bus. Since the VZ328 address space is separate from the PCI address space, PCI DMA transfers cannot specify a source or destination that is within the VZ328 memory space.

[0052] The Cypress Cy7C09449 contains a 32K8 dual-ported memory that is used to bridge the VZ328 memory space to PCI memory space. Since there may be more than one PCI device in a system, there can be more than one PCI device driver installed at any given time. This condition compels us to treat the dual-ported memory as a shared resource and to balance efficiency with performance.
[0053] The kernel function kmallocQ, which calls get free-pages(), was designed to allocate such special memory using GFP_ flags. GFP-DMA is defined for PC
implementations and denotes a page that is bounded by a 16M memory limit and does not cross a 64K boundary (this was due to the limitations of the 8237 DMA
controller at the time).
[0054] Since PCs share processor and PCI memory address spaces, there is no special flag defined to select memory for use with DMA and PCI. it appears that the PC
standard here is designed around the special case. To compound the problem, there is no central resource to initiate a DMA transfer, as device drivers initiate transfers by writing to nonstandard registers on the device hardware. Generally speaking, this code needs to be altered to become bridge-aware. Therefore, to facilitate sharing the dual-ported RAM on the bridge, the PCI BIOS has been extended to include kmalloc memory tables and a GFP-PCI flag. A device driver may allocate and deallocate DPram on a transfer-by-transfer basis or request a block of memory that it will own permanently, until the device driver is closed.
(0055] Finally, interrupts are handled using the register_interruptQ system call. PCI
specifies an 8-bit field for interrupt number, so the VZ328 PCI BIOS can assign a mach interrupt number that can be handled by a device driver using the register_interruptQ
system call.
[0056] Signal Descriptions The complete listing of signal descriptions of the preferred embodiment described herein is shown below in Table 2:
[0057] Table 2 1 ETHRX- ETHTX- 43 CBE[1]# AD[15]

2 ETHRX+ ETHTX+ 44 +3.3V PAR

3 45 SERR# Ground 4 46 +3.3V SBO#

ETHLNKLED ETHACTLE 47 PERR# SDONE

6 VBAT EGND 48 LOCK# +3.3V

7 PlD EMUIRQ 49 Ground STOP#

8 EMUBRK EMUCS SO DEVSEL# Ground 9 Ground Ground 51 +3.3 TRDY#
V

SCIB+ SCIB- 52 IRDY# Ground 11 SCIARTS SCIACTS 53 Ground FRAME#

12 SCIARXD SC1ATXD 54 CBE[2]# +3.3V

13 Reserved Reserved 55 AD[17] AD[16]

i4 LCONTRAST Reserved 56 +3.3V AD[18]

LFRM LLP 57 AD[19] Ground 16 LCLK LACD 58 AD[21] AD[20]

17 LCDi LCDO 59 Ground AD[22]

18 LCD3 LCD2 60 AD[23] +3.3V

19 Ground Ground 61 CBE[3]# Ij7SEL

USER USER 62 +3.3V AD[24]

21 +5V D- 63 AD[25] Ground 22 D+ Ground 64 AD[27] AD[26]

23 +5V SPIINTl 65 Ground AD[28]

24 SPI1NT0 CSO 66 AD[29] +3.3V

CS1 CS2 67 AD[31] AD[30]

26 CS3 SS 68 +3.3V(I/O)Reserved 27 MISO +5V 69 REQ# Ground 28 Ground MOSI 70 Ground GNT#

29 SCLK Ground 7t CLK +3.3V(I!O) ' +3.3V (I/O)+3.3V 72 Ground CLKI
(I/O}

31 AD[01 ] AD[00] 73 CLK2 Ground ' 32 Gmund AD[02] 74 SYSEN# CLK3 33 AD[03] Ground 75 RST# PRST#

34 AD[OS] AD[04] 76 +5V +3.3V(I/O) +3.3V AD[06] 77 INTD# +5V

36 AD[07] +3.3V 78 I1VT'B# IlVTC#

37 AD[08] CBE[0]# 79 +5V INTA#

38 M66EN AD[09] 80 REQ3# +5V

39 AD[10] Ground 81 REQ2# GNT3#

AD[12] AD[11] 82 Ground GNT2#
.

41 Ground AD[13] 83 REQ1# +12V

42 AD[14] +3.3V 84 -12V GNTl#

[0058] Potential ApplicationsThe present invention has been developed with several applications in mind, including asset management, remote-access data acquisition and instrumentation, industrial networking and control, security and power management.
Using Internet technologies, the present invention may enable a new class of Internet appliances that brings the rich graphical environment of a web browser to small embedded devices. The platform of the present invention differs significantly from other embedded implementations, most notably in its ability to act as a web server directly bypassing the need to have a data server.
[0059] As will be apparent to those skilled in the art, various modifications, adaptations and variations of the foregoing specific disclosure can be made without departing from the scope of the invention claimed herein. The various features and elements of the described invention may be combined in a manner different from the combinations described or claimed herein, without departing from the scope of the invention.

Claims (5)

1. A single board computer wherein the board comprises a DIMM form factor, the computer comprising:
(a) a microprocessor;
(b) memory; and (c) a PCI interface port;
wherein the memory and the PCI interface port are operatively connected to the microprocessor.

2. The single board computer of claim 1 further comprising a network interface port.

3. The single board computer of claim 2 wherein the network interface port comprises, either singly or in combination, an Ethernet interface port, an RS232 interface port, or an RS 485 interface port.

4. The single board board computer of claim 1 further comprising an embedded operating system.

5. The single board computer of claim 4 wherein the operating system comprises a Linux system.