KR970059914A

KR970059914A - Flash memory system

Info

Publication number: KR970059914A
Application number: KR1019960001692A
Authority: KR
Inventors: 가끼누마 유지; 가리베 히로시; 테라사끼 유끼오
Original assignee: 히로시 사또; 티디케이 코포레이션
Priority date: 1996-01-26
Filing date: 1996-01-26
Publication date: 1997-08-12
Also published as: KR100222908B1

Abstract

플래시 메모리(20,21)는 한쌍의 데이타버스(27,28)와, 한쌍의 버퍼메모리(22,23)를 갖춘 플래시 메모리 콘트롤러(2)를 통해 호스트 컴퓨터(1)에 연결된다. 상기 데이타버스 각각은 관련 플래시 메모리와, 상기 호스트 컴퓨터에 연결된 관련된 버퍼메모리에 연결된다. 상기 데이타버스(22,23)는 동시에 동작하도록 제어되어 상기 플래시 메모리가 병렬형태로 동시에 억세스되도록 한다. 상기 호스트 컴퓨터에의 데이타는 상기 버퍼메모리와 상기 데이타버스를 통해 상기 플래시 메모리로 전송되고, 그 역으로도 전송된다. 모든 소자(20,21,2)는 코넥터를 통해 호스트 컴퓨터에 연결된, 플래시 메모리 카드라 불리우는 지지카드(100)에 장착된다. 병렬 형태로 동작하는 다수의 버스를 하용하기 때문에, 호스트 컴퓨터와 플래시 메몰 카드사이에 데이타 전송시간은 짧아진다.The flash memories 20 and 21 are connected to the host computer 1 through a pair of data buses 27 and 28 and a flash memory controller 2 having a pair of buffer memories 22 and 23. Each of the data buses is connected to an associated flash memory and an associated buffer memory connected to the host computer. The data buses 22 and 23 are controlled to operate simultaneously so that the flash memory can be simultaneously accessed in parallel. Data to the host computer is transferred to the flash memory via the buffer memory and the data bus, and vice versa. All elements 20, 21, 2 are mounted on a support card 100, referred to as a flash memory card, which is connected to the host computer via a connector. Since a plurality of buses operating in parallel form are used, the data transfer time between the host computer and the flash memory card is shortened.

Description

Flash memory system

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제 1A도는 본 발명에 따른 플래시 메모리 시스템(flash memory system)의 블록도,Figure 1A is a block diagram of a flash memory system in accordance with the present invention;

제 1B도는 본 발명에 따른 플래시 메모리 시스템의 구조를 도시한 도면,1B is a diagram showing the structure of a flash memory system according to the present invention,

제 2도는 제1A도의 일부를 더욱 상세히 도시한 블록도,FIG. 2 is a block diagram further illustrating a portion of FIG. 1A;

제 3도는 종래의 플래시 메모리 시스템의 블록도.Figure 3 is a block diagram of a conventional flash memory system.

Claims

A flash memory system connected to a host computer, comprising: a plurality of flash memory chips; and a flash memory controller for controlling the transfer of data between the memory chip and the host computer, wherein the flash memory controller comprises: An address buffer coupled to the data bus via a gate for supplying address information to the flash memory chip with the data bus, a plurality of address buses connected to the data bus via a plurality of data buses, A plurality of buffer memories connected to the flash memory chip and / or a data bus associated with the host computer for temporarily storing data transmitted from the flash memory chip, and a plurality of flash memory chips connected in parallel, And a flash memory sequencer for simultaneously controlling the buffer memory and the data bus in order to enable the flash memory to operate at the same time.

The flash memory controller of claim 1, wherein the flash memory controller comprises: a plurality of comparators for comparing state information provided by the associated flash memory chip with predetermined reference information; AND circuitry for providing a logical AND operation for the output of the comparator; Wherein the AND circuit provides a positive output signal only when all of the flash memory chips correctly operate with the previous operation.

The flash memory system according to claim 1, wherein the number of the data bus, the flash memory chip, the buffer memory, and the comparator is two.

The flash memory system of claim 1, wherein data on each of said data buses is in parallel form.

2. The flash memory system of claim 1, wherein each of said data buses transfers data and, of course, addresses and instructions to a flash memory chip.

3. The flash memory sequencer of claim 2, wherein the flash memory sequencer comprises a counter, a sequencer RAM for storing a microinstruction at an address indicated by the counter, a microinstruction coupled to the sequencer RAM for decoding a microinstruction, A microcommand decoder for causing the flash memory chip to be transferred to the flash memory chip; and a determination circuit for adjusting the contents of the counter according to the output of the AND flashing.

The flash memory system of claim 1, wherein each of the flash memory chips has 8 bits at each address.

The flash memory system of claim 1, wherein the system comprises the flash memory chip and a support card on which the flash memory controller is mounted, the support card having a connector connected to the host computer.

A flash memo controller for controlling the transfer of data between a flash memory chip and a host computer, the flash memory chip being connected to the controller and having an associated flash memory chip for transferring data to and / or from the flash memory A plurality of data buses connected to each other, a plurality of buffer memories connected to the host computer and the associated data bus, respectively, for temporarily storing data transferred to and / or from the flash memory chip, and a plurality of flash memories And a flash memory controller for simultaneously controlling the buffer memory and the data bus so that the chips can be simultaneously accessed.

※ Note: It is disclosed by the contents of the first application.