CA2318318C - High-speed test cycle counter - Google Patents

Abstract

A high-speed wide range counter for Automated Test Equipment applications is divided into two separate, parallel counting blocks for counting over a wide range of count values including short and minimum counts while optimizing gate utilization. The first counting block based on pipeline logic circuitry is used to perform lo ng counts and the second counting block based on wide parallel logic circuitry is used to perform short counts. The two blocks operate one at a time, exclusively of each other. The ir outputs are combined to provide a final count value. The overall counter is optimize d for high speeds as required in today's ATE applications since the combinatorial logic delay with polynomial counter decoding stages is avoided in the case of short count values. The counter also supports loading on a cycle-by-cycle basis.

Description

HIGH-SPEED TEST CYCLE COUNTER
FIELD OF THE INVENTION
The invention relates to test cycle generation and more specifically to a high-speed polynomial counter used to generate test cycle timing values in automated test s equipment (ATE).
BACKGROUND OF THE INVENTION
Automated test equipment used for testing memories, ASICs, microprocessors and other types of digital circuits requires the generation of test cycles having variable io durations in order to examine the performance of the device under test (DUT) in different operating modes during predetermined timing intervals. A test cycle essentially consists of a portion of time during which a certain test operation is performed on the DUT. One ATE feature illustrating this requirement is to provide the user the ability to change the duration of a test cycle on a cycle-by-cycle basis. For example, data can be is written to the device under test at one frequency and read out at a different frequency, requiring the ATE to be able to generate different durations for each test cycle.
Generating such variable duration test cycles requires varying degrees of timing resolution. Essentially, a test cycle consists of two portions, a coarse timing portion requiring coarse timing resolution and a fine or precise portion requiring fine timing 2o resolution. The coarse portion of the test cycle is typically implemented using a counter which counts an integer number of system clock cycles. The fine portion of the test cycle is typically implemented using additional circuitry that accumulates fine delay portions and generates a carry signal when the accumulated result of fractional clock fine delays is greater than one system clock period.
With reference to the coarse portion of the test cycle timing, since ATEs typically operate over a wide range of frequencies, wide range counters are needed to support s timing generation in ATE applications. The counters must not only have a wide range to support a multitude of testing frequencies but they must also be quickly re-loadable in order to allow the user to redefine the test cycle period on a cycle-by-cycle basis with no "dead" time. Typically, synchronous counters operating in these applications can be reloaded at the maximum rate of one reload every 2 system clocks where one clock io cycle is needed to load the counter and one clock cycle is needed to perform the actual count.ln the case of a minimum count, i.e. a count of 0, the counter would require 2 system clock cycles to perform the minimum count.
It has been found that using polynomial counters to provide an integer number of clocks representative of the coarse delay portion of a test cycle is optimal for ATE
is applications due to the structure of such counters. Polynomial counters, otherwise known as linear feedback shift registers (LFSRs), can operate at much higher frequencies than binary counters. Typically, binary counters require multiple stages of combinatorial logic circuits to resolve carry propagation, whereas polynomial counters use a shift register implementation and a feedback path which together can reliably 2o count at much higher frequencies. In a conventional polynomial counter, a feedback path is taken from two or more predetermined tap positions (depending on the number of register stages) and combined in an exclusive OR function to be fedback to the input of the first stage of the shift register to produce a pseudo-random polynomial count

2 sequence. An n-bit polynomial counter is reset to an initial valid count value (typically 1000...00) and sequences through a series of (2"-1 ) pseudo-random states (typically ending at 0000...01 ) and circulates continuously through all valid states. A
'No-Op' (no operation) state is specifically avoided although such a state (typically defined by all 0's) s can be loaded into the counter to generate a 'No-Op'.
Polynomial counters are typically used as pre-scalar counters, the outputs of which are usually applied to slower binary counters. The outputs of the shift register portion of a polynomial counter are typically decoded by combinatorial logic.
This decoding logic introduces significant delay which at high speeds approaching 1 GHz, as io required in today's ATE applications, begins to limit the operating speed of the counter.
For example, as long as the operating frequency of the ATE is relatively low (less than 100MHz), using a polynomial counter having an n-bit timing input will generate a count having (2"-1) unique states within the required test cycle window. However, as the frequency of the ATE is increased significantly (over 100MHz to up to 1GHz), as is the is case in today's high speed applications, the output of a polynomial counter can no longer keep up with the speed of the test cycle pipeline due to the polynomial counter decoding logic - especially in the case of low count values. For example, for a count of 0 or 1, the combinatorial logic associated with the output of the polynomial counter would take too long to decode the count result in order to provide a "true 0 count" to the 2o system within one test cycle pipeline stage. As a result, one or more additional pipeline stages) must be inserted on the count output of the polynomial counter. For example, in case where one pipeline stage is added, this additional pipeline stage adds one clock count to the polynomial counter sequence which previously would count over the range

3 (2"-1 ):0 and now will count over the range 2":1. Therefore, the polynomial counter is no longer able to count the required minimum count value representing the required output clock latency.
Although conventional polynomial counters are attractive for their high speed s operating characteristics, they are nonetheless somewhat rigid in applicability, having one less count than a binary counter with the same number of bits, and counting through a (pseudo-random) polynomial sequence rather than a more convenient binary sequence. Furthermore, the decoding logic associated with generating a counter output begins to limit the operating speed of polynomial counters at high testing speeds, io especially for low count values.
Accordingly , there is a need for a high speed wide range test cycle counter which can be loaded on a cycle-by-cycle basis and which ensures maximum gate utilization.
is SUMMARY OF THE INVENTION
The present invention seeks to overcome the disadvantages of the prior art associated with high-speed test cycle counters.
The test cycle counter of the present invention is comprised of a long cycle counter and a short cycle counter both of which receive test cycle timing value inputs as 2o well as a carry input from fine delay circuits. The long cycle counter performs long count sequences and the short cycle counter performs short count sequences including a minimum count.

4 In accordance with an aspect of the present invention, there is provided a counter responsive to timing input signals and a carry signals for providing a count output signal, which includes: (a) a first counting block responsive to a first group of timing signals providing a first count sequence for generating a first count signal s upon completion of stepping through the first count sequence; (b) a second counting block responsive to a second group of timing signals providing a second count sequence for generating a second count signal upon completion of a stepping through the second count sequence; (c) a combining block for combining the first and second count signals and generating a feedback signal for enabling loading of io the first and second counting blocks with new values for the first and second groups of timing signals; (d) a first selecting block for selectively delaying the first count signal by a predetermined number of clock delays in response to the carry signal;
and (e) a second selecting block for selectively delaying the second count signal by the predetermined number of clock delays in response to the carry signal.
~s In accordance with a further aspect of the present invention, there is provided a counter for receiving a carry signal indicative of carry information and providing a counter output equivalent to an integer number of system clock periods. The counter output is generated in response to either one of a long continuing sequence or a short counting sequence. The short counting sequence includes a minimum count.
2o The counter includes: (a) a long count block for stepping through the long counting sequence in response to a first group of timing value inputs and for generating a long count output signal; (b) a short count block for stepping through the short counting sequence in response to a second group of timing value inputs and for generating a short count output signal; (c) an output block for receiving either one of the long 2s output signal or the short output signal and for generating a feedback signal for alternately loading new timing value inputs into either one of the long count block or the short count block; and (d) a first delay means and a second delay means for selectively delaying either one of the long count signal or the second group of timing value inputs by a predetermined number of system clock periods in response to the 3o carry signal.

In accordance with a further aspect of the present invention, there is provided a counter responsive to timing input signals and a carry signals for providing a count output signal, which includes: (a) a first counting block responsive to a first group of timing signals providing a first count sequence for generating a first count signal s upon completion of stepping through the first count sequence; (b) a second counting block responsive to a second group of timing signals providing a second count sequence for generating a second count signal upon completion of a stepping through the second count sequence; (c) a first delay block receiving the first count signal for generating a first delayed count signal; (d) a second delay block receiving ~o the second count signal for generating a second delayed count signal; (e) a first selecting block receiving the first count signal and the first delayed count signal for selectively providing either the first count signal or the first delayed count signal as a first output count signal to a combining block; (f) a second selecting block receiving the second count signal and the second delayed count signal for selectively is providing either the second count signal or the second delayed count signal as a second output count signal to the combining block; and (g) the combining block for combining the first and second output count signals and generating a feedback signal for enabling loading of the first and second counting blocks with new values for the first and second groups of timing signals.
BRIEF DESCRIPTION OF THE DRAWINGS:
Fig. 1 is a block diagram of a high-speed wide range counter according to an embodiment of the invention;
Fig. 2 is detailed schematic illustrating a preferred embodiment of the invention;
2s Fig. 3 is a timing diagram of the embodiment of Fig. 2;
Fig. 4 is a table illustrating all the count states of the counter according to an embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION
There are two factors which limit the speed of operation of a polynomial counter:
the combinatorial logic used to decode the outputs of the shift register stages into a single output, and the feedback path used to drive the counter through its sequence of s valid states. Of these two, the combinatorial logic generates the longest delay. When the speed of operation of a counter is very high, as in the case of counters used in automatic test equipment (ATE), the delay required to properly operate the polynomial counter and produce the correct output result becomes too large compared to the window of operation allocated for the counter to complete this task by the test cycle io pipeline control. As a result, there is a need to insert an additional pipeline delay stage after the output of the counter. This additional pipeline stage delays the output of the polynomial counter by one additional count. If a short count value is required for a particular test cycle, for example a count of 0 or 1, as previously mentioned, the combinatorial decoding logic of a conventional polynomial counter becomes the critical is path of the counter, limiting its speed of operation. According to an embodiment of the invention, one way of recapturing such short count cycles is to separate the overall counter into two parallel counting blocks operating separately where one long cycle counting block is responsible for long counts where the combinatorial logic associated with generating its output is not a constraining issue, and a short cycle count counting 2o block which counts short counts and operates much more quickly than the long cycle counting block by by-passing the large combinatorial logic of the long count counting block.

Fig. 1 is a simplified block diagram of an n-bit high-speed wide range polynomial counter 10 according to an embodiment of the invention. The counter 10 includes a first counting block 12 (designated as Long Cycle Counter or LCC) and a second counting block 14 (designated as Short Cycle Counter or SCC). The first counting block s comprises an (n-m)-bit counter 17, and a carry circuit 9 comprising a latch 13a, and a multiplexes 15a. Counter 17 receives as inputs test cycle timing value signals CTV[(n-1) m], i.e. the most significant bits, a reset signal RSTN, a synchronization signal MARK, a test cycle freeze signal HOLD, and the system clock signal CLK. The RSTN
signal is an asynchronous signal which is used to reset the counter stages. The MARK
signal io defines the timing boundaries of a test cycle by marking the loading (on the next system clock rising edge) of a new test cycle timing value into counter 17. The HOLD
signal allows an ATE user-initiated asynchronous freeze of counter 17 when asserted.
Such a HOLD function is useful in testing data cell retention for example, whereby test data would typically be written into selected cells and in response to the HOLD
signal being is asserted, the test condition would be frozen for a predetermined time to analyze data retention. The latch 13a receives as an input the output of counter 17 and is clocked by the system clock CLK. The output of the counter 17 can be delayed by one clock based on the state of a CARRY signal generated by a fine delay portion (not shown).
The latch 1'3a in conjunction with the multiplexes 15a are used to implement the CARRY
2o function within the pipeline stages where the counter 17 can be considered to be part of pipeline stage p and the carry circuit 9 can be thought of as being part of pipeline stage p+1. Generally, when the CARRY signal is logic '1', the latch 13a introduces one clock delay and provides the output of counter 17 to the multiplexes 15a one clock delay after a its occurrence. The other input of the multiplexer 15a is taken from counter 17 directly without an additional clock delay, thereby allowing the multiplexer 15a to selectively add one clock delay to the output of counter 17 based on the CARRY input. The CARRY
input is provided to the multiplexer 15a through a pipeline latch 19, which is clocked by s a pipeline clock PCLK. The pipeline clock PCLK, as will be described in further detail below, is a pulse which is derived from the MARK signal. The latch 19 is used to align the pipeline CARRY to the output of the counter, i.e. the previous pipeline stage CARRY
is aligned with the current pipeline stage. If CARRY is logic '1', then the output of counter 17 is delayed by one pipeline stage, if CARRY is logic '0', then the output of io counter 17 is not delayed and instead provided directly to the combining circuit 16. For speed performance considerations, the long combinatorial logic delay path of the Long Cycle Counter is realigned to the system clock CLK using the latch 13e.
A second counting block 14 includes an m-bit counter 18 which can be implemented using another polynomial counter, and a second carry circuit 8 comprising is two multiplexers 15b and 15c and three latches 13b, 13c and 13d. The purpose of the second counting block 14 is to rapidly provide the remainder of the full count which cannot be provided by the first counting block 12. Whereas the first block 12 receives test cycle timing values CTV[(n-1 ) : m], the second block 14 receives cycle timing values CTV[(m-1 ) : 0], i.e. the least significant bits. Preferably, m has a value which is 2o significantly smaller than n and m should be as small as possible, for example, m04. As can be seen, the carry circuit 8 in this case is implemented in a pipeline stage prior to the m-bit counter, i.e. before the counter is loaded. As described with reference to the first counting block 17, the second counting block 14 can also be thought of as being distributed over two pipeline stages: the carry circuit 8 is implemented in pipeline stage p and the m-bit counter is implemented in pipeline stage p+1. The m-bit counter 18 receives as inputs the m-bit count value either delayed by one clock through latch 13d or provided directly from test cycle timing value inputs CTV[(m-1) : 0]
depending on the s state of the CARRY input. The CARRY input passes through a delay stage 13b which is clocked by the system clock CLK. If CARRY is logic '1', the cycle timing value inputs are delayed one clock delay through 13d. Alternately if CARRY is logic '0', then the cycle timing value inputs are taken directly as inputs into the multiplexer 15c. Counter 18 also receives the RSTN reset signal as an input for asynchronously resetting the io count value. In addition, the counter 18 receives the MARK synchronization signal either delayed by one clock through latch 13c or passed directly through multiplexer 15b. Optionally, a HOLD signal can also be input into the second counting block 14 (although according to a preferred embodiment, the HOLD signal is not provided to the second counting block due to speed considerations; i.e. the second counting block has is a small number of bits resulting in a small count value, thereby making a hold function not practical since HOLD and MARK cannot be asserted simultaneously). The m-bit counter 18 is clocked by the system clock CLK and provides its Short Count Out output to the combining circuit 16. The multiplexers 15b and 15c are controlled by the output CARRY signal similarly to the way multiplexer 15a was also controlled by the 2o CARRY signal, i.e. through a pipeline latch. The CARRY signal must be stable for the entire counter loading period so a delay of one clock through latch 13b is inserted to ensure this occurs. Therefore multiplexers 15b and 15c are controlled by the CARRY
signal status latched in latch 13b. If the CARRY signal is logic '1' indicating that a carry io has occurred, then multiplexers 15b and 15c select the MARK and CTV inputs which are delayed by one clock delay, 13c and 13d respectively. On the other hand, if CARRY is logic '0', then multiplexers 15b and 15c select the MARK and CTV
inputs which are not delayed by a clock delay. It should be noted that the CARRY
signal is s provided as an input to both the LCC 12 and the SCC 14.
As can be seen, the m-bit counter 18 has the carry function implemented before loading in order to reduce the combinatorial logic delay accumulated by the Short Count Out signal. Consequently, the loading of the MARK signal and CTV[(m-1 0] are conditioned by the CARRY signal. If CARRY is logic '1' these signals are to delayed by one clock, if CARRY is logic '0' these signals are not delayed.
A gate connected to the on the input of the counter 10 can be used to asynchronously stop the counter 10. For example, the CTV inputs can be combined in an AND gate 37 with an active logic '0' STOP signal as shown in Fig. 1.
It should be noted that the first and second counting blocks 12 and 14 Is respectively cannot operate simultaneously since they are intended for two different count functions. The first block 12 is intended for long count values while the second block 14 is intended for short or minimum count values. Therefore the second counting block 14 must have a counting range greater than or equal to the minimum counting range of the first counting block 12; for example according to a preferred embodiment 2o where n=9 , m=1 the full counter range is [511:0] with the first counting block counting over the range [511:1] and the second counting block counting over the range of [0], i.e.
a 1-bit counter. In terms of actual system clock delays, since a minimum count=0 takes 2 system clocks to execute, the range of actual system clock cycles for the counter a would be [513:2] with the first counting block counting [513:3] clocks and the second counting block counting 2 clocks.
The general operation of the high speed test cycle counter 10 of Fig. 1 will now be described. The RSTN reset signal clears the contents of the two counting blocks 12 s and 14, allowing the ATE user to load/program a new test cycle. New cycle timing value inputs are loaded into the counting blocks 12 and 14. The START signal is asserted for one full system clock cycle and counting begins. For counting block 12 which contains the [(n-1):m]-bit polynomial counter 17, the counting proceeds as previously described, by stepping through a pseudo-random sequence of valid states to through the clocked shift register stages based on the cycle timing value inputs CTV. If the user wishes to freeze the test sequence at any time, the HOLD signal is asynchronously asserted and the count sequence is stopped for the specified number of HOLD cycles. By deactivating HOLD, the count sequence is resumed.
As the counter 17 continues through its polynomial count sequence, it will is eventually get to the second last state in the sequence. As will be described in more detail later, this second last state is used to force the polynomial counter 17 into a state which effectively stops the count from resuming again, unlike most conventional polynomial counters which will continue to proceed through the count sequence repeatedly until stopped by external intervention. Once counter 17 has reached the 2o final state in the sequence, it outputs a signal to the pipeline latch 13a which is clocked through to the multiplexer 15a on the next rising edge of the system clock CLK. The last state is also provided directly as the other input to multiplexer 15a.
Based on the state of the CARRY signal and the pipeline clock PCLK, one of the two inputs of multiplexer 15a is provided to the combining circuit 16 on the next rising edge of the system clock CLK. This sequence of operational steps is taken if the period timing value inputs specify a count between (n-1 ) to m, i.e. a long cycle count.
Alternately, for a short cycle count, i.e. a count in the range (m-1 ) : 0, counting s block 14 is used. As in the case of the first counting block 12, the RSTN
reset signal clears the contents of the second counting 14, allowing the ATE user to load/program a new test cycle. New cycle timing value inputs CTV[(m-1 ) : O], i.e. the least significant bits are loaded into the counting blocks 12 and 14. The START signal is asserted and counting begins. Both the MARK signal and the CTV inputs are conditioned on the to state of the CARRY input. If CARRY is logic '0', the MARK and CTV inputs are passed directly to multiplexers 15 and 15c which subsequently provide the m-bit counter 18 with its short count value. Alternately, if CARRY is logic '1', both MARK and CTV
inputs are delayed by one clock delay and the m-bit counter 18 receives its count value one clock delay later. The system clock CLK synchronizes the input of the m-bit value from is multiplexer 15c on the next rising edge of the system clock CLK. The output of counter 18, is then provided to the combining circuit 16 on the next clock rising edge. The output of the combining circuit 16 is combined by NOR gate 31 with the START
signal to produce the MARK signal which is fedback to both the first and second counting blocks 12 and 14 to indicate the beginning of the next count sequence. In the absence 20 of the MARK signal, i.e. for the first count sequence, the START signal alone initiates the counting sequence.
It should be noted that the separation of the overall counter into two separate, parallel counting blocks allows the handling of a wide range of count values including short, minimum counts while optimizing gate utilization. By using the first counting block based on pipeline logic gates to implement long counts and the second counting block based on wide parallel logic gates to implement short counts and then combining the output to provide a final count value, the overall counting function is optimized for high s speeds as required in today's ATE applications since the combinatorial logic delay with polynomial counter decoding stage is avoided in the case of short count values. This implementation also allows the counting blocks to be loaded on a cycle-by-cycle basis since the feedback path provided by the MARK signal provides the counting blocks with new timing values only after the current count is completed.
to A more specific structure of the first and second counting blocks 12 and 18 will now be discussed in more detail with reference to Fig. 2. According to a preferred embodiment of the invention, the high-speed counter 10 comprises the first counting block 12 and the second counting block 14. The first counting block 12 is implemented using a polynomial counter 17 comprising [(n-1):m] shift register stages. In a preferred is embodiment, with n=9 and m=1, counter 17 has 9 stages, starting with stage 9 28, and ending with stage 1 20 and therefore is capable of counting over the range [(2" - 1):m]
or [511:1]. In terms of actual clock cycle delays, given the 2 clock delay for the minimum count, the actual clock cycle range becomes [513:3] clocks. Each of these polynomial counter stages (only 4 of the 9 stages are shown) 28, 24, 21, 20 comprise 2o an input multiplexer controlled by the MARK signal and a conventional D-type flip-flop clocked by the system clock CLK and reset by the RSTN signal. Taking one of the stages as an example, stage 28 consists of D-type flip-flop 28a, an input multiplexer 28b and a second multiplexer 28c. The two multiplexers essentially operate as a 3:1 multiplexer with the following possible conditions: normal LFSR operation (i.e. count sequence), load new cycle timing value, hold count. More specifically, the input multiplexer 28b passes either the test cycle timing value input CTV[9] to load a new cycle value or provides a fedback Q output signal C9 of the flip-flop 28a through s multiplexer 28b under the control of the MARK signal; i.e. when MARK is logic '1', the new cycle timing value input CTV9 is provided to the D-input, and if MARK is logic '0', the output of the second multiplexer 28c is provided to the D-input as part of the normal LFSR count sequence. The second multiplexer 28c provides as its output either the fedback version of the Q-output of the flip-flop 28a or, in the case of the last stage 28 of io the counter, the multiplexer 28c takes the output of a feedback block comprising an AND gate 35 and an exclusive OR gate 34 according to conventional polynomial counter feedback connection practices. Multiplexer 28c is controlled by the HOLD signal which allows values stored in the shift register stages to be frozen for a duration selected by the user. The output of stage 28, i.e. the Q-output of the D-type flip-flop 28a is is provided to a multi-input combining gate which in this implementation is shown as an OR gate 43 as is also provided as an input to the next counting stage 24. All stages in counter 17 have the same structure as stage 28 with the exception of the first stage 20 in which case the Q\ output of the D-type flip-flop 20a is also used in addition to the Q-output. In this case, it is the Q\ output which is provided to the combining gate 43 rather 2o than the Q-output as was the case with all the other counter stages. By providing the Q\
output to the combining gate 43, the counter 17 is able to detect the second last count state prior to count completion. In other words, instead of allowing the counter 17 to continue directly to the final count value and then begin the count cycle again as a is conventional polynomial counter would do, counter 17 uses the second last state to signify the upcoming end of count and feeds this information back to the last stage of the counter to prevent the counter from beginning to cycle through the count sequence once again. More specifically, AND gate 35 inserted in the feedback path is used to s allow counter 17 to detect the second last state in the count sequence and stop counting (after which, the short cycle counter will take over to count the last sequence).
For example in this case, the second last count state will occur when all outputs of the shift register stages except the last one, i.e. stage 20 are all logic '0'.
Since the Q\
output is taken from stage 20 instead of the Q output, this output will also be logic '0'.
to Therefore, all inputs into the OR gate 43 are logic '0'. This condition is fedback into AND gate 35 to produce a logic '0' output which is then fed into the '0' input of multiplexer 28c. Once this state has been detected, counter 17 forces the last sequence, which in this case is designated by code '0x0' (in hexadecimal format - a more detailed description of the count sequence codes will be described later). This is No Op state is usually avoided in conventional polynomial counter design.
However, according to the invention, this No Op state is intentionally loaded into the long cycle counter while passing the remaining counting responsibility to the short cycle counter.
Therefore, one novel feature of the invention is that the No Op state is loaded to stop the counting sequence of the LCC and allow the remainder of the count to be handled 2o by the SCC. As a result, the two counting blocks can operate one at a time to optimize the operation of the entire counting system.
Continuing with the description of Fig. 2, the output of the combining OR gate is inverted through inverter 44 to provide an active logic '1' signal and provided as the output of counter 17 to a latch 54 which introduces one clock delay as described with reference to Fig. 1. The output of combining gate 43 is also provided to the AND gate 35 of the feedback block. The other input of the AND gate 35 is provided by the exclusive OR gate 34, which in turn receives its two inputs from the fifth and first stages s of the counter 17 which are selected to provide the appropriate count operation for the 9 bit counter implementation. The latch 54 is clocked by the system clock CLK
and provides its output to multiplexer 56 which under control of pipeline latch 48 containing the pipeline CARRY information, selects between the output of inverter 44 i.e.
the direct Count Out or latch 54 the Count Out delayed by one system clock CLK. The output of io multiplexer 56 is provided to a second latch 58 which generates the Long Count Out signal which in turn is provided as one of the inputs to the OR gate 60. The other input of OR gate 60 is the Short Count Out signal which is provided from the second counting block 14 as described in Fig. 1. More specifically, with reference to Fig. 2, with m=1, the 1-bit counter 18 is implemented by a D-type flip/flop plus multiplexer combined Is circuit 29 which has the same structure as all the other count stages in the first counting block 17. Multiplexer 46 and 45 correspond to multiplexers 15b and 15c respectively in Fig. 1 and pipeline latches 49, 47, and 50 correspond to pipeline latches 13b, 13c and 13d of Fig. 1 respectively.
The operation of the preferred embodiment of the invention illustrated in Fig.

2o will now be described with reference to timing diagram shown in Fig. 3 and with reference to pseudo-random codes table shown in Fig. 4. A number of representative test cycles are shown (cycle 1-cycle 7) all having different durations and different requirements. For example, while cycles 1-4 are comprised of different user-specified m system clock delays, cycles 5-7 also comprise user-specified hold and carry instructions. Fig. 3 illustrates the various transitions and states of the control signals and counter inputs and outputs for these test cycles. The system clock CLK is a continuous free-running clock which runs at a predetermined frequency. The START, s and HOLD signals are provided by ATE user input. The CARRY signal is provided as a feedback from fine delay circuits (not shown) indicating the accumulation of fine delays equal to one full system clock delay.
Prior to the beginning of cycle 1, the START signal is asserted by ATE user input for one full system clock and the cycle timing values for cycle 1, i.e. the minimum count to value count=0 (requiring a minimum of 2 system clocks, i.e. 2CLK and designated as 1 in hexadecimal format as shown in Fig. 4) is provided to the input of the counter. As previously explained, this minimum count is handled by the second counting block 14.
The MARK signal, generated by the START signal through OR gate 31, marks the beginning of cycle 1 and, on the first subsequent rising edge of the system clock CLK
is following the beginning of cycle 1, the counter is loaded with the test cycle timing value of 1 and begins stepping through the count sequence , as shown by the Counter Status timing line. The "1" status is the first step in the sequence followed by "0", the final step in this sequence. The pipeline clock pulse PCLK is generated one clock delay after assertion of the MARK signal. The PCLK clocks the CARRY information into the 2o current counting cycle. In the case of cycle 1, the CARRY signal is logic '0' so it has no effect on the count. On the second rising edge of the system clock CLK after the beginning of cycle 1, the counter provides the completed count signal Count Out to subsequent circuitry in the pipeline as well as to NOR gate 31. The feedback path is through NOR gate 31 reasserts the MARK signal marking the beginning of the next test cycle, cycle 2.
Cycle 2 has a count value count=1 (requiring 3CLK delays as shown in Fig. 4, which is designated as 2 in hexadecimal format). This desired count value is loaded s into the counting block 14 on the rising edge of the system clock following the assertion of the MARK signal. Stage C9=0, ... stage C5=0, stage C2=0 and stage C1=1, all generate a logic "1" on the output of OR gate 43. One system clock later, Long Count Out goes to a logic "1", making Count Out go to a logic"1" through OR
gate 60 and eventually MARK go to a logic "1" through OR gate 31. Pipeline clock to pulse PCLK, is once again generated on the next rising edge of the system clock CLK
following the assertion of the MARK signal, thereby providing the CARRY for the current pipeline stage. The counter once again steps through its sequence of count states, 2,0,0 in this case as shown in the Counter Status timing line. Once the last count is detected, AND gate 35 is turned off thereby turning off the Long Cycle Counter. Once is the final count state has been counted by the Short Cycle Counter, the Count Out signal is asserted which in turn reasserts the MARK signal and begins cycle 3.
Cycle 3 is identical to cycle 1, requiring a count=0 to be performed as previously described except that the cycle is initiated by the rising edge of MARK rather than the START signal. The first clock in cycle 3, as in all cycles, is required to generate the 2o rising edge of MARK.
In cycle 4, a count value count=2 is requested by the test cycle timing inputs (corresponding to 4 in hexadecimal format and taking 4CLK to complete as indicated in Fig. 4). As with the preceding cycles, the rising edge of the MARK signal initiates cycle 4 and on the rising edge of the system clock following the assertion of the MARK signal, the counter loads the new CTV value. Pipeline clock pulse PCLK, is once again generated on the next rising edge of the system clock CLK following the assertion of the MARK signal, thereby providing the CARRY for the current pipeline stage. The counter s steps through the counting sequence, 4,2,0,0 in this case, as shown in the Counter Status timing line. Once the counter has completed its count, which in this case is performed by the first counting block 12, the MARK signal is reasserted and cycle 5 begins.
Cycle 5 comprises a count value count=2 (4 in hexadecimal) and 2 HOLD
io instructions. The MARK signal initiates cycle 5 and the Counter Status line provides the corresponding counter states which in this case start off with 4 followed by 2. At that point, the 2 HOLD instruction causes the counter to hold the current state for 2 clock cycles, creating two more states of 2 on the Counter Status line. After the 2HOLD has been completed, HOLD is de-asserted and the counter continues to finish the 4 CLK
Is count, by stepping to the final two count states 0, 0 as shown in the Counter Status timing line. The Count Out output is pulsed at the end of the cycle 5 and reasserts the MARK signal, thereby initiating cycle 6. It should also be noted that a CARRY
signal is asserted during cycle 5 in preparation for the next cycle, cycle 6 which requires a CARRY.
2o Cycle 6 begins much the same as has been already discussed with a count value count=0, requiring 2CLK cycles. However, since a CARRY has been input as part of this test cycle, loading of the count value is delayed by one clock cycle, shown in the Counter Status line by an additional 1 state. This is because since the count=0 is performed by the short cycle counter block 14, the CARRY signal is provided to the input stage of that block, i.e. latch 50 and delays the input of the CARRY
signal by one clock delay. On the third rising edge of the system clock CLK after the beginning of cycle 6, the Counter Status timing line shows the value 1, i.e. the first step in the s count=0 sequence, which is followed by 0 which is the second and final state in the count=0 sequence. Once the count completes, the Count Out signal is asserted which reasserts the MARK signal signifying the beginning of cycle 7.
Test cycle 7 consists of a count=2 and a CARRY. The counter proceeds much the same as described above with reference to cycle 6 except that in this case, the to CARRY signal is applied after the counter (first counting block 12) has completed its count to multiplexer 56. As shown in the Counter Status timing line, the count sequence 4,2,0,0 corresponding to count=2 (4 in hexadecimal format requiring 4CLK to complete) is followed by the CARRY delay, shown as an additional 0 state. Once the count is complete the Count Out signal is asserted which reasserts MARK thereby beginning is the next cycle (not shown). Note that for CT=2, the sequence proceeds from state 4 to 2 and when state 2 is detected, the remaining state, i.e. 1 is then subsequently counted by the short cycle counter. In general, all the states in the counter sequence beyond 2 are handled by the long cycle counter and the last state, 1 is handled by the short cycle counter, as shown in Fig. 4. The two counting blocks LCC and SCC therefore operate 2o in an alternating mode.
It is also important to note that in the last two cycles, cycle 6 and cycle 7, the CARRY was handled differently as described with reference to Fig. 2. In the case of cycle 6, since the count required was a minimum count, the CARRY was applied to the input of the counter, thereby by-passing combinatorial logic delays associated with the first counting block 12. On the other hand, in the case of cycle 7, since the count required was larger than the minimum count, the CARRY was applied after the output of the first counting block 12. In this manner, both long and short counts can be flexibly s and rapidly processed using maximum gate utilization.
Although only 7 test cycles have been illustrated, it can be appreciated that similar cycles and corresponding signal behaviour would arise given the many other count states outlined in Fig. 4.
A high speed wide range counter for ATE applications comprising two counting Io blocks has been described. The counter includes a first counting block responsible for handling long count values and a second counting block responsible for handling short count values including a minimum count. The counter receives a carry input from fine delay circuitry. The first counting block is based on pipelined logic and combinatorial circuitry whereas the second counting block is based on wide parallel logic circuitry.
is Only one of the two counting blocks are active at any time and their outputs are combined to provide an overall counter output.
The embodiments of the invention described above are provided only as illustrations and should not be construed as limiting the scope of the present invention.
Numerous modifications and improvements may occur to those skilled in the art.
2o Therefore, it is to be understood that this invention is not limited to the illustrated embodiments but rather any number of alternate embodiments which are covered by the appended claims.

Claims (5)

What we claim is:

1. A counter responsive to timing input signals and a carry signals for providing a count output signal comprising:
(a) a first counting block responsive to a first group of timing signals providing a first count sequence for generating a first count signal upon completion of stepping through said first count sequence;
(b) a second counting block responsive to a second group of timing signals providing a second count sequence for generating a second count signal upon completion of a stepping through said second count sequence;
(c) a combining block for combining the first and second count signals and generating a feedback signal for enabling loading of the first and second counting blocks with new values for said first and second groups of timing signals;
(d) a first selecting block for selectively delaying said first count signal by a predetermined number of clock delays in response to said carry signal; and (e) a second selecting block for selectively delaying the second count signal by the predetermined number of clock delays in response to said carry signal.

2. The counter of claim 1, wherein said first counting block is comprised of an n-stage linear feedback shift register.

3. A counter for receiving a carry signal indicative of carry information and providing a counter output equivalent to an integer number of system clock periods, said counter output being generated in response to either one of a long continuing sequence or a short counting sequence, said short counting sequence including a minimum count, said counter comprising:

(a) a long count block for stepping through said long counting sequence in response to a first group of timing value inputs and for generating a long count output signal;
(b) a short count block for stepping through said short counting sequence in response to a second group of timing value inputs and for generating a short count output signal;
(c) an output block for receiving either one of said long output signal or said short output signal and far generating a feedback signal for alternately loading new timing value inputs into either one of said long count block or said short count block; and (d) a first delay means and a second delay means for selectively delaying either one of said long count signal or said second group of timing value inputs by a predetermined number of system clock periods in response to said cany signal.

4. The counter of claim 3, wherein said tong count block is comprised of a linear feedback shift register having n stages.

5. A counter responsive to timing input signals and a carry signals for providing a count output signal comprising:
(a) a first counting block responsive to a first group of timing signals providing a first count sequence for generating a first count signal upon completion of stepping through said first count sequence;
(b) a second counting block responsive to a second group of timing signals providing a second count sequence for generating a second count signal upon completion of a stepping through said second count sequence;
(c) a first delay block receiving said first count signal for generating a first delayed count signal;
(d) a second delay block receiving said second count signal for generating a second decayed count signal;

(e) a first selecting block receiving said first count signal and said first delayed count signal for selectively providing either the first count signal or the first delayed count signal as a first output count signal to a combining block;
(f) a second selecting block receiving said second count signal and said second delayed count signal for selectively providing either the second count signal or the second delayed count signal as a second output count signal to said combining block; and (g) the combining block for combining the first and second output count signals and generating a feedback signal for enabling loading of the first and second counting blocks with new values for said first and second groups of timing signals.