CA2309032A1 - Device and method for generating orthogonal codes in mobile communication system - Google Patents
Device and method for generating orthogonal codes in mobile communication system Download PDFInfo
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- CA2309032A1 CA2309032A1 CA002309032A CA2309032A CA2309032A1 CA 2309032 A1 CA2309032 A1 CA 2309032A1 CA 002309032 A CA002309032 A CA 002309032A CA 2309032 A CA2309032 A CA 2309032A CA 2309032 A1 CA2309032 A1 CA 2309032A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J13/00—Code division multiplex systems
- H04J13/10—Code generation
- H04J13/12—Generation of orthogonal codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J13/00—Code division multiplex systems
- H04J13/0007—Code type
- H04J13/004—Orthogonal
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/02—Channels characterised by the type of signal
- H04L5/023—Multiplexing of multicarrier modulation signals
- H04L5/026—Multiplexing of multicarrier modulation signals using code division
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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Abstract
A device and method for generating orthogonal codes differing in length according to symbol rates. An orthogonal code length corresponding to a variable symbol rate is calculated to determine an effective bit number. A
chip count value is sequentially generated up to a maximum value, which can be counted by the effective bit number. An orthogonal code is generated by a logic operation of an orthogonal code index which is converted into the binary number of the effective bit number and the sequentially generated chip count values.
chip count value is sequentially generated up to a maximum value, which can be counted by the effective bit number. An orthogonal code is generated by a logic operation of an orthogonal code index which is converted into the binary number of the effective bit number and the sequentially generated chip count values.
Description
DEVICE AND_METHOD FOR GENERATING ORTHOGONAL CODES
IN MOBILE COMMUNICATION SYSTEM
BACKGROUND OF THE INVENTION
1. Field of the Invention The present invention relates to a device and method for generating orthogonal codes in a mobile communication system, and in particular, to a device and method for generating orthogonal codes differing in length according to various symbol rates.
IN MOBILE COMMUNICATION SYSTEM
BACKGROUND OF THE INVENTION
1. Field of the Invention The present invention relates to a device and method for generating orthogonal codes in a mobile communication system, and in particular, to a device and method for generating orthogonal codes differing in length according to various symbol rates.
2. Descr~tion of the Related Art Typically, orthogonal codes are used for spreading channels and for distinguishing between channels as identifiers. In a conventional transmitter using an IS-95 CDMA system, a Walsh code (which is one form of the orthogonal code) having a 64-chip length has been used to maintain orthogonality between channels and to spread bands. By using the 64-chip Walsh code, a band spreading rate of 1.2288 Mcps is obtained, since the symbol rates of coded data for various channels which are provided from a modulator of the transmitter to a spreader are uniformly maintained at 19.2 Kbps. For this, a 64 x 64 Walsh code table has been used.
However, in a CDMA-2000 (Code Division Multiple Access-2000) mobile communication system applied to an IMT-2000 system, for example, symbol rates of data provided to a spreader in the process of modulating forward channels differ according to channel types, and thus Walsh codes having lengths which vary with the channels are needed.
To generate Walsh codes having different lengths in a conventional way, Walsh code tables are provided which correspond to the different lengths. This requires multiple varying memories, while still making it difficult to flexibly use Walsh codes having different lengths according to various symbol rates.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a device and method for generating orthogonal codes differing in length according to various symbol rates in a mobile communication system.
It is another object of the present invention to provide a device and method for generating orthogonal codes by an orthogonal code index and a chip count in a mobile communication system.
In accordance with one aspect of the present invention, a device for generating orthogonal codes in a mobile communication system includes a memory having registers for respectively storing an effective bit number, an orthogonal code index and a chip count value, and an orthogonal code generating circuit for sequentially generating the chip count value up to a maximum value which can be counted by the effective bit number, and generating an orthogonal code by logic operation of the orthogonal code index and the sequentially generated chip count values.
In accordance with another object of the present invention, a method for generating orthogonal codes in a mobile communication system includes the steps of: calculating an orthogonal code length corresponding to a variable symbol rate;
determining an effective bit number by the calculated orthogonal code length;
sequentially generating a chip count value up to a maximum value which can be counted by the effective bit number; converting an orthogonal code index into a binary number of the effective bit number; and performing a logic operation of the orthogonal code index converted into the binary number and the sequentially generated chip count values to generate an orthogonal code.
BRIEF DESCRIPTION OF THE DRAWINGS
The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which:
FIG. 1 is a block diagram illustrating a modulator of a mobile communication system according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating an orthogonal code generating process expressed by an equation according to an embodiment of the present invention;
and FIG. 3 is a circuit diagram illustrating the orthogonal code generator illustrated in FIG. 1.
DETAILED .DESCRIPTION OF THE PREFERRED EMBODIMENT
A preferred embodiment of the present invention will be described hereinbelow with reference to the accompanying drawings. In the following description, well-known functions or constructions are not described in detail as not to obscure the invention in unnecessary detail.
FIG. 1 illustrates a modulator of a mobile communication system according to an embodiment of the present invention. The description of the modulator will be focused on parts relating to orthogonal spreading.
Referring to FIG. l, a demultiplexer (DEMUR) & signal mapping circuit 1 11 demultiplexes input symbol data (or coded data) to separately output an I-channel (or first channel) signal and a Q-channel (or second channel) signal.
The DEMUR & signal mapping circuit 111 also converts a level of the symbol data, for instance, "0" into "+1" and "1" into "-1". First and second channel gain controllers 115 and 116 control gains of the first and second channel signals output from the DEMUR & signal mapping circuit 111, respectively, by a gain control signal provided by a controller 113. A memory 112 stores data for various programs and data temporarily generated in the course of executing the programs.
The memory 112 includes a register having information about orthogonal code lengths varying with symbol rates of channels, a register having orthogonal code indexes assigned to the channels, and a register having chip counts, which are obtained by counting one symbol to be orthogonally spread by a corresponding chip clock. The information about the orthogonal code lengths, which is described below, can be defined as a meaning to restrict an actually effective bit number of the orthogonal code index and chip count. The controller 113 controls the overall operation of the modulator. More particularly, the controller 113 reads parameters relating to generating the orthogonal code from the memory 112 and provides the parameters to an orthogonal code generator 114 of each channel generator. The orthogonal code generator 114 generates a corresponding -S-orthogonal code according to the orthogonal code length information (i.e., the effective bit number), orthogonal code index and chip count provided from the controller 113. First and second multipliers 117 and 118 multiply the first and second channel signals output from the first and second channel gain controllers S 1 15 and 116 by the orthogonal code to generate orthogonally modulated first and second channel signals IW and QW, respectively.
In achieving a device for generating the orthogonal code according to the present invention, the memory 112, controller 113, and orthogonal code generator 114 may be indispensable constituents. To refer to both the controller 113 and orthogonal code generator 114, the term "orthogonal code generating circuit"
will be used.
In the orthogonal spreading operation of the modulator above, the coded data (or symbol data) is separated by the DEMUR & signal mapping circuit 111 I S into the first and second channel signals. The separated signals are gain-controlled by the first and second channel gain controllers 115 and I16, as instructed by the controller 113. The gain-controlled first and second channel signals are respectively provided to the first and second multipliers 117 and 118.
The controller 113 receives the orthogonal code length corresponding to a symbol rate of the coded data, the chip count and the orthogonal code index to be assigned to the channel. Those parameters are obtained by accessing the registers contained in the memory 112 and provided to the orthogonal code generator 114 of a con-esponding channel generator. The orthogonal code generator 114 then generates a corresponding orthogonal code through a program stored in its internal DSP (Digital Signal Processor) or through an ASIC (Application Specific Integrated Circuit). The generated orthogonal code is provided to the multipliers 117 and 118. The multipliers 117 and 118 respectively multiply the gain-controlled first and second channel signals output from the first and second cham~el gain controllers 115 and 116 by the orthogonal code, to generate the orthogonally modulated first and second channel signals IW and QW
corresponding to the I and Q channels, respectively.
The process of generating the orthogonal code will now be described in more detail. The orthogonal code generating process is executed by the orthogonal code generating circuit, which consists of the controller 113 and the orthogonal code generator 114. It should be noted that the orthogonal code length information is used interchangeably as the effective bit number.
The orthogonal code generating process is broadly divided into two steps;
a first step of generating information needed to generate the orthogonal code, and a second step of generating the orthogonal code based on the generated information. The information needed is the orthogonal code index assigned to each channel, the chip count obtained by counting one symbol period by a chip clock, and the orthogonal code length.
The first step of generating the information based on the orthogonal code index, chip count and orthogonal code length will now be described.
In the CDMA-2000 system, a symbol rate of data provided to a spreader in the process of modulating forward channels differs according to channel types, unlike the conventional IS-95 CDMA system. To uniformly adjust a band spreading rate, orthogonal code lengths become different according to the different symbol rates. For instance, the orthogonal code lengths may have 8, 16, 32, O4, 128, 256, 512, and 1024 chips. If the band spreading rate is 3.6864 Mcps, and the symbol rates of data provided to the spreader are 14.4 Kbps, 28.8 Kbps, 57.0 Kbps and 115.2 Kbps, the orthogonal code lengths become 256 chips, 128 chips, 64 chips and 32 chips to produce the band spreading rate of 3.6864 Mcps.
That is, S
14.4 Kbps x 25G chips = 3.G8G4 Mcps 28.8 Kbps x 128 chips = 3.6864 Mcps 57.G Kbps x 64 chips = 3.6864 Mcps 115.2 Kbps x 32 chips = 3.6864 Mcps Thus, the orthogonal codes having different lengths according to the various symbol rates of data provided to the spreader are generated to obtain a uniform band spreading rate. To this goal, a processor for controlling the modulator provides information relating to the orthogonal code length to the modulator. As an example, the orthogonal code lengths varying according to the symbol rates can be expressed by 2 raised to the power of a prescribed number.
For instance, 4 = 22, 8 = 23, 1G = 24,..., and 1024 = 2'°.
As noted above, the base corresponding to each orthogonal code length is 2 and only the exponent differs. Therefore, the orthogonal code length information determined by the symbol rate uses the exponent. The processor provides the exponent to the modulator as orthogonal code length information I.
The range of an orthogonal code index n assigned to each channel and a chip count t, which is obtained by counting one symbol period using a chip clock, can flexibly be enlarged or reduced by the various orthogonal code lengths 4, 8, 1 O, O4, 128,~.., WO 00/13431 PC'T/KR99/00494 _g_ More particularly, the orthogonal code index n and the chip count t are each determined within the same range of 0 <_ n, t <_ 2'-1. The orthogonal code index indicates a value expressing one of the integers within the above range as a binary number of I bits. The chip count sequentially designates an integer within the above range by a binary number of I bits. Assuming that the orthogonal code length information I is 4, the orthogonal code index becomes a binary number expressing one of integers 0 to 15 as 4 bits. As the chip count, binary number values of 4 bits, that is, 0000 through 1111 are sequentially provided to designate integers ranging from 0 to 15. Although the above example restricts the bit number of the orthogonal code index and chip count to I bits, the bit number need not be restricted. Namely, it is possible to assign the bit number of the orthogonal code index and chip count up to the maximum bit number. Then aII bits except actually effective bits among the assigned bit number are set to "0". The maximum bit number is determined on the basis of the longest Walsh code used 1 S in a mobile communication system. The actually effective bits represent the bit number of the orthogonal code index and chip count. For instance, if the longest Walsh code which is usable in the mobile communication system is 128 (=2') chips, the maximum bit number is 7 bits.
Consequently, if the symbol rate is designated, the orthogonal code length is determined by the designated symbol rate, and the range of the chip count and the orthogonal code index are determined by the orthogonal code length. Once the range of the chip count is determined, the chip count is sequentially increased within the determined range. The orthogonal code length, the orthogonal code index, and the increased chip count are provided as information for generating the orthogonal code. If the orthogonal code generator 114 has a function which can estimate the orthogonal code length by the orthogonal code index, the controller _9_ 113 need not provide the orthogonal code length information.
1n the second step, the orthogonal code is generated by using the orthogonal code length information, the orthogonal code index assigned to each channel, and the chip count which are provided from the processor. That is, an algorithm is supplied with the orthogonal code length information in addition to the orthogonal code index and chip count so that the orthogonal codes of differing length can be generated.
The processor for controlling the modulator determines the orthogonal code length information based on the symbol rate and provides this information to the orthogonal code generator 114, thereby generating the orthogonal code having a variable length according to the symbol rate. The orthogonal code of a necessary length is generated by restricting the number of digits of the orthogonal code index n and chip count t expressed as a binary number through the orthogonal code length information. This can be represented by Equation l:
[Equation 1 ]
W(I,n,t)=(n~_, xt,_,). . .(n4xt4)~(n3xt3)~(n2xt2)~(n, xt~ )~{noxtO) where I is orthogonal code length information (i.e., 2, 3, 4,...), n is an orthogonal code index assigned to each channel, and t is a chip count obtained by counting one symbol period by a chip clock.
1f the orthogonal code length information, the orthogonal code index and the chip count are designated by Equation 1, a corresponding one-chip orthogonal code is generated. As can be appreciated from Equation l, an effective calculation range is determined by the orthogonal code length information I. Meanwhile, the orthogonal code of one bit is obtained by logic operation of bits constituting the chip count and bits constituting the orthogonal code index within the effective calculation range. That is, the chip count and the orthogonal code index are ANDed in the unit of bits and the ANDed results are XORed.
The effective calculation range determined according to the orthogonal code length information I is illustrated in FIG. 2. If the orthogonal code length information I is 3 (=011), the range of the chip count t is 0 to 7, and the orthogonal code index n is 3 (i.e., n2,n~,no 0,1,1), a one-chip orthogonal code is generated using the range corresponding to a reference numeral 214 shown in FIG. 2. That is:
W(3,3,t) _ (n2xt2)~(n,xt~)~(noxto) wheren=(O11)and0_<t<_7.
There fore, for t = 0(000), W(3,3,0) _ (0x0)~( 1 x0)~( 1 x0) = 0;
for t = I {001 ), W(3,3,1 ) _ (0x0)~( 1 x0)~( 1 x 1 ) = 1;
for t = 2(010), W{3,3,2) _ (0x0)~( 1 x 1 )~( 1 x0) = 1;
for t = 3(01 I _ (0x0)~( 1 x 1 )~( ), W(3,3,3) 1 x 1 ) = 0;
for t = 4( 100), _ (Ox 1 )~( 1 x0)~( W(3,3,4) 1 x0) = 0;
for t = 5(101), _ (0x1)~(1x0)~(1x1) W(3,3,5) = 1;
for t = 6( 110), _ (Ox 1 )~( 1 x 1 )~( W(3,3,6) 1 x0) = 1; and for t = 7( 1 I 1 ), W(3,3,7) _ (Ox 1 )m( 1 x 1 )~( 1 x 1 ) = 0.
Finally, an orthogonal code (0 1 1 0 0 1 1 0) is generated. The orthogonal code generating process based on Equation 1 can be expressed by Equation 2, which is written in C language:
[Equation 2]
Walsh(int length, int index, int count) int i, we = 0;
for (i = 0; i<length; i++) we = we~(((index » i)&0x01 )&((count » i) & 0x01 ) return(wc);
where i is a temporary count parameter; we is a parameter in which a final value is to be stored; length is a parameter having an orthogonal code length information value determined according to the symbol rate; index is an orthogonal code index assigned to a channel; and count is a chip count obtained by counting one symbol period by a chip clock.
The range of the chip count differs according to the orthogonal code length as listed below in Table 1:
[Table 1 ]
Length Count range Orthogonal Code Length 2 0~3 -The orthogonal code generating process may be achieved by a program as shown in Equation 2 on a DSP or by algorithm such as HDL (Hardware Development Language) on an ASIC.
An example for achieving the orthogonal code generator on the ASIC is illustrated in FIG. 3. Refernng to FIG. 3, the orthogonal code generator includes an AND gate circuit 310 consisting of a plurality of AND gates 310 0,...,310 M-1 and an XOR gate 320. The number of AND gates constituting the AND gate circuit 310 is the same as the maximum bit number determined on the basis of the longest orthogonal code. If the orthogonal code lengths are 4, 8, 16, 32, 64 and 128 chips, the number of the AND gates is determined on the basis of 128 (=
2') chips. In this case, the number of the AND gates will be 7, which corresponds to the bit number, the orthogonal code index, and chip count. When the orthogonal code having a length shorter than the longest orthogonal code length is generated, all bits other than the actually effective bits are considered to be "0". In other words, bits except the actually effective bits are considered masked to "0".
The AND gates 310 0,...,310 M-1 each perform an AND operation of a con-esponding bit of the orthogonal code index and a corresponding bit of the chip count. The XOR gate 320 performs an XOR operation of the outputs of the AND gate circuit 310 to generate one bit constituting the orthogonal code. A
reference symbol Walsh Index is a register for storing the orthogonal code index to be calculated; Chip count is a register for storing the current chip count;
Walsh-code is a currently calculated orthogonal code value; and M is a value expressing the longest orthogonal code length as 2 to the power of a prescribed number (for instance, if the longest orthogonal code length is 128 chips, M is 7).
The operation of the orthogonal code generator of FIG. 3 will now be described by way of example, on the assumption that the orthogonal code length information I is 3(011), the chip count t is 0-7, and the orthogonal code index n is 3(n,, n,, no = 0, 1, 1). It is also assumed that the longest orthogonal code length is 128 chips, that is, M is 7. Therefore, the number of the AND gates actually required by the orthogonal code information I (= 3) is restricted to 3.
As the orthogonal code index, the actual information 011 is continuously provided together with 4 bits masked to "0". As the chip count, 4 bits masked to "0" and 3 least significant bits varying from 000 to 111 are provided. The output of the AND gate circuit 310 according to the orthogonal code index and the chip count is listed in below in Table 2.
[Table 2]
Orthogonal Chip Output Code Count (q) Index (n) of (n) AND
Gate n" n;n, n, n_ n, no tV is t, t, tz t~ to qb qs q4 q3 qz q~ 90 The outputs qo to qG of the AND gates 310 0,...,310 M-1 are provided to the XOR gate 320. The XOR gate 320 generates the orthogonal code "01100110"
by XOR operation of the outputs qo to qb.
In the preferred embodiment of the present invention, the controller 113 has determined the information for generating the orthogonal code, including the chip count, and provided the information to the orthogonal code generator 114.
However, the controller 113 may provide only the orthogonal code length and orthogonal code index, and the orthogonal code generator 114 generates the chip count. In this case, the orthogonal code generator should include a counter to generate the chip count based on the orthogonal code length.
As described above, since the orthogonal codes having different lengths according to the symbol rates can be generated, the present invention may usefully be applied to a CDMA-2000 mobile communication system in which symbol rates vary according to channel types. Furthermore, since there is no need to make various types of orthogonal code tables corresponding to the different orthogonal code lengths, multiple varying memories are not required and the hardware configuration can be realized by a common structure which is applicable to various symbol rates.
While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
However, in a CDMA-2000 (Code Division Multiple Access-2000) mobile communication system applied to an IMT-2000 system, for example, symbol rates of data provided to a spreader in the process of modulating forward channels differ according to channel types, and thus Walsh codes having lengths which vary with the channels are needed.
To generate Walsh codes having different lengths in a conventional way, Walsh code tables are provided which correspond to the different lengths. This requires multiple varying memories, while still making it difficult to flexibly use Walsh codes having different lengths according to various symbol rates.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a device and method for generating orthogonal codes differing in length according to various symbol rates in a mobile communication system.
It is another object of the present invention to provide a device and method for generating orthogonal codes by an orthogonal code index and a chip count in a mobile communication system.
In accordance with one aspect of the present invention, a device for generating orthogonal codes in a mobile communication system includes a memory having registers for respectively storing an effective bit number, an orthogonal code index and a chip count value, and an orthogonal code generating circuit for sequentially generating the chip count value up to a maximum value which can be counted by the effective bit number, and generating an orthogonal code by logic operation of the orthogonal code index and the sequentially generated chip count values.
In accordance with another object of the present invention, a method for generating orthogonal codes in a mobile communication system includes the steps of: calculating an orthogonal code length corresponding to a variable symbol rate;
determining an effective bit number by the calculated orthogonal code length;
sequentially generating a chip count value up to a maximum value which can be counted by the effective bit number; converting an orthogonal code index into a binary number of the effective bit number; and performing a logic operation of the orthogonal code index converted into the binary number and the sequentially generated chip count values to generate an orthogonal code.
BRIEF DESCRIPTION OF THE DRAWINGS
The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which:
FIG. 1 is a block diagram illustrating a modulator of a mobile communication system according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating an orthogonal code generating process expressed by an equation according to an embodiment of the present invention;
and FIG. 3 is a circuit diagram illustrating the orthogonal code generator illustrated in FIG. 1.
DETAILED .DESCRIPTION OF THE PREFERRED EMBODIMENT
A preferred embodiment of the present invention will be described hereinbelow with reference to the accompanying drawings. In the following description, well-known functions or constructions are not described in detail as not to obscure the invention in unnecessary detail.
FIG. 1 illustrates a modulator of a mobile communication system according to an embodiment of the present invention. The description of the modulator will be focused on parts relating to orthogonal spreading.
Referring to FIG. l, a demultiplexer (DEMUR) & signal mapping circuit 1 11 demultiplexes input symbol data (or coded data) to separately output an I-channel (or first channel) signal and a Q-channel (or second channel) signal.
The DEMUR & signal mapping circuit 111 also converts a level of the symbol data, for instance, "0" into "+1" and "1" into "-1". First and second channel gain controllers 115 and 116 control gains of the first and second channel signals output from the DEMUR & signal mapping circuit 111, respectively, by a gain control signal provided by a controller 113. A memory 112 stores data for various programs and data temporarily generated in the course of executing the programs.
The memory 112 includes a register having information about orthogonal code lengths varying with symbol rates of channels, a register having orthogonal code indexes assigned to the channels, and a register having chip counts, which are obtained by counting one symbol to be orthogonally spread by a corresponding chip clock. The information about the orthogonal code lengths, which is described below, can be defined as a meaning to restrict an actually effective bit number of the orthogonal code index and chip count. The controller 113 controls the overall operation of the modulator. More particularly, the controller 113 reads parameters relating to generating the orthogonal code from the memory 112 and provides the parameters to an orthogonal code generator 114 of each channel generator. The orthogonal code generator 114 generates a corresponding -S-orthogonal code according to the orthogonal code length information (i.e., the effective bit number), orthogonal code index and chip count provided from the controller 113. First and second multipliers 117 and 118 multiply the first and second channel signals output from the first and second channel gain controllers S 1 15 and 116 by the orthogonal code to generate orthogonally modulated first and second channel signals IW and QW, respectively.
In achieving a device for generating the orthogonal code according to the present invention, the memory 112, controller 113, and orthogonal code generator 114 may be indispensable constituents. To refer to both the controller 113 and orthogonal code generator 114, the term "orthogonal code generating circuit"
will be used.
In the orthogonal spreading operation of the modulator above, the coded data (or symbol data) is separated by the DEMUR & signal mapping circuit 111 I S into the first and second channel signals. The separated signals are gain-controlled by the first and second channel gain controllers 115 and I16, as instructed by the controller 113. The gain-controlled first and second channel signals are respectively provided to the first and second multipliers 117 and 118.
The controller 113 receives the orthogonal code length corresponding to a symbol rate of the coded data, the chip count and the orthogonal code index to be assigned to the channel. Those parameters are obtained by accessing the registers contained in the memory 112 and provided to the orthogonal code generator 114 of a con-esponding channel generator. The orthogonal code generator 114 then generates a corresponding orthogonal code through a program stored in its internal DSP (Digital Signal Processor) or through an ASIC (Application Specific Integrated Circuit). The generated orthogonal code is provided to the multipliers 117 and 118. The multipliers 117 and 118 respectively multiply the gain-controlled first and second channel signals output from the first and second cham~el gain controllers 115 and 116 by the orthogonal code, to generate the orthogonally modulated first and second channel signals IW and QW
corresponding to the I and Q channels, respectively.
The process of generating the orthogonal code will now be described in more detail. The orthogonal code generating process is executed by the orthogonal code generating circuit, which consists of the controller 113 and the orthogonal code generator 114. It should be noted that the orthogonal code length information is used interchangeably as the effective bit number.
The orthogonal code generating process is broadly divided into two steps;
a first step of generating information needed to generate the orthogonal code, and a second step of generating the orthogonal code based on the generated information. The information needed is the orthogonal code index assigned to each channel, the chip count obtained by counting one symbol period by a chip clock, and the orthogonal code length.
The first step of generating the information based on the orthogonal code index, chip count and orthogonal code length will now be described.
In the CDMA-2000 system, a symbol rate of data provided to a spreader in the process of modulating forward channels differs according to channel types, unlike the conventional IS-95 CDMA system. To uniformly adjust a band spreading rate, orthogonal code lengths become different according to the different symbol rates. For instance, the orthogonal code lengths may have 8, 16, 32, O4, 128, 256, 512, and 1024 chips. If the band spreading rate is 3.6864 Mcps, and the symbol rates of data provided to the spreader are 14.4 Kbps, 28.8 Kbps, 57.0 Kbps and 115.2 Kbps, the orthogonal code lengths become 256 chips, 128 chips, 64 chips and 32 chips to produce the band spreading rate of 3.6864 Mcps.
That is, S
14.4 Kbps x 25G chips = 3.G8G4 Mcps 28.8 Kbps x 128 chips = 3.6864 Mcps 57.G Kbps x 64 chips = 3.6864 Mcps 115.2 Kbps x 32 chips = 3.6864 Mcps Thus, the orthogonal codes having different lengths according to the various symbol rates of data provided to the spreader are generated to obtain a uniform band spreading rate. To this goal, a processor for controlling the modulator provides information relating to the orthogonal code length to the modulator. As an example, the orthogonal code lengths varying according to the symbol rates can be expressed by 2 raised to the power of a prescribed number.
For instance, 4 = 22, 8 = 23, 1G = 24,..., and 1024 = 2'°.
As noted above, the base corresponding to each orthogonal code length is 2 and only the exponent differs. Therefore, the orthogonal code length information determined by the symbol rate uses the exponent. The processor provides the exponent to the modulator as orthogonal code length information I.
The range of an orthogonal code index n assigned to each channel and a chip count t, which is obtained by counting one symbol period using a chip clock, can flexibly be enlarged or reduced by the various orthogonal code lengths 4, 8, 1 O, O4, 128,~.., WO 00/13431 PC'T/KR99/00494 _g_ More particularly, the orthogonal code index n and the chip count t are each determined within the same range of 0 <_ n, t <_ 2'-1. The orthogonal code index indicates a value expressing one of the integers within the above range as a binary number of I bits. The chip count sequentially designates an integer within the above range by a binary number of I bits. Assuming that the orthogonal code length information I is 4, the orthogonal code index becomes a binary number expressing one of integers 0 to 15 as 4 bits. As the chip count, binary number values of 4 bits, that is, 0000 through 1111 are sequentially provided to designate integers ranging from 0 to 15. Although the above example restricts the bit number of the orthogonal code index and chip count to I bits, the bit number need not be restricted. Namely, it is possible to assign the bit number of the orthogonal code index and chip count up to the maximum bit number. Then aII bits except actually effective bits among the assigned bit number are set to "0". The maximum bit number is determined on the basis of the longest Walsh code used 1 S in a mobile communication system. The actually effective bits represent the bit number of the orthogonal code index and chip count. For instance, if the longest Walsh code which is usable in the mobile communication system is 128 (=2') chips, the maximum bit number is 7 bits.
Consequently, if the symbol rate is designated, the orthogonal code length is determined by the designated symbol rate, and the range of the chip count and the orthogonal code index are determined by the orthogonal code length. Once the range of the chip count is determined, the chip count is sequentially increased within the determined range. The orthogonal code length, the orthogonal code index, and the increased chip count are provided as information for generating the orthogonal code. If the orthogonal code generator 114 has a function which can estimate the orthogonal code length by the orthogonal code index, the controller _9_ 113 need not provide the orthogonal code length information.
1n the second step, the orthogonal code is generated by using the orthogonal code length information, the orthogonal code index assigned to each channel, and the chip count which are provided from the processor. That is, an algorithm is supplied with the orthogonal code length information in addition to the orthogonal code index and chip count so that the orthogonal codes of differing length can be generated.
The processor for controlling the modulator determines the orthogonal code length information based on the symbol rate and provides this information to the orthogonal code generator 114, thereby generating the orthogonal code having a variable length according to the symbol rate. The orthogonal code of a necessary length is generated by restricting the number of digits of the orthogonal code index n and chip count t expressed as a binary number through the orthogonal code length information. This can be represented by Equation l:
[Equation 1 ]
W(I,n,t)=(n~_, xt,_,). . .(n4xt4)~(n3xt3)~(n2xt2)~(n, xt~ )~{noxtO) where I is orthogonal code length information (i.e., 2, 3, 4,...), n is an orthogonal code index assigned to each channel, and t is a chip count obtained by counting one symbol period by a chip clock.
1f the orthogonal code length information, the orthogonal code index and the chip count are designated by Equation 1, a corresponding one-chip orthogonal code is generated. As can be appreciated from Equation l, an effective calculation range is determined by the orthogonal code length information I. Meanwhile, the orthogonal code of one bit is obtained by logic operation of bits constituting the chip count and bits constituting the orthogonal code index within the effective calculation range. That is, the chip count and the orthogonal code index are ANDed in the unit of bits and the ANDed results are XORed.
The effective calculation range determined according to the orthogonal code length information I is illustrated in FIG. 2. If the orthogonal code length information I is 3 (=011), the range of the chip count t is 0 to 7, and the orthogonal code index n is 3 (i.e., n2,n~,no 0,1,1), a one-chip orthogonal code is generated using the range corresponding to a reference numeral 214 shown in FIG. 2. That is:
W(3,3,t) _ (n2xt2)~(n,xt~)~(noxto) wheren=(O11)and0_<t<_7.
There fore, for t = 0(000), W(3,3,0) _ (0x0)~( 1 x0)~( 1 x0) = 0;
for t = I {001 ), W(3,3,1 ) _ (0x0)~( 1 x0)~( 1 x 1 ) = 1;
for t = 2(010), W{3,3,2) _ (0x0)~( 1 x 1 )~( 1 x0) = 1;
for t = 3(01 I _ (0x0)~( 1 x 1 )~( ), W(3,3,3) 1 x 1 ) = 0;
for t = 4( 100), _ (Ox 1 )~( 1 x0)~( W(3,3,4) 1 x0) = 0;
for t = 5(101), _ (0x1)~(1x0)~(1x1) W(3,3,5) = 1;
for t = 6( 110), _ (Ox 1 )~( 1 x 1 )~( W(3,3,6) 1 x0) = 1; and for t = 7( 1 I 1 ), W(3,3,7) _ (Ox 1 )m( 1 x 1 )~( 1 x 1 ) = 0.
Finally, an orthogonal code (0 1 1 0 0 1 1 0) is generated. The orthogonal code generating process based on Equation 1 can be expressed by Equation 2, which is written in C language:
[Equation 2]
Walsh(int length, int index, int count) int i, we = 0;
for (i = 0; i<length; i++) we = we~(((index » i)&0x01 )&((count » i) & 0x01 ) return(wc);
where i is a temporary count parameter; we is a parameter in which a final value is to be stored; length is a parameter having an orthogonal code length information value determined according to the symbol rate; index is an orthogonal code index assigned to a channel; and count is a chip count obtained by counting one symbol period by a chip clock.
The range of the chip count differs according to the orthogonal code length as listed below in Table 1:
[Table 1 ]
Length Count range Orthogonal Code Length 2 0~3 -The orthogonal code generating process may be achieved by a program as shown in Equation 2 on a DSP or by algorithm such as HDL (Hardware Development Language) on an ASIC.
An example for achieving the orthogonal code generator on the ASIC is illustrated in FIG. 3. Refernng to FIG. 3, the orthogonal code generator includes an AND gate circuit 310 consisting of a plurality of AND gates 310 0,...,310 M-1 and an XOR gate 320. The number of AND gates constituting the AND gate circuit 310 is the same as the maximum bit number determined on the basis of the longest orthogonal code. If the orthogonal code lengths are 4, 8, 16, 32, 64 and 128 chips, the number of the AND gates is determined on the basis of 128 (=
2') chips. In this case, the number of the AND gates will be 7, which corresponds to the bit number, the orthogonal code index, and chip count. When the orthogonal code having a length shorter than the longest orthogonal code length is generated, all bits other than the actually effective bits are considered to be "0". In other words, bits except the actually effective bits are considered masked to "0".
The AND gates 310 0,...,310 M-1 each perform an AND operation of a con-esponding bit of the orthogonal code index and a corresponding bit of the chip count. The XOR gate 320 performs an XOR operation of the outputs of the AND gate circuit 310 to generate one bit constituting the orthogonal code. A
reference symbol Walsh Index is a register for storing the orthogonal code index to be calculated; Chip count is a register for storing the current chip count;
Walsh-code is a currently calculated orthogonal code value; and M is a value expressing the longest orthogonal code length as 2 to the power of a prescribed number (for instance, if the longest orthogonal code length is 128 chips, M is 7).
The operation of the orthogonal code generator of FIG. 3 will now be described by way of example, on the assumption that the orthogonal code length information I is 3(011), the chip count t is 0-7, and the orthogonal code index n is 3(n,, n,, no = 0, 1, 1). It is also assumed that the longest orthogonal code length is 128 chips, that is, M is 7. Therefore, the number of the AND gates actually required by the orthogonal code information I (= 3) is restricted to 3.
As the orthogonal code index, the actual information 011 is continuously provided together with 4 bits masked to "0". As the chip count, 4 bits masked to "0" and 3 least significant bits varying from 000 to 111 are provided. The output of the AND gate circuit 310 according to the orthogonal code index and the chip count is listed in below in Table 2.
[Table 2]
Orthogonal Chip Output Code Count (q) Index (n) of (n) AND
Gate n" n;n, n, n_ n, no tV is t, t, tz t~ to qb qs q4 q3 qz q~ 90 The outputs qo to qG of the AND gates 310 0,...,310 M-1 are provided to the XOR gate 320. The XOR gate 320 generates the orthogonal code "01100110"
by XOR operation of the outputs qo to qb.
In the preferred embodiment of the present invention, the controller 113 has determined the information for generating the orthogonal code, including the chip count, and provided the information to the orthogonal code generator 114.
However, the controller 113 may provide only the orthogonal code length and orthogonal code index, and the orthogonal code generator 114 generates the chip count. In this case, the orthogonal code generator should include a counter to generate the chip count based on the orthogonal code length.
As described above, since the orthogonal codes having different lengths according to the symbol rates can be generated, the present invention may usefully be applied to a CDMA-2000 mobile communication system in which symbol rates vary according to channel types. Furthermore, since there is no need to make various types of orthogonal code tables corresponding to the different orthogonal code lengths, multiple varying memories are not required and the hardware configuration can be realized by a common structure which is applicable to various symbol rates.
While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A device for generating orthogonal codes in a mobile communication system, comprising:
a memory having registers for respectively storing an effective bit number, an orthogonal code index and a chip count value; and an orthogonal code generating circuit for sequentially generating said chip count value up to a maximum value which can be counted by said effective bit number, and generating an orthogonal code by logic operation of said orthogonal code index and said sequentially generated chip count values.
a memory having registers for respectively storing an effective bit number, an orthogonal code index and a chip count value; and an orthogonal code generating circuit for sequentially generating said chip count value up to a maximum value which can be counted by said effective bit number, and generating an orthogonal code by logic operation of said orthogonal code index and said sequentially generated chip count values.
2. The device as claimed in claim 1, wherein said effective bit number designates a bit number of an exponent when an orthogonal code length corresponding to a variable symbol rate is expressed as 2 raised to the power of a prescribed number.
3. The device as claimed in claim 1, wherein said orthogonal code generating circuit receives said effective bit number, orthogonal code index and chip count value and generates an orthogonal code according to the equation:
W(I,n,t)=(nI-1xtI-1)...(n4xt4)~(n3xt3)~(n2xt2)~(n1xt1)~(n0xt0) where I is an effective bit number, n (=nI-1,,..,n4,n3,n2,n1,n0) is an orthogonal code index, and t (=tI-1,...,t4,t3,t2,t1,t0) is a chip count value.
W(I,n,t)=(nI-1xtI-1)...(n4xt4)~(n3xt3)~(n2xt2)~(n1xt1)~(n0xt0) where I is an effective bit number, n (=nI-1,,..,n4,n3,n2,n1,n0) is an orthogonal code index, and t (=tI-1,...,t4,t3,t2,t1,t0) is a chip count value.
4. The device as claimed in claim 2, wherein said orthogonal code generating circuit includes:
a controller for determining said effective bit number, sequentially generating said chip count value up to a maximum value which can be counted by said effective bit number, and converting said orthogonal code index into a binary number of said effective bit number; and an orthogonal code generator for generating an orthogonal code by logic operation of said orthogonal code index converted into the binary number and the sequentially generated chip count values.
a controller for determining said effective bit number, sequentially generating said chip count value up to a maximum value which can be counted by said effective bit number, and converting said orthogonal code index into a binary number of said effective bit number; and an orthogonal code generator for generating an orthogonal code by logic operation of said orthogonal code index converted into the binary number and the sequentially generated chip count values.
5. The device as claimed in claim 4, wherein said orthogonal code generator includes:
AND gates for ANDing bits of said orthogonal code index converted into the binary number and bits of said sequentially generated chip count values;
and an XOR gate for XORing outputs of said AND gates to generate an orthogonal code in a chip unit.
AND gates for ANDing bits of said orthogonal code index converted into the binary number and bits of said sequentially generated chip count values;
and an XOR gate for XORing outputs of said AND gates to generate an orthogonal code in a chip unit.
6. A method for generating orthogonal codes in a mobile communication system, comprising the steps of:
calculating an orthogonal code length corresponding to a variable symbol rate;
determining an effective bit number based on the calculated orthogonal code length;
sequentially generating a chip count value up to a maximum value which can be counted by said effective bit number;
converting an orthogonal code index into a binary number of said effective bit number; and performing a logic operation on said orthogonal code index converted into the binary number and said sequentially generated chip count values in order to generate an orthogonal code.
calculating an orthogonal code length corresponding to a variable symbol rate;
determining an effective bit number based on the calculated orthogonal code length;
sequentially generating a chip count value up to a maximum value which can be counted by said effective bit number;
converting an orthogonal code index into a binary number of said effective bit number; and performing a logic operation on said orthogonal code index converted into the binary number and said sequentially generated chip count values in order to generate an orthogonal code.
7. The method as claimed in claim 6, wherein said effective bit number designates an exponent when said orthogonal code length is expressed as 2 raised to the power of a prescribed number.
8. The method as claimed in claim 6, wherein said logic operation includes the steps of:
ANDing bits of said orthogonal code index converted into the binary number and bits of said sequentially generated chip count values; and XORing the ANDed results.
ANDing bits of said orthogonal code index converted into the binary number and bits of said sequentially generated chip count values; and XORing the ANDed results.
9. A method for generating orthogonal codes in a mobile communication system, comprising the steps of:
calculating an orthogonal code length corresponding to a variable symbol rate to determine an effective bit number; and receiving said effective bit number, an orthogonal code index and a chip count value and generating an orthogonal code in accordance with the following equation:
W(I,n,t)=(nI-1 xtI-1)...(n4xt4)~(n3xt3)~(n2xt2)~(n1 xt1)~(n0xt0) where I is an effective bit number, n (=nI-1,...,n4,n3,n2,n1,n0) is an orthogonal code index, and t (=t1-1,,..,t4,t3,t2,t1,t0) is a chip count value.
calculating an orthogonal code length corresponding to a variable symbol rate to determine an effective bit number; and receiving said effective bit number, an orthogonal code index and a chip count value and generating an orthogonal code in accordance with the following equation:
W(I,n,t)=(nI-1 xtI-1)...(n4xt4)~(n3xt3)~(n2xt2)~(n1 xt1)~(n0xt0) where I is an effective bit number, n (=nI-1,...,n4,n3,n2,n1,n0) is an orthogonal code index, and t (=t1-1,,..,t4,t3,t2,t1,t0) is a chip count value.
10. The method as claimed in claim 9, wherein said effective bit number designates an exponent when said orthogonal code length is expressed as 2 raised to the power of a prescribed number.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1998/35118 | 1998-08-28 | ||
| KR19980035118 | 1998-08-28 | ||
| PCT/KR1999/000494 WO2000013431A2 (en) | 1998-08-28 | 1999-08-28 | Device and method for generating orthogonal codes in mobile communication system |
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| Publication Number | Publication Date |
|---|---|
| CA2309032A1 true CA2309032A1 (en) | 2000-03-09 |
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|---|---|---|---|
| CA002309032A Abandoned CA2309032A1 (en) | 1998-08-28 | 1999-08-28 | Device and method for generating orthogonal codes in mobile communication system |
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| Country | Link |
|---|---|
| EP (1) | EP1057287A2 (en) |
| CN (1) | CN1286840A (en) |
| AU (1) | AU732063B2 (en) |
| BR (1) | BR9906781A (en) |
| CA (1) | CA2309032A1 (en) |
| WO (1) | WO2000013431A2 (en) |
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| JP3601816B2 (en) | 1999-05-31 | 2004-12-15 | 韓國電子通信研究院 | Modulator, terminal, and modulation method in mobile communication system |
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| FI925472A (en) * | 1992-12-01 | 1994-06-02 | Nokia Mobile Phones Ltd | Data transfer procedure and system |
| JPH0918450A (en) * | 1995-06-27 | 1997-01-17 | Sony Corp | Code division multiplex transmitter |
| JP3317866B2 (en) * | 1996-12-20 | 2002-08-26 | 富士通株式会社 | Spread spectrum communication system |
-
1999
- 1999-08-28 CA CA002309032A patent/CA2309032A1/en not_active Abandoned
- 1999-08-28 AU AU55310/99A patent/AU732063B2/en not_active Ceased
- 1999-08-28 BR BR9906781-1A patent/BR9906781A/en not_active IP Right Cessation
- 1999-08-28 EP EP99941826A patent/EP1057287A2/en not_active Withdrawn
- 1999-08-28 CN CN 99801662 patent/CN1286840A/en active Pending
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| WO2000013431A2 (en) | 2000-03-09 |
| WO2000013431A3 (en) | 2000-06-29 |
| BR9906781A (en) | 2000-12-05 |
| CN1286840A (en) | 2001-03-07 |
| EP1057287A2 (en) | 2000-12-06 |
| AU5531099A (en) | 2000-03-21 |
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