KR100300357B1 - apparatus and method for generating walsh code in cdma communication system - Google Patents

Abstract

The present invention relates to an apparatus and method for generating an orthogonal code having a different length according to a symbol rate in a mobile communication system. The present invention relates to an orthogonal code length corresponding to a variable symbol rate to determine an effective number of bits. Orthogonal code generation apparatus and method for generating an orthogonal code through a logical operation by generating the chip counter value sequentially up to the orthogonal code index converted to the number binary code and the highest count value that can be counted by the number of significant bits Characterized in that implements.

Description

Apparatus and method for generating walsh code in cdma communication system}

The present invention relates to an apparatus and method for generating an orthogonal code in a mobile communication system, and to an apparatus and method for generating an orthogonal code having a different length according to various symbol rates.

Orthogonal code generally refers to a code used for the spread of the channel and the purpose of the identifier for distinguishing each channel. In the conventional transmitter using the IS-95 CDMA scheme, a 64 chip length Walsh code is used for spreading the spectrum while maintaining orthogonality between channels. This is because the symbol rate of the coded data symbols of the various channels inputted from the transmitter's modulator to the spreader was all maintained at a constant rate (19.2 kbps), so it was only 1.2288 cpss using a 64-chip orthogonal code. Made the rate of In order to actually implement this method, a 64 × 64 Walsh code table is created and an orthogonal code corresponding to an index of an orthogonal code assigned to each channel is read and used from the memory table.

However, in the same method as CDMA2000 applied to the IMT-2000, the symbol rate input to the spreader during the modulation process of the forward channel is different for each type of channel, and accordingly, orthogonal codes having different lengths are required for each channel.

Therefore, in order to generate orthogonal codes of different lengths in order to implement IMT-2000 according to the conventional method, an orthogonal code table corresponding to each length should be separately used. In the real hardware implementation, very much memory is required, and there is a problem in that it cannot flexibly cope with orthogonal codes having different lengths according to various symbol rates.

Accordingly, an object of the present invention is to provide an orthogonal code generation apparatus and method for generating orthogonal codes having different lengths according to various symbol rates in a mobile communication system.

Another object of the present invention is to provide an orthogonal code generation apparatus and method for generating an orthogonal code having an orthogonal code index value and a chip counter value in a mobile communication system.

An orthogonal code generating apparatus of a mobile communication system for achieving the above objects includes a memory having registers for storing a valid bit number, an orthogonal code index, and a chip count value, and up to a maximum count value that can be counted with the valid bit number. And an orthogonal code generation unit that generates the orthogonal code by sequentially generating the chip counter value and setting the chip counter value as the chip count value, reading the orthogonal code index and the chip counter values, and performing a predetermined logical operation.

Orthogonal code generation method of the mobile communication system to achieve the above object, orthogonal code length corresponding to a variable symbol rate to determine the effective number of bits, and the orthogonal code index and the effective number converted to binary code of the effective number of bits The chip counter value is sequentially generated up to the highest count value that can be counted by the number of bits, and a quadrature code is generated through a logical operation.

1 is a diagram illustrating a modulator configuration of a mobile communication system according to an embodiment of the present invention.

2 is a diagram illustrating a method for generating an orthogonal code according to an embodiment of the present invention.

3 is a diagram illustrating an example of an orthogonal code generator illustrated in FIG. 1.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, in adding the reference numerals to the components of each drawing, the same components have the same reference numerals as much as possible even if displayed on different drawings. In describing the present invention, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

1 is a diagram illustrating a configuration of a modulator according to an embodiment of the present invention. Hereinafter, only a portion related to orthogonal diffusion among the configurations of the modulator will be described.

Referring to FIG. 1, a signal converter (DEMUX & signal power mapping part) 111 demultiplexes input symbol data (coded data) into I and Q channels so as to transmit the first channel signal and Output as a second channel signal. In addition, the signal converter 111 converts the level of symbol data. For example, the signal converter 111 converts 0 into +1 and 1 into -1. The first channel gain adjuster 115 inputs a first channel signal output from the signal converter 111 and adjusts and outputs a gain of the first channel signal by a gain control signal provided from the controller 113. The second channel gain adjuster 116 inputs a second channel signal output from the signal converter 111, and adjusts and outputs a gain of the second channel signal by a gain control signal provided from the controller 113. The memory 112 stores various program data and temporary data generated during the execution of the program. In particular, according to the present invention, the memory 112 includes a register having information on an orthogonal code length that varies according to the symbol rate of each channel, a register having an orthogonal code index assigned to the channel, and a orthogonal code. And a register having a chip count that counts one symbol to be spread with a corresponding chip clock. The information on the orthogonal code length will be described later. However, the information on the orthogonal code length may be defined to mean an actual number of valid bits of the orthogonal code index and the chip count value. The control unit 113 controls the overall operation of the modulator. In particular, according to the present invention, the controller 113 reads a variable value related to the orthogonal code generation from the memory 112 and provides it to the orthogonal code generator 114 of each channel generator. An orthogonal code generator 114 corresponds to an orthogonal code corresponding to orthogonal code length information (effective number of bits), orthogonal code index, and chip count provided from the control unit 113. Create and print The multiplier 117 multiplies the first channel signal output from the first channel gain adjuster 115 and the orthogonal code to generate a first channel signal that is orthogonally modulated. The multiplier 118 multiplies the second channel signal output from the second channel gain adjuster 116 by the orthogonal code to generate a quadrature modulated second channel signal.

Among the above-described configurations, essential components in implementing the orthogonal code generation device proposed by the present invention will be a memory 112, a control unit 113, and an orthogonal code generator 114. In addition, when the control unit 113 and the orthogonal code generator 114 are to be collectively referred to, the term orthogonal code generator is used.

Referring to the orthogonal diffusion operation of the modulator based on the configuration of FIG. 1, first, coded data (symbol data) is separated into a first channel signal and a second channel signal through a signal converter 111. The separated signals are gain adjusted by the first channel regulator 115 and the second channel regulator 116 under the control of the controller 113, respectively. The gain adjusted first and second channel signals are output to corresponding multipliers 117 and 118. At this time, the controller 113 obtains an orthogonal code length corresponding to a symbol rate of the coded data (symbol data), a value of a chip count, and an orthogonal code index to be allocated to a channel. The information is obtained by accessing a register provided in the memory 112, and the obtained information is provided to an orthogonal code generator 114 of the corresponding channel generator. Then, the orthogonal code generator 114 generates an orthogonal code corresponding to the three pieces of information through a program or an ASIC implemented on a DSP provided therein. The generated orthogonal codes are output to the multipliers 117 and 118. The multiplier 117 multiplies the first channel signal output from the first channel gain adjuster 115 by the orthogonal code to generate a first channel signal IW orthogonally modulated. The multiplier 118 multiplies the second channel signal output from the second channel gain adjuster 116 by the orthogonal code to generate a second channel signal QW that is orthogonally modulated. In this case, the orthogonally modulated first channel signal may correspond to an I channel, and the orthogonally modulated second channel signal may correspond to a Q channel.

Hereinafter, an orthogonal code generation process according to an embodiment of the present invention will be described in detail. First, the orthogonal code generation process to be described below is a process performed by the orthogonal code generation unit including the control unit 113 and the orthogonal code generator 114, which have been described above. On the other hand, in the description of the embodiment of the present invention, it should be noted that even if the orthogonal code length information and the effective number of bits are used interchangeably, the same meaning is used.

The generation of the orthogonal code consists of two steps. The first step is to generate the information required for generating the orthogonal code, and the second step is to generate the orthogonal code based on the generated information. In this case, the required information includes an orthogonal code index allocated to each channel, a value obtained by counting one symbol period with a chip clock, and a length of an orthogonal code.

First, a series of operations for generating and providing information including an orthogonal code index, a count value, and an orthogonal code length by the first step will be described in detail.

Unlike the CDMA scheme of the conventional IS-95, in the case of the CDMA-2000 of the new scheme, the symbol rate of the symbol data input to the spreader is different for each channel type in the modulation process of the forward channel. Therefore, in order to match a constant spread spectrum rate, the length of the orthogonal code varies for different symbol rates, and the range is from 4 to 8, 16, 32, 64, 128, 256, 512, and 1024. For example, when the spread spectrum rate is 3,6864 Mcps, the symbol rates input to the spreader differ by 14.4kbps, 28.8kbps, 57.6kbps, 115.2kbps, and the like. As a result, the length of the orthogonal code is changed to 256 chips, 128 chips, 64 chips, 32 chips, etc., respectively, to match the spread spectrum rate of 3.6864 Mcps.

14.4kbps × 256 chip = 3.686Mcps

28.8 kbps × 128 chip = 3.686 Mcps

57.6kbps × 64 chip = 3.686Mcps

115.2kbps × 32 chip = 3.686Mcps

As described above, in order to match the constant spreading rate, orthogonal codes having different lengths are generated according to various types of symbol rates input to the spreader. Therefore, in the processor controlling the modulator, information related to the length of an orthogonal code that depends on the symbol rate is generated and provided to the modulator. As an example, since the length of the orthogonal code required according to the symbol rate is a multiple of 4 as mentioned above, the length of each orthogonal code can be expressed as an index having a predetermined multiplier with a length of 2 below. The example is as follows.

4 = 2 ² , 8 = 2 ³ , 16 = 2 ⁴ ,. , 1024 = 2 ¹⁰

As described above, the base corresponding to the length of all orthogonal codes is common as 2, and the information on the length of the orthogonal code determined by the symbol rate as having a difference in the multiplier uses the multiplier disclosed above. Therefore, the processor generates a multiplier as information related to the length of the orthogonal code and provides the modulator.

At this time, the range of the orthogonal code index (n) allocated to each channel and the value (t) of counting one symbol period by a chip clock can be extended or reduced by the length of the orthogonal code. 4,8,16,64,128,... It can be used flexibly with various orthogonal codes.

If this More specifically, the orthogonal code index and the count value is determined in the range of ^{'0≤n≤2 l -1, 0≤t≤2 l -1} '. That is, the orthogonal code index is provided as a value representing an integer of any one of the integers in the range as a binary number of l bits, and the count value is a value expressed as a binary number of l bits by sequentially specifying an integer within the range. Is provided. For example, assuming that the information on the orthogonal code length is determined as '4', the orthogonal code index will be a binary value representing any one of integers in the range of 0 to 15 as 4 bits. On the other hand, the count value will be a binary value represented by 4 bits that '2 ⁴ ', that is, 16 is determined as the final count value and sequentially specifies an integer in the range of 0 to 15. That is, binary values of '0000 to 1111' are provided sequentially. Meanwhile, in the above example, the number of bits of the orthogonal code index and the count value is limited to 1 bit, but it is not necessarily limited. The reason for this will be described later, but the method can be implemented by allocating the bit number of the orthogonal code index and the count value as the maximum number of bits and setting '0' to all bits except the actual valid bits among the allocated number of bits. Do. The maximum number of bits is determined based on the longest Walsh code used in the mobile communication system. In addition, the actual valid bits mean the number of bits of the orthogonal code index and count value described above. For example, if the longest Walsh code available in a mobile communication system is 128 (2 ⁷ ) chips, the number of bits determined will be 7 bits.

In conclusion, if the symbol rate is specified, the orthogonal code length is determined by the designated symbol rate, and the orthogonal code index is determined with the range of count values by the determined orthogonal code length. When the range of the count value is determined, the count value is sequentially increased within the determined range, and the orthogonal code length, the orthogonal code index, and the increased count value generate orthogonal codes at a time point at which the count value is increased. It is provided as information for. On the other hand, if the orthogonal code generator 114 has a processing function capable of inferring the orthogonal code length through the provided orthogonal code index, the controller 113 may not provide the orthogonal code length.

Next, a series of operations for generating an orthogonal code by the second step will be described in detail.

The present invention generates the required orthogonal code using the following algorithm using the information related to the orthogonal code length provided by the processor, the orthogonal code index assigned to each channel, and the chip counter value. That is, the algorithm is improved by adding new information about the orthogonal code length so that the orthogonal code length is variable with the orthogonal code index and the chip counter value.

As described above, the processor controlling the modulator determines information about the length of the orthogonal code according to the symbol rate, and provides the orthogonal code generator to the orthogonal code generator to change the length of the orthogonal code according to the symbol rate rather than the fixed length. Create a sign generator. That is, when the values of n and t are expressed in bits as shown in Equation 2, an orthogonal code having the required length is generated by limiting the number of bit digits through the information on the length.

W (l, n, t) = (n _l-1 × t _l-1 )... (n ₄ × t ₄ ) xor (n ₃ × t ₃ ) xor (n ₂ × t ₂ ) xor (n ₁ × t ₁ ) xor (n ₀ × t ₀ )

Where l; Information about orthogonal code lengths (2,3,4,…)

n; Orthogonal Index Assigned to Each Channel

t; Count of one symbol period in chip clock

When the information on the length of the orthogonal code, the orthogonal code index, and the count value are specified by using Equation 1, an orthogonal code of one chip is generated. That is, as can be seen from Equation 1, the effective calculation range is determined by the information '1' of the orthogonal code length. On the other hand, one bit of the orthogonal code is obtained by performing a logical operation on a bit-by-bit basis between bits constituting the chip count value and bits constituting the orthogonal code index provided within the determined effective calculation range. In this case, as described in Equation 1, the logical operation is configured by performing a logical multiplication operation on a chip count value and an orthogonal code index in units of bits, and then performing exclusive logical sum operations on the resultant values.

In Equation 1, an effective calculation range is determined according to the orthogonal code length information l, as shown in FIG. Referring to FIG. 2, for example, the orthogonal code length information l is 3 (011), so that the chip counter t is 8 (0-7), and the orthogonal code index n is 3 (n ₂ , n ₁ , Assume that n ₀ = _0, 1, 1), as shown in the drawing, an orthogonal code of one chip is generated using a range corresponding to reference numeral 214.

Equation (1) for the above assumption is shown as a chip count value provided sequentially increased.

W (3,3, t) = (n ₂ × t ₂ ) xor (n ₁ × t ₁ ) xor (n ₀ × t ₀ )

Where n = (0 1 1), the counter range is (0≤ t ≤ 7)

Thus t = 0 (0 0 0), W (3,3,0) = (0x0) xor (1x0) xor (1x0) = 0

t = 1 (0 0 1), W (3,3,1) = (0 × 0) xor (1 × 0) xor (1 × 1) = 1

t = 2 (0 1 0), W (3,3,2) = (0 × 0) xor (1 × 1) xor (1 × 0) = 1

t = 3 (0 1 1), W (3,3,3) = (0 × 0) xor (1 × 1) xor (1 × 1) = 0

t = 4 (1 0 0), W (3,3,4) = (0 × 1) xor (1 × 0) xor (1 × 0) = 0

t = 5 (1 0 1), W (3,3,5) = (0 × 1) xor (1 × 0) xor (1 × 1) = 1

t = 6 (1 1 0), W (3,3,6) = (0 × 1) xor (1 × 1) xor (1 × 0) = 1

t = 7 (1 1 1), W (3,3,7) = (0 × 1) xor (1 × 1) xor (1 × 1) = 0

As a result, the orthogonal code generated finally becomes (0 1 1 0 0 1 1 0).

In addition, the contents of the improved method based on Equation 1 are expressed in Equation 2 below.

walsh (int length, int index, int count)

{

int i, wc = 0;

for (i = 0; i <length; i ++)

wc = wc ^ (((index >> i) & 0x01) & ((count >> I) & 0x01)

return (wc);

}

Where i: temporary count variable

wc: Variable to store final result

length: A variable with information about the length of an orthogonal code, determined by the symbol rate

index: Orthogonal code index assigned to the channel

count: The value of counting 1 symbol period as chip clock is used as the chip count value when the above function is called.

Here, as described above, the range of count values given depends on the length value. For example, as shown in Table 1 below.

length Count range Orthogonal length 2 0-3 4 3 0-7 8 4 0-15 16 5 0-31 32

In addition, the present invention may be actually implemented on a digital signal processor (DSP) by writing a program as shown in Equation (2), or by writing an algorithm such as HDL (Hardware Development Language) to create an ASIC (Application- specific IC).

A configuration according to an example of implementing the orthogonal code generator as an application-specific IC (ASIC) is as shown in FIG. 3. The orthogonal code generator illustrated in FIG. 3 includes a plurality of logical product gates 310 and exclusive logical sum gates 320. In this case, the number of the logical product gate 310 is equal to the maximum number of bits determined based on the longest Walsh code. That is, when the length of the orthogonal code is 4, 8, 16, 32, 64, 128 chips, the number of logical product gates 310 is determined based on the longest 128 chip. In this case, the number of the logical product gates 310 to be determined will be seven corresponding to 7 bits, which is the number of bits of the orthogonal code index and the chip count value. Accordingly, when generating an orthogonal code for an orthogonal code length shorter than the above defined pseudo long orthogonal code length, bits other than the actual valid value are regarded as '0'. In other words, bits other than the actual valid values are masked with '0'.

Each of the logical product gates 310 logically multiplies corresponding bits of a provided orthogonal code index and a chip count value and outputs the result. The exclusive logical sum gate 320 outputs one bit constituting an orthogonal code by performing an exclusive logical sum operation on values output from each of the logical product gates 310. On the other hand, Walsh_Index disclosed in the figure can be seen as a register that stores the orthogonal code index value to be calculated, Chip_count can be seen as a register that stores the current chip count value. Walsh_code represents the current orthogonal code value computed. M is the value representing the longest length of the orthogonal code length used in bits. If the orthogonal code length is 128 chips, M is 7 bits.

An example of the operation will be described with reference to the above configuration. In this case, it is assumed that the information provided from the control unit 113 is the same as the value presented above. That is, the orthogonal code length information l is 3 (011), so that the chip counter t is 8 (0-7), and the orthogonal code index n is 3 (n ₂ , n ₁ , n ₀ = ₀ , ₁ , ₁ ). Assume that

In this case, it is assumed that the longest orthogonal code length used in the mobile communication system is 128 chips, and M is 7. Therefore, among the seven logical product gates 310 determined by the value of M, the logical product gate 310 substantially required by the value '3' of l is limited to three.

In the above state, as the orthogonal code index, 4 bits masked with 0 and 0,1,1, which are actual orthogonal code index information, are continuously provided. Meanwhile, four bits masked with zero are continuously provided as the chip count value, and only the lower 3 bit values representing the chip count value are changed and provided. The provided lower 3 bit value will vary from 000 to 111. The output of the logical product gate 310 according to the orthogonal code index and the chip count value provided as described above may be represented as shown in Table 2 below.

Cartesian index (n) Chip count value (t) Logic Product Gate Output (q) n ₆ n ₅ n ₄ n ₃ n ₂ n ₁ n ₀ t ₆ t ₅ t ₄ t ₃ t ₂ t ₁ t ₀ q ₆ q ₅ q ₄ q ₃ q ₂ q ₁ q ₀ 0 0 0 0 0 One One 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 One 0 0 0 0 0 0 One 0 0 0 0 0 One 0 0 0 0 0 0 One 0 0 0 0 0 0 One One 0 0 0 0 0 One One 0 0 0 0 One 0 0 0 0 0 0 0 0 0 0 0 0 0 One 0 One 0 0 0 0 0 0 One 0 0 0 0 One One 0 0 0 0 0 0 One 0 0 0 0 0 One One One 0 0 0 0 0 One One

The outputs q ₀ to q ₆ of the logical product gates obtained as shown in Table 2 are provided as an exclusive logical sum gate 320. Thus, the exclusive logical sum gate 320 takes an exclusive logical sum association for all bits, resulting in an orthogonal code of '01100110'.

On the other hand, the configuration and operation according to an embodiment of the present invention described above to determine the orthogonal code generation information including the chip count value in the control unit 113 to provide to the orthogonal code generator 114, the orthogonal code generator 114 by the information provided Orthogonal code is generated. However, in another embodiment, the control unit 113 provides the orthogonal code length and the orthogonal code index to the orthogonal code generator 114, and the count value is generated by the orthogonal code generator 114. At this time, the orthogonal code generator 114 has to have a counter therein to generate a chip count value by the orthogonal code length.

As described above, the present invention can generate orthogonal codes having different lengths according to symbol rates, and thus can be usefully used in CDMA2000 mobile communication systems having different symbol rates according to channel types. In addition, since it is not necessary to create various kinds of orthogonal code tables having different lengths of orthogonal codes, there is an advantage in that hardware can be implemented in a common structure that can be applied to various symbol rates since much memory is not required in actual implementation.

Claims (10)

A memory having a register for storing a valid bit number, an orthogonal code index, and a chip count value, respectively; The chip counter value is sequentially generated and set to the chip count value up to the highest count value that can be counted as the number of significant bits, and the orthogonal code is generated by performing a predetermined logical operation by reading the orthogonal code index and the chip counter values. Orthogonal code generation device of a mobile communication system, characterized in that consisting of an orthogonal code generation unit. The method of claim 1, wherein the number of significant bits is And an orthogonal code length corresponding to a varying symbol rate as an exponent of 2 below, which is a multiplier of the expressed exponent. The method of claim 1, wherein the orthogonal code generation unit, Orthogonal code generation method according to Equation 3 below receiving the effective number of bits, an orthogonal code index, and a chip count value. W (l, n, t) = (n _l-1 × t _l-1 )... (n ₄ × t ₄ ) xor (n ₃ × t ₃ ) xor (n ₂ × t ₂ ) xor (n ₁ × t ₁ ) xor (n ₀ × t ₀ ) Where l is the number of significant bits, n = (n _l-1 ,..., N ₄ , n ₃ , n ₂ , n ₁ , n ₀ ) is an orthogonal code index, and t = (t _l-1 ,... , t ₄ , t ₃ , t ₂ , t ₁ , t ₀ ) means the chip count value. The method of claim 2, wherein the orthogonal code generation unit, A controller configured to determine the valid number of bits and sequentially generate the chip counter value up to the highest count value that can be counted by the determined valid number of bits, and convert the orthogonal code index into a binary code of the valid number of bits; And an orthogonal code generator configured to generate an orthogonal code by performing a logical operation on the orthogonal code index converted to the binary code and the chip counter values sequentially generated. The method of claim 4, wherein the orthogonal code generator, Logical product gates for performing a logical product operation on each of bits of the orthogonal code index converted to the binary code corresponding to each other and bits of the sequentially generated chip count values; And an exclusive logic sum gate configured to generate an orthogonal code in chip units by performing an exclusive logic sum operation on the output bits of the logical product gates. Calculating an orthogonal code length corresponding to a variable symbol rate; Determining an effective number of bits based on the calculated orthogonal code length; Sequentially generating the chip counter value up to the highest count value that can be counted as the number of significant bits; Converting an input orthogonal code index into a binary code of the effective number of bits; And generating an orthogonal code by performing a logical operation on the orthogonal code index converted to the binary code and the chip counter values sequentially generated. The method of claim 6, wherein the number of significant bits, Orthogonal code generation method of claim 2, wherein the orthogonal code length is represented by an exponent of 2 below. The method of claim 6, wherein the logical operation, Performing a logical multiplication operation on the bits of the orthogonal code index converted to the binary code corresponding to each other and the bits of the sequentially generated chip count values; And generating an orthogonal code by performing an exclusive logical sum operation on the output bits by the logical multiplication operation. Determining an effective number of bits by calculating an orthogonal code length corresponding to a variable symbol rate; And receiving an effective number of bits, an orthogonal code index, and a chip count value, to generate an orthogonal code by Equation 4 below. W (l, n, t) = (n _l-1 × t _l-1 )... (n ₄ × t ₄ ) xor (n ₃ × t ₃ ) xor (n ₂ × t ₂ ) xor (n ₁ × t ₁ ) xor (n ₀ × t ₀ ) Where l is the number of significant bits, n = (n _l-1 ,..., N ₄ , n ₃ , n ₂ , n ₁ , n ₀ ) is an orthogonal code index, and t = (t _l-1 ,... , t ₄ , t ₃ , t ₂ , t ₁ , t ₀ ) means the chip count value. The method of claim 9, wherein the number of significant bits is Orthogonal code generation method of claim 2, wherein the orthogonal code length is represented by an exponent of 2 below.