CA1234881A - Carrier detection circuit - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE

A carrier detection circuit includes a rectification stage, an integrator, a comparator, and a digital counter.
The rectifier stage provides a switched capacitor in com-bination with switched input signals to achieve a recti-fied output signal from a comparator. Hysteresis is provided in the comparator stage to assure that slight fluctuations in the carrier level do not change the state of the output signal from the comparator.

Description

:~23~8~

2 Yusuf A. Haque S
6 This invention rela-tes to a circuit for detecting 7 the presence of a carrier signal on a transmission line 8 and, more particulaxly, relates to a carrier detection 9 circuit suitable for fabrication as a single integrated circuit, or a portion of a larger integrated circuit, 11 requiring no off-chip components.

13 Modern developments in telecommunications have led 14 to distributed processing, the widespread use of remote terminals and a plethora of stand alone data transmission/
16 receiving stations which communicate with other data 17 transmission/receiving stations. In many cases the 18 individual stations are not manned. Even if they are 19 manned, the information which is received is in an elec-tronic format which is not directly intelligible to the 21 human operator. It is necessary, therefore, for the 22 equipment at each individual station to be able to sense 23 when a carrier signal is being received. This permits 24 -the equipment to be readied to receive data. During the times when no carrier signal is being received the indi-26 vidual station may be used for other functions or the 27 human operator may carry out tasks at other locations.

29 Prior art techniques of ascertaining the presence of 30 a carrier signal in a transmission include measurement of 31 the power level of a carrier signal. These approaches 32 have invariably required the assembly of discrete compo-33 nents and have employed complex signal processing tech-34 niques. See, e.g., M. Ahmed, et al, "Carrier Detection 35 Circuit", U.S. Patent No. 3,746,993, and A.P. Clark, et 36 al, "Detection Processes for a 9600 Bit/Second Modem", 37 The Radio & Electronic Engineer, v.51, p.544(1~81).

-2- ~ ~ 3 4 ~ a 1 1 Carrier detection 2 circuits necessarily require sensitivity to very small

3 signals and have very long time constants. Consequently,

4 previous implementations have either required the use of well controlled off-chip components such as discrete capa-6 citors and resistors and an attendant increase in -the num-7 ber of package leads, or have required the use of digital 8 to analog converters with digital processing circuitry, 9 which requires a large integrated circuit chip area. In order to provide a carrier detection circuit useable with lL portable terminals, with remote stations, or with modems, 12 it is highly desirable to have a circuit which is capable 13 of being manufactured on a-single integratPd circuit 14 chip with small die area, reduced number of package leads, and no external components required in order to establish 16 the reguired time constants.

18 The carrier detection circuit of the present inven-19 tion detects a carrier signal on a transmission line with-out having to resort to digitizing the incoming carrier and 21 then processing the function digitally. The presence of a 22 carrier signal is indicated when a threshold magnitude is 23 exceeded for a specified period of time. A l'mark" must 24 also be detected in order for a valid signal to be indi-catèd. One embodiment of this invention is a circuit 26 which incorporates a full wave rectification with gain 27 stage, a sampled integrator stage, a comparator stage with 28 hysteresis,a mark detect subcircuit, and a digital counter 29 chain. The full wave rectification with gain stage makes use of the full signal strength and provides first stage 31 amplification. The comparator stage compares the output 32 signal from the rectification stage with a reference signal 33 to determinP whether the threshold signal strength has been 34 exceeded. Hysteresis in~ures that slight fluctuations about the value of the reference voltage do not affect the com-36 parison. The digital counter accepts a positive output 37 signal from the comparator stage and counts as long as the 38 positive output signal appears continuously, in order to ~23~1~81 determine whether the threshold time period has been ex-ceeded. In conjunction with a de~ection of the presence of a mark, the presence of a valid carrier signal is indicated on the output lead of the detection circuit.
One embodiment of this invention uses analog switched capacitor signal processing techniques with digital counters to implement this carrier detection function.
The use of switched capacitor techniques in accordance with the teachings of this invention provides precision amplificati~n and time constants. Further, still larger time constants are obtained by coupling the switched GapaCitor (or analog signal processing) circuitry with digital counters. This makes it possible to eliminate use of large external resistors or capacitors which were necessary components of prior art circuits.
Thus in one aspect the present invention provides a rectifier with gain stage comprising:
an input lead for receiving an input signal;
an amplifier means having an inverting input lead and having an output lead for providing an output signal from said rectifier with gain stage;
a first capacitor having a first plate connected to said output lead of said amplifier means and a second plate connected to said inverting input lead of said ampli~ier means;
a sec~nd capacitor having a first plate connected to said inverting input lead of said amplifier means, and having a second plate;
first switch means connected between said output lead and said inverting input lead of said amplifier means;
second switch means connected between said input lead and said second plate of said second capacitor;
third switch means connected between said second plate of said second capacitor and a reference volt-a~e lead for receiving a reference vol~age; and ..~,.

~234~8~
-3a-means for controlling said first, second, and third switch means wherein, when said input signal is more negative than said reference voltage, during a first time period said first and second switch means are closed and said third switch means is open, and during a second time period said first and second switch means are open and said third switch means is closed, thereby providing said output signal on said output lead which is equal to -~vin, where ~ is the gain of said amplifier means and Vin is the voltage of said input signal, and wherein said input signal is more positive than said reference voltage, during a first time period said second switch means ls open and said ~irst and third switch means are closed, and during a second time period said second switch means is closed and said first and third switch means are open, thereby providing an output signal on said output lead which is equal to +~Vin.
In another aspect the invention provides an automatic gain control circuit comprising:
means for providing a plurality of reference voltages;
means for determining the presence and level of a carrier signal by 6equentially comparing said carrier signal with said plurality of reference voltages; and means for amplifying said carrier signal, said means for amplifying providing a gain which is selected to provide an amplified caxrier signal of a desired level.

3~
-3b-In still a further aspect the invention pr~vides a compar:itor with hysteresis comprising:
an operational amplifier having a first input lead for receiving an input signal to said comparator, a second input lead, and an output lead, said output lead providing a comparator output signal having high and low values; and means for applying a selected voltage to said second input lead of said operational amplifier, said selected voltage being positive when said input signal is positive and said selected voltage being negative when said input signal is negative;
said selected vol~age having a smaller value when said output signal on said output lead is high and having a larger ~alue when said output signal on said output lead is low.
In still a further aspect the invention provides a comparitor with hysteresis comprising:
a first input lead for receiving an input voltage;
a second input lead for receiving a reference voltage;
an output lead for providing an output signal;
an intermediate node which is sequentially provided with said input voltage and said reference voltage;
means for generating from said input voltage and said reference voltage the difference between said input voltage and said reference voltage; and amplification means for amplifying said difference and presenting said amplified difference as said output signal to said output lead.

, _ ~234~38 -3c-1 Brief Description of the Drawings 2 For a more complete understanding of the carrier 3 detection circuit of the pxesent invention, reference may 4 be had to the accompanying drawings which-are--incorporated

5 herein by reference and in which:

6 Fig. l is a block diagram showing the functional

7 blocks of a carrier detection circuit constructed in

8 accordance with one embodiment of this invention;

9 Fig. 2 is a detailed circuit schematic of one embod-

10 iment of the rectifier with gain, one of the functional

11 blocks of the carrier detection circuit of Fig. l;

12 Fig. 3 is a detailed circuit schematic of an embodiment

13 of the switched capacitor integrator utilized in the

14 carrier detection circuit of Fig. l;
Fig. 4 is a detailed circuit schematic of one embod-16 iment of the comparator with hysteresis utilized with the 17 carrier detection circuit of Fig. l;
18 Fig. 5 is a simplified schematic of another embodiment 19 of the rectifier with gain for use with the detection 20 circuit of Fig. 1;
21 Figs. 6a, 6b, and 6c form a set of timing diagrams 22 illustrating the method of operation of the _4_ 123~
1 rectifier with gain of Fig. 5;
2 Fig. 7 is a simplified schematic of another embodiment 3 of a switched capacitor integrator for use with the 4 carrier detection circuit of Fig. l; and Fig. 8 is a graph of the input signal, full wave 6 rectifier output signal, and integrator output signal for 7 the functional blocks of Fig. 1.

9 Detailed Description Carrier detection circuits are required in computer 11 terminals, modems and the like for use in de~ecting the 12 arrival of a carrier signal which potentially carries 13 data. The protocol for determining whether a carrier 14 signal is present on a line will typically involve both amplitude and time thresholds. It will vary by country, 16 or system. For example, in North America a power level 17 of -43 dbm is typically defined as the minimum acceptable 18 power level for a carrier signal. In order to ensure 19 that a valid carrier signal is present and not merely a flurry of noise, the signal must be present for some 21 minimum time, e.g., 100 milliseconds. With some protocols 2~ it is required that a "mark" (binary "one" data transmis-23 sion) be present in the signal for the required minimum24 time. For example, data transmission over telephone lines reguires that the data transmitted control some 26 characteristic of the carrier signal. For example, in 27 Frequency Shift Keying Modems, data ~logical ones and 28 logical zeros, also called "mark" and "space", respec-29 tively) is used to modulate a carrier for transmission.
For proper demodulation or reconversion of the datà on 31 the carrier to logical ones and zeros (received data), 32 the carrier being received must meet certain predefined 33 conditions. The presence of a carrier signifies that 34 valid data will follow. When the carrier signal and a mark is detected for the reguisite minimum time, the 36 modem or associated eguipment is ac~uated- In addition, 37 there is sometimes a requirement in the protocol that the 38 signal must drop below a certain level for a certain time .. . .

123~381 l in order to indicate that a carrier signal is no longer 2 present. For example, once the carrier is detected, it may be required that the carrier strength drop below 4 -48 dbm for about 10 milliseconds before it is considered that the carrier signal is no longer present.
6 The typical prior art approach to detec~ing the 7 carrier signal requires large valued discrete xesistors 8 and capacitors in addition to operational ampli~iers 9 which require large power supplies (+12V). This does not permit integration of the carrier detect circuit on a 11 single integrated circuit chip with no external components.
1~ Recently, a carrier detect circuit (The Texas Instruments 13 TMS99352) has been integrated that uses an -external 14 resistor and capacitor and makes it necessary to make available additional pins on the integrated circuit ~6 package. Another method of detecting the presence of a 17 carrier consists of digitizing the incoming carrier with 18 an analog to digital converter and applying the resulting 19 data to a carrier detect circuit constructed using digital design technigues. This technigue results in a large 21 integrated circuit die size and so is not economically 22 desirable-23 In contrast to prior art carrier detection circuits, 24 the present invention uses analog sampled data techni~ues to build rectifiers, gain stages and integrators. Switched26 capacitor techniques are also used and allow the use of 27 precision components (capacitors) which provide precise 28 and large time constants. Without switched capacitor 29 techni~ues large time constants can be"achieved,on chip u~ing resistors. However, resistance values are not 31 highly controllable in integrated circuits and thus time 32 constants based on resistance values vary by moxe than 33 300%, thus precluding their use here. The time constants 34 required here are extremely large (typically from hundreds of miliseconds to several seconds) and even the use of 36 conventional prior axt switched capacitor analog circuits 37 to construct a carrier detection circuit requires a large 38 die area. In accordance with this invention, this situa-, . . .

~2~

1 tion is alleviated by partitioning the design between an 2 analog signal processing section (consisting of a rectifier 3 with gain, integrators and comparator with hysteresis 4 providing precise, small time constants) and a digital timing section providing very long time constants without 6 re~uiring any external components and thus not requiring 7 additional package leads dedicated for conneckion to 8 external components, as is reguired in all prior art 9 carrier detection circuits which do not use digital to analog converters followed by digital signal processing.
11 This digital timing section serves to provide the addi-12 tional variable and large time constants required by the 13 circuit after completion by the analog signal processing ~4 section of some of the critical signal processing require-ments. This particular partitioning allows an efficient 16 design where analog switched capacitor techniques are 17 used to perform most of the signal processing and the 18 digital part of the circuit performs logical and timing 19 functions re~uired. The circuit operates by fully recti-fying and amplifying a very weak signal to provide a 21 useable signal. The amplification also amplifies offset 22 voltages and therefore measures are taken to minimize offset 23 voltages and their effects on the proper operation of 24 the cirCuit-Referring now to the block diagram of one embodiment 26 of this invention shown in Figure 1, an input carrier 27 signal Vin is received on input line 16., The input signal is rectified and amplified by rectification and 29 gain stage 10. The output signal from stage lO is a measure of the instantaneous amplitude of the incoming 31 carrier signal Vin. Since the incoming signal Vi~ is 32 alternating, it is necessary to first rectify Vin and 33 then integrate the rectified Vin signal over a known 34 time period to determine the power level of the input carrier signal Vin. This is accomplished by sampled 36 integrator 11 which, in one embodiment of this invention, 37 is a switched capacitor integrator. These three signals 38 Vin, the output of fullwave rectifier lO, and the output signal _7_ ~23~
1 from sampled integrator 11 are shown in Fig. 8. The out-2 put signal from sampled integrator stage 11 is provided 3 as an input signal to comparator 12 for compar~son with a reference signal Vref to determlne whether the carrier S signal Vref exceeds the threshold voltage level established as that voltage level above which a carrier is present. I~
7 the input carrier signal Vi exceeds the threshold voltage 8 as indicated by the output signal from comparator 12, the 9 digital counter 13 is actuated and begins to count in order to determine the total period of time that a carrier signal 11 Vin having a magnitude greater than the threshold voltage 12 has been detected. In one embodiment of this invention a 13 mark must also be detected in order for the amplitude and 14 total time thresholds to signify the presence of a valid `
carrier signal on input lead 16. The presence of a mark 16 is detected by mark detect circuit 14. In this embodiment, 17 if a coincidence occurs between the positive comparison 18 from comparator 12, sufficient time detected by counter 19 chain 13, and the detection of a mark by mark detect circuit 14, then a signal is provided on output lead 17 21 indicating that a carrier signal has been detected on 22 input lead 16.
23 The pri~cipal circuit blocks of the carrier detection 24 circuit of the present invention can be implemented by conventional circuit techniques. For purposes of illus-26 tration of the operation of this invention, embodiments 27 of the full wave rectifier with gain 10 and the sample 28 integrator 11 will now be described.
29 One embodiment of a full wave rectifier with gain 50 suitable for use with this invention is shown in Fig. 5. A
31 switched capacitor approach is used whereby transistors 95, 32 96 and 97 are operated in accordance with the timing dia-33 grams of Figs. 6a-6c in order to charge and discharge capa-34 citors 94 and 99. For a general description of the use of switched capacitors see K. Irie, et al., "A Single-Chip ADM
36 LSI Codec", IEEE Tranactions on Acoustics, Speech, and 37 Signal Processing, v.31, No. 1, February 1983, p. 281, at 38 p. 283-~L2348~

1 The operation of the recti~ier of Fig. 5 can be 2 understood with reference to the timing diagrams of Figs.
3 6a-6c. The switching sequence is controlled by the sign 4 of the incoming carrier signal Vin. A comparator (not shown) provides the rectifier with gain 50 with the sign 6 of the input signal Vin. For a negative input signal 7 Vin, clock signals ~1 and ~2 both go high and ~3 go~s low. The operational amplifier 98 is thus placed in the unity gain mode, 9 capacitor 99 is discharged, and the inherent offset voltage of operational amplifier 98 is present on both the 11 inverting input lead and the output lead of operational 12 amplifier 98. This causes node a (one plate of capaci-13 tor 94) to be connected to Vin while the other plate of 14 capacitor 94 is connected to the offset voltage Voff of operational amplifier 98, thus charging capacitor 94 to 16 Vi -Voff. Then~ 2 g low and ~3 goes high~ thus 17 opening switches 97, 95 and closing switch 96. Operational ~8 amplifier 98 is now configured to act like a gain stage 19 with the gain being set by the ratio of the capacitances of capacitors 94 and 99: G98 = Cg4/Cg9. When ~3 is high, 21 node a is co~nected to ground; hence, ap~itive voltage 22 transition occurs at node a (~rom Vin~to 0,where Vin is negative) 23 which is integrated on capacltor 99, thus providing a 24 negative voltage on the output lead of amplifier 98.
Conversely, when the input voltage Vin is positive, 26 ~1 and ~3 go high and ~2 goes low, thereby connecting 27 node a to ground, discharging capacitor 99, and charging 28 capacitor 94 to (0-Voff). Then, ~1 and ~3 go low and ~2 29 goes high. This connects node a to the positive signal Vin and causes a positive transition (Vin-(O-Voff)) of 31 node a. This is integrated on capacitor 99 to provide a 32 negative transition on the output lead of amplifier 98.
33 Thus, a full wave rectification with gain is achieved 34 simply by controlling switching sequence of clock signals ~ 2 and ~3 as a function of the sign of the incoming 36 signal. This allows full wave rectification and gain in 37 the same stage and, because the input signal has already 38 been sampled and held, provides a rectified, amplified 9 ~34l38~
output signal suitable for further processing by other analog signal processing blocks.
3 Another embodiment of a rectifier with gain circuit 19 4 suitable for use in accordance with this invention is illustrated in Fig. 2. The input signal Vin from input 6 lead 16 is provided to the inverting input lead of opera-7 tional amplifier 23. The noninverting input lead of 8 operational arnplifier 23 is connected to a refe~ence 9 voltage obtained by the voltage drop across resistor Ra~
The source of the voltage applied to resistor R is 11 either the negative supply Vss or the positive supply Vdd 12 depending upon which of MOS switch~s 20 or 21 is turned 13 on. The actuation of either of MOS switches 20 or 21 is 14 controlled by latch 24 which is driven by the clock signal supplied on line 25 and holds the information as 16 to polarity of the input signal. The switching of tran-17 sistors 20, 21 is selected in such a manner as to comple-18 ment the instantaneous polarity of the incoming signal.
19 For example, when Vin is positive, the signal on the output lead of operational amplifier 23 goes low, turning 21 switch 20 on and switch 21 off, thus applying a negative 22 (Vss is negative) input signal on the noninverting input 23 lead of operational amplifier 23. Then, in order to 24 cause the output signal provided on the output lead of operational amplifier 23 to go high, Vin must become more 26 negative. In contrast, when Vin is negative, the signal 27 on the output lead of operational amplifier 23 goes high, 28 turning switch ~0 off and switch 21 on, thus applying a 29 positive (VDD is positive) input signal on the noninvert-ing input lead of operational amplifier 23. Then, in 31 order to cause the output signal provided on the output 32 lead of operational amplifier 23 to go low, Vi~ must 33 become more positive. This provides a hysteresis which 34 is necessary to suppress transitions of the comparators due to thepresence of noise.
36 Rectification of the input signal Vin occurs by the 37 use of a switched capacitor gain stage under a controlled 38 switching sequence as described in Figs. 6a, 6b, 6c.

-10- ~23~
1 Operational amplifier 44 of Fig. 2 is analagous to opera-2 tional amplifier 98 of Fig. 5. SWitCh 97 in Fig. 5 is 3 analogous to switch 40 in Fig. 2. Similarly, switches 28 4 and 29 in Fig. 2 are analagous to switches 95 and 96, 5 respectively, in Fig. 5. Capacitor 94 (in Fig. 5) con- -6 sists of any combination of capacitors 45, 46, 47 in Fig, 2, 7 The embodiment of Fig. 2 permits any combination of 8 capacitors 45, 46 or ~7 to be used to program the closed 9 loop gain of operational amplifier 44. The selectio~ of capacitor 45 is made by having signal X4 high and signal 11 X5 low; of capacitor 46 by having X1 low and X2 high; and 12 of capacitor 47 by having X6 low and X3 high- ~apacitors 45, 13 46, 47 serve to set the closed loop gain of operational 14 amplifier 44 and thus the gain of stage 19.
One embodiment of the sampled integrator 11 of 16 ~ig. 1 is shown in Fig. 7. This embodiment entails the 17 use of a switched capacitor integrator, as described in 18 the K. Irie, et al., reference cited above. The purpose 19 of the sampled integrator is to integrate the output signal from rectifier 10 (Fig. 1). Clock phase ~5 peri-21 odically goes high in order to turn on transistor 101 and 22 thus discharge capacitor 102. The ratio of the capaci-23 tance of capacitor 102 to the capacitance of capacitor 10724 determines the closed loop gain of amplifier 100. The input voltage Vrect applied to the source of transis-26 tor 109 is provided by the output signal from the preceding 27 full wave rectification with gain stage 10 ~Fig. 1).
28 Clocks ~1 and ~3 go high in order to turn on switches 103, 29 109 and turn off switches 104, 110 and thus charge capaci-tor C107 to Vrect (node b) minus ground (node a) Then 31 clocks ~1 and ~3 go low to turn off transistors 103, 109 32 and turn on transistors 104 and 110. This causes node b 33 to be connected to ground and node a is forced to go to 34 virtual ground by being connected to the inverting input lead of operational amplifier 100. As a result of this, 36 the input voltage Vrect is integrated on capacitor 102 37 and appears on output terminal c. The input stage (103, 38 104, 109, 110) is repeatedly used in this fashion and the ~234l~

output signal on the integrator output lead c continues to update its old output value by adding the incremental 3 output voltage charge provided by the operation of 4 switches 103, 104, 109 and 110. After many cycles of integration, the integrator is reset by clock ~5 going 6 high, thus closing switch 101 to discharge capacitor 102.
7 Switches 105 and 106, when turned on by a high clock ~6 8 connect capacitor 108 in parallel with capacitor 107, 9 thus increasing the effective capacitance connected between nodes a and b. This is useful in changing the 11 gain of the integrator.
12 Another embodiment of a sampled integrator 11 suit-13 able for use~in this invention is shown in Fig. 3. This 14 embodiment is a switched capacitor integrator which is programmable to permit capacitors, e.g., capacitors 72 16 and 73, to be selected singularly or in combination as 17 the gain setting capacitors for operational amplifier 67 18 and thus for integrator 11. Selection of capacitors 72, 19 73 is made by means of the control line 5.
A subcircuit 9 for ~eneration of a clock signal is 21 shown in the lower left-hand portion of Fig. 3. If 2~ desired, such a subcircuit can be provided for each clock 23 used in switched capacitor integrator 11, but is only 24 shown for the purposes of illustration with respect to Clock 1. ~1 is shown as being generated by means of 26 cross-coupled chains consisting first of NAND gate 50, 27 inverter 52 and inverter gate 53, and secondly of NAND
28 gate 51, inverter 54 and inverter 55. The clock ~1 and 29 clock ~1 signals are supplied as control signals to MOS
switches 56 and 57. For simplicity, the sources of the 31 other clocks for producing clocks ~5, etc., are not 32 shown. All clock signals are generated such that the 33 clock signals used to control each pair of switches 34 (e.g., switches 56, 57) are nonoverlapping.
The input voltage Vrect to khe integrator 11 is 36 supplied to the sources of transistors 61 and 62. When ~1 37 and ~8 g low, switches 63, 64, 57 turn off and switches 61, 38 62 and 56 are turned on, thus connecting node b to Vrect, , , ..

~23~

l and connecting node a to ground, thereby charging capaci-( rect )- Then ~l and ~8 g high thus turning 3 on transistors 57, 63, 64.
4 Thus node b is connected to ground and node a is connected to virtual ground, thus discharging capacitor C58 6 through capacitor 72, thereby integrating the input 7 signal Vrect on integrator capacitor 72. The integrated 8 output voltage Vint is available from node c, the output ~ lead of Qperational amplifier 67.
In another embodiment of this invention, another 11 sequence of steps is used here, wherein ~8 goes high 12 (transistors 63, 64 turn on) and ~1 goes low ~transistor 56 13 turns on), thus connecting nodes a and b to ground, and 14 discharging capacitor C58. Then, ~8 goes low (transis-lS tors 61, 62 turn on) and ~1 goes high (transistor 57 16 turns on), integrating the input signal Vrect on integrator 17 capacitor 72. This alternative sequence of steps produces 18 an output voltage having opposite sign to that of the 19 output voltage produced by the earlier sequence.
In one embodiment of this invention cancellation of 21 operational amplifier and switch feed~through offset 22 voltages in the integrator is achieved by operating the 23 integrator or n cycles using the first sequence of steps 24 described above. Then the next n cycles are operated with the input lead grounded (Vin=0) and using the second 26 sequence of steps described above. Since, in the second 27 n cycles, the sign of the offset voltage is opposite from 28 that of the first n cycles, the offset voltages are 29 canceled over 2n cycles. In an alternative embodiment, the circuit is operated over n cycles using the first 31 sequence of steps, then (with Vin=0) capacitors C57, C58 32 are connected in parallel by turning on switches 58 33 and S9. This increases the gain of the integrator by 34 a factor of m because the ratio of the sum of the capaci-tance of capacitors C57 and C58 to the capacitance of 36 capacitor C58 alone is mn. The circuit is then operated 37 for m cycles using the second sequence of steps. The 38 offset voltages again cancel. As is easily understood by -13- ~3~
1 those in the art, in this embodiment, capacitor C57 need 2 not be used, in which case n=m.
3 Comparator 12 of Fig. 1 functions as an operational 4 amplifier in which the input signal from sampled integrator 11 5 is applied to its inverting input lead and the voltage applied 6 to the noninverting input lead is a reference voltage having 7 the same sign as the input signal from sampled lntegrator 11.
8 Alternatively, the noninverting input lead of the operatlonal g amplifier may be connected to sampled integrator 11 with the 10 inverting input lead connected to a reference voltage source 11 having the sign of the input signal from sampled integrator 11.
12 A comparator 12 suitable for use with this invention 13 is shown in Fig. 4. The particular embodiment shown in 14 Fig. 4 includes a hysteresis feature. The input voltage

15 Vint is received from output node c of integrator 11

16 (Figs. 1, 3) and presented to the sources of transistors

17 80 and 81 which are controlled, respectively, by clock

18 signals ~2 and ~2 The reference voltage Vref is

19 supplied to the sources of transistors 82 and 83 whose

20 gates are controlled, respectively, by clock signals

21 ~1 and ~1 The polarity of difference between Vint and

22 Vref indicates whether the input voltage Vint exceeds the

23 value of the reference voltage Vref. Thus, it is important

24 to amplify this difference and determine this polarity,

25 i.e., to determine when Vint crosses over Vref. This -

26 difference signal with appropriate polarity is provided

27 on output node d after being amplified by the four amplifier

28 stages. Each gain stage includes an MOS switch, a capacitor

29 and an inverting amplifier. The first stage consists of

30 MOS switch 75, capacitor 88 and amplifier 84; the second 3L stage consists of MOS switch 76, capacitor 89 and ampli-32 fier 85; the third stage consists of MOS switch 77, 33 capacitor 90 and amplifier 86; and the fourth stage 34 consists of MOS switch 78, capacitor 91 and amplifier 87.
35 The output difference voltage VCOmp supplied on output 3~ terminal d is available for input to ~he digital counter 37 chain 13 of Fig. 1.

~23~1~8~
-13a-1 When ~A goes high all inverting amplifiers 84, 85, 2 86, 87 are reset and self-biased. Also,at this time,~2is high and 3 transistors 80 and 81 are turned on so that Vint is 4 connected to input node e. Then ~A and ~2 and ~1 go low and ~1 and ~2 g high so that the value Vint minus Vref 6 is now presented to the input lead of the first stage and 7 is amplified by the four amplifier stages to produce a 8 comparator output voltage VCOmp which signifies either a g logical 1 or a logical 0 on output terminal d. Thus, the signal on the output lead of comparator 12 is a voltage -14- ~34~
1 which signifies either a digital "1" or a digital ~0".
2 The value of Vref is related to the protocol defining 3 the acceptable threshold signal. Vref is higher for 4 higher threshold values and lower for lower threshold values. In one embodiment Vref is programmable on the 6 integrated circuit chip to permit different power lavels 7 to be used to define when a carrier is present. This 8 programmability also permits the detection of dierent 9 energy levels which can be used, for example, for automatic gain control. For example, in one embodiment n different 11 energy levels are detected by employing n different 12 voltage references, and the result is stored in a memory.
13 These results can then directly control the gain of a 14 digitally programmable gain stage, with greater gain -being provided for lower level input signal levels.
16 In one embodiment hysteresis is provided in the 17 comparator circuit of Fig. 4. One embodiment causes Vref 18 to change slightly as a function of the output signal l9 VCOmp on output terminal d. Typically, the value of the reference voltage will usually be given by Vref = Xdbm, 21 where X is a selected value. The sense of the output 22 signal is that if Vint is greater than Xdbm, then a 23 digital "1"-is signifiedi if Vint is less than Ydbm 24 (where Y is a selected value less than X) a digital "0"
is signified. To provide a comparator with hysteresis, 26 the output remains a digital "1" for small fluctuations 27 of the absolute value of input signal Vint. To guarantee 28 this, as soon as the output signal VCOmp signifies a 29 digital "1", the reference voltage Vref is decreased by a small amount. Thus, it will take more than a minor

31 noise-related fluctuation of the input carrier Vin (Fig. 1),

32 which in turn provides a minor fluctuation of the inte-

33 grated voltage Vint, to change the output from a "1" to a

34 "0". The reverse approach can, if desired, also be used

35 by increasing the value of Vref once a digital "0" is

36 reached, e.g., once Ydbm is detected. This circuitry is

37 not shown but will become readily apparent to one of

38 ordinary skill in the art in light of the teachings of ~234~

this specification.
The output signal VCOmp of comparator 12 is intro-3 duced to the digital counting chain 13 (Fig. 1). Counting 4 chain 13 counts the time that a particular digital state, e.g. a digital "1", is p~esent, providing that state 6 signifies that a carrier signal of sufficient threshold 7 amplitude is present on the input lead. In a preferred 8 embodiment, once the threshold conditions are met (after 9 completion of handshake routines, as is well known in the art) and determination is made of the threshold amplitudes, 11 it is n~cessary to detect a mark ~or a specified period 12 of time in order for a satisfactory carrier signal 13 to be indicated to be present. The mark is detect-ed 14 in subcircuit 14, of well known design. This mark will represent a logical "l" (i.e., carrier is received 16 having a frequency representing a logical one).
17 In one embodiment, digital counter chain 13 also 18 contains a delay which requires a digital "1" to be 19 absent for at least a predefined minimum period of time in order to provide an output signal on line 17 which 21 signifies the absence of a carrier signal. Thus, if the 22 digital "1" is absent for only a short period of time 23 (less than the predefined period of time) the output 24 signal on line 17 will continue to indicate the presence ~5 of a carrier in order to prevent undesired termination of 26 the transmission of data due to a very short, and incon-27 sequential, absence of a carrier.
28 The specific embodiments presented in the specifica-29 tion are intended to serve by way of example only and are 3~ not to be construed as limitations on the scope of my 31 invention. Many other embodiments of my invention will 32 become apparent to those of ordinary skill in the art in 33 light of the teachings of this specification.

Claims (2)

1. Claim 1. A rectifier with gain stage comprising:
   an input lead for receiving an input signal;
   an amplifier means having an inverting input lead and having an output lead for providing an output signal from said rectifier with gain stage;
   a first capacitor having a first plate connected to said output lead of said amplifier means and a second plate connected to said inverting input lead of said amplifier means;
   a second capacitor having a first plate connected to said inverting input lead of said amplifier means, and having a second plate;
   first switch means connected between said output lead and said inverting input lead of said amplifier means;
   second switch means connected between said input lead and said second plate of said second capacitor;
   third switch means connected between said second plate of said second capacitor and a reference volt-age lead for receiving a reference voltage; and means for controlling said first, second, and third switch means wherein, when said input signal is more negative than said reference voltage, during a first time period said first and second switch means are closed and said third switch means is open, and during a second time period said first and second switch means are open and said third switch means is closed, thereby providing said output signal on said output lead which is equal to -.alpha.Vin, where .alpha. is the gain of said amplifier means and Vin is the voltage of said input signal, and wherein said input signal is more positive than said reference voltage, during a first time period said second switch means is open and said first and third switch means are closed, and during a second time period said second switch means is closed and said first and third switch means are open, thereby providing an output signal on said output lead which is equal to +.alpha.Vin.
2. Claim 2. The structure as in Claim 1 which further comprises additional capacitors which can be selectively connected to select the gain of said amplifier means.