CA1056522A - Multiplex digital echo suppression system - Google Patents
Multiplex digital echo suppression systemInfo
- Publication number
- CA1056522A CA1056522A CA207,291A CA207291A CA1056522A CA 1056522 A CA1056522 A CA 1056522A CA 207291 A CA207291 A CA 207291A CA 1056522 A CA1056522 A CA 1056522A
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- CA
- Canada
- Prior art keywords
- receiving
- signal
- output
- transmitting
- timer
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/02—Details
- H04B3/20—Reducing echo effects or singing; Opening or closing transmitting path; Conditioning for transmission in one direction or the other
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
- Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
The invention discloses a multiplex digital echo suppression system in which on each of the transmitting and receiv-ing sides the PCM signal for each channel is converted into an absolute value signal representing the absolute value of the PCM
signal by eliminating the sign bit; thus converted signals are accumulated for a predetermined time in transmitting-side and receiving-side accumulators and then compared in a comparator so that an output is derived from the comparator when the accumulated signal in the transmitting-side accumulator is higher in level than the signal accumulated in the receiving-side accumulator;
in response to the output signal from the comparator, a first timer is set to a first predetermined time during which a signal is derived from the first timer; when the signal level in the receiving-side accumulator is higher than a predetermined level of a threshold level comparator, an output is derived therefrom and applied to a second timer which in turn is set to a second predetermined time shorter than the time of the first timer, an output signal being derived from the second timer during said second predetermined time. The output from the first timer is applied to a receiving-side logic circuit which controls attenuation of the receiving-side PCM signal while the outputs from the first and second timers are applied to a transmitting-side logic circuit which controls echo suppression.
The invention discloses a multiplex digital echo suppression system in which on each of the transmitting and receiv-ing sides the PCM signal for each channel is converted into an absolute value signal representing the absolute value of the PCM
signal by eliminating the sign bit; thus converted signals are accumulated for a predetermined time in transmitting-side and receiving-side accumulators and then compared in a comparator so that an output is derived from the comparator when the accumulated signal in the transmitting-side accumulator is higher in level than the signal accumulated in the receiving-side accumulator;
in response to the output signal from the comparator, a first timer is set to a first predetermined time during which a signal is derived from the first timer; when the signal level in the receiving-side accumulator is higher than a predetermined level of a threshold level comparator, an output is derived therefrom and applied to a second timer which in turn is set to a second predetermined time shorter than the time of the first timer, an output signal being derived from the second timer during said second predetermined time. The output from the first timer is applied to a receiving-side logic circuit which controls attenuation of the receiving-side PCM signal while the outputs from the first and second timers are applied to a transmitting-side logic circuit which controls echo suppression.
Description
~6S;i~Z
BAC~GROUND OF THE I~VENTION:
The present invention relates to a multiplex digital echo suppression system for suppressing the echos produced in the channels of the satellite communications, system and the marine cable communication system without converting the digitally coded and multiplexed signal.
The prior art analog echo suppression system requires that one analog echo suppressor must be provided for each channel.
The analog suppressor is large in size and its power consumption is high. Moreover, in case of the domestic or internal satellite communications with a plurality of telephone channels, the analog echo suppressor must be provided for each channel at each earth station, thus resulting in the increase in both initial cost and installation space.
There has been also devised and demonstrated a digital echo suppressor of the type in which analog signals are converted into the digital signals by an analog-to-digital converter. How-ever, one echo suppressor must be still provided for each channel.
There has been also proposed a digital echo suppressor system in which various complex logic operations of digital signals are carried o~t so that the crest value of the audio signals may be detected, but this system is very complex in arrangement.
SUMMARY OF THE INVENTION:
-In view of the above, one of the objects of the pre-sent invention is to provide a multiplex digital echo suppression system capable of suppressing the echo without the conversion of the digitally coded audio signal.
Another object of the present invention is to provide a multiplex digital echo suppression system capable of suppres-sing the echo in a plurality of channel by only one echo suppres-sion system.
BAC~GROUND OF THE I~VENTION:
The present invention relates to a multiplex digital echo suppression system for suppressing the echos produced in the channels of the satellite communications, system and the marine cable communication system without converting the digitally coded and multiplexed signal.
The prior art analog echo suppression system requires that one analog echo suppressor must be provided for each channel.
The analog suppressor is large in size and its power consumption is high. Moreover, in case of the domestic or internal satellite communications with a plurality of telephone channels, the analog echo suppressor must be provided for each channel at each earth station, thus resulting in the increase in both initial cost and installation space.
There has been also devised and demonstrated a digital echo suppressor of the type in which analog signals are converted into the digital signals by an analog-to-digital converter. How-ever, one echo suppressor must be still provided for each channel.
There has been also proposed a digital echo suppressor system in which various complex logic operations of digital signals are carried o~t so that the crest value of the audio signals may be detected, but this system is very complex in arrangement.
SUMMARY OF THE INVENTION:
-In view of the above, one of the objects of the pre-sent invention is to provide a multiplex digital echo suppression system capable of suppressing the echo without the conversion of the digitally coded audio signal.
Another object of the present invention is to provide a multiplex digital echo suppression system capable of suppres-sing the echo in a plurality of channel by only one echo suppres-sion system.
-2-`` ~056522 A further object of the present invention is to provide a multiplex digital echo su~pression system which may be made up of conventional integrated circuit elements readily available at the market with the resultant reduction in manufacturing cost and which is simple in construction, compact in size and light in weight yet highly reliable in operation.
Briefly stated, the present invention provldes a multi-plex digital echo suppression system comprising a transmitter-side absolute value converter for converting the transmitting-side PCM signal ~or each channel into a parallel PCM signal withthe sign bit eliminated and representing the absolute value of the transmitting-side PCM signal, a receiving-side absolute value converter for converting the receiving-side PCM signal for each channel into a parallel PCM signal with the sign bit eliminated and representing the absolute value of the receiving-side PCM
signal, a transmittlng-side accumulator and a receiving-side accumulator each for accumulating the output signal from the corresponding absolute value converter for a predetermined time, first comparator means for comparing the output signal of each channel derived from said transmitting-side accumulator in syn-chronism with the transmitting-side PCM signal with the output signal for the corresponding channel derived from said receiving-side accumulator in synchronism with the receiving-side PCM signal and for generating an output signal when the output from said transmitting-side accumulator, is higher than the output from said receiving-side accumulator, first timer means which is set for a first predetermined time in response to the output signal from said first comparator means and continuously generates an output signal during said first predetermined time, threshold level comparator means for comparing a predetermined threshold level with the output for each channel derived from said 1056~22 receiving-side accumulator and or generating an output signal when the output from said receiving-side accumulator is higher than said predetermined threshold level, second timer means which is set for a second predetermined time shorter than said first predetermined time in response to the output signal ~rom said threshold level comparator means and continuously generates an output signal during said second predetermined time, receiving-side logic circuit means including attenuator means for attenua ting the recei~ing-side input PCM signal in said certain channel in response to the output for said certain channel from said first timer means, and transmitting-side logic circuit means for controlling echo suppression for said certain channel in res-ponse to a logical combination of the outputs for said certain channel from said first and second timer means.
Each of the transmitting-side and receiving-side accu-mulators preferably comprises a memory and an adder. Each me-mory and each of the first and second timer means are preferably of the random access memory type.
BRIEF DESCRIPTION OF THE DRAWING:
_ .
Fig. 1 is a block diagram of one preferred embodiment of a multiplex digital echo suppression system in accordance with the present invention;
Fig. 2 shows the frames of PCM signals used for the explanation of the mode of operation thereof; and Fig. 3 shows the output of an absolute value converter thereof.
DESCRIPTION OF THE PREFERRED EMBODIMENT:
Referring to Fig. 1, reference numeral 1 and 4 denote absolute value converters, 2 and 5, adders; 3 and 6, storage devices; 7, a comparator; 8, a first timer with a hangover time of the order of one-hundred and tens of miliseconds; 9, a second ~0~6~Z
timer with a hangover time of the order of tens of miliseconds;
10, a logic circuit on the transmitting side; 11, a logic circuit on the receiving side; and 12, a threshold level comparator.
CHl, CH2, ...... , and CHn in the storage devic~s 3 and 6 and in the timers 8 and 9 denote the channel numbers, respectively.
Reference characters Rin denotes a receiving-side input terminal;
Rout, a receiving-side output terminal; Sin, a transmitting side input terminal; Sout, a transmittin~-side output terminal; Scop, a comparison pulse input terminal at the side of the transmitting side; and Sclp, a clear pulse input terminal at the transmitting side.
The output terminal Sout and the input terminal Rin are coupled through a long-distance PCM transmission line to an input terminal at the receiving side of an echo suppressor in a remote station and to an output terminal at the transmitting side thereof, respectively. The output terminal Rout and the input terminal Sin are coupled to the associated terminals of a PCM terminal equipment. Various pulses to be applied to the comparison pulse input terminal Scop, and the clear pulse input terminal Sclp, may be generated by the PCM terminal equipment in a manner well known in the art.
Referring still to Fig. 1, the digitally coded multi-plex signals to be referred to as the "PCM signals" hereinafter in this specification are applied from the PCM terminal equipment to the input terminals Sin and Rin. The pulse frames of~ for instance, the binary coded PCM signals are shown in Fig. 2.
Next the mode of operation will be described with par-ticular reference to a specific channel of the natural binary PCM signals. First, the mode of operation of each device will be described. The first bit in each channel shown in Fig. 2 is a sign bit representing the positive or negative sign so that ~056SZ~:
the absolute value converter 1 or 4 eliminates the first bit of each channel as shown in Fig. 3. The ~utput signal of the absolute value converter 1 or 4 is applied to the adder 2 or 5, which makes up an accumulator together with the storage device 3 or 6, and is added to the signal of the correspondin~ channel read out from the storage device 3 or 6. The sum oE a ne~ absolute value and the former value in the storage device is accumulated in the adder and stored again in the storage device 3 or 6. The storage device 3 or 6 is initially set to zero. Therefore, the content in the storage device 3 or ~ is gradually increased as the above operations are cycled several times or tens of times. The outputs of the storage devices 3 and 6 are applied to the co~parator 7 to be compared with each other. When the content in the storage device 6 is higher than that in the device 3, the timer 8 is triggered so that the output "1" is derived therefrom. After that the output "1" may be maintained during the hangover time of the order of one-hundred and tens of miliseconds.
The content in the storage device 3 is compared in the threshold level comparator 12 with a predetermined thre~shold level, and when the content in the storage device 3 exceeds the predetermined threshold level the corresponding channel in the timer 9 is actuated during the hangover time of the order of tens of miliseconds so that the output signal "1" is derived therefrom.
When and only when the output of the timer 9 is "1"
while the output of the timer 8 is "0", the logic circuit 10 on the transmitting side gives the output PCM signal containing no audio signal during a time interval of the corresponaing channel at the transmitting side. When the outputs of the timers 8 and 9 do not satisfy the above condition, the PCM signal received at the input terminal Sin is transmitted through the logic circuit 10 to the output terminal Sout. That is, the logic circuit 10 ~(~56S2~
is driven into the so-called "through" condition or state.
When the output of the timer 8 is "1" regardless of the output of the timer 9 being "1" or "0", the logic circuit 11 at the receiving side accomplishes the logical conversion of the communication signal (that is, the PCM signal of the audio signal) so that the level of the audio signal may be attenuated during the associated channel time. Thus, the echo is attenuated.
The communication signal received at the input terminal Rin is, in general, the signal which is compressed by a non-linear coding circuit in the PCM terminal equipment. Therefore, the communication signal which has passed through the logic circuit 11 on the receiving side is substantially similar to the com-pressed signal. The desired characteristic in the echo suppres-sion system that the higher the level of the audio signal or audio level, the greater the equivalent attenuation becomes may be attained. Therefore, the logic circuit 11 on the receiving side is not required to have the non-linear characteristic.
When the above described accumulation operations by the adder 2 and storage device 3 or the adder 5 and storage device 6 are accomplished by a predetermined number of times, the comparison pulse in synchronism with the transmitting PCM
signal appears at the comparison pulse input terminal Scomp and is applied to the comparator 7 so as to compare the content of the storage device 3 with the storage device 6, and immediately after the comparison pulse, the clear pulse in synchronism with the transmitter channel pulse appears at the clear pulse input terminal Sclp and is applied to the storage devices 3 and 6 so that the respective channels in them are cleared or reset to "O"s. The timers 8 and 9, which are triggered in response to the output signal "l"s in the manner described hereinbefore, are automatically reset after a predetermined hangover time.
: IL051652;~
Next the five modes o~ operation will be described in more detail hereinafter.
(1~ Operation when the communication signal for a specific channel is received only at the receiving-side input terminal Rin:
~ hen the logic circuit 11 at the receiving side is put into the "through state or condition", the communication signal passes through the logic circuit 11 to the output terrninal Rout, from which the communication signal is not on]y transmitted to the PCM terminal equipment but also applied to the absolute value converter 1. The output of the timer 9 becomes "1" while the output of the timer 8 becomes "0" in response to the output of the comparator 7 in the manner described hereinbefore, so that the logic circuit 10 at the transmitting side is turned off while the logic circuit 11 at the receiving side is put into the "through state or condition".
As described above, when the communication signal ap-pears only at the receiving side, no comrnunication signal is transmitted from -the output terminal Sout at the transmitting side. Therefore, even when the communication signal received at the receiving-side input terrninal Rin appears at the transmitting-side input terminal due to the poor characteristics of the hybrid coil, the echo may be completely suppressed.
(2) Operation when the communication signal appears only at the transmitting-side input terrninal Sin:
The communications signals are accumulated by the absolute value converter 4, the adder 5 and the storage device 6 in the manner described hereinbefore. Since no communication signal appears at the receiving side, the content in the storage device 3 is "0", so that the output of the timer 9 is "0" while the output of the timer 8 is " 1'! . Therefore the transmitti~g-
Briefly stated, the present invention provldes a multi-plex digital echo suppression system comprising a transmitter-side absolute value converter for converting the transmitting-side PCM signal ~or each channel into a parallel PCM signal withthe sign bit eliminated and representing the absolute value of the transmitting-side PCM signal, a receiving-side absolute value converter for converting the receiving-side PCM signal for each channel into a parallel PCM signal with the sign bit eliminated and representing the absolute value of the receiving-side PCM
signal, a transmittlng-side accumulator and a receiving-side accumulator each for accumulating the output signal from the corresponding absolute value converter for a predetermined time, first comparator means for comparing the output signal of each channel derived from said transmitting-side accumulator in syn-chronism with the transmitting-side PCM signal with the output signal for the corresponding channel derived from said receiving-side accumulator in synchronism with the receiving-side PCM signal and for generating an output signal when the output from said transmitting-side accumulator, is higher than the output from said receiving-side accumulator, first timer means which is set for a first predetermined time in response to the output signal from said first comparator means and continuously generates an output signal during said first predetermined time, threshold level comparator means for comparing a predetermined threshold level with the output for each channel derived from said 1056~22 receiving-side accumulator and or generating an output signal when the output from said receiving-side accumulator is higher than said predetermined threshold level, second timer means which is set for a second predetermined time shorter than said first predetermined time in response to the output signal ~rom said threshold level comparator means and continuously generates an output signal during said second predetermined time, receiving-side logic circuit means including attenuator means for attenua ting the recei~ing-side input PCM signal in said certain channel in response to the output for said certain channel from said first timer means, and transmitting-side logic circuit means for controlling echo suppression for said certain channel in res-ponse to a logical combination of the outputs for said certain channel from said first and second timer means.
Each of the transmitting-side and receiving-side accu-mulators preferably comprises a memory and an adder. Each me-mory and each of the first and second timer means are preferably of the random access memory type.
BRIEF DESCRIPTION OF THE DRAWING:
_ .
Fig. 1 is a block diagram of one preferred embodiment of a multiplex digital echo suppression system in accordance with the present invention;
Fig. 2 shows the frames of PCM signals used for the explanation of the mode of operation thereof; and Fig. 3 shows the output of an absolute value converter thereof.
DESCRIPTION OF THE PREFERRED EMBODIMENT:
Referring to Fig. 1, reference numeral 1 and 4 denote absolute value converters, 2 and 5, adders; 3 and 6, storage devices; 7, a comparator; 8, a first timer with a hangover time of the order of one-hundred and tens of miliseconds; 9, a second ~0~6~Z
timer with a hangover time of the order of tens of miliseconds;
10, a logic circuit on the transmitting side; 11, a logic circuit on the receiving side; and 12, a threshold level comparator.
CHl, CH2, ...... , and CHn in the storage devic~s 3 and 6 and in the timers 8 and 9 denote the channel numbers, respectively.
Reference characters Rin denotes a receiving-side input terminal;
Rout, a receiving-side output terminal; Sin, a transmitting side input terminal; Sout, a transmittin~-side output terminal; Scop, a comparison pulse input terminal at the side of the transmitting side; and Sclp, a clear pulse input terminal at the transmitting side.
The output terminal Sout and the input terminal Rin are coupled through a long-distance PCM transmission line to an input terminal at the receiving side of an echo suppressor in a remote station and to an output terminal at the transmitting side thereof, respectively. The output terminal Rout and the input terminal Sin are coupled to the associated terminals of a PCM terminal equipment. Various pulses to be applied to the comparison pulse input terminal Scop, and the clear pulse input terminal Sclp, may be generated by the PCM terminal equipment in a manner well known in the art.
Referring still to Fig. 1, the digitally coded multi-plex signals to be referred to as the "PCM signals" hereinafter in this specification are applied from the PCM terminal equipment to the input terminals Sin and Rin. The pulse frames of~ for instance, the binary coded PCM signals are shown in Fig. 2.
Next the mode of operation will be described with par-ticular reference to a specific channel of the natural binary PCM signals. First, the mode of operation of each device will be described. The first bit in each channel shown in Fig. 2 is a sign bit representing the positive or negative sign so that ~056SZ~:
the absolute value converter 1 or 4 eliminates the first bit of each channel as shown in Fig. 3. The ~utput signal of the absolute value converter 1 or 4 is applied to the adder 2 or 5, which makes up an accumulator together with the storage device 3 or 6, and is added to the signal of the correspondin~ channel read out from the storage device 3 or 6. The sum oE a ne~ absolute value and the former value in the storage device is accumulated in the adder and stored again in the storage device 3 or 6. The storage device 3 or 6 is initially set to zero. Therefore, the content in the storage device 3 or ~ is gradually increased as the above operations are cycled several times or tens of times. The outputs of the storage devices 3 and 6 are applied to the co~parator 7 to be compared with each other. When the content in the storage device 6 is higher than that in the device 3, the timer 8 is triggered so that the output "1" is derived therefrom. After that the output "1" may be maintained during the hangover time of the order of one-hundred and tens of miliseconds.
The content in the storage device 3 is compared in the threshold level comparator 12 with a predetermined thre~shold level, and when the content in the storage device 3 exceeds the predetermined threshold level the corresponding channel in the timer 9 is actuated during the hangover time of the order of tens of miliseconds so that the output signal "1" is derived therefrom.
When and only when the output of the timer 9 is "1"
while the output of the timer 8 is "0", the logic circuit 10 on the transmitting side gives the output PCM signal containing no audio signal during a time interval of the corresponaing channel at the transmitting side. When the outputs of the timers 8 and 9 do not satisfy the above condition, the PCM signal received at the input terminal Sin is transmitted through the logic circuit 10 to the output terminal Sout. That is, the logic circuit 10 ~(~56S2~
is driven into the so-called "through" condition or state.
When the output of the timer 8 is "1" regardless of the output of the timer 9 being "1" or "0", the logic circuit 11 at the receiving side accomplishes the logical conversion of the communication signal (that is, the PCM signal of the audio signal) so that the level of the audio signal may be attenuated during the associated channel time. Thus, the echo is attenuated.
The communication signal received at the input terminal Rin is, in general, the signal which is compressed by a non-linear coding circuit in the PCM terminal equipment. Therefore, the communication signal which has passed through the logic circuit 11 on the receiving side is substantially similar to the com-pressed signal. The desired characteristic in the echo suppres-sion system that the higher the level of the audio signal or audio level, the greater the equivalent attenuation becomes may be attained. Therefore, the logic circuit 11 on the receiving side is not required to have the non-linear characteristic.
When the above described accumulation operations by the adder 2 and storage device 3 or the adder 5 and storage device 6 are accomplished by a predetermined number of times, the comparison pulse in synchronism with the transmitting PCM
signal appears at the comparison pulse input terminal Scomp and is applied to the comparator 7 so as to compare the content of the storage device 3 with the storage device 6, and immediately after the comparison pulse, the clear pulse in synchronism with the transmitter channel pulse appears at the clear pulse input terminal Sclp and is applied to the storage devices 3 and 6 so that the respective channels in them are cleared or reset to "O"s. The timers 8 and 9, which are triggered in response to the output signal "l"s in the manner described hereinbefore, are automatically reset after a predetermined hangover time.
: IL051652;~
Next the five modes o~ operation will be described in more detail hereinafter.
(1~ Operation when the communication signal for a specific channel is received only at the receiving-side input terminal Rin:
~ hen the logic circuit 11 at the receiving side is put into the "through state or condition", the communication signal passes through the logic circuit 11 to the output terrninal Rout, from which the communication signal is not on]y transmitted to the PCM terminal equipment but also applied to the absolute value converter 1. The output of the timer 9 becomes "1" while the output of the timer 8 becomes "0" in response to the output of the comparator 7 in the manner described hereinbefore, so that the logic circuit 10 at the transmitting side is turned off while the logic circuit 11 at the receiving side is put into the "through state or condition".
As described above, when the communication signal ap-pears only at the receiving side, no comrnunication signal is transmitted from -the output terminal Sout at the transmitting side. Therefore, even when the communication signal received at the receiving-side input terrninal Rin appears at the transmitting-side input terminal due to the poor characteristics of the hybrid coil, the echo may be completely suppressed.
(2) Operation when the communication signal appears only at the transmitting-side input terrninal Sin:
The communications signals are accumulated by the absolute value converter 4, the adder 5 and the storage device 6 in the manner described hereinbefore. Since no communication signal appears at the receiving side, the content in the storage device 3 is "0", so that the output of the timer 9 is "0" while the output of the timer 8 is " 1'! . Therefore the transmitti~g-
-3-~1~35~;522 side logic circuit 1~ is put into the "through state or condi-tion" ~hile the receiving-side logic circuit is driven into the "echo attenuation state".
(3) Operation when the communication signal appears at the transmitting side when the communication signal has been received only at the receiving side:
When the communication signal is appearing only at the receiving side, the transmitting-side logic circuit 10 is trans-mitting the PCM signal corresponding to no audio signal in the manner described above. That is, the communication signal is not transmitted. When the communication signal appears at the trans-mitting side, the communication signal is accumulated in the storage device 6.
In response to the reception of the comparison pulse, the contents in the storage devices 3 and 6 are compared with each other, and when the content in the storage device 6 becomes in excess of that in the storage device 3, that is, when the volume at the transmitting side of the communication signal becomes greater than that at the receiving side, the operation substantially similar to that described in (2) above is carried out. That is, the output of the timer 8 becomes "1" so that the transmitting-side logic circuit 10 is put into the "through state"
permitting the transmission of the communication signal. How-ever, the receiving-side logic circuit 11 is driven into the 'iecho attenuation state". Therefore even though the echo is not completely eliminated, but it is sufficiently attenuated.
When the volume of the communication signal at the transmitting side is smaller than that at the recei~ing side, the content in the storage device 6 becomes smaller than that in the storage device 3 so that the operation described in (1) above is carried out. That is, the transmitting-side logic :1~5~522 circuit transmits the PCM signal corresponding to no audio signal from the output terminal Sout. The receiving-side logic circuit 11 is driven into the "through state" so that the communication signal is transmitted through the circuit 11 from the input terminal Rin to the output terminal Rout. Therefore, the com-munication signal which appears at the input terminal Rin is not transmitted from the output terminal Sout so that the echo may be completely suppressed.
(3) Operation when the communication signal appears at the transmitting side when the communication signal has been received only at the receiving side:
When the communication signal is appearing only at the receiving side, the transmitting-side logic circuit 10 is trans-mitting the PCM signal corresponding to no audio signal in the manner described above. That is, the communication signal is not transmitted. When the communication signal appears at the trans-mitting side, the communication signal is accumulated in the storage device 6.
In response to the reception of the comparison pulse, the contents in the storage devices 3 and 6 are compared with each other, and when the content in the storage device 6 becomes in excess of that in the storage device 3, that is, when the volume at the transmitting side of the communication signal becomes greater than that at the receiving side, the operation substantially similar to that described in (2) above is carried out. That is, the output of the timer 8 becomes "1" so that the transmitting-side logic circuit 10 is put into the "through state"
permitting the transmission of the communication signal. How-ever, the receiving-side logic circuit 11 is driven into the 'iecho attenuation state". Therefore even though the echo is not completely eliminated, but it is sufficiently attenuated.
When the volume of the communication signal at the transmitting side is smaller than that at the recei~ing side, the content in the storage device 6 becomes smaller than that in the storage device 3 so that the operation described in (1) above is carried out. That is, the transmitting-side logic :1~5~522 circuit transmits the PCM signal corresponding to no audio signal from the output terminal Sout. The receiving-side logic circuit 11 is driven into the "through state" so that the communication signal is transmitted through the circuit 11 from the input terminal Rin to the output terminal Rout. Therefore, the com-munication signal which appears at the input terminal Rin is not transmitted from the output terminal Sout so that the echo may be completely suppressed.
(4) Operation when the communication signal appears at the receiving side when the communication signal has been appearing on the transmitting side:
The operatlon is similar to that described in (2) when the co~munication signal appears only at the transmitting side.
That is, the logic circuit 10 is driven into the "through state"
so that the communication signal is transmitted, but the com-munication signal which appears at the receiving side is atten-uated by the receiving-side logic circuit 11. When the level of the communication signal received at the input terminal Rin is higher than that of the transmitting side communication signal, the content in the storage device 3 becomes in excess of a threshold level so that the timer 9 gives instantaneously an output "1". When the comparison pulses arrives, the content in the storage device 3 is greater than that in the storage device 6 so that the output of the timer 8 reverses to "0" in response to the output signal from the comparator 7. As a result the transmitting side logic circuit 10 is reversed from the "through state" to cut off state so that the PCM signal corresponding to no audio signal is transmitted from the output terminal Soutu In response to the output 1-0 from the timer 8, the receiving side logic circuit 11 is reversed from the "attenuation statel' to the "through state". Therefore the operation des-i~S6522 cribed in (1) is carried out. The communication signal is transmitted through the receiving side, but is not transmitted through the transmitting side so that the echo may be completely suppressed.
When the communication signal with the level less than that of the communication signal which has been appearlng only at the transmitting side, appears on the receiving side, the content in the storage device 3 exceeds a threshold level so that the output of the timer 9 reverses to "1".
However, the output of the timer 8 is still "1" so that the transmitting side logic circuit 10 remains in the same through state. When the comparison pulses arrives, the content in the storage device 6 is greater than that in the storage device 3 so that the output of the timer 8 remains "1"~ There-fore, when the communication signal which appears at the re-ceiving side has a level less than the communication signal at the transmitting side, the operation described in (2) is carried out.
The operatlon is similar to that described in (2) when the co~munication signal appears only at the transmitting side.
That is, the logic circuit 10 is driven into the "through state"
so that the communication signal is transmitted, but the com-munication signal which appears at the receiving side is atten-uated by the receiving-side logic circuit 11. When the level of the communication signal received at the input terminal Rin is higher than that of the transmitting side communication signal, the content in the storage device 3 becomes in excess of a threshold level so that the timer 9 gives instantaneously an output "1". When the comparison pulses arrives, the content in the storage device 3 is greater than that in the storage device 6 so that the output of the timer 8 reverses to "0" in response to the output signal from the comparator 7. As a result the transmitting side logic circuit 10 is reversed from the "through state" to cut off state so that the PCM signal corresponding to no audio signal is transmitted from the output terminal Soutu In response to the output 1-0 from the timer 8, the receiving side logic circuit 11 is reversed from the "attenuation statel' to the "through state". Therefore the operation des-i~S6522 cribed in (1) is carried out. The communication signal is transmitted through the receiving side, but is not transmitted through the transmitting side so that the echo may be completely suppressed.
When the communication signal with the level less than that of the communication signal which has been appearlng only at the transmitting side, appears on the receiving side, the content in the storage device 3 exceeds a threshold level so that the output of the timer 9 reverses to "1".
However, the output of the timer 8 is still "1" so that the transmitting side logic circuit 10 remains in the same through state. When the comparison pulses arrives, the content in the storage device 6 is greater than that in the storage device 3 so that the output of the timer 8 remains "1"~ There-fore, when the communication signal which appears at the re-ceiving side has a level less than the communication signal at the transmitting side, the operation described in (2) is carried out.
(5) Operation when no communication signal is re-ceived by neither of the transmitting and receiving sides;
When no communication signal appears at neither the transmitting and receiving sides, the contents in the storage devices 3 and 6 are "0"s so that the output of the timer 9 is also "0". When the comparison pulses arrives, the contents of the storage devices 3 and 6 are "0"s so that the comparator 7 cannot trigger the timer 8. Therefore, the output of the timer 8 is "0".
Therefore, both the transmitting and receiving side logic circuits 10 and 11 are in the "through state". Consequent-ly, the audio signal is to b~ transmitted both through thetransmitting and receiving sides. That is, the transmitting ~s~s~z and receiving sides are "wating state" of the signals.
From the foregoing description, it is apparent that the echo suppression system in accordance with the present invention is different in construction and mode of operation from the prior art echo suppressors. That is, the devices which must be pro-vided for each channel are only storage devices 3 and 6 and timers ~ and 9 while other devices and circuits are used in common for all the channels in a time~-division manner. Various control pulses for selecting a speciic channel such as comparison pulses, clear pulses and so on are derived from the existing PCM
terminal equipment in a simple manner so that no special device is required. More particularly, many of the existing PCM ter-minal equipments comprises, in general, a unit for mainly coding and multiplexing (and demultiplexing and decoding) the audio signal into the PCM signal and a unit for extracting and gene-rating various control signals therefore so that the control pulses which are required for the control of the echo suppressor in accordance with the present may be derived from the pulse extracting and generating unit in a simple and easy manner.
When no communication signal appears at neither the transmitting and receiving sides, the contents in the storage devices 3 and 6 are "0"s so that the output of the timer 9 is also "0". When the comparison pulses arrives, the contents of the storage devices 3 and 6 are "0"s so that the comparator 7 cannot trigger the timer 8. Therefore, the output of the timer 8 is "0".
Therefore, both the transmitting and receiving side logic circuits 10 and 11 are in the "through state". Consequent-ly, the audio signal is to b~ transmitted both through thetransmitting and receiving sides. That is, the transmitting ~s~s~z and receiving sides are "wating state" of the signals.
From the foregoing description, it is apparent that the echo suppression system in accordance with the present invention is different in construction and mode of operation from the prior art echo suppressors. That is, the devices which must be pro-vided for each channel are only storage devices 3 and 6 and timers ~ and 9 while other devices and circuits are used in common for all the channels in a time~-division manner. Various control pulses for selecting a speciic channel such as comparison pulses, clear pulses and so on are derived from the existing PCM
terminal equipment in a simple manner so that no special device is required. More particularly, many of the existing PCM ter-minal equipments comprises, in general, a unit for mainly coding and multiplexing (and demultiplexing and decoding) the audio signal into the PCM signal and a unit for extracting and gene-rating various control signals therefore so that the control pulses which are required for the control of the echo suppressor in accordance with the present may be derived from the pulse extracting and generating unit in a simple and easy manner.
Claims (3)
1. A multiplex digital echo suppression system comprising a. a transmitter-side absolute value converter for converting the transmitting-side PCM signal for each channel into a parallel PCM signal with the sign bit eliminated and representing the absolute value of the transmitting-side PCM signal, b. a receiving-side absolute value converter for converting the receiving-side PCM signal for each channel into a parallel PCM signal with the sign bit eliminated and representing the absolute value of the receiving-side PCM signal, c. a transmitting-side accumulator and a receiving-side accumulator each for accumulating the output signal from the corresponding absolute value converter for a predetermined time, d. first comparator means for comparing the output signal of each channel derived from said transmitting-side accumulator in synchronism with the transmitting-side PCM signal with the output signal for the corre-sponding channel derived from said receiving-side accumulator in synchronism with the receiving-side PCM
signal and for generating an output signal when the output from said transmitting-side accumulator is higher than the output from said receiving-side accumulator, e. first timer means which is set for a first predeter-mined time in response to the output signal from said first comparator means and continuously generates an output signal during said first predetermined time, f. threshold level comparator means for comparing a predetermined threshold level with the output for each channel derived from said receiving-side accumulator and for generating an output signal when the output from said receiving-side accumulator is higher than said predetermined threshold level, g. second timer means which is set for a second predetermined time shorter than said first predetermined time in response to the output signal from said threshold level comparator means and continuously generates an output signal during said second pre-determined time, h. receiving-side logic circuit means including attenuator means for attenuating the receiving-side input PCM signal in said certain channel in response to the output for said certain channel from said first timer means, and i. transmitting-side logic circuit means for controlling echo suppression for said certain channel in response to a logical combination of the outputs for said certain channel from said first and second timer means.
signal and for generating an output signal when the output from said transmitting-side accumulator is higher than the output from said receiving-side accumulator, e. first timer means which is set for a first predeter-mined time in response to the output signal from said first comparator means and continuously generates an output signal during said first predetermined time, f. threshold level comparator means for comparing a predetermined threshold level with the output for each channel derived from said receiving-side accumulator and for generating an output signal when the output from said receiving-side accumulator is higher than said predetermined threshold level, g. second timer means which is set for a second predetermined time shorter than said first predetermined time in response to the output signal from said threshold level comparator means and continuously generates an output signal during said second pre-determined time, h. receiving-side logic circuit means including attenuator means for attenuating the receiving-side input PCM signal in said certain channel in response to the output for said certain channel from said first timer means, and i. transmitting-side logic circuit means for controlling echo suppression for said certain channel in response to a logical combination of the outputs for said certain channel from said first and second timer means.
2. A multiplex digital echo suppression system as set forth in claim 1 wherein each of said transmitting-side and receiving-side accumulators comprises a memory and an adder.
3. A multiplex digital echo suppression system as set forth in claim 2 wherein said memory, and said first and second timer means are of the random access memory type.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9237173A JPS5317451B2 (en) | 1973-08-20 | 1973-08-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1056522A true CA1056522A (en) | 1979-06-12 |
Family
ID=14052550
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA207,291A Expired CA1056522A (en) | 1973-08-20 | 1974-08-19 | Multiplex digital echo suppression system |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPS5317451B2 (en) |
| CA (1) | CA1056522A (en) |
| DE (1) | DE2439655A1 (en) |
| FR (1) | FR2246131A1 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5545761Y2 (en) * | 1976-07-29 | 1980-10-27 | ||
| JPS5828971B2 (en) * | 1977-12-20 | 1983-06-20 | 日本電気株式会社 | Multiplexed digital echo rejection device |
| JPS54179843U (en) * | 1978-06-05 | 1979-12-19 | ||
| JPS5554901A (en) * | 1978-10-20 | 1980-04-22 | Hidetoshi Tanaka | Production of shoe insole |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3499999A (en) * | 1966-10-31 | 1970-03-10 | Bell Telephone Labor Inc | Closed loop adaptive echo canceller using generalized filter networks |
| US3562448A (en) * | 1968-06-21 | 1971-02-09 | Bell Telephone Labor Inc | Common control digital echo suppression |
| US3632905A (en) * | 1969-12-19 | 1972-01-04 | Bell Telephone Labor Inc | Method for improving the settling time of a transversal filter adaptive echo canceller |
-
1973
- 1973-08-20 JP JP9237173A patent/JPS5317451B2/ja not_active Expired
-
1974
- 1974-08-19 FR FR7428429A patent/FR2246131A1/en active Granted
- 1974-08-19 CA CA207,291A patent/CA1056522A/en not_active Expired
- 1974-08-19 DE DE19742439655 patent/DE2439655A1/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5042717A (en) | 1975-04-18 |
| JPS5317451B2 (en) | 1978-06-08 |
| FR2246131B1 (en) | 1980-03-21 |
| DE2439655A1 (en) | 1975-03-27 |
| FR2246131A1 (en) | 1975-04-25 |
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