JPS5828971B2 - Multiplexed digital echo rejection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an echo suppression device for suppressing echoes that cause deterioration of call quality in long-distance telephone transmissions, and particularly relates to an echo suppression device for suppressing echoes that cause deterioration of call quality in long-distance telephone transmissions, and in particular when signals on a communication path are digitized and time-division multiplexed. This invention relates to a multiplexed digital echo rejection device with an operation monitoring function, which is used for transmission lines.

Conventionally, to monitor the operation of the multiplexed echo rejection device as described above, a dedicated measuring device is used, and each channel is disconnected from the line before it becomes a multiplexed digital signal, and the analog signal is used to ensure that the echo rejection device is functioning correctly. This method uses the conventional monitoring method for analog echo rejection devices, which tests whether or not the echo is being detected.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multiplexed digital echo suppression device that automatically captures a communication path where there is no communication, and inserts a monitoring signal in the form of a digital signal into the communication path to monitor the operation. be.

The present invention provides a multiplexing digital echo rejection device used when the transmission path is digitized and time-division multiplexed.
Based on the information, it is determined whether each communication path is in use or not, and a monitoring signal with a specific pattern is inserted into the time slot of one or more communication paths that are determined to be not in use, and multiplexed. The corresponding output from the digital echo rejection device is monitored to ensure that there is no difference greater than the error from the output when the multiplexed digital echo rejection device is operating normally, and if there is a difference, an alarm is issued and maintenance is performed. At the same time, the communication path that is not being monitored is disabled (that is, the function as an echo suppression device is stopped, and the transmission loss in both the transmitting and receiving directions is reduced to 0 (dB)). In addition, when the signal on the channel into which a monitoring signal is inserted changes and a call state is established, the channel to be monitored is immediately switched to another channel that is not in use, and all calls are This is a multiplexed digital echo prevention device that has a function of stopping monitoring when the line is busy and a function of inhibiting the alarm output that occurs transiently at the time of switching.

FIG. 1 is a diagram showing an embodiment of the present invention.
, n (ff positive integer) is an n-bit input and m-bit output priority encoder 201 . A delay circuit 202, a no-call detection circuit 200 consisting of two matching circuits 203 and 204, gate circuits 205, 206, and 207, and a transmitting circuit 301. A receiving circuit 302, a monitoring circuit 300 consisting of two 7-lip flops 303, 304, a gate circuit 305, an inverting circuit 401, and a gate 4
02 to 410 are provided.

The operation of this embodiment shown in FIG. 1 will be explained below.

S I G1. S I G2””” S I G n
is the signal (signaling) corresponding to each of the n communication paths
It is assumed that the value is 1 when there is a call and O when there is no call.

This signal information is transmitted from the transmission path signal on the transmitting side or the receiving side.
It can be easily extracted using well-timed pulses.

Also, CHNo is n channel multiplexing digital echo blocking circuit 1.
00 is an m-bit binary code indicating the number of the channel being processed.

(b) Channel multiplexing digital echo blocking circuit 100 is published in the literature/Journal of Electronics and Communication Engineers +77/3■oβ.

J60-A Tsuta 3pp, 237-244 As described in "One configuration method of a multiplexed digital echo suppressor", it is installed on a transmission path where audio signals are digitized and multiplexed, and - Digitally multiplexed echo prevention function that prevents echoes by detecting the voice on the receiving side and controlling the echo suppression switch on the transmitting side and the reception loss insertion switch on the receiving side.

Furthermore, S IN, S OUT. RIN and ROUT each have n channel multiplexing digital echo prevention function,
These are the transmitting output, the receiver's power, and the receiving output.

AIM is an alarm output and becomes 1 when an alarm occurs.

Now, when one or more of SIG1-5IGn becomes 0, indicating a no-call state, JSI GJ~' is output as the output of the well-known priority encoder.
An m-bit binary code indicating the highest priority channel number among the 5IGnJ is obtained.

This is matched with "CHNOo" in the minus number circuit 204, and in the time slot where both match, a selector for switching between S IN and S side monitoring signal consisting of gates 402 to 404, and RIN consisting of gates 407 to 409 are selected. and the R side monitoring signal are switched to the monitoring signal side, and at the same time, the anti-games 1-405 and 406 are closed so that the monitoring signal processed by the multiplexed digital echo blocking circuit 100 is not sent to the external transmission path.

The monitoring signal processed by the n-channel multiplexing digital echo rejection circuit 100 is input to the receiving circuit 302 in the monitoring circuit 300 in order to determine whether the processing is being performed correctly.

The operations of the transmitting circuit 301 and receiving circuit 302 will be described later, but
When the receiving circuit 302 determines that the processing of the n-channel multiplexing digital echo blocking circuit 100 for the monitoring signal is incorrect, it generates an alarm output ALM and at the same time uses this as a disable signal to disable the n-channel multiplexing digital echo blocking circuit. Stop 100 functions.

However, in this case, if the channel that is being monitored is also de-cebuild, the n-channel multiplexing digital echo blocking circuit 100 will be considered to be malfunctioning even after the cause of the alarm output ALMj has been eliminated. was made, and henceforth ``
The alarm output ALMJ remains generated.

In order to avoid such a situation, the AND gate 410 prohibits the communication path being monitored from being disabled.

Now, of the signal information indicating the no-call state, if the one with the highest priority changes to the call state, or if the signal information with a higher priority changes from the call state to the no-call state, of course The output of priority encoder 201 changes.

On the other hand, the output of the delay circuit 202 configured to delay one sample period of signal information has not changed yet.

Therefore, the output of the - number circuit 203 changes to O at this time,
Two flip-flops 303.3 in the monitoring circuit 300
The reset input of 04 is reset to 0, and the gate 305 is inhibited to inhibit generation of the transient alarm output ALM.

In addition, when all the signal information becomes 1 and there are no communication channels in a non-call state, the output of the gate 205 becomes O, and the selector that inhibits the regate 207 and switches between the audio signal and the monitoring signal on the S side and the R side is activated. Switching to the supervisory signal side is prohibited, and the two flip-flops 303 and 304 are further reset to prohibit generation of the alarm output ALM.

To cancel this prohibition, it is necessary that the output of the - number circuit 203 is stable at 1, and that any one of "5IG1" to "5IGnj" is in a no-call state, but these two conditions are not met. If you enable the alarm output ALM immediately after the
A transient alarm output ALM that occurs due to operating time, recovery time, etc., which is a characteristic of 0, is sent to the outside.

In order to prevent this, a binary counter consisting of flip-flops 303 and 304 is provided, and the prohibition of the alarm output ALM is canceled only after counting two pulses of the Re s e signal applied to the receiving circuit 302 in the monitoring circuit 300. Ru.

This "Re5et" signal has one or more cycles of the R-side monitoring signal and the S-side monitoring signal, and is also input to the receiving circuit 302 in order to return the receiving circuit 302 to the initial state every cycle. .

Next, the transmitting circuit 301 and receiving circuit 3 in the monitoring circuit 300
02 will be explained.

FIG. 2 is a block diagram showing an example of the transmitting circuit 301 and the receiving circuit 302.

In the transmitting circuit 301, a counter 351 counts frame pulses "FP" generated each time data of n channels are taken into the n channel multiplexing digital echo prevention circuit 100, that is, every sampling period of the audio signal, and outputs the frame pulses "FP". RO
M (read-only memo IJ) 352 is input.

The ROM 352 is preprogrammed with a monitoring signal having a specific pattern, that is, when expressed in analog terms, binary data having an envelope as shown in FIG. Thereafter, it is output as the R side monitoring signal R8V.

On the S side, in the same way as R8V, data that can be expressed in analog form as shown in Figure 3 is sent to the S side monitoring signal SS■.
occurs as.

When R8V and SSV are respectively input to RIN' and SIN' of the n channel multiplexing echo rejection circuit 100, the respective levels are compared with a fixed threshold value or with each other, and the transmitting side circuit operates according to the result. After an appropriate loss is given in the receiving side loss circuit, ROUT', S OUT
' is output.

The outputs ROUT' and SOUT' should be binary data that can be expressed in an analog manner as shown in FIG. 3c and d.

Here, ■, ■, ■, ■, and ■ are the suppression recovery time, suppression operation time (receiving, constant level), interrupt recovery time (receiving, constant level), and interrupt operation time (sending, level constant), respectively. ), interrupt recovery time (constant transmission level) ( CCITT Green book, Re
(according to corrmendat 1onG161).

The other two ROMs (356, 357
) is ROM (352.

353), each of the n channel multiplexed digital echo rejection circuits 100 processes the R S
Binary data imitating the V signal and the SS■ signal is generated and input to the receiving circuit 302.

The operation of the receiving circuit 302 is exactly the same for the receiving side and the transmitting side.

The receiving side output ROUT' and the sending side output SOUT' of the n channel multiplexing digital echo prevention circuit 100 are connected to the receiving circuit 3.
The data is input to serial/parallel conversion circuits 372 and 379 in 02 and becomes parallel data.

This parallel data is matched in matching circuits 373 and 380 with the outputs of ROMs 356 and 357 in the transmitting circuit.

If the n channel multiplexing digital echo rejection circuit 100 is operating correctly, the two matching circuits 373 and 380 should each be 1, but in reality, there is an error in the time axis direction, so they are not always 1. No.

Therefore, the output of the matching circuit is sampled by flip-flops 374 and 381 which output the D input to Q at the rising edge of the C input, and further flip-flops 375 and 382
gives a delay of one sample period.

Flip-flops 374 and 37 connected in cascade
The logical sum of the outputs of 5 degrees 381 and 382 is always l if the sampling period is greater than or equal to the error in the time axis direction.

This situation is shown in FIG. Point (2) is the point at which there is an error in ROUT'.

Also, the state when the output of the OR gate 376 becomes O is 0.
In this case, assuming that ROUT' has an error greater than the error, the two gates 377 and 378 set the R-S flip-flop that is reset by "Re se tj" at every appropriate period, and output an alarm. Let be 1.

From the above operation, it is clear that -number circuit 373.3
It is sufficient that the period for sampling the 80 outputs is slightly wider than the allowable error.

Pulses for sampling are generated by the frequency dividing circuit 371 using a part of the output of the counter 351, but if there is another suitable pulse source, it may be used.

As described above, in this embodiment, the n channel multiplexing digital echo blocking circuit 100 is configured.

It is possible to monitor the operation of most parts, including the voice detection section, timer circuit, transmission-side suppression circuit, and reception-side loss circuit.

[Brief explanation of drawings]

FIG. 1 shows one embodiment of the present invention, FIG. 2 shows an example of a detailed configuration of a transmitting circuit and a receiving circuit in FIG. 1, and FIG.
The figure shows an example of a monitoring signal (waveform) according to the invention and the waveform after the monitoring signal has been processed by the echo rejection device, and FIG. 4 shows a time chart in the receiving circuit. 100...n channel multiplexing digital echo blocking circuit, 2
00... No call detection circuit, 201... Priority encoder, 202... Delay circuit, 203...
Matching circuit, 204... Matching circuit, 300... Monitoring circuit, 301... Transmitting circuit, 302... Receiving circuit, 3
03゜304...Front frame, 351.
...Counter, 352...ROM, 353...Parallel-serial conversion circuit, 354...1 (OM, 355...Parallel-serial conversion circuit, 356 357...ROM, 371...
・Frequency divider circuit, 372...Serial-to-parallel conversion circuit, 373...
・Concordance circuit, 374...Flip-flop, 375・
...Flip-flop, 379...Serial-to-parallel conversion circuit,
380... Matching circuit, 38L382... Flip-flop.

Claims (1)

[Claims] 1. In a multiplexed digital echo rejection device having an echo rejection circuit and installed in a digital time division multiplex transmission line equipped with a time slot for carrying specific signal information capable of determining the call/non-call state of the Kodo channel, the above-mentioned a non-communication path detection means for detecting a communication path in a non-communication state based on signal information; and at least one communication path detected by the detection means that is not in a communication state.
an insertion means for inserting a supervisory signal into a time slot of one communication path and outputting the supervisory signal to the echo prevention circuit; a transmitter that generates the supervisory signal and supplies the supervisory signal to the insertion means; monitoring means having a reception determination unit that receives the monitoring signal and determines whether or not the received signal is a signal that has been correctly processed by the echo prevention circuit; and means for stopping the echo prevention function of the echo prevention circuit for a communication path other than the communication path into which the monitoring signal is inserted when a malfunction of the echo prevention circuit is detected. blocking device.