AU610988B2 - Method and apparatus for decoding error correction code - Google Patents

Description

i 1 I I I I I A S F R f: 85474 FORM COMMONWEALTH OF AUSTRALIA PATENTS ACT 1952 COMPLETE SPECIFICATI 1 0 9 8 610980 o

(ORIGINAL)

FOR OFFICE USE: Class Int Class 0 Complete Specification Lodged: Accepted: Published: Priority: o Related Art: Name and Address of Applicant: Sony Cnrporation 7-35, Kiashlnagawa 6-Chome Shinagawa-Ku Tokyo

JAPAN

Spruson Ferguson, Patent Attorneys Level 33 St Martins Tower, 31 Market Street Sydney, New South Wales, 2000, Australia Address for Service: Complete Specification for the invention entitled: Method and Apparatus for Decoding Error Correction Code The following statement is a full description of best method of performing it known to me/us this invention, including the 40) Q 0 0. 0 2 5845/4

SPECIFICATION

TITLE OF THE INVENTION METHOD AND APPARATUS FOR DECODING ERROR CORRECTION CODE TECHNICAL FIELD This invention relates to a method and an apparatus for decoding error correction code.

The present application is a further application under the provisions of S51 of the Australian Patents Act and based on parent Australian patent application no.37812/85 0 S to the same applicant.

9o BACKGROUND ART Product code are well known such that information a symbols are arranged in two-dimensional form, error correcto o.

ion code are encoded for each reo' -nd column on tne tw:dimensional arrange:rnt sc that each information 0°00* included in two error correction code series. In dc _in S the product code, error correction code is decoded for ecch S 0 0 o 00 row by employing of the decoce information. The decode information is called a pointer.

0 00 In the conventionil method, since each information symbol is associated with a pointer, it is required that the total number of pointers is at least equal to the number of the information symbols.

Further, in the case where erasure correction is made by employing the pointers, since the pointer are read out from a pointer memory and the error values is calculated every row, there exists a problem in that the number of processing steps such as memory accesses, calculations and I 1 so on inevitably increases.

On the other hand, in the case where complicated codes such as BCH codes are employed as error correction codes, since the operations for obtaining error values become inevitably complicated, there exists a problem in that a great number of program steps are required in the case where the calculation are implemented by hardware.

DISCLOSURE OF THE INVENTION An object of this invention is to provide a method S and an apparatus for decoding error correction code which 0 a 0 oo enable to reduce the number of pointer required in decoding .oO:0 as well as the memory regions for pointers and the number .0 of times of reading and writing the pointers.

o o0 Another object of this invention is to provide a o":o method and an apparatus for decoding error correction code which enable to markedly reduce the number of processing steps in dependence upon the fact that the pointers with 0 0 respect to each row are the same.

Still another object of this invention is to provide 0 0 0 o oo o an apparatus for decoding error correction code which enable to reduce the number of calculating steps in an erasure correction.

Still further object of this invention is to provide a method for decoding error correction code which can obtain error values in decoding in dependence upon a simple construction and a small number of pocessing steps.

3ruryt? a- 4r ^1 Thoo^l n-o- flc nifd f i I1 k 'n-6d i 'l-.rhi hhia^an 2 3 According to one aspect of the present invention there is provided a method for decoding and correcting erasure in Reed=Solomon code in accordance with the roots of: solving the expression SY Xk k k=1 where,\ 0 to d 2 n Number of erasure Xk Location of kth element Sy': Syndrome i0 Y Magnitude of error in the erasure of kth element S00 k I, d Minimum distance of code characterized in that the roots are obtained by solving the following oo equation 0o o n-1 SY -7 ni j k Xi k i where A ni Coefficient of Z J of (z Xk)3 00."0 0 k 1 o 0 0 0 0 S: Any integer more than or equal to 0 which o °5 satisfies e d n 1.

According to another aspect of the present invention there is provided an apparatus for decoding and correcting erasure in Reed=Solomon aSo code In accordance with the roots of Sy= X Yk k 1 where,v 0 to'd 2 n Number of erasure

X

k Location of kth element Sy: Syndrome HRF/0369y 3a Yk Magnitude of error in the erasure of kth element d Minimum distance of the code characterized by syndrome register means for storing syndrome S and operating logic means for obtaining the roots YI of the above equation by solving the following equation: n-1h n Yi 2 nij S i (x x i j=0 k=1 k-i where nij Coefficient of Z 3 of I[ (Z Xk)] k=l kti SAny integer more than or equal to 0 which satisfies t d n characterized in that said operating logic means includes register means for storing syndrome Sy register means for storing X( Yi; register means for storing X; Y adder means for adding Sy- and X i

Y

1 and for supplying said register mea:;n and syndrome register means with Sy

X

1 Yi; multiplyer means for multiplying Xi and Xi Y, and for supplying said register means with X Y 1 000 15 oa o i 0 5 o0 0 O0 o 49Y I i -4- BRIEF DESCRIPTION OF THE DRAWINGS Fig, 1 is a schematic block diagram showing an encoder according to an embodiment of the present invention.

Fig. 2 is a schematic diagram for assistance in explaining the operation of an embodiment of the present invention.

Fig. 3 is a schematic block diagram showing a decoder according to one embodiment of this invention.

Fig. 4 is a block diagram showing an embodiment of this 0 0 invention.

0 0 0 Fig. 5 is a block diagram showing an essential portion of o.an embodiment of this invention.

000 Fig. 6 is a block diagram showing an construction of an 0 0 0 00embodiment for use with this iLnvention.

Fig. 7 is a block diagram for assistance in exp~lning a 000 00 processing circuit of Fig. 6.

0 0 0 0 00 BEST MODE FOR CARRYING OUT THE INVENTION 0 00 An emoietof tepresent ineto will be dc.beu, referring to the drawings. Fig. 1 show#s a structure of an encoder 0 0 termirnal, the reference numeral 2 denotes a C 2 (the second error correction code) parity generator. The input data frowr the input terminal 1 are supplied to the C 2 parity generator 2 and one input terminal of a selector 3, and the C 2 parity data formed by the C2 parity generator 2 are supplied to the other input terminal of the selector 3. The selector 3 repeats k1 times the operations for selecting (n 2 k 2 parity data after k 2 information symbols are selected. During 'this operation, the information symbols and the parity data are stored in a RAM (Random Access Memory) 4 in sequence under control of an address controller The data read out from the RAM 4 are supplied to a C 1 (the first error correction code) parity generator 6 and one input terminal of a selector 7 and the C 1 parity data formed by the C, parity generator 6 are supplied to the other input terminal of the selector 7. The selector 7 selects 1 k 1 x k 2 C, parity data of after having selected (k 1 x n symbols including the C 2 pa rity data. The digital data derived from art outoput terminal 8 of the selector 7 are transmitted or recorded on a magnetic tape (not shown) with a magnetic head, for instance. In this case, it is possible to write again the encoded output once into the RAY. 4 and to read out it in different sequence for recording.

as Fig. 2 shows an configuration of code formed by the encoder &described above. The information symbols are arranged in two o dimension of (k I x k 2 The k2information symbols in every lateral direction, that is, in every row of the two-dimensional 00 arrangement are subjected to encoding process for the C 2 code. The k1 information symbols in every vertical direction, that is, in every column are subjected to encoding process for the C 1 code. The C, parity data are also encoded into the C, code. The C, code is, for instance, (nl, kl) Reed-Solomon code, by which it is possible to correct errors of up to (n I k 1 U2 symbols.

The general method of decoding the Reed-Solomon code w'ill be described.

6 The hamming distance of the k) Reed-Solomon code (n denotes the code length and k den6tes the number of information symbols) on a Galois Field GF(2 m can be expressed as (d n k 1) and the generator polynomial can be expressed as d-2 II (x i If the received words are (r 0 r 1 r 2 rn- 1 l' i=0 n the syndrome can be obtained by operating the following expression: n-1 Sj r~ 1r i (3 0, 1, d-2) i=0 (1) i o

L

Iooa An error'location polynomial and an error evaluation S polynomial are obtained by employing the syndrome S As to 0o* this method, Euclid's mutual division method, Varlay-Camp's method, °o Peterson's method and so on have been proposed.

By solving 0, the error location X i can be obtained.

o oo S For this purpose, Chien search is employed.

o Q0 SThen, the error value Yi can be obtained on the basis of o the error location X i and the error evaluation polynomial Q(z).

The above calculations in the decoding steps are explained Soo00 number of errors), and the error value as Yi. Since the Reed-Solomon code is a liniear code, the syndrome can be expressed as: e Sj E i X 3 (D 1, 2, d-2) i=l if the syndrome is expressed by a polynomial as: (2) I j~l_ -7d-2 S(Z) Sj zi 3 j=0 a following expression is obtained: e d-2 S(z) Y(X= Z) i l (mod. d-.

a. 1Xi z if the error location polynomial and the error evaluation polynomial are defined as 0 0 0 0 0 e 6(z) ri; (1 Xj z) 0000 U C(z) 6(z) S(z) (6) 0oo then cLj(z) can be expressed as 0 e e U I r I=1 (IX z 0 004 0 00a e Yi ri (21 Z) (mod. z (7) The error value Y can be cbtaned try substitutng X into and by transaforring the expressiton 4z ollowa: e 1 Y 17 (l X" 'X Xi 8 As an exsample, (32, 24) Reed-solomon code having roots of 0 to N7 will be explained. Since this code is it is possible to correct errcrs of up to 4 symbols. If the error locations of the 4 symbcls are X 1 to X 4 and the error values are Y. to Y 4 the syndrome is obtained from following expression.

4 S= U yi Xi) 0 to 3) i=l Namely, S O is as follows among 4 syndromes: 4 i=l Once the error values Y, Y 2

Y

3 can be obtained, the remaining error value Y4 is obtained as follows without implementing 0 0* complicated calculations: 0 00 Y4 S0 Y 2 Y3 a a 4 02 In codeo on GF(2m), a subtraction is equivalent to an addition of (mod. 2).

00 Fig. 3 shows a configuration of the encoder of this embodiment. In Fig. 3, the reproduced data are supplied from an input terminal designated by the reference numeral 11 and to a C 1 decoder 12. In the C decoder 12, the decoding of the C 1 code is performed. All1 errors of up to (n I k1)/2 symbols are corrected in the C 1 decoding. In the case, however, where the number of errors in a single series of C 1 code is more than or equal to a kl)/ 2 the C, pointers of this series is set to the 9other pointers are set to "On. In Figs. 2 and 3 the r elere-nce numeral 13 denotes a pointer memory for storing the pointers cop the 01 code, which has no bits. The output of thu 3ecoder 12 io stored temporarily in a PAY 14 in sequence under the control of an address controller The outp~ut read out from the RAM 2.4 are supplied to a C 2 decoder 16 to be subjected to the decoding of the 0 2 code, The 02 decoder 16 is supplied with trie C, pointer from the pointer memory 13. Since the Cl pointer is common to the all of K, series of C 2 0 0 0code, it is possible to decode the 02 code in accordance with the Ssame procedure in each series, The C, decoder 16 corrects arrorr? of up to (n 2 symbols an4 generate three kinds of po~rnte-s 0 00a In the C02 code which is stored in a pointer memory 17, 0When error correction perfomed by the C 2 decoder 16, the

C

2 pointers with respect to tnie series is set to When error correction can not be performed by the C02 decoder 16 and the C1 0 0pointers are copied b.ecause of its hijh rellability, thle c 2 pointers is set to When error correction can not be performled o1 0 Q0. by the C 2 decoder 16 and all symbols are determined to be erroneouso Symbols becn-,uze of low rlaltyof the C 1 PoInte' tile C 2 pointers are set to Therefore, the C2, pointero have 2 bits and the pointer memory 17 2X, 1 tits.

Those pointer memcries 13 and 17 ,re 4.sposed zeparately trom the kAM 14 for storing irformation sytnbols and parity data ir' decoding or dizpo.sed in common with the RAM 14 1by using a parit cl memory regions of the RAM 14.

YkMagnitude of error in the erasure of kth element d Minimum distance of code characterized in that the roots are obta 1 ,ed by solving the following Without being limited to 1 bit, the C 1 pointer may have 2 bits or more. Further, it is possibl.e to implement the error L correction code processing of C code for the C 1 parity, while 21 providi nd a C 2 pointer memory of (2n) bits.

Tj2a output data of the C decoder 16 are supplied to an 2 interpolation circu-,t 18 to conceal error- in the symbols which have not been corrected The interpolation circuit 18 performs e mean value interpocatior., for intstance. The interpolation ci.rCui.

18 is controlled by a control circuit 19 which is supplied with the C 1 pointers and the C 2 pointers from the pointer memories 13 and 17. TPhe output data of the interpolation circuit 18 are derived at an output terminal 20, The control circuit 19 determines by every information symb~ol whether interpol~ation neces;,ry on t;e basis of the C, pointer and c, pointer. in Fig. 2, There ex:ist all the combinations of C 1 pointers designated as 13' and C, pointers desi~nated as 17'.

Woen the C, Pcinter is I'D" irrespective of the fact that th*,e C, pointpvr is or P1,the interpolation circult 18 does not work. When the C pointer is I'll and the C 1 pointer is "on, since 4t is determined ttat the informtin symbol has no erro~r, no nterpolation is done, When the C 2 poin~ter is "I and the C 1 pointer is I"l1"p r~Ce it is determined that it ic erroneous symrclt the intortpolation operation is performed. Further when the C, pointer is 0211 irrespective of the fact that, the C 1 pointer is n Ot! or since it is 6etermined 1;,hat it it erroneous symbol, the inmtt,.rpolation operation is perforie6.

Sd n-1 characterized in that said operating logic means includes register means for storing syndrome Sy; register means for storing X yi I1 The reliability of the C, pointers is evaluated by the C 2 er. For instance, provided that up to 2 symbol errors can be corrected by the C 2 code, if correction by the C 2 code can not be performed in spite of the fact that only one C 1 pointer is Oin, it is det ;rmined that the reliability of the C 1 pointer is low because the above is abnormal. Even if errors are not corrected by the C 2 code, it is possible to eliminate the necessity of interpolation by providing three kinds 0, 1, 2 of the C 2 pointers and by discriminating the copies of C 1 pointers from all errors.

in the above mentioned C 2 decoder 16, when the C 1 pointers are copied, the erasure correction is made where the number of the C pointers is less than or equal to (n 2 k 2 and when the erasure correction is made, the C 2 pointer is set to As described above, the decoding of the Reed-Solomon code is performed by calculation of the error location polynomal e(z) and the error evaluation polynomial l(z) every row and by employing syndrome obtained by n, symbols in each row. In the case of erasure correction, since the locations where the C 1 pointers ate "ni are detrmned as the error locations, it is possible to obtain the error value Yi from the error location X i and the error evaluation polynomiala'(z). That is to say, by substituting X

I

in -lace of Z, Y' can be obtained as follows as in expression (8) Yi rI (I x jxi O (where i I, 2, 3, s s denotes the number of symbols) I~Ib ii. I U ji.pj U ~27E~ r- 12 In the above expression, the term of denominator can be determined by only the error locations. For instance, provided that the error locations shown by the C 1 pointer are Xl, X 2

X

3 the terms of denominator of the expressions for obtaining the error values Y,, Y 2' Y3 are Denominator of Y (1 X 2 X (1 X 3 x -1) Denominator of Y2; (1 X 1

X

3 (1 X 2 X3-) Denominator of Y (1 X 1 X (1 X 3

X

Here, the pointers stored in the pointer memory 13 are the same in the all of K 1 series of the C 2 code. Therfore, it is sufficient to implement the calculation of term of denominator in the above expression to obtain error value only once with respect to the k.

series.

a Fig. 4 shows the configuration of an error correcting a• decoder for use with the aoove mentioned C 1 decoder and C decoder.

The received data are supplied to an input terminal designated by o0% the reference numeral 21 and supplied to a delay circuit 22 and a syndrome generating circuit 23. The syndromes formed by the o 01, syndrome generating circuit 23 are supplied to an error location and error value calculating circuit 24. The error data from the error location and error value calculating circuit 24 are supplied to an exclusive OR gate 25 and added to the received data from the delay circuit 22 in (mod. The received data from the delay circuit 22 and the error corrected data from the exclusive OR gate are supplied to a selector 26. The selector 26 is controlled by the error location data. At the error locations, the output of the ~ir _Z .d .JL Y -Y eY~ P~ 1IYLIC q~q~ r~ 5845/4 1[" 13 exclusive OR gate 25 is selected by the selctor 26 to be derived at an output terminal 27 in place of the received data.

In the case of an audio PCM signal recording and reproducing apparatus, the reproduced data are once written in a RAM. By use of the data read out from the RAM, the syndrome is generated and on the basis of which the error locations and the error values are calculated. Fig. 5 shows a part of the error location and error value calculating circuit 24. In Fig. 5, the reference numeral 28 denotes a data bus through which data and syndrome and so on are transfered.

000i In Fig. 5, the reference numeral 29 denotes a syndrome register in which the syndrome S is stored through the data bus 28, a bus buffer 30 and an exclusive OR gate 31. the syndrome S 0 S has m bits in the case of Reed-Solomon code on GF( 2 The o a syndrome S, from the syndrome register 29 is supplied to the exclusive OR gate 31 and the bus buffer 32.

When the syndrome S O is stored in the syndrome register 29, 0 the obtained error values Y 1

Y

2 Yj are supplied to the excl-sive OR gate 31 in sequence from the data bus 28 through the bus buffer 30. Therefore, the output of the exclusive OR gate 31 is (S 0 Y Y)

(S

O C Y1 Y 2 and (S 1 Y 1

Y

2

Y

3 y 4 The error value Y is left in the syndrome register 29. The error value Y4 is outputted 4 4 to the data bus 28 through the bus buffer 32 to be employed for error correction.

Fig. 6 shows another example of hardware for decoding in an erasure corrction. A main RAM 35 is connected to the data bus 28 processing steps such as memory accesses, calculations and -1 14 through a writing register 33 and a reading register 34. The syndrome register 29, a working RAM 36 and an operation logic circuit 37 are provided to the data bus 28.

The erasure correction by Reed-Solomon code can be concluded by solving the following n-order liniear simultaneous equations in the same way as in expression (2) n =S X Yk k=l where, V 0 to d 2 n Number of erasure 0

X

k Location of kth o0O S Syndrome Yk Magnitude of error in the erasure of kth od Minimum distance of code °O Here, n, Xk, are known, Yk is unknown.

To solve the above equation, the following method has -been conventionally adopted: if n A(z) 1- (1 X i

Z)

i=l S(z) A mod.

Z

d l Yi can be obtained as in expression as follows: .1l n Xj -11 Y, II (I X i In this method, however, if the number of actual calculation steps is counted when d 9 and n for instance.

SI B 64Nq--1 4zzxz -zd -n -1,ic ora-ur czrr'ctiv G ~p~LI~ 2~ -2 Expansion of A z) Number of multiplications 1 2 7 28 Number of additions I 2 7 28 (ii) Previous calculations for obtaining the denominator of 04*0 Q 40 C, 4 4 9

CO.

CC I 8 Y.i and Y. 1-1 (1 X.i X.

2. ji i=l Number of reciprocals Number of multiplications Number of additions (iii) Calculations for obtaining a Number of n-ultipl ications Nuzmber of addi.-,s (iv) Calculations for ob"taining J Number of reciprocals Number of mu ltipl Ications Number of add~tions calculations for oc-taining Y Number of divisior 1 x 8 =8 (7 6) x 8 =104 7 x 8 =56 s mod. Z 1 2 7 =28 1 2 7 =28 1 X8 8 7 x 8 =56 7 x 8 56 1 x8 When these calculations need each one step, the 408 in total.

in the circuit shown in Fig. 6t the roots are calculated by: 8 number of steps is of expression (9) n-l Y i F nij j~ i ri (X 1

X)

j=0 k~i (11) JbA -LOLdL lVII UlrI i IIi"- Sy): Syndrome HRF/0369y -16where ACoefficient of Zi of f I (z x~ Hk n13 k=1 kLil Q.;Any integer more than or equal to 0 which satisfies d n 1 That is Co say, in order to implement erasure correction, i =n are substituted into the expression (11) as follows: n-1 n-i Yn= Z AniS. 17 (xk x n) ,BIy this calculation, Yn is obtained and Y nX' is added to each n nn s~ -yndrome S as follows: S -Y n where 9 0 to n-2 Since the data at the location X nare correct, the syndrome includ es erasures. Therefore, by reducing n by 1 can be obtained: j=0 k= By this calculation, Yn is obtained and Y X is added to n-l n-l n1-1 each syndrome S as fo2llows: S 4e- S Y X) Id n-l n-l where 0 to n-3 By repeating the above, the last remaining erasure Y Ican be obtained as Y 1=S8 17 As explained above, an erasure correction can be implemented.

In this case, the actual number of operation steps is counted in the same way as in the conventional method, provided that d 9 and n 8.

Expansion of A nj Number of multiplications 1 2 6 21 Number of additions 1 2 6 21 (ii) Previous calculations for obtaining the denominator of n-l Yn I n (X k

X

n where it is sufficient to k=l obtain only II3 to II8, since II2 X+ Y2 n331* Number of multiplications 1 2 6 213 Number of additions 1 2 6 =21 (iii) Calculations for obtaining the numerator of Y n Number of multiplications 7 6 1 28 Number of additions 7 6 1 28 (iv) Calculations for obtaining Yn since Y 1

S

Number of divisions 7 S, S, Yn X Number of multiplications 6 5 1 21 Number of additions 7 6 1 28 The number of the above calculations steps is 202 in total.

Therefore, in the case of expression it is possible to reduce the number of calculation steps to 50% of the conventional case in the expression Further, in the case where the above mentioned correction code is a product code, provided that 30 symbols are arranged in -18 the vertical direction, 128 symbols are arranged in the lateral direction, the C 1 code is formed to the vertical direction, and the C 2 code is formed to the lateral direction, the erasure corresponds to the location of the C 1 pointers, and the location Xk (k=l to n) is the same in all the C 2 code series. This means n-1 that it is possible to previously calculate A j and -I (xk X n k=1 in expression (11) without calculating these terms every the C 2 decoding. That is to say, in this example, the above calculation is implemented only once while the C 2 decoding is performed times.

Therefore, in the number of the above calculation steps, since the number of the calculations of and (ii) is only once every 30 times of C 2 decoding, provided that the number of steps of and (ii) is 90/30 3, the total number of steps is 115.

compared with that in the conventional method, where the number of steps in and (ii) is 224/3 74.7 and the total number of steps is 191.5, it is possible to reduce the number of steps by about Accordingly, the method as above described has advantages such that it is possible to markedly reduce the number of calculation steps, processing time, hardware load for processing and so on as compared with the conventional method.

Additionaly, although the above calculations are performed by employing the operation logic 37, in the case where, for example, Sy S, X Yi is obtained, a concept as shown in Fig. 7 is adopted, In Fig. 7, the reference numerals 38, 39,

L

19 denote registers, the reference numeral 41 denotes an adder, the reference numeral 42 denotes a multiplier, the reference numeral 43 denotes a selector, which are all built in the operation logic 37. In this circuit,

S

O is set to the register 38, Yi is set to the register is set to the register 40, respectively through the data bus 28 from the syndrome register 29 and the working RAM 36 and so on. S O Yi is outputted from the adder 41 to the data bus 28.

(21 The content of the multiplier 42, X. Y. is set (feedbacked) to the register 39 through the selector 43, and is set to the register 38 from the data bus 28. Therefore, S 1

X

i

Y

is outputted from the adder 41 to the data bus 28.

2 Farther, the content of the multiplier 42, X 2 Yi is feedbacked to the register 39 through the selector 43, and S2 is 2 set to the register 38 from the data bus 28, Therefore, S 2 Xi Y is outputted from the adder 41 to the data bus 28.

By repeating the above steps, S X, Y S X 4 Yi are ootained sequentially, and supplied to the syndrome register 29 through the data bus 28 so as to rewrite each value.

The calculation are implemented as described above.

In the above explanation, although all of X to X are assumed as erasures, in the case where X to Xn 1 are erasures and

X

n is an error, it is possible to correct the symbols. In this case, the number of unknown quantity are of Y to Y and X n X can be obtained by using the above Annj as follows: J. n n-l E ~Annj S j4+1 X j= (121 n n-1 Annj Sj+e j=0 Therefore, the unknown quantity are Y1 to Yn, and thereafter, these unknown quantity can be obtained in the same way as in the erasure correction.

For instance, in the case where d 9 (6 erasures 1 error) in product code, 11 Check locations of the erasures X X 2

X

Obtain and store A ,j here 21 symbols in total of A221 X1 331 -221 2' 332 '221 X2' 771 1.."77:6 n-1 Obtain and store 5 symbol: In total of T1 (Xk )n k =1 (n 2 to 6).

Tne above processings are made once for each 30 times, [41 Calculate syndromes S0 to 7' Obtain x 7 by an expression as follows: 6

S

77j +1 X 0 77 i \77j Sj [16) Obtain Y7 by the following expression and feedback the syndrome

Y

7 X 21 n-1 Y7 (j A77j Sj) l k

X

7 j=0 Thereafter, Y 6 to Y1 S are sequentially obtained.

Although a case where expression is used is shown in this example, the operation is the same if 1 0.

As described above, it is possible to implement the correction of errors including erasures and one error. In this case, the number of calculation steps can be reduced as in the erasure correction described above.

The proof of the above expressions (11) and (12) will be described hereinafter; (Lemma) If n A 1 (z k=l k i AA= U the following expression is cleary obtained: n-i (Theorem 11 The n-order linear simultaneous equatlons: n k=1 0 to n-l Y1 is unknown quantity) has the roots ast 22 n-i j=0 n it ni S) ra Axk x kki (Proof) Right side n-l2 n

(AY

J:~O

xk jYk) n n1 (Xk x i k=1 k~i n riI (X k X i k=1 k~i =k AZI ,j Xkj k=1 j=0 n Y. x +X k~ k k~ jq ki n Iin ni S k, 72 (X (X k kQi (Crola) 1)i dal y usauii n k iy kn-i 11I it rwooadX i natt

/AN

23 n-l 2 1 ~nnj sj+ .+l x j=0o n n-i P6Annj S j+ j=0 (Proof) From Corollary 1, Y x I- xk xn) Right side nl Left side Yn Xn Fl (X 1 X n k=l Therefore, it is understood from Theorem 1 that errors can be corrected in the erasure correction by use of any of SI to Sn S2 S I -n to Sd 2 ao'n- the SU,$ "c!Of Sn I' That is, n continluous syndromes aoc- rir-az V frr n iSUres correction, the remaining syndtoi;, 0 usailerr Lrcsung o that n d-1.

Further, to obtain frn th t- 1;urn 2 totc n 1 syndromes of Sl to Sn'+1 are nces'sary, so thlat n K d<2- n this case, the number of era'ures is n-1 d- 3. Thu ema inirn syndromes, can be used for checking an in the above cas, in the conventional method, the pointecr areais are equired for the tta. numbr of aata (a 1 corrsponding to t:h error correction code, According to the present invention, however it is panible to reduce the number of pointers to (n 2 2ni) and furthor to reduce the capacity of the1: memory required in decoding Further, according to the present invtiion, it in po sible to toduce the nuber of s;teps for writinj or reading the 0ietu r 1 -24 Further, ac ,.rdinq to the pro rent invention, in thecase where the erasure correction in the decoding is implemented by the use of pointers formedI by the C 1 decoding, since the pattcorn of the pointers with respect to each series of C 2 code is common and a part of the operat-ons to obtair; error value become common, it is possit-,le to implem,-ep.: the operation only once. Therefore it is pos-sible to ma0'ked~v reduce the number of processing steps in diecodinc- ands to realize a high-speed in decoding operation.

Furthermore, according to the present invention, without necessity to obta.,r the whole error values in accordance with compl.iCated error evaluation poiynomiail in obtaining a plurality of error values, it IS possible to obtained one of the error values by simmple construction and to reduce the nuier of the processing steps.

Moreovert ac-cordinq to the present invention, it is possib..e to mar~ealy reauce t~rie numnber of oal~u 'aton steps in evasu'e correction,

Claims (2)

1. A method for decoding and correcting erasure in Reed=Solomon code in accordance with the roots of: solving the expression S n X I SXk k k=1 where, 0 to d 2 n Number of erasure Xk Location of kth element Sy Syndrome Yk Magnitude of error in the erasure d Minimum distance of code characterized in that the roots are obtained of kth element by solving the following equation n-1 P n Yi .nij s Xi 1 ^k i k i whereA nij Coefficient of Z j of r (z Xk)] k=l Any integer more than or equal satisfies t d n 1. An apparatus for decoding and correcting in accordance with the roots of to 0 which erasure in Reed-Solomon 2, code Sy= Z Xk k k l where, Y= 0 to d 2 n Number of erasure X k Location of kth element Sy- Syndrome URF/0369y 4 4, I, 44 f 26 Yk Magnitude of error in the erasure of kth element d Minimum distance of the code characterized by syndrome register means for storing syndrome S and operating logic means for obtaining the roots Yi of the above equation by solving the following equation: n-l i (I-7 nij Xi k i (X k X) j=o- k=1 k-i where nij Coefficient of Z 3 of n (Z Xk)] k 1 SAny integer more than or equal to 0 which satisfies d-n 1 characterized in that said operating logic means includes register means for storing syndrome register means for storing X Y register means for storing Xi; adder means for adding Sy and i Y and for supplying said register means and syndrome register means with S X Yi; multiplyer means for multiplying X i and X i Yi and for supplying said register means with Xi Y' 3, A method as claimed in claim 1 and as hereinbefore particularly described with reference to what is shown in the accompanying drawings.

4. An apparatus as claimed in claim 2 and as hereinbefore particularly described with reference to what is shown in the accompanying drawings. DATED this TWENTY FIRST day of AUGUST 1990 Sony Corporation Patent Attorneys for the Applicant SPRUSON FERGUSON URF/0369y c