AU610987B2 - Method and apparatus for decoding error correction code - Google Patents

Description

S l 068L99VEZg 1111'ZA-- zXMAnsjbdouWa|!, L,6jpqo I2 I.4 A i A ZAXMAnisNodONWWrIHO90aDOv "d0

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125 1-4 S F Ref: 85500 FORM COMMONWEALTH OF AUSTRALIA PATENTS ACT 1952 1 0 9 8 7 COMPLETE SPECIFICATIO

(ORIGINAL)

FOR OFFICE USE: Class Int Class Complete Specification Lodged: Accepted: Published: o° Priority: S Related Art: o I' (C 0 o Name and Address of Applicant: Address for Service: Sony Corporation 7-35, Kitashinagawa 6-Chome Shinagawa-Ku Tokyo

JAPAN

Spruson Ferguson, Patent Attorneys Level 33 St Martins Tower, 31 Market Street Sydney, New South Wales, 2000, Australia Complete Specification for the invention entitled: Method and Apparatus for Decoding Error Correction Code The following statement Is a full description of this Invention. including the best method of performing it known to me/us 5845/4 5845/3

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SPECIFICATION

TITLE OF THE INVENTION METHOD AND APPARATUS FOR DECODING ERROR CORRECTION CODE TECHNICAL FIELD This invention relates to a method and an apparatus for decoding error correction code.

This application is a further application 1 ,!oceeding under Section 51 of the Australian Patents Act and based on parent Australian patent application no.37812/85 to the same 00 applicant.

00,000 BACKGROUND ART 0 000 Product code are well known such that information 0 symbols are arranged in two-dimensional form, error correct- 00 0 0 Q ion code are encoded for each row and column on the twodimensional arrangement so that each information symbol is 0 included in two error correction code series. In decoding 0 the product code, error correction code is decoded for each 00 0 0o 00~ row by employing of the decode information. The decode information is called a pointer.

00 00 In the conventional method, Aince each information 0 0 0 symbol is associated with a pointer,. it is required that the total number of pointers is at least equal to the number of the information symbols.

Further, in the case where erasure correction is made by employing the pointers, since the pointer are read out from a pointer memory and the error values is calculated every row, there exists a problem in that the number of processing steps such as memory acoesses# calculations and -1I- JTA:73N Ii -i--II-n

I-I

0 so on inevitably increases.

On the other hand, in the case where complicated codes such as BCH codes are employed as error correction codes, since the operations for obtaining error values become inevitably complicated, there exists a problem in that a great number of program steps are required in the case where the calculation are implemented by hardware.

DISCLOSURE OF THE INVENTION An object of this invention is to provide a method 0o°° and an apparatus for decoding error correction code which 0 o enable to reduce the number of pointer required in decoding 0 as well as the memory regions for pointers and the number o o S of times of reading and writing the pointers.

00 0 o o 0 Another object of this invention is to provide a method and an apparatus for decoding error correction code 00o0 0 9 0 00 0 which enable to markedly reduce the number of processing oa 00 steps in dependence upon the fact that the pointers with 0°o o respect to each row are the same.

Still another object of this invention is to provide an apparatus for decoding error correction code which 0 00 enable to reduce the number of calculating steps in an erasure correction.

Still further object of this invention is to provide a method for decoding error correction code which can obtain error values in decoding in dependence upon a simple construction and a small number of pocessing steps.

r~i:LV' S -3- According to one aspect of the present invention there is disclosed an apparatus for decoding a non-dualistic error correction code by which errors of a plurality of symbols in the series of received symbols can be corrected, the apparatus comprising: syndrome generating means for obtaining a plurality of syndromes from the error correction code; one of the plurality of syndromes is a result of an addition of a series of received symbols in (mod 2) and; syndrome register means for storing the plurality of syndromes from said syndrome generating means; wherein an error value with respect to a symbol is formed by subtracting another error value from a value stored in said syndrome register in correcting plurality of erroneous symbols.

0oo oo 0 00 0 o o 0 0 0 0 o o o 315 o o 0 amg/0367y ,i -4- BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic block diagram showing an encoder according to an embodiment of the present invention.

Fig. 2 is a schematic diagram for r&ssistance in explaining the operation of an embodiment of the present invention.

Fig. 3 is a schematic block diagram showing a decoder according to one embodiment of this invention.

Fig. 4 is a block diagram showing an embodiment of this invent ion.

0 Fig. 5 is a block diagram showing an essential portion of an embodiment of this invention.

000 Fig. 6 is a block diagram showing an construction of an 0 6 0 embodiment for use with this invention.

Fig, 7 is a block diagram fo-r assistance in explaining a .000. processing circuit of Fig. 6.

oo BEST MODE FOR CARRYING3 OUT THE INVENTION oo 0An embhodiment of the present invention will, be described, referring to the drawings. Fig. 1 shows a structure of an encoder for product code. The reference numL-ral 1 denotes an input 0 0 q terminalf the reference numeral 2 denotes a C 2 (the second error correction code) parity generator. The input data from the input terminal 1 are supplied to the C 2 parity generator 2 and one input terminal of a selector 3, and the C 2 parity data formed by the C 2 parity generator 2 are supplied to the other input terminal of the selector 3. The selector 3 repeats k 1times t~ie operations for selecting (n 2 k 2 parity data after k 2 information symbols are 5 selected. During this operation, the information symbols and the parity data are stored in a RAM (Random Access Memory) 4 in sequence under control of an address controller The data read out from the RAM 4 are supplied to a C 1 (the first error correction code) parity generator 6 and one input terminal of a selector 7 and the C 1 parity data formed by the C 1 parity generator 6 are supplied to the other input terminal of the selector 7. The selector 7 selects kl) x k 2

C

1 parity data of after having selected (k 1 x n 2 symbols including the C 2 parity data. The digital data derived from an outoput terminal 8 of the 0 selector 7 are transmitted or recorded on a magnetic tape (not o o o°0 shown) with a magnetic head, for instance. In this case, it is o a 0°0 possible to write again the encoded output once into the RAM 4 and to read out it in different sequence for recording.

o0 0 Fig. 2 shows an configuration of code formed by the encoder oo00o as described above. The information symbols are arranged in two o0o 0 dimension of (k I x k 2 The ki information symbols in every o oo lateral direction, that is, in every row of the two-dimensonal 0rrangement are subjected to encoding process for the C 2 code. The k I information symbols in every vertical direction, that is, in ivery column are subjected to encoding process for the C 1 code. The

C

2 parity data are also encoded into the C 1 code. The C 1 code is, for instance, (nl, Reed-Solomon code, by which it is possible to correct errors of up to (n kl)/2 symbols.

The general method of decoding the Reed-Solomon code will be described, -6- The hamming distance of the k) Reed-Solomon code (n denotes the code length and k denotes the number of information symbols) on a Galois Field GF(2 m can be expressed as (d n k 1) and the generator polynomial can be expressed as d-2 II (x L i) If the received words are (r 0 rl, r 2 rn-l), i=0 the syndrome can be obtained by operating the following expression: n-1 r r i (i j (j 1, d-2) Cl) i=0 00 00 0 0 An error location polynomial 6z) and an error evaluation 0 0 0 0 0 0000o polynomial O(z) are obtained by employing the syndrome Si. As to this method, Euclid's mutual division method, Varlay-Camp's method, oo Peterson's method and so on have been proposed.

By solving Cz) 0, the error location X. can be obtained.

For this purpose, Chien search is- employed.

00 Then, the error value Yi can be obtained on the basis of 00 0 the error location X i and the error evaluation polynomial The above calculations in the decoding steps are explained with the error location as X Ci 2, e e denotes the 0 o 00 number of errors), and the error value as Yi. Since the Reed-Solomon code is a liniear code, the syndrome can be expressed as: e Si j Yj xiJ j 1, 2, d-2) 2 (2) jul if the syndrome is expressed by a polynomial as: 7 d-2 S(z) Sj (3) j=0 a following expression is obtained: e d-2 S(z) Yi (Xi z)3 i=l j=0 1 X (mod. d (4) n o0 o oo0 0 0 0 00 If the error location polynomial and the error evaluation o0o 0 000 .o.0 polynomial are defined as 0 o 0 0 e o dZ) I (1 X. z) j=1 0oo0o W d(z) s(z) (6) 00 0 0: 0 then WJ(z) can be expressed as oo e Y e W(zo =L Y e i=1 1 j=1 The errr alue can be obtained by subs itutX gz X into z and Y I (1 X z) (mod. z d (7) The error value Y can be obtained by substituting X into z and by transforming the expression as follows: Yi (1 X X (8) 7ii -8- As an exsample, (32, 24) Reed-solomon code having roots of 6 0 to 0 7 will be explained. Since this code is it is possible to correct errors of up to 4 symbols. If the error locations of the 4 symbols are X 1 to X 4 and the error values are Y1 to Y4' the syndrome is obtained from following expression.

4 Jy L) (j 0 to 3) i=l Namely, S 0 is as follows among 4 syndromes: 4 too# 0 0 00 0 4i 4 L Y 00 Once the error values Y 1

Y

2

Y

3 can be obtained, the remaining error value Y is obtained as follows without implementing 0 o complicated calculations:

Y

4

S

0

Y

1 -Y2 Y3 In codes on GF(2m), a subtraction is equivalent to an addition of (mod. 2).

oo0:. Fig. 3 shows a configuration' of the encoder of this embodiment. in Fig. 3, the reproduced data are supplied from an input terminal designated by the reference numeral 11 and to a C 1 decoder 12. In the C 1 decoder 12, the decoding of the C 1 code is performed. All errors of up to (n 1 kl)/2 symbols are corrected in the C 1 decoding. In the case, however, where the number of errors in a single series of C 1 code is more than or equal to a n. (n

I

the C 1 pointers of this series is set to the -9other pointers are set to 1O0. In Figs. 2 and 3, the reference numeral 13 denotes a pointer memory for storing the pointers of the C 1 code, which has n 2 bits. The output of the C 1 decoder 12 is stored temporarily in a RAM 14 in sequence under the control of an address controller Th(,i output read out from the RAM 14 are supplied to a C 2 decoder 16 to be subjected to the decoding of the C 2 code. The C 2 decoder 16 is supplied with the C 1 pointer from the pointer memory 13. Since the C 1 pointer is common to the all of K 1 series of C 2 *04 code, it is possible to decode the C 2 code in accordance with the, o00 same procedure in each series. The C 2 decoder 16 corrects errors o of up to (n 2 k symbols and generate three kinds of pointers Sin the C 2 code which is stored in a pointer memory 17.

When error correction is perfomed by the C 2 decoder 16, the 0 0 00 000 2 pointers with respect to the series is set to When error do correction can not be performed by the C 2 decoder 16 and the C 1 S:pointers are copied because of its high reliability, the C 2 poin'ters is set to I'l. When errc ,r correction can not be performed by the C 2 decoder 16 and all! Cymb'.ils are determined to be erroneous symbols because of low reliability of the C 1 pointer, the C 2 pointers are set to 112". Therefore, the C 2 pointers have 2 bits and the pointer memory 17 has 2K, bits.

These pointer memories 13 and 17 are disposed separately from the RAM 14 for storing information symbols and parity data in~ decoding or disposed in common with the RAM 14 by using a part of memory regions of the $RAM 14. 1 Without being limited to 1 bit, the C, pointer may have 2 bits or more. Further, it is possible to implement the error correction code processing of C2code for the C 1 I parity, while providing a C 2 pointer memory of (2n) bits.

The output data of the C 2decoder 16 are supplied to an interpolation circuit 18 to conceal error in the symbols which mean value interpolation, for instance. The interpolation circuit 18 is controlled by a control circuit 19 which is supplied with the C 1 pointera and the C 2 pointers from the pointer memories 13 and 17. The output data of the interpolation circuit 18 are 0 derived at an output terminal 20. The control circuit 19 o determines by every information symbol whether interpolation is necessary on the basis of the c, pointer and c2 pointer. In 00 Fig. 2, There exist all the combinations of C 1 pointers designated 0 0 .00 as 13' and C 2 pointers designated as 17!.

000 0When the C 2 pointer is 11011 irrespective of the fact that the

C

1 pointer is 110" or "1"1f the interpolation circuit 18 does not 0 work. when the C 2 pointer is "111 and the C 1 pointer is 110"t since it is determined that the information symbol has no error? no interpolation is done. When the C 2 pointer is "1"1 and the C 1 pointer is since it is determined that it is erroneous symbol, the interpolation operation is performed. Further when the. C 2 pointer is "2"1 irrespective of the fact that the C 1 pointer is or since it is cdeterminee.' that it is erroneous symbolf the interpolation operation is performed.

11 The reliability of the C 1 pointers is evaluated by the C 2 decoder. For instance, provided that up to 2 syliibol errors can be corrected by the C 2 code, if correction by the C 2 vode can not be performed in spite of the fact that only one C 1 pointer is 1 it is determined that the reliability of the C 1 pointer is low because the above is abnormal. Even if errors are not corrected by the C 2 code, it is possible to eliminate the necessity of interpolation by providing three kinds 0, 1, 2 of the C 2 pointero and by discriminating the copies of C 1 pointers from all errors.

In the above mentioned C 2 decoder 16, when the C 1 pointers are copied, the erasure correction is made where the number of the C 1 pointers is less than or equal to (n 2 k 2 and when the erasure correction is made, the C 2 pointer is set to As described above, the decoding of the Reed-Solomon code is performed by calculation of the error location polynomial 6(z) and the error evaluation polynomial W(z) every row and by employing o 1 syndrome obtained by n 2 symbols in each row. In the case of erasure correction, since the locations where the C 1 pointers are are detrmined as the error locations, it is possiblp to obtain the error value Y from the error location x and the er evaluation polynomial That is to say, by substituting X i in place of z, Yi can be obtained as follows as in expression (8)

(X-

I

Yi I-I (Q -l iX J~i ji) (where i I, 2, 3, s s denotes the number of symbols) 12 In the above expression, the term of denominator can be determined by only the error locations. For instance, provided that the error locations shown by the C 1 pointer are XI, X 2

X

3 the terms of denomiatfor of the expressions for obtaining the error values Y

Y

2 f Y 3 are Denominator of Y1 X 2 X X 3 X Denominator of Y2 X 1 X3 (1 -X 2 X3-') Denominator of Y 3 (1 X 1) (l X 3 X2- 1 Here, the pointers stored in the pointer memory 13 are the same in the all of K. series of the C 2 code. Therfore, it is sufficient to implement the calculation of term of denominator in the above expression to obtain error value only once with respect to the k 1 series.

Fig. 4 shows the configuration of an error correcting decoder for use with the above mentioned C 1 decoder and C 2 decoder.

The received data are supplied to an input terminal designated by the reference numeral 21 and supplied to a delay circuit 22 and a syndromo gene-ating circuit 23. The syndromes formed by the syrdrome g5nerating circuit 23 are supplied to an error location and error value calculating circuit 24. The error data from the error location and error value calculating circuit 24 are supplied to an exclusive OR gate 25 and added to the received data from the delay circuit 22 in (mod. The received data from the delay circuit 22 and the error corrected data from the exclusive OR gqan'e are supplied to a selector 26. The selector 26 is controlled by the error location data. At the error locations, the output of the iL C 0 19 5845/4 13lusive OR gate 25 is selected by the seictor 26 to be derived at an output terminal 27 in place of the received data.

in the case of an audio PCM signal recording and reproducing apparatus, the reproduced data are once written in a RAM. By use of the data read out from the RAM, the syndrome is generated and on the basis of which the error locations and the error values are calculated. Fig. 5 shows a part of the error location and error value calculating circuit 24. In Fig. 5, the reference numeral 28 denotes a data bus through which data and syndrome and so on are transfered.

In Fig. 5, the reference numeral 29 denotes a syndrome register in which the syndrome S 0 is stored through the data bus 28, a bus buffer 30 and an exclusive OR gate 31. the syndrome S 0 has -m bits in the case of Reed-Solomon code on GF(2m) The syndrome s 0 from the syndrome register 29 is supplied to the exclusive OR gate 31 and the bus buffer 32.

When the syndrome S 0 is stored in the syndrome register 29, the obtained error values Y l, Y 2

Y

3 are supplied to the exclusive OR gate 31 in sequence from the data bus 28 through the bps buffer Therefore, the output of the exclusive OR gate 31. is (So 0 5Y 1 (SO Yl( Y 2 and (SO C+ Y1 (D Y 2 S Y 3

:!Y

4 The error value Y4is left in the syndrome register 29. The error value Y4is outputted to the data bus 28 through the bus buffer 32 to be employed for error~ correction, Fig. 6 shows another example of hardware for decoding in an erasure cor-rction, A main PAM4 35 is connected to the data bus 28 every row, tnere exists a proo-em nL11 Vi-a Liti- LiLuiLuJe- LLL processing steps such as memory accesses, calculations and 1 14 through a writing register 33 and a reading register 34. The syndrome register 29, a working RAM 36 and an operation logic circuit 37 are provided to the data bus 28.

The erasure correction by Reed-Solomon code can be concluded by solving the following n-order liniear simultaneous equations in the same way as in expression n Sv l k=l Xk Yk (9) op oo 0 0 0 0 0 0 4 OqOl 4 0 qoo

I

00 0 a l 04 0 0 0 0 o oo «Qo a 0 00 0000 a o o 44 0 0 40i 0 0 0 0 0 0 04> where, 0 to d 2 n Number of erasure Xk Location of kth Sp Syndrome Yk Magnitude of error in the erasure of kth d Minimum distance of code Here, n, Xk, are known, Yk is unknown.

To solve the above equation, the following method has *been conventionally adopted: if n A(z) ri (1 x i

Z)

1=1 S(z) A(z) mod. Z d l Yi can be obtained as in expression as follows: Sn Y i (X II (1 X X- 1 i i In this method, however, if the number of actual calculation steps is counted when d 9 and n 8, for instance.

f~rm Shnrn Ic p-ro-vidcd-an- *-atf~-p-aEu.- 'I A 0 A C ~J0 4.

g 15 Expansion of A(z) Number of multiplications 1 2 7 28 Number of additions 1 2 7 28 (ii) Previous calculations for obtaining the denominator of Yi and Yi I (1 X. X j=i i=1 Number of reciprocals 1 Number of multiplications (7 6 Number of additions 7 00'° (iii) Calculations for obtaining 0 Number of multiplications 1 2 o Number of additicns 1 2 (iv) Calculations for obtaining 6)(X i o a SNumber of reciprc:als 1 x 8 Number of multiplications 7 x 8 Number of additic-.s 7 x 8 a 0 00000 o. Calcul tions for c-:taining Y Number of divisio.- 1 x 8 00 00 0 0 I 0 t When these calculations need each one step, the 408 in total.

00 In the circuit shown in Fig. 6, the roots are calculated by: x 8 8 x 8 104 x 8 56 S(z) mod. Z 8 7 28 7 28 8 56 56 8 number of steps is of expression (9) n-1 i Anij x (Xk X amg/0367y IJII I I: 16 n where A Coefficient of Z of II (z Xk)) nk= k k41 ki Any integer more than or equal to 0 which satisfies d n 1 That is to say, in order to implement erasure correction, 1 0, i n are substituted into the expression (11) as follows: n-1 n-1 Yn (E A.nnj S) I (Xk Xn) j=0 3k=1 j 0 a0y this calculation, Y is obtained and Y X is added to each n n n o0,g qo:'sndrome S as follows: 0' CSA- S Y X :n n 0 .where y? 0 to n-2 Since the data at the location X are correct, the syndrome includes (n-l erasures. Therefore, by reducing n by 1, Y n-1 can be obtained; 00 n-2 n-2 00 'Yn- k n-1 0 k =1 j 0O By this calculation, Y is obtained and Y X is addqd to n-l n-i n-I 'each syndrome S as follows: S S Y X y n-i n-1 where 0 to n-3 By repeating the above, the last remaining erasure Y1 can be obtained as Yl SO0 Y1= 1 0 4 4 C. C* C C

C

CC

C p

AC.,

AC

C a A CCC o A A AC o OP A A A 0 o *e

AAOA

P A p PA P A CA A p A A AA CA A A A 0 o CO A AC OP C C CC 17 As explained above, an erasure correction can be implemented.

in this case, the actual number of operation steps is counted in the same way as in the conventional method, provided that d 9 and n =8.

Expansion of A nnj Number of multiplications 1 2 Z 21 Number of additions 1 2 6 21 (ii) Previous calculations for obt:aining the denominator of n-1 Y n' I -n r (X k X n) where it is suf ficient to obtain only 11 3 to 1181 since 11 2 X 1 Y2= A331* Number of multiplications :1 2 6 =21 Number of additions :1 2 6 21 (iii) Calculations for obtaining the numerator of Yn Numbr o muliplcatons 7 6 1= n Number of mulitipliaton 7 6 1 =28 (iv) Calculations for obtaining Y n, since Y Number of divisions :7 S

X

nn Number of multiplications 6 5 1 21 Number of additions 7 6 1 28 The number of the above calculations steps is 202 in total.

Therefore, in the case of expression (11) it is possible to reduce the number of calculation steps to 50% of the conventional case in the expression (10) Further, in the i,,ase where thi above mentioned correction code is a product code, provided that 30 symbols are arranged in described, l -18 the vertical direction, 128 symbols are arranged in the lateral direction, the C 1 code is formed to the vertical direction, and the C 2 code is formed to the lateral.direction, the erasure corresponds to the location of the C 1 pointers, and the location Xk (k=l to n) is the same in all the C 2 code series. This means n-i that it is possible to previously calculate Annj and II (xk X) nnj k k n k=l in expression without calculating these terms every the C 2 decoding. That is to say, in this example, the above calculation is implemented only once while the C 2 decoding is performed times. *q s.

I

Therefore, in the number of the above calculation steps, since the number of the calculations of and (ii) is only once 0 every 30 times of C 2 decoding, provided that the number of steps 0o o 0° °o of and (ii) is 90/30 3, the total number of steps is 115.

compared with that in the conventional method, where the number of o" steps in and (ii) is 224/3 74.7 and the total number of 0 0 0 0 0 steps is 191.5, it is possible to reduce the number of steps by o about Accordingly, the method as above described has advantages ooO such that it is possible to markedly reduce the number of 0o 0 calculation steps, processing time, hardware load for processing and so on as compared with the conventional method.

Additionaly, although the above calculations are performed by employing the operation logic 37,. in the case where, for example, S So Xi, Yi is obtained, a concept as shown in Fig. 7 is adopted. In Fig. 7, the reference numerals 38, 39, described.

19 denote registers, the reference numeral 41 denotes an adder, the reference numeral 42 denotes a multiplier, the reference numeral 43 denotes a selector, which are all built in the operation logic 37. In this circuit, [11 S O is set to the register 38, Yi is set to the register is set to the register 40, respectively through the data bus 28 from the syndrome register 29 and the working RAM 36 and so on. S 0 Y. is outputted from the adder 41 to the data bus 28.

[21 The content of the multiplier 42, X i Yi is set (feedbacked) to the register 39 through the selector 43, and S is S set to the register 38 from the data bus 28. Therefore, S 1 X. Yi Sis outputted from the adder 41 to the data bus 28.

[31 Further, the content of the multiplier 42, X2 Y is feedbacked to the register 39 through the selector 43, and S 2 is 2 set to the register 38 from the data bus 28. Therefore, S 2 X2 Y yi is outputted from the adder 41 to the data bus 28.

3 4 By repeating the above steps, S 3 X Y S X Yi are obtained sequentially, and supplied to the syndrome register 29 through the data bus 28 so as to rewrite each value.

The calculation are implemented as described above.

In the above explanation, although all of X 1 to Xn are assumed as erasures, in the case where X 1 to Xn, are erasures and X n is an error, it is possible to correct the symbols. In this case, the number of unknown quantity are of Y1 to Yn and X n Xn can be obtained by using the above Ann j as follows: n nj 1 1 j r--j .Cii~ n-l A .s nj n] 4+1 x (12) n j nj A S j=0 Therefore, the unknown quantity are Y1 to n, and thereafter, these unknown quantity can be obtained in the same way as in the erasure correction.

For instance, in the case where d 9 (6 erasures 1 error) in product code, 11 Check locations of the erasures X 1

X

2 12) Obtain and store A nj here 21 symbols in total of 221 11 21 2 33? -22a 2' 771 'A776' :7n-1 13) Obtain and store 5 sym'sbol. in total of :i (X IX (n 2 to 6), The above processings ate mradc once for each 30 tirmes.

141 Calculate syndromes SO to S 7 Obtain X 7 by an expression as follows: 6 77j j+1 j=0 76 77j i j=0 Obtain Y7 by the following expression and feedback the syndromrne Y.7 X.

i* I I I r 1 21- 6 n-1 Y7 A 7 7 j S) (Xk X 7 j=0 Thereafter, Y 6 to Y1 S 0 are sequentially obtained.

Although a case where expression is used is shown in this example, the operation is the same if As described above, it is possible to implement the correction of errors including erasures and one error. In this case, the number of calculation steps can be reduced as in the erasure correction described above.

The proof of the above expressions (11) and (12) will be Sdescribed hereinafter: [Lemmal If n Ai n (z X k=l kWi Anij Ani(Z)] the following expression is cleary obtained: n-i nij II (z X k j=0 k=l [Theorem 1] The n-order linear simultaneous equations: n S Yk k=l 0 to n-i Yi is unknown quantity) has the roots as: c (nl k 1 the C, pointers of this series is set to the i 22 n-1 A nij sj) r (xk x k'i (Proof) Right side -i n j=0 k=1 n Xk k) rtI Xi) k =1 ki n n-1 F I) (Xi x) kn n i k=1 j=o k i n Y (rx? X) P( X.) k~l j+

Y.

(Corollary 1) n-1 Y

"F

j=0

I

An 0 j Xi 1 1 x k -i 0) (Proof) It is clearly by substitutin 0 sj++ S k1 (V~core 2 2 X tif X iBa:;UrC e nd X i: an L, 23 n-1 J/ A nnj Sj++1 n n-1 LE A nnj Sj j=0 (Proof) From Corollary 1, e+1 n-1 Y X T (Xk X n) Right side k-1 Left side Y I (x K X Yn Xn k n k=1 Therefore, it is understood from Theorem 1 that errors can be corrected in the erasure correction by use of any of S 1 to S S to Sn+l' d-l-n to Sd-2 among the seies of SO to S n-.

That is, n continuous syndromes are necessary for n erasures correction, the remaining syndcomes are usable for checking, so that n d-1.

Further, to obtain X from the theorem 2, total n+l syndromes of S 1 to S are necessary, so that n d-2. In this case, the number of erasures is n-i A d-3. The remaining syndromes can be used for checking as in the above case.

In the conventional method, the pointer areas are required for the total nm'ber of data (nl, n 2 corrsponding to the eL'ro correction code. According to the present invention, however it is possible to reduce the number of pointers to (n 2 2n) and further to reduce the capacity of the memory required in decoding Further, according to the present invention, it is possible to reduce the number of steps for writing or oeading the pointers, Y -I -24 Further, according to the present invention, in thecase where the erasure correction in the C 2 decoding is implemented by the use of pointers formed by the C 1 decoding, since the pattern of the pointers with respect to each series of C 2 code is common and a part of the operations to obtain error value become common, it is possible to implement the operation only once. Therefore it is possible to markedly reduce the number of processing steps in decoding and to realize a high-speed in decoding operation.

Furthermore, according to the present invention, without necessity to obtain the whole error values in accordance with complicated error evaluation polynomial in obtaining a plurality of error values, it is possible to obtained one of the error values by a simple construction and to reduce the number of the processing steps.

Moreover, according to the present invention, it is possible to markedly reduce the number of calculation steps in erasure correction.

Claims (3)

1. An apparatus for decoding a non-dualistic error correction code by which erro's of a plurality of symbols in the series of received symbols can be corrected, the apparatus comprising: syndrome generating means for obtaining a plurality of syndromes from the error correction code; one of the plurality of syndromes is a result of an addition of a series of received symbols in (mod 2) and; syndrome register means for storing the plurality of syndromes from said syndrome generating means; wherein an error value with respect to a symbol is formed by subtracting another error value from a value stored in said syndroma register in correcting plurality of erroneous symbols,

2. An apparatus according to claim 1, further comprising: input and output means; error location and error value calctlation means including said syndrome register means having input and output and for generating n (n is an integer) error locations and n error values according to the syndromes; and error correction means connected to said input and output means and error location and error value calculation means and for correcting an erroneous symbol by adding the error val ie and output means connected to said error correction means whereby said error location and error value calculation means includes adder means having one and another inputs and one output, the one input of said adder means being connected to the inpui and output of said syndrome register, the another output of said adder m6ans being supplied with n 1 error values in sequence and the output of said adder means beig connected to the input and output of said syndrome register, and whereby said adder means is supplied with the content of said syndrome register and the kth (k 1 to n 1) error values in sequence so aF to generate a s'tm of the kth error values and the content of said syndrome register so as to be stored in said syndrome registor instead of the p,,vious content in sequence, and the sum finally storci in said synduoime register is derived as the nth error value,

3. An apparatus according to claim 1, wherein said adder means is an exclusive-OR gate 'aving one and another inputs and one output, the one amg/0367y PUidJ 44 J~Nt1 JJ L .3 LUQ 111 UQL-a JU ll l 1" input of said exclusive-OR gate being connected to the output of said syndrome register, the another output of said exclusive-OR gate being supplied with n 1 error values in sequence and the output of said exclusive-OR gate being connected to the input of said syndrome register. DATED this SIXTH day of MARCH 1991 Sony Corporation Patent Attorneys for the Applicant SPRUSON FERGUSON amg/0367y