AU592011B2

AU592011B2 - Improvements relating to data transmission systems

Info

Publication number: AU592011B2
Application number: AU77543/87A
Authority: AU
Inventors: Anthony Peter Hulbert
Original assignee: Plessey Overseas Ltd
Current assignee: BAE Systems Defence Systems Ltd
Priority date: 1986-07-25
Filing date: 1987-07-27
Publication date: 1989-12-21
Anticipated expiration: 2007-07-27
Also published as: AU7754387A; EP0276272A1; WO1988001118A3; GB8618206D0; GB2193863A; GB2193863B; JPH01500950A; WO1988001118A2

Description

IMPROVEMENTS RELATING TO DATA TRANSMISSION SYSTEMS

This invention relates to data transmission systems and relates more especially to such systems in which short data packets (i.e. groups of data bits) are required to be transmitted and received. By way of example, in a so- called frequency hopping data transmission system in which the frequency of the transmitted data is changed to provide 100 hops/per second the data packets may comprise about 160 data bits. However, transmitted data packets may comprise as few as 16 data bits.

One of the difficulties experienced with the reception of short data packets in non-return to zero (NRZ) data modulation transmission systems resides in the acquisition and synchronisation of the usual synchronised clock by the averaging of data transition timing errors sufficiently rapidly to avoid the loss of incoming data bits.

In accordance with the present invention a receiver for a data transmission system in which data packets are transmitted, comprises a data synchronisation unit and a first-in first-out data store connected in parallel to receive incoming data signals, in which the data store delays the incoming data signals by a time period which corresponds to the time required for the synchronisation unit to achieve synchronisation of a clock with the incoming data signals and in which data gate or sampler means responsive to signals from the synchronisation unit indicating that clock synchronisation has been achieved enables data signals to be passed from the store to a data line.

By storing the incoming data signals in the data store clock synchronisation can be achieved without loss of incoming data bits.

The data store may be of analogue or digital form and may also provide for the reception of medium length data packets provided that the store delay, although shorter than the duration of the data packet, permits clock acquisition and synchronisation to be achieved.

By way of example the present invention will now be described with reference to the accompanying drawing which shows a block schematic diagram of a data transmission system receiver constructed in accordance with the present invention.

Referring to the drawing a receiver R for a data transmission system (e.g. frequency hopping or packet radio system) comprises a data input terminal DI for receiving incoming data packets from a remote transmitter (not shown) of the system.

The receiver R comprises an analogue store AS which may be of the so-called bucket-brigade type producing a high resolution delay for delaying the appearance at the output end of the store of the data bits of an incoming data packet received, or being received, into the store from the input data terminal DI, until a synchronised clock SC of a synchronisation unit SU has been acquired and synchronised with the incoming data signals.

For the purpose of controlling the clock SC to achieve synchronisation with the incoming data signals the unit comprises a pulse shaper PU and a pair of parallelled monostable devices MON1 and MON2 operable respectively to the leading and trailing edges of incoming data bits. An output from the parallelled monostable devices is gated to an early/late gating circuit EL together with the output from the clock SC. Early or late outputs from the gate EL are fed to another gate CB which is controlled by an up/down counter CO receiving an edge signal from the early/late gate EL. Control of the gate CB provides an output therefrom for advancing or retarding the clock SC to achieve synchronisation with the incoming data signals. The clock output is applied to a digital sampler DS which also receives the delayed data store output from the analogue store AS. The sampling rate of the sampler DS which is dependent upon the clock output should be higher than the nominal nyquist rate (i.e. one sample/bit) in order to ensure that the replica of the data input signal waveform can be reconstructed at the analogue data store output.

It may here be mentioned that when a short data packet is received at the receiver R the NRZ waveform will initially be imposed on a pedestal voltage of height proportional to the frequency difference between the receiver and transmitter. The pedestal voltage will decay with a time constant determined by the receiver high pass filtering. A short time constant is required to produce rapid elimination of the pedestal voltage but too short a time constant will result in distortion pf the data waveform (i.e. modulation droop) which could cause errors. To achieve the desired elimination of the pedestal voltage without the occurrence of errors, incoming data packets may be fed to an integrator IN having a time constant (T) equal to the duration of data packets. The start of a data packet which may be determined by carrier signal sense may be arranged to "clear" and release the integrator IN. At the end of the incoming data packet which is fed into the analogue store AS the clock will be correctly synchronised with the data timing and the integrator will be charged to the level of the pedestal voltage of the received data waveform. The integrator should therefore be switched to the 'hold' state 'T' seconds after its release. Thus the clock, in conjunction with the sampler SA, effectively samples the data from the analogue store AS which has an integral bit delay corresponding exactly to the number of bits in a dat packet whilst the integrator output can be used as the slicing threshold.

As will be apparent from the foregoing description of one embodiment of the present invention, the invention is eminently suitable for use in both frequency hopping and packet radio systems and enables all the data packets received at the receiver R to be fully recovered without loss of any data bits of the packet due to the delay of the synchronising clock in acquiring to the incoming data timing. Moreover, the use of an integrator as just above desribed permits threshold determination of the incoming data signal to be achieved.

PCT WORLD INTELLECTUAL PROPERTY ORGANIZATION International Bureau

INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT)

(51) International Patent Classification (11) International Publication Number: WO 88/ 01

A3 H04L 7/02,25/06 (43) International Publication Date: 11 February 1988 (11.0

(21) International Application Number: PCT/GB87/00531 (81) Designated States: AT (European patent), AU, BE ropean patent), CH (European patent), DE (E

(22) International Filing Date : 27 July 1987 (27.07.87) pean patent), FR (European patent), IT (Euro patent), JP, LU (European patent), NL (Europea tent), SE (European patent), US.

(31) Priority Application Number: 8618206

(32) Priority Date: 25 July 1986 (25.07.86) Published

With international search report.

(33) Priority Country: GB Before the expiration of the time limit for amendin claims and to be republished in the event of the recei amendments.

(71) Applicant (for all designated States except US): PLES-

SEY OVERSEAS LIMITED [GB/GB]; Vicarage (88) Date of publication of the international search report: Lane, Ilford, Essex IG1 4AQ (GB). 19 May 1988 (19.05.

(72) Inventor; and

(75) Inventor/ Applicant (for US only) : HULBERT, Anthony, Peter [GB/GB]; 6 Hanley Road, Shirley, Southampton (GB).

(74) Agent: SORENTI, Gino; The Plessey Company pic, Intellectual Property Department, Vicarage Lane, Ilford, Essex IG1 4AQ (GB).

(54) Title: IMPROVEMENTS RELATING TO DATA TRANSMISSION SYSTEMS

(57) Abstract

A data transmission system receiver comprising a data synchronisation unit and fϊrst-in first-out data store connected in parallel to receive incoming data signals, in which the data store delays the incoming data signals by a time period which corresponds to the time required for the synchronisation unit to achieve synchronisation of a clock with the incoming data signals and in which data gate or sampler means responsive to signals from the synchronisation unit indicating that synchronisation has been achieved enables data signals to be passed from the store to a data line.

FOR THE PURPOSES OFINFORMAHON ONLY

Codes used to identify States party to the PCT on the front pages of pamphlets publishing international applications under the PCT.

AT Austria FR France ML Mali

AU Australia GA Gabon MR Mauritania

•B Barbados GB United Kingdom MW Malawi-

BE Belgium HU Hungary NL Netherlands

BG Bulgaria IT Italy- NO Norway

BJ Benin JP Japan RO Romania

BR Brazil KP Democratic People's Republic SD Sudan

CF Central African Republic of Korea SE Sweden

CG Ccng^Λ KR Republic of Korea SN Senegal

CM Switzerland LI Liechtenstein SU Soviet Union

CM Cameroon LK Sri Lanka TD Chad

DE Germany, Federal Republic of LU Luxembourg TG Togo

DE Denmark MC Monaco US United States of America π Finland MG Madagascar

Claims

1. A data transmission system receiver comprising a data synchronisation unit and first-in first-out data store connected in parallel to receive incoming data signals, in which the data store delays the incoming data signals by a time period which corresponds to the time required for the synchronisation unit to acheive synchronisation of a clock with the incoming data signals and in which data gate or sampler means responsive to signals from the synchronisation unit indicating that clock synchronisation has been acheived enables data signals to be passed from the store to a data line.

2. A data transmission system receiver as claimed in claim 1, in which the data store is of analogue form.

3. A data transmission system receiver as claimed in claim 1 or claim 2, in which the synchronisation unit comprises a pulse shaper and a pair of monostable devices connected in parallel and responsive to the leading and trailing edges of incoming data bits, the output from the monostable devices being gated to an early/late gating circuit which serves to control advancement or retardation of a synchronisation clock to acheive synchronisation with incoming data signals.

4. A data transmission system receiver as claimed in claim 3, in which the early/late gating circuit provides an appropriate early or late signal which is fed to another gating circuit under the control of a counter which is also controlled by a signal derived from the early/late gating circuit, an advance or retard signal being accordingly applied to the synchronisation clock to provide synchronisation thereof with the incoming data signals.

5. A data transmission system receiver as claimed in claim 3 or claim 4, in which the synchronisation clock provides an output which is applied to a sampler which also receives the delayed data store output.

6. A data transmission system receiver as claimed in any preceding claim in which the incoming data signals are fed to an integrator having a time constant equal to the duration of incoming data packets whereby threshold determination of incoming data signals can be acheived.

7. A data transmission system receiver as claimed in any preceding claim, in which the data store provides for the reception of medium length data packets even though the store delay is shorter than the duration of the data packet.