AU2003257121A8 - Various methods and apparatuses to track failing memory locations to enable implementations for invalidating repeatedly failing memory locations - Google Patents

Various methods and apparatuses to track failing memory locations to enable implementations for invalidating repeatedly failing memory locations

Info

Publication number
AU2003257121A8
AU2003257121A8 AU2003257121A AU2003257121A AU2003257121A8 AU 2003257121 A8 AU2003257121 A8 AU 2003257121A8 AU 2003257121 A AU2003257121 A AU 2003257121A AU 2003257121 A AU2003257121 A AU 2003257121A AU 2003257121 A8 AU2003257121 A8 AU 2003257121A8
Authority
AU
Australia
Prior art keywords
memory locations
failing memory
invalidating
apparatuses
track
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003257121A
Other versions
AU2003257121A1 (en
Inventor
Husnara Khan
Sitaram Yadavalli
Garrett Drysdale
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of AU2003257121A1 publication Critical patent/AU2003257121A1/en
Publication of AU2003257121A8 publication Critical patent/AU2003257121A8/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/076—Error or fault detection not based on redundancy by exceeding limits by exceeding a count or rate limit, e.g. word- or bit count limit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0766—Error or fault reporting or storing
    • G06F11/0772—Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Debugging And Monitoring (AREA)
AU2003257121A 2002-08-12 2003-08-01 Various methods and apparatuses to track failing memory locations to enable implementations for invalidating repeatedly failing memory locations Abandoned AU2003257121A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/217,984 US7168010B2 (en) 2002-08-12 2002-08-12 Various methods and apparatuses to track failing memory locations to enable implementations for invalidating repeatedly failing memory locations
US10/217,984 2002-08-12
PCT/US2003/024141 WO2004015717A2 (en) 2002-08-12 2003-08-01 Various methods and apparatuses to track failing memory locations to enable implementations for invalidating repeatedly failing memory locations

Publications (2)

Publication Number Publication Date
AU2003257121A1 AU2003257121A1 (en) 2004-02-25
AU2003257121A8 true AU2003257121A8 (en) 2004-02-25

Family

ID=31495244

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003257121A Abandoned AU2003257121A1 (en) 2002-08-12 2003-08-01 Various methods and apparatuses to track failing memory locations to enable implementations for invalidating repeatedly failing memory locations

Country Status (7)

Country Link
US (1) US7168010B2 (en)
EP (1) EP1579460A2 (en)
JP (1) JP4283221B2 (en)
CN (2) CN101019192B (en)
AU (1) AU2003257121A1 (en)
TW (1) TWI254206B (en)
WO (1) WO2004015717A2 (en)

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US7493534B2 (en) * 2003-08-29 2009-02-17 Hewlett-Packard Development Company, L.P. Memory error ranking
US7484065B2 (en) 2004-04-20 2009-01-27 Hewlett-Packard Development Company, L.P. Selective memory allocation
US7555677B1 (en) * 2005-04-22 2009-06-30 Sun Microsystems, Inc. System and method for diagnostic test innovation
US7430145B2 (en) * 2005-09-16 2008-09-30 Hewlett-Packard Development Company, L.P. System and method for avoiding attempts to access a defective portion of memory
IL171963A0 (en) 2005-11-14 2006-04-10 Nds Ltd Secure read-write storage device
EP1808863A1 (en) * 2006-01-16 2007-07-18 Deutsche Thomson-Brandt Gmbh Method and apparatus for recording high-speed input data into a matrix of memory devices
DE102006008017A1 (en) * 2006-02-21 2007-08-30 Infineon Technologies Ag Production method for producing integrated semiconductor, involves installing integrated semiconductor memory, which has multiple state with memory cell field and memory cell for storage of data value and storage circuit for storage of data
US20080010566A1 (en) * 2006-06-21 2008-01-10 Chang Tsung-Yung Jonathan Disabling portions of memory with non-deterministic errors
KR101413736B1 (en) 2007-09-13 2014-07-02 삼성전자주식회사 Memory system with improved reliability and wear-leveling technique thereof
US8635491B2 (en) * 2007-09-28 2014-01-21 Seagate Technology Llc Storage device maintenance in a portable device based on a power event
US20090132876A1 (en) * 2007-11-19 2009-05-21 Ronald Ernest Freking Maintaining Error Statistics Concurrently Across Multiple Memory Ranks
US8032706B2 (en) * 2008-08-05 2011-10-04 Intel Corporation Method and apparatus for detecting a data access violation
US9678878B2 (en) 2008-09-30 2017-06-13 Intel Corporation Disabling cache portions during low voltage operations
JP5456063B2 (en) * 2009-01-23 2014-03-26 エルエスアイ コーポレーション Method and system for dynamic storage tiering using allocate-on-write snapshots
JP2011018187A (en) * 2009-07-09 2011-01-27 Fujitsu Ltd Test method, test program, test device and test system
US8103900B2 (en) * 2009-07-28 2012-01-24 International Business Machines Corporation Implementing enhanced memory reliability using memory scrub operations
US9042191B2 (en) 2009-08-12 2015-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Self-repairing memory
US20110041016A1 (en) * 2009-08-12 2011-02-17 Taiwan Semiconductor Manufacturing Company, Ltd. Memory errors and redundancy
US8750059B2 (en) 2009-08-12 2014-06-10 Taiwan Semiconductor Manufacturing Company, Ltd. Self-repairing memory
US8640006B2 (en) * 2011-06-29 2014-01-28 International Business Machines Corporation Preemptive memory repair based on multi-symbol, multi-scrub cycle analysis
DE102011107936B4 (en) * 2011-07-19 2015-07-23 Texas Instruments Deutschland Gmbh A semiconductor device and method for tracing a memory of a semiconductor device
JP5962269B2 (en) * 2012-07-09 2016-08-03 富士通株式会社 Evaluation device, distributed storage system, evaluation method and evaluation program
US8924775B1 (en) * 2012-09-25 2014-12-30 Western Digital Technologies, Inc. Methods, devices and systems for tracking and relocating intermittently defective disk sectors to prevent indefinite recycling thereof
US9389937B2 (en) * 2013-11-19 2016-07-12 Lenovo Enterprise Solutions (Singapore) Pte. Ltd. Managing faulty memory pages in a computing system
KR102532581B1 (en) * 2016-03-17 2023-05-17 에스케이하이닉스 주식회사 Memory system including memory device and operation method thereof
US9910606B2 (en) 2016-03-23 2018-03-06 Seagate Technology Llc End of life extension of solid state memory
US9852060B2 (en) * 2016-03-31 2017-12-26 Dell Products L.P. Storage class memory (SCM) memory mode cache system
CN107122256B (en) * 2017-06-13 2018-06-19 北京邮电大学 The high-performance on piece caching fault-tolerant architecture of dynamic repairing
CN109522175B (en) 2017-09-18 2020-09-04 华为技术有限公司 Memory evaluation method and device
US11740928B2 (en) 2019-08-26 2023-08-29 International Business Machines Corporation Implementing crash consistency in persistent memory
US11928497B2 (en) 2020-01-27 2024-03-12 International Business Machines Corporation Implementing erasure coding with persistent memory
CN114637616A (en) * 2020-12-15 2022-06-17 超威半导体(上海)有限公司 Method and system for recording and recording error handling information
CN112601153B (en) * 2021-03-01 2021-05-07 成都大熊猫繁育研究基地 Automatic sound acquisition and transmission device and use method thereof

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GB2276255A (en) 1993-02-17 1994-09-21 Andor Int Ltd Track buffer with embedded error data
EP0675436B1 (en) 1994-03-31 1999-10-27 STMicroelectronics, Inc. Recoverable set associative cache
US5974576A (en) * 1996-05-10 1999-10-26 Sun Microsystems, Inc. On-line memory monitoring system and methods
US6085334A (en) * 1998-04-17 2000-07-04 Motorola, Inc. Method and apparatus for testing an integrated memory device
US6505305B1 (en) * 1998-07-16 2003-01-07 Compaq Information Technologies Group, L.P. Fail-over of multiple memory blocks in multiple memory modules in computer system
US6370622B1 (en) * 1998-11-20 2002-04-09 Massachusetts Institute Of Technology Method and apparatus for curious and column caching
US6282617B1 (en) * 1999-10-01 2001-08-28 Sun Microsystems, Inc. Multiple variable cache replacement policy
US6467048B1 (en) * 1999-10-07 2002-10-15 Compaq Information Technologies Group, L.P. Apparatus, method and system for using cache memory as fail-over memory
US6496538B1 (en) * 1999-12-31 2002-12-17 Intel Corporation Method and apparatus for motion estimation for digital video encoding
US6691252B2 (en) * 2001-02-23 2004-02-10 Hewlett-Packard Development Company, L.P. Cache test sequence for single-ported row repair CAM
JP4181500B2 (en) * 2001-11-09 2008-11-12 サン・マイクロシステムズ・インコーポレーテッド Method and apparatus for correcting bit errors encountered between cache references without blocking
US6865694B2 (en) * 2002-04-30 2005-03-08 Texas Instruments Incorporated CPU-based system and method for testing embedded memory

Also Published As

Publication number Publication date
AU2003257121A1 (en) 2004-02-25
US7168010B2 (en) 2007-01-23
JP4283221B2 (en) 2009-06-24
TW200413915A (en) 2004-08-01
EP1579460A2 (en) 2005-09-28
TWI254206B (en) 2006-05-01
WO2004015717A2 (en) 2004-02-19
CN101019192A (en) 2007-08-15
WO2004015717A3 (en) 2006-06-01
US20040030957A1 (en) 2004-02-12
CN101019192B (en) 2014-10-01
JP2006510071A (en) 2006-03-23

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase