CN107122256B - The high-performance on piece caching fault-tolerant architecture of dynamic repairing - Google Patents
The high-performance on piece caching fault-tolerant architecture of dynamic repairing Download PDFInfo
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
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Abstract
Patent of the present invention proposes a kind of high-performance on piece caching fault-tolerant architecture of dynamic repairing, can timely, efficiently, the processing intermittence position failure of low overhead and permanent fault.By the Exchange rings of a Fault-Sensitive, the failure of kainogenesis can be tolerated at any time, ensures caching normal work, the situation of access is then utilized according to the cache blocks, and by dynamic patching fault sub-block, mitigating failure influences the performance of caching.
Description
Technical field
Patent of the present invention is related to a kind of caching fault-tolerant architecture for repairing intermittence and permanent error, especially can dynamically repair
The caching fault-tolerant architecture of the high-performance on piece of benefit.
Background technology
Not only permanent fault caused by missing inspection and wear and aging impacts the reliability of the chip after manufacture, moreover,
It is difficult to what is detected before manufacture, occurs at random on the time, position is fixed, continues some cycles, but recoverable intermittence
Position failure, which also results in the reliability of the chip after manufacture, to be seriously affected.Effectively error correcting and detecting code is being handled reply transient fault
When intermittence position is failed, the problem of delay expense is big is also faced, and the processing to transient fault can be weakened, cause the event of multidigit position
Barrier.And the cache structure of some reply permanent faults proposed at present, such as sub-block disabling scheme, Lothrus apterus mending option etc.,
Static bypass or alternative are all based on, needs, when system starts or electric voltage frequency adjusts, to carry out the processing of failure.
The processing of these methods is not in time, it is impossible to successfully manage the intermittent position failure occurred at random on the time.
Invention content
This patent proposes the high-performance on piece caching fault-tolerant architecture of dynamic repairing, can timely, efficiently, low overhead
Processing intermittence position failure and permanent fault.By the Exchange rings of a Fault-Sensitive, kainogenesis can be tolerated at any time
Failure ensures caching normal work, and the situation of access is then utilized according to the cache blocks, passes through dynamic patching fault
Block, mitigating failure influences the performance of caching.
This buffer structure, as shown in Figure 1, with following feature：
One cache blocks of this cache lines structure include several sub-blocks, and the structure of cache blocks mainly includes sub-block failure domain,
Whether cache blocks disable domain, and sub-block offset adjustment counter domain is directed toward the pointer field of repairing array, represents whether data are changed
Domain, safeguard the domain of replacement state and tag identifier domain.The sub-block offset actually mapped is by sub-block offset and block bias internal phase
Add to obtain.
1. mark mark position：Represent the label of the cache blocks.
2. sub-block failure bitmap domain：The sub-block malfunction of each cache blocks is indicated, comprising several positions, corresponds to several
Sub-block is configured the position to distinguish with normal sub-block if sub-block is failure sub-block.Change domain when system is initial into
Row filling, electric voltage frequency dynamic are updated when adjusting, can be timely updated according to the result of even-odd check, if repeatedly continuous find position
Failure, it is believed that intermittent position failure occurs, so as to time update SFM domains.
3. whether caching disables domain：Indicate whether the cache blocks are disabled, if there is no continuous in a cache blocks
Fault-free sub-block, then the cache blocks are disabled, and the value in the domain is configured, and distinguished with good for use.
4. whether data change domain：Whether designation date is changed, and modifies if modification to changing domain, otherwise constant.
5. sub-block deviates regulatory domain：For adjusting the practical Map Offsets position of sub-block.Its size can represent sub-block
Number
6. it is directed toward the pointer field of repairing array：Array is repaired for being directed toward
7. substitution indicia position：Record situation about replacing
The present invention proposes a kind of Fault-Sensitive mechanism algorithm, is divided into two situations of the ordained by Heaven false hit of neutralization, respectively as schemed
Shown in 2, Fig. 3：
When occurring ordained by Heaven middle:
Step 1：As block is removed, cache request R, certain block Sblock (R) are the cache blocks v for selecting to replace bottom of stack
k。
Step 2:The sub-block for judging ((k+ counter C (v)) MOD SN) is trouble-free, i.e. B (v) [(k+C (v)) MOD
SN] numerical check, step 3 is gone to if fault-free, if faulty go to step 4
Step 3：The value of counter C is constant.Skip to step 5.
Step 4：The counter C of cache blocks is adjusted, is stopped when SFM (v) [(k+NewC (v)) MOD SN] value represents fault-free
It only adjusts, Counter Value is set as NewC.
Step 5：The data of request can be placed into the fault-free sub-block of cache blocks v.The Promotion Strategy similar with LRU into
The adjustment of the replacement state of cache blocks, cache blocks v are thus lifted to the top of storehouse in row storehouse.
When false hit occurs：
Step 1:The cache blocks fv for selecting to replace bottom of stack is as removal block
Step 2:Whether fv is judged comprising swollen data, if carrying out write-back comprising if.Step 3 is gone to after the completion
Step 3:Adjust the Counter Value of fv so that B (fv) [RSblockfv (R)] value is expressed as unfaulty conditions
Step 4:Carry out deletion condition processing.
Step 5:According to Promotion Strategy, fv is promoted to stack top, other cache lines update its order successively in stack.
The fault-tolerant cache structure mode of this buffer structure, overall architecture are as shown in Figure 7:
The content of reference numeral expression is in figure：1. whether mark mark, 2. sub-block failure bitmap domains, 3. cachings disable
Whether domain, 4. data change domain, and the pointer field that 5. sub-blocks offset adjustment count field currently repairs array for 000,6. directions is current
It is 000101,7. replacement mode bits, 8. partition identifications, 00 is free cells, and 01 is starts unit, and 10 be temporary location, and 11 are
Terminate unit.
In the tag field of cache blocks, the pointer field for being directed toward repairing array stores the first address of repairing unit.Repairing is single
Member is provided by certain an array, which is a separate modular being separately addressed, it includes several units.Each unit
It is mainly made of two parts, mark domain and data field wherein mark domain part include several positions.It is combined to represent (1) respectively
The unit is idle, is not previously allocated away for patching fault sub-block.(2) it is the starting list of repairing section to represent the unit
Member.(3) it is the end unit of repairing section to represent the unit.(4) it is repairing Component units to represent the unit.The institute of one cache blocks
Faulty sub-block is a repairing, because the cache blocks for being considered being worth repairing are all to reuse higher cache blocks.Moreover, it repaiies
The repairing unit for mending a cache blocks is continuous what is disposably distributed in the array, forms a repairing section.Repairing section
The mark domain of start element is assigned expression situation (1), and the mark domain of end unit is assigned situation (3), temporary location
Mark domain is assigned situation (4).
The present invention provides a kind of dynamics to repair mechanism process, is divided into false hit, ordained by Heaven to neutralize three kinds of situations of missing, respectively
Such as Fig. 4, Fig. 5, shown in Fig. 6：
During vacation hit：
Assuming that the cache blocks that false missing occurs are fv, and the quantity of its failure sub-block is k.
Step 1:It checks with the presence or absence of k continuous free cells in the particular array, if it is not, EP (end of program).
Otherwise step 2 is gone to
Step 2:The data that adjustment counter guarantee is newly asked are placed in the fault-free sub-block of cache blocks fv.If it looks for
To a continuous free cells of k, then this k continuous one repairing of free cells composition save, with then will repairing the beginning of section
(it is assumed to be A) in the storage to some domain of cache blocks fv of location, while the mark domain of setting repairing section each unit respectively.
Step 3:It is loaded into data again from standby storage, partial data is placed to the fault-free sub-block of cache blocks fv
In, another part data are sequentially placed in repairing unit by the pointer in A domains, sequentially by the offset of failure sub-block from small
To longer spread.
When ordained by Heaven middle：
Assuming that hit cache blocks are v.
Step 1:Value according to some domain (being assumed to be A) assembles requested data.Check the cache blocks with the presence or absence of pair
The repairing unit answered, if then illustrating that requested data are stored in the fault-free sub-block of cache blocks v.If it is not, it then says
The bright cache blocks are there is corresponding repairing unit, and the initial address for repairing unit is recorded in A domains, the value in foundation A domains,
Direct addressin accesses corresponding repairing unit, according to the label of mark domain, can disposably be quickly found out all repairing lists
Member.
2. a part of data are read from the fault-free sub-block of cache blocks v, a part directly reads from repairing unit and puts
It puts in built-in register, then the value according to some domain (being assumed to be B), the value of counter are assembled, and formation one is complete
Whole data block.
During missing：
Value of the step 1. according to some domain (being assumed to be B), the value of counter so that request data is placed to cache blocks
In fault-free sub-block.
Step 2. is when a cache blocks are chosen by sensitive mechanism algorithm to sacrifice cache blocks, if the cache blocks are changed
It crosses, needs first to write back.Check the value in some domain (being assumed to be A), if being marked with repairing unit, after writing back, corresponding repairing
The mark domain that unit needs are retracted these i.e. units is arranged to idle state.
The invention has the advantages that delay expense is relatively low, for average hit access time and the performance of caching
It influences smaller.When in face of different position failure rates, the fluctuation of performance is small, under higher probability of malfunction can also efficient operation,
Ensure the stabilization of performance.Particular array only needs the memory space of 0.26KB~0.5KB, it is possible to which Efficient software patching position failure rate reaches
When 0.01 32KB L1 caching, and with fault-free cache compared with, hydraulic performance decline within 1%, make L1 caching can down to
Efficient operation under 400 millivolts of supply voltage.
Description of the drawings
Fig. 1 is the structure chart of the cache blocks tag field of this buffer structure.
Fig. 2 is algorithm flow chart when false hit occurs for Fault-Sensitive mechanism algorithm
Fig. 3 is algorithm flow chart when Fault-Sensitive mechanism algorithm occurs ordained by Heaven middle
Fig. 4 is algorithm flow chart when false hit occurs for dynamic repairing mechanism process
Fig. 5 is algorithm flow chart when dynamic repairing mechanism process occurs ordained by Heaven middle
Fig. 6 is algorithm flow chart when dynamic repairing mechanism process lacks
Fig. 7 is the fault-tolerant cache structure schematic diagram of this buffer structure
Fig. 8 is the content of the initial cache lines of this buffer structure, the reliability state mark Line-Status of cache lines and right
The value schematic diagram for the counter answered
Specific embodiment
Citing illustrates sensitive mechanism algorithm below：
Assuming that the caching group that a common degree of association of L1 cachings is 4, i.e. a caching group cache lines containing there are four, just
The content of the cache lines of beginning, the reliability state mark Line-Status of cache lines and value such as Fig. 8 institutes of corresponding counter
Show.Wherein each cache lines are made of mark part and data portion, and mark part includes mark mark position, sub-block failure bitmap
Whether domain, caching disable domain, and whether data change domain, and sub-block offset regulatory domain is directed toward the pointer field for repairing array, substitution indicia
Position, for data portion then using the continuous space of 8 bytes as a sub-block, a caching group includes 8 sub-blocks.Initial cache lines
Content is faulty for the first caching the 3rd, 5 sub-block of every trade, and the 5th, 6 sub-block of the second cache lines is faulty, and the 3rd of third cache lines the
Sub-block is faulty, and the 3rd, 7,8 sub-block of the 4th cache lines is faulty.The value of corresponding counter is respectively the first behavior 001, the
Two behaviors 010, third behavior 000, fourth line 001.If a domains are the third sub-block of the 4th cache lines, b domains are the second cache lines
The 5th sub-block, c domains be third cache lines the 6th sub-block, d domains be the first cache lines third sub-block, e domains for second caching
The 4th capable sub-block.The corresponding SFM thresholdings of each cache lines are respectively 00101000,00001100,00100000 and 00100001.
When cache request R1 occurs, request data g, request lacks, it is assumed that request address is mapped to the inclined of the sub-block of cache lines
Shifting is 7, first looks for candidate removal block, which can select to replace the cache lines L4 of bottom of stack, if Line4 includes swollen number
It is failure sub-block since B domains (L4) [7] and B domains (L4) [8] are equal to 1 according to then write-back Line4, therefore, the meter of cache lines L4
Number device is set as 2, and according to formula, certain block RSblock (R) is equal to (7+2) MOD 8, i.e., equal to 1, request data g actual storages arrive
The sub-block for 1 is deviated, then according to strategy is risen, Line4 is raised to stack top, other cache lines update its order successively in stack.It connects
Get off, when cache request R2 occurs, request data e, data e is had been placed in request data b in Line3, but
It is that data e is placed in failure sub-block, therefore, as request data e, false hit occurs.The algorithm thinks vacation hit
It is missing from, and the candidate block that removes just selects that the cache lines of false hit occur.But it is directly loaded into data block again to the caching
Guild makes the valid data of request be placed into failure sub-block, it is therefore desirable to first adjust the counter of the cache lines.For cache lines
Line3, due to Sblock (e) equal to 4, SFM (L3) [4] equal to " 0 ", therefore, it is 0 that can set counter so that RSblock
(e) equal to 4, data e is placed in fault-free sub-block.Update for the replacement state after false hit, it is tactful according to rising,
The replacement state of all cache lines all remains unchanged.
When cache request R3 arrives, request data b again, but cache request R2 causes 80 false hit so that it is slow
It deposits row Line3 to be loaded into again, and adjust counter so that data b has been placed in failure sub-block, therefore request data
B also results in false hit.Processing of the algorithm to request R3, can cause counter to be again set to 1, data b can be interviewed
It asks, and data e is placed in failure sub-block.Therefore, it is frequent to result in cache blocks Line3 by access data e and access data b
There is false hit, data block Line3 is loaded into L1 level caches repeatedly, generates the phenomenon of jolting of false hit.
Claims (3)
1. a kind of high-performance on piece caching fault-tolerant architecture of dynamic repairing, it is characterised in that：One cache blocks includes several height
Block, the structure of cache blocks have newly increased domain, and the sub-block and the domain include：
(1) mark mark position, for representing the label of the cache blocks；
(2) sub-block failure bitmap domain has been used to indicate the sub-block malfunction of each cache blocks, and comprising several positions, correspondence is several
A sub-block is configured to be distinguished with normal sub-block the position if sub-block is failure sub-block, and the domain is when system is initial
It is filled, electric voltage frequency dynamic updates when adjusting, and can be timely updated according to the result of even-odd check, if repeatedly continuous find
Position failure, it is believed that intermittent position failure occurs, so as to sub-block failure bitmap domain described in time update；
(3) whether caching disables domain, and whether be used to indicate the cache blocks disabled, if there is no continuous in a cache blocks
Fault-free sub-block, then the cache blocks are disabled, and the value in the domain is configured, and distinguished with good for use；
(4) whether data change domain, are used to indicate whether data are changed, and modify if modification to the domain, otherwise constant；
(5) sub-block offset regulatory domain, for adjusting the practical Map Offsets position of sub-block, size can represent sub-block number
；
(6) pointer field of repairing array is directed toward, array is repaired for being directed toward；And
(7) substitution indicia position, for recording situation about replacing；
The sub-block offset wherein actually mapped is deviated by sub-block to be added to obtain with block bias internal.
2. a kind of high-performance on piece caching fault-tolerant architecture of dynamic repairing according to claim 1, it is characterised in that：It is described
Framework tolerates the failure of kainogenesis, ensures caching normal work, the failure at any time by the Exchange rings of a Fault-Sensitive
Sensitive Exchange rings are based on least recently used (Least RecentlyUsed:LRU) replace algorithm, consider data reusing with
And the malfunction of sub-block, it is adjusted according to newly-increased caching fault-tolerant architecture come the counter to cache blocks so that request
Data can be put into trouble-free sub-block, and the replacement algorithm is divided into two kinds of situations of the ordained by Heaven false hit of neutralization：
(1) when occurring ordained by Heaven middle, the replacement algorithm steps include：
Step 1：For the cache blocks v for selecting to replace bottom of stack as removal block, cache request R, certain block Sblock (R) are k；
Step 2：The sub-block for judging ((k+ counter C (v)) MOD SN) is trouble-free, i.e. B (v) [(k+C (v)) MOD SN] numbers
Value checks, step 3 is gone to if fault-free, if faulty go to step 4；
Step 3：The value of counter C is constant, skips to step 5；
Step 4：The counter C of cache blocks is adjusted, stops adjusting when SFM (v) [(k+NewC (v)) MOD SN] value represents fault-free
Whole, Counter Value is set as NewC；
Step 5：The data of request are placed into the fault-free sub-block of cache blocks v, and the Promotion Strategy similar with LRU is carried out in storehouse
The adjustment of the replacement state of cache blocks, cache blocks v are thus lifted to the top of storehouse；
(2) when false hit occurs, the replacement algorithm steps include：
Step 1：The cache blocks fv for selecting to replace bottom of stack is as removal block；
Step 2：Judge that fv whether comprising dirty data, if carrying out write-back comprising if, goes to step 3 after the completion；
Step 3：Adjust the Counter Value of fv so that B (fv) [RSblockfv (R)] value is expressed as unfaulty conditions；
Step 4：Carry out deletion condition processing；
Step 5：According to Promotion Strategy, fv is promoted to stack top, other cache lines update its order successively in stack.
3. a kind of high-performance on piece caching fault-tolerant architecture of dynamic repairing according to claim 2, it is characterised in that：It is described
Dynamic patching fault sub-block is the cache blocks for failure sub-block, and it is slow by this that continuous space is found in domain is repaired
It deposits caching fault-tolerant architecture some domain A and some domain B of structure and replaces failure sub-block to correspond to, and to repairing after cache blocks use
The replacement block in space is discharged, and the process of the dynamic patching fault sub-block is divided into false hit, ordained by Heaven to neutralize three kinds of missing
Situation is respectively：
(1) when false hit occurs, the step of dynamic patching fault sub-block, includes：
Assuming that the cache blocks that false missing occurs are fv, and the quantity of its failure sub-block is k；
Step 1：It checks and whether there is k continuous free cells in the particular array, if it is not, EP (end of program), otherwise
Go to step 2；
Step 2：The data that adjustment counter guarantee is newly asked are placed in the fault-free sub-block of cache blocks fv, if finding k
A continuous free cells, then the k continuous one repairing section of free cells composition, then deposit the start address for repairing section
In the domain A for storing up cache blocks fv, while the mark domain of setting repairing section each unit respectively；
Step 3：It is loaded into data again from standby storage, partial data is placed in the fault-free sub-block of cache blocks fv, separately
Outer a part of data are sequentially placed in repairing unit, are sequentially arranged from small to large by the offset of failure sub-block by the pointer of domain A
Row；
(2) when occurring ordained by Heaven middle, the step of dynamic patching fault sub-block, includes：
Assuming that hit cache blocks are v；
Step 1：Value according to domain A assembles requested data, checks the cache blocks with the presence or absence of corresponding repairing unit, if
Then illustrate that requested data are stored in the fault-free sub-block of cache blocks v, there is right if it is not, then illustrating the cache blocks
The repairing unit answered, and the initial address for repairing unit is recorded in the A of domain, and according to the value of domain A, direct addressin accesses corresponding
Unit is repaired, according to the label of mark domain, is disposably quickly found out all repairing units；
Step 2：A part of data are read from the fault-free sub-block of cache blocks v, a part is directly read from repairing unit
And be placed into built-in register, then the value according to the value of domain B and counter is assembled, and forms a complete data
Block；
(3) when lacking, the step of dynamic patching fault sub-block, includes：
Step 1：According to the value of domain B and the value of counter so that request data is placed in the fault-free sub-block of cache blocks；
Step 2：When a cache blocks are chosen by the replacement algorithm of the Exchange rings of the Fault-Sensitive to sacrifice cache blocks
When, if the cache blocks are modified, need first to write back, check the value of domain A, it is right after writing back if being marked with repairing unit
The repairing unit answered is retracted, i.e. the mark domain of these units is arranged to idle state.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6810489B1 (en) * | 2000-09-06 | 2004-10-26 | Hewlett-Packard Development Company, L.P. | Checkpoint computer system utilizing a FIFO buffer to re-synchronize and recover the system on the detection of an error |
| WO2012005938A3 (en) * | 2010-07-05 | 2012-03-08 | Intel Corporation | Fault tolerance of multi-processor system with distributed cache |
| CN103870353A (en) * | 2014-03-18 | 2014-06-18 | 北京控制工程研究所 | Multicore-oriented reconfigurable fault tolerance system and multicore-oriented reconfigurable fault tolerance method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7168010B2 (en) * | 2002-08-12 | 2007-01-23 | Intel Corporation | Various methods and apparatuses to track failing memory locations to enable implementations for invalidating repeatedly failing memory locations |
| CN105005513B (en) * | 2015-08-19 | 2017-12-05 | 首都师范大学 | The detection of cache long numeric data upset mistake and fault tolerance facility and method |
| CN105335247B (en) * | 2015-09-24 | 2018-04-20 | 中国航天科技集团公司第九研究院第七七一研究所 | The fault-tolerant architecture and its fault-tolerance approach of Cache in highly reliable System on Chip/SoC |
-
2017
- 2017-06-13 CN CN201710298651.7A patent/CN107122256B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6810489B1 (en) * | 2000-09-06 | 2004-10-26 | Hewlett-Packard Development Company, L.P. | Checkpoint computer system utilizing a FIFO buffer to re-synchronize and recover the system on the detection of an error |
| WO2012005938A3 (en) * | 2010-07-05 | 2012-03-08 | Intel Corporation | Fault tolerance of multi-processor system with distributed cache |
| CN103870353A (en) * | 2014-03-18 | 2014-06-18 | 北京控制工程研究所 | Multicore-oriented reconfigurable fault tolerance system and multicore-oriented reconfigurable fault tolerance method |
Non-Patent Citations (5)
| Title |
|---|
| 《A fault-tolerant directory-based cache coherence protocol for CMP architecture》;Ricardo Fernandez-Pascual等;《International Conference on Dependable Systems & Networks》;20080630;全文 * |
| 《Analyzing the Optimal Voltage/Frequency Pair in Fault-Tolerant Caches》;Vicente Lorente;《IEEE International Conference on High Performance Computing and Communications》;20141031;全文 * |
| 《CacheFI：基于架构级故障注入的片上缓存容错评估工具》;黄智濒等;《国防科技大学学报》;20161031;第38卷(第5期);全文 * |
| 《Fault-Tolerant Features in the Hal Memory Management Unit》;Nirmal R.Saxena等;《IEEE TAANSACTIONS ON COMPUTERS》;19950228;第44卷(第2期);全文 * |
| 《混合架构下多请求模式的缓存替换模型研究》;曹旻等;《计算机科学》;20150630;第42卷(第6期);全文 * |
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