ZA9010006B - Memory management in a multi-processor system - Google Patents

Memory management in a multi-processor system

Info

Publication number
ZA9010006B
ZA9010006B ZA9010006A ZA9010006A ZA9010006B ZA 9010006 B ZA9010006 B ZA 9010006B ZA 9010006 A ZA9010006 A ZA 9010006A ZA 9010006 A ZA9010006 A ZA 9010006A ZA 9010006 B ZA9010006 B ZA 9010006B
Authority
ZA
South Africa
Prior art keywords
memory management
processor system
processor
management
memory
Prior art date
Application number
ZA9010006A
Other languages
English (en)
Inventor
Nicholas Peter Holt
Peter Holt Nicholas
Laurence Robin Smith
Robin Smith Laurence
Original Assignee
Int Computers Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Int Computers Ltd filed Critical Int Computers Ltd
Publication of ZA9010006B publication Critical patent/ZA9010006B/xx

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B7/00—Recording or reproducing by optical means, e.g. recording using a thermal beam of optical radiation by modifying optical properties or the physical structure, reproducing using an optical beam at lower power by sensing optical properties; Record carriers therefor
    • G11B7/12—Heads, e.g. forming of the optical beam spot or modulation of the optical beam
    • G11B7/13—Optical detectors therefor
    • G11B7/131—Arrangement of detectors in a multiple array
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
ZA9010006A 1990-01-18 1990-12-12 Memory management in a multi-processor system ZA9010006B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB909001156A GB9001156D0 (en) 1990-01-18 1990-01-18 Memory management in a multiprocessor system

Publications (1)

Publication Number Publication Date
ZA9010006B true ZA9010006B (en) 1991-11-27

Family

ID=10669513

Family Applications (1)

Application Number Title Priority Date Filing Date
ZA9010006A ZA9010006B (en) 1990-01-18 1990-12-12 Memory management in a multi-processor system

Country Status (6)

Country Link
EP (1) EP0437928B1 (xx)
JP (1) JPH04211848A (xx)
AU (1) AU631713B2 (xx)
DE (1) DE69033052T2 (xx)
GB (1) GB9001156D0 (xx)
ZA (1) ZA9010006B (xx)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7103728B2 (en) * 2002-07-23 2006-09-05 Hewlett-Packard Development Company, L.P. System and method for memory migration in distributed-memory multi-processor systems

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4504902A (en) * 1982-03-25 1985-03-12 At&T Bell Laboratories Cache arrangement for direct memory access block transfer
JPH0622015B2 (ja) * 1987-11-30 1994-03-23 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン データ処理システムの制御方法

Also Published As

Publication number Publication date
EP0437928A3 (en) 1992-07-29
DE69033052D1 (de) 1999-05-20
EP0437928A2 (en) 1991-07-24
AU6940391A (en) 1991-07-25
EP0437928B1 (en) 1999-04-14
AU631713B2 (en) 1992-12-03
DE69033052T2 (de) 1999-11-18
GB9001156D0 (en) 1990-03-21
JPH04211848A (ja) 1992-08-03

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