WO2026001092A1 - 系统不可恢复故障处理方法、装置、电子设备及存储介质 - Google Patents

系统不可恢复故障处理方法、装置、电子设备及存储介质

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Publication number
WO2026001092A1
WO2026001092A1 PCT/CN2025/082706 CN2025082706W WO2026001092A1 WO 2026001092 A1 WO2026001092 A1 WO 2026001092A1 CN 2025082706 W CN2025082706 W CN 2025082706W WO 2026001092 A1 WO2026001092 A1 WO 2026001092A1
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WIPO (PCT)
Prior art keywords
fault
register
bmc
location information
processor
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PCT/CN2025/082706
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English (en)
French (fr)
Inventor
张传玺
张秀波
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Suzhou Metabrain Intelligent Technology Co Ltd
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Suzhou Metabrain Intelligent Technology Co Ltd
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Publication of WO2026001092A1 publication Critical patent/WO2026001092A1/zh
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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operations
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/1438—Restarting or rejuvenating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0793—Remedial or corrective actions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • This application relates to the field of computer technology, and in particular to a method, apparatus, electronic device, and non-transitory readable storage medium for handling unrecoverable system faults.
  • RAS Reliability, Availability, and Serviceability
  • CPU Central Processing Unit
  • This application provides a method, apparatus, electronic device, and non-transitory readable storage medium for handling unrecoverable system faults, in order to solve the problem that in existing methods for handling unrecoverable system faults, the processor workload is high, which affects the processor's performance in processing real user services.
  • This application provides a method for handling unrecoverable system failures, applied to a BMC (Baseboard Management Controller), including the following steps.
  • BMC Baseboard Management Controller
  • the processor's register data is collected.
  • the fault check signal is sent to the BMC by the on-chip controller after it detects that the flag bit of the fault isolation register has been set.
  • Triggering a system warm restart During the system warm restart process, the location information is used to instruct the host BIOS to disable the corresponding faulty device based on the location information.
  • the processor register data is collected, including: after detecting the fault check signal, collecting the register data of the registers in the register configuration table stored in the BMC, wherein the register configuration table contains the configuration information of the processor registers.
  • the register data of the registers in the register configuration table stored in the BMC is collected, including the following steps.
  • the configuration information includes: register offset address, access mode, CPU number, data length, output location, and register name.
  • the framing format is determined based on the access method.
  • a data frame is generated in a framing format for accessing the processor.
  • the data frame is then sent to the processor as write data.
  • the data frame is used to instruct the processor, if it confirms that the CPU number is the same as its own number, to read the register value in the register corresponding to the offset address with a length equal to the data length, and to return the register value to the BMC.
  • register name and register value are combined into key-value pairs to form register data.
  • An intermediate file is generated based on the register data and written to the specified storage path in the output location.
  • system unrecoverable fault handling method further includes: during the system hot restart process, if a fault check signal is detected again, the processor register data is collected again, an intermediate file is generated again, the regenerated intermediate file is merged with the previously generated intermediate file, and for registers whose data has been collected previously, the corresponding register values are retained only from the previous register values.
  • the system unrecoverable fault handling method after the system hot restart is completed, it also includes: deleting the intermediate file generated for the first time or the merged intermediate file.
  • the method for handling unrecoverable system failures provided in this application further includes: prompting that the system cannot start when the number of system hot restarts exceeds the preset number of restarts and the system cannot start.
  • the method further includes: the on-chip controller pulls high the checkstop pin connected to the BMC; after the BMC detects that the checkstop pin is pulled high, it considers that a fault check signal has been detected; the BMC obtains the processor's register data through I2C and the replaceable unit interface.
  • the register data is analyzed to obtain the location information of the faulty device, including the following steps.
  • the register name obtained from the register data is the first target register value corresponding to the device status.
  • the second target register value corresponding to the device address is obtained.
  • the second target register value is the address information of the faulty device, and the address information is determined as the location information.
  • the register data is analyzed to obtain the location information of the faulty device, including the following steps.
  • the register name obtained from the register data is the first target register value corresponding to the device status.
  • the second target register value is the address information of the faulty device.
  • the address information of the faulty device is converted into the device identifier of the faulty device based on the conversion relationship between the device address information and the device identifier recorded in the asset information, and the device identifier is determined as the location information.
  • PCIe Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard
  • a fault analysis table is generated based on the location information of the faulty equipment.
  • the fault analysis table is sent to shared memory for storage, so that the host BIOS can retrieve the fault analysis table from the shared memory during a system hot restart.
  • a fault analysis table is generated based on the location information of the faulty device, including the following steps:
  • the number of times the target faulty device in the historical fault analysis table has failed is counted.
  • the target faulty device is the faulty device currently analyzed.
  • This application also provides a method for handling unrecoverable system failures, applied to the BIOS on the host side, including the following steps.
  • the on-chip controller When the flag bit of the fault isolation register is set, the on-chip controller is triggered to send a fault check signal to the BMC.
  • the fault check signal is used to instruct the BMC to collect and analyze the processor's register data to obtain the location information of the faulty device and trigger a system hot restart.
  • the corresponding faulty device is blocked based on the location information.
  • This application also provides a method for handling unrecoverable system faults, which triggers the on-chip controller to send a fault check signal to the BMC when the flag bit of the fault isolation register is set, including the following steps.
  • the on-chip controller When the interrupt function is executed, the on-chip controller is triggered to send a fault check signal to the BMC.
  • This application also provides a method for handling unrecoverable system faults, which involves shielding the corresponding faulty device based on location information during a system hot restart, including the following steps.
  • a fault analysis table is retrieved from shared memory. This table is generated by the BMC based on the location information of the faulty device.
  • the location information is parsed from the fault analysis table, and the corresponding faulty device is blocked based on the location information.
  • This application also provides a method for handling unrecoverable system faults, which parses location information from a fault analysis table, and further includes: identifying the location information of each faulty device from the fault analysis table using special symbols, wherein the location information is separated in the fault analysis table by special symbols.
  • This application also provides a method for handling unrecoverable system faults, which further includes: the on-chip controller pulls up the checkstop pin connected to the BMC, and the BMC considers the detection of the checkstop pin as a fault check signal; the BMC obtains the processor's register data through I2C and the replaceable unit interface.
  • This application also provides a system unrecoverable fault handling device, applied to BMC, including the following modules.
  • the data collection module is configured to collect processor register data after a fault check signal is detected.
  • the fault check signal is sent to the BMC by the on-chip controller after it detects that the flag bit of the fault isolation register is set.
  • the data analysis module is configured to analyze register data to obtain the location information of the faulty device.
  • the restart trigger module is set to trigger a system hot restart.
  • the location information is used to instruct the host BIOS to disable the corresponding faulty device based on the location information.
  • This application also provides a system unrecoverable fault handling device, applied to the BIOS on the host side, including the following modules.
  • the fault detection module is configured to monitor the status of the flag bits in the fault isolation register.
  • the fault check signal sending module is configured to trigger the on-chip controller to send a fault check signal to the BMC when the flag bit of the fault isolation register is set.
  • the fault check signal is used to instruct the BMC to collect and analyze the processor's register data to obtain the location information of the faulty device and trigger a system hot restart.
  • the fault device shielding module is configured to shield the corresponding faulty device based on the location information during system hot restart.
  • This application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor.
  • the processor executes the program, it implements any of the above-described methods for handling unrecoverable system faults applied to a BMC, or implements any of the above-described methods for handling unrecoverable system faults applied to a BIOS on the host side.
  • This application also provides a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements any of the above-described methods for handling unrecoverable system faults applied to a BMC, or implements any of the above-described methods for handling unrecoverable system faults applied to a BIOS on the host side.
  • the system unrecoverable fault handling method, apparatus, electronic device, and non-transitory readable storage medium collect processor register data by the BMC after detecting a fault check signal.
  • the fault check signal is sent to the BMC by the on-chip controller after detecting that the flag bit of the fault isolation register is set.
  • the BMC analyzes the register data to obtain the location information of the faulty device and triggers a system warm restart. During the system warm restart, the location information is used to instruct the host BIOS to disable the corresponding faulty device based on the location information.
  • the BMC collects and analyzes the processor's register data out of band. The data collection and analysis process does not consume processor resources, greatly reducing the processor's workload, ensuring the processor's performance requirements for processing actual user services, and improving the stability of the server system.
  • Figure 1 is a schematic diagram of a system hardware structure used in the system unrecoverable fault handling method provided in this application.
  • FIG. 2 is one of the flowcharts of the system unrecoverable fault handling method provided in this application.
  • FIG. 3 is a second flowchart of the system unrecoverable fault handling method provided in this application.
  • FIG. 4 is the third flowchart of the system unrecoverable fault handling method provided in this application.
  • FIG. 5 is the fourth flowchart of the system unrecoverable fault handling method provided in this application.
  • FIG. 6 is the fifth flowchart of the system unrecoverable fault handling method provided in this application.
  • Figure 7 is a schematic diagram of the interaction between the processor, BIOS and BMC in the system unrecoverable fault handling method provided in this application.
  • Figure 8 is one of the structural schematic diagrams of the unrecoverable fault handling system provided in this application.
  • Figure 9 is the second structural schematic diagram of the unrecoverable fault handling system provided in this application.
  • Figure 10 is a schematic diagram of the structure of the electronic device provided in this application.
  • FIG. 1 shows a schematic diagram of the OpenPower server hardware structure.
  • RAS Remote Assurance
  • the system hardware error checker detects an unrecoverable error, it sets the flag bit of the Fault Isolation Register (FIR).
  • FIR Fault Isolation Register
  • the BIOS detects the set flag bit, it triggers the on-chip controller (OCC) to collect fault data and save it to the system's shared memory (flash), and sends a fault check signal (i.e., a checkstop signal) to the Baseboard Management Controller (BMC).
  • OCC on-chip controller
  • BMC Baseboard Management Controller
  • the BIOS After the system warm restart, the BIOS reads and analyzes the fault data, generates a RAS record, and isolates the abnormal component based on the RAS record before triggering another system warm restart. Since the abnormal component has been isolated, it will not be restarted after the system warm restart, and the system can operate normally.
  • Both the on-chip controller's fault data collection and the BIOS's fault data analysis require processor (CPU) resources. Especially during the fault data collection phase, this increases the CPU workload and affects the processing performance of normal user services.
  • the system unrecoverable fault handling method of this application embodiment includes the following steps S210 to S230.
  • Step S210 After detecting a fault check signal, collect processor register data.
  • the fault check signal is sent to the BMC by the on-chip controller after detecting that the flag bit of the fault isolation register is set.
  • the system hardware error checker detects an unrecoverable error in the system, it sets the flag bit of the fault isolation register.
  • the BIOS detects that the flag bit of the fault isolation register is set, it triggers the on-chip controller OCC to send a fault check signal to the BMC, as shown in Figure 1, that is, the on-chip controller OCC pulls high the checkstop pin connected to the BMC.
  • the BMC detects that the checkstop pin is pulled high, it considers that a fault check signal has been detected and begins to collect processor register data. Because the processor registers record the status and address information of each device in the system, by collecting the processor register data, the status of each device can be obtained for subsequent analysis to determine whether it is a faulty device.
  • Step S220 Analyze the register data to obtain the location information of the faulty device.
  • the BMC can analyze whether the device is faulty based on the status of each device in the system recorded in the processor's registers, and can directly use the address information as the location information to obtain the location information of the faulty device.
  • Step S230 Trigger a system warm restart.
  • the location information is used to instruct the host BIOS to disable the corresponding faulty device based on the location information.
  • the BMC After collecting and analyzing the processor's register data, the BMC triggers a system warm restart, so that during the system warm restart, the BIOS disables the corresponding faulty device based on the location information to ensure that the server system can start normally.
  • the BMC collects and analyzes the processor's register data to obtain the location information of the faulty device.
  • a system warm restart is triggered, allowing the host-side BIOS to block the corresponding faulty device based on the location information during the restart process. That is, after detecting an unrecoverable system fault, the BMC collects and analyzes the processor's register data out of band.
  • the data collection and analysis process of the RAS detection function does not consume processor resources, greatly reducing the processor's workload, ensuring the processor's performance requirements for processing actual user services, and improving the stability of the server system.
  • the out-of-band collection and analysis of register data by the BMC avoids the problem in traditional solutions where an abnormality in the on-chip controller OCC itself prevents complete collection of fault data, leading to failed isolation of the faulty component.
  • system unrecoverable fault handling method in this embodiment is not limited to the OpenPower server system, but can also be used for other server systems.
  • step S210 includes: after detecting a fault check signal, collecting register data from registers in the register configuration table stored in the BMC, wherein the register configuration table contains configuration information of the processor's registers.
  • the register configuration table contains configuration information of the processor's registers.
  • I2C Inter-Integrated Circuit
  • FSI Field Replaceable Unit Service Interface
  • the processor's register data can be obtained through I2C and the FSI.
  • the register configuration table pre-stored in the BMC which contains configuration information of the processor's registers, allows the BMC to purposefully collect data from registers that record device status and addresses in the system, rather than collecting register data from all processors, thereby improving data collection efficiency.
  • the register data of the registers in the register configuration table stored in the BMC is collected, including the following steps S310 to S340.
  • Step S310 Obtain the configuration information from the register configuration table.
  • the configuration information includes: the register's offset address, access mode, CPU number, data length, output location, and register name.
  • the offset address uniquely identifies a register; the access mode specifies the register's access method (different registers have different access modes); the CPU number indicates which CPU the register belongs to; the data length is the length of the register value; and the output location is the directory where the obtained register value is saved.
  • the configuration information in the register configuration table is as follows.
  • OutputPath indicates the output location
  • rdmcinfo indicates the access mode
  • 1 indicates the CPU number
  • 0x123 indicates the offset address
  • 8 indicates the data length
  • mc1_status indicates the register name
  • MC1 indicates the variable of the register value
  • CpuBankInfo indicates the CPU's bank information.
  • Step S320 Determine the frame format according to the access method.
  • Different registers have different access methods. For example, registers that access basic CPU information use the ping access method, while registers that access CPU bank information use the rdmcinfo access method. Different access methods have different frame formats.
  • Step S330 Generate a data frame for accessing the processor according to the offset address of the register, the CPU number, and the data length in a framing format. Send the data frame to the processor as write data. The data frame instructs the processor, upon confirming that the CPU number matches its own, to read the register value of length equal to the data length from the register corresponding to the offset address and return the register value to the BMC.
  • a data frame composed according to the framing format corresponding to the rdmcinfo access method is: i2ctest w1@0x30 0x123 r8.
  • Step S340 Combine register names and register values into key-value pairs to form register data, generate an intermediate file based on the register data, and save the intermediate file to the specified storage path in the output location. For example: combine mc1_status and its corresponding register value, and mc1_addr and its corresponding register value to form register data.
  • the BMC can efficiently collect data from the RAS detection function through the above four steps.
  • the system unrecoverable fault handling method further includes: during a system warm restart, if a fault check signal is detected again, the processor register data is collected again, an intermediate file is generated again, and the newly generated intermediate file is merged with the previously generated intermediate file. For registers whose data was previously collected, only the previous register value is retained. If a fault check signal is detected again during a system warm restart, it indicates that the BIOS failed to successfully disable the faulty device, or that some register data was not collected during the first data collection due to I2C transmission issues. Therefore, during a system warm restart, if a fault check signal is detected again, the processor register data is collected again, and an intermediate file is generated again.
  • the collected register data better reflects the actual situation of the unrecoverable fault. Therefore, by comparing the intermediate files corresponding to the two data collections, for registers whose data was previously collected, only the previous register value is retained, i.e., the re-collected register value is discarded.
  • the method for handling unrecoverable system failures further includes deleting the first-generated intermediate file or the merged intermediate file after a system hot reboot is completed.
  • a system hot reboot indicates that the devices causing the unrecoverable system failure have been successfully masked. Deleting the first-generated intermediate file or the merged intermediate file prevents conflicts between the intermediate file obtained from the collected register data and the previous intermediate file during normal system operation, while also saving system flash memory space.
  • the system unrecoverable fault handling method further includes: if the number of system hot restarts exceeds the preset number of restarts and the system cannot be started, prompting that the system cannot be started, that is, prompting maintenance personnel that the faulty device cannot be blocked and manual troubleshooting is required.
  • step S220 is as shown in FIG4, including the following steps S410 to S420.
  • Step S410 Obtain the first target register value corresponding to the device status from the register data.
  • This first target register value represents the device status, and it can be used to determine whether the device is faulty.
  • BIOS engineers have developed a set of RAS diagnostic rules based on the characteristics of RAS faults. For example, they can infer whether the CPU error or memory error is caused by using the CPU bank status information in the RAS.
  • Step S420 If the first target register value represents the fault status, obtain the second target register value corresponding to the device address.
  • the second target register value is the address information of the faulty device, and the address information is used as the location information.
  • the register value corresponding to register mc1_status represents the device status
  • the register value corresponding to register mc1_addr corresponds to the device address information, thus the address information of the faulty device can be obtained.
  • the BMC can quickly obtain the address information of the faulty device by parsing the register values representing the device status and device address in the register data, and directly use the address information as the location information, so that the BIOS can block the corresponding faulty device according to the address information.
  • step S220 is as shown in FIG5, including the following steps S510 to S540.
  • Step S510 Obtain the first target register value in the register data whose register name corresponds to the device status.
  • Step S520 If the first target register value represents the fault state, obtain the second target register value corresponding to the device address whose register name is the second target register value.
  • the second target register value is the address information of the faulty device.
  • Step S530 Determine the type of faulty device based on the asset information stored in the BMC.
  • the asset information includes the addresses, types, and identifiers of all devices in the system, which are automatically loaded into the BMC during system startup.
  • Step S540 If the faulty device is a PCIe device, the address information of the faulty device is converted into its device identifier based on the conversion relationship between the device address information and device identifier recorded in the asset information. This device identifier is then used as the location information.
  • the device identifier is BDF (Bus, Device, Function). The system typically uses BDF to locate and access PCIe devices. Therefore, if the faulty device is a PCIe device, the BMC converts the address information of the faulty device into its device identifier based on the conversion relationship between the device address information and device identifier recorded in the asset information. The BIOS can then directly use this device identifier to block the corresponding PCIe device, avoiding the need to convert address information and device identifier in the BIOS and reducing processor resource consumption.
  • BDF Bus, Device, Function
  • the method before triggering a system warm restart, the method further includes: generating a fault analysis table based on the location information of the faulty device; and sending the fault analysis table to a shared memory for storage, so that the host BIOS can retrieve the fault analysis table from the shared memory during the system warm restart process.
  • the shared memory is a flash memory, which can also save data during system restart, so that the BIOS can also retrieve the fault analysis table after restart.
  • the fault analysis table can be generated according to a predetermined format based on the location information of the faulty device. For example, the location information of each faulty device is separated by a special symbol, and the BIOS parses the fault analysis table according to the predetermined format to obtain the location information of each faulty device.
  • the steps for generating a fault analysis table based on the location information of the faulty device are as follows: All currently analyzed faulty devices are considered target faulty devices. For each target faulty device, the number of times it has failed in the historical fault analysis table is counted, and the frequency is used as the priority for each target faulty device. In the currently generated fault analysis table, the corresponding location information is arranged according to the priority of the target faulty device; that is, location information with higher priority is listed first, and location information with lower priority is listed last. When the BIOS reads the fault analysis table, the faulty device corresponding to the location information read first has a higher priority and is prioritized for blocking, avoiding system crashes or other device failures caused by untimely blocking.
  • the system unrecoverable fault handling method of this application embodiment is applied to the BIOS on the host side and includes the following steps S610 to S630.
  • Step S610 Monitor the status of the flag bit of the fault isolation register.
  • the flag bit of the fault isolation register is set, and the BIOS monitors the status of the flag bit of the fault isolation register.
  • Step S620 When the flag bit of the fault isolation register is set, the on-chip controller is triggered to send a fault check signal to the BMC.
  • the fault check signal is used to instruct the BMC to collect and analyze the processor's register data to obtain the location information of the faulty device and trigger a system hot restart.
  • Step S630 During the system hot restart process, the corresponding faulty device is blocked according to the location information.
  • the BIOS on the host side detects the system unrecoverable fault, it triggers the BMC to collect and analyze the processor's register data out of band.
  • the data collection and analysis process does not occupy processor resources, which greatly reduces the processor's workload, ensures the processor's performance requirements for processing real user services, and improves the stability of the server system.
  • step S620 includes: triggering the execution of an interrupt function corresponding to an unrecoverable system fault when the flag bit of the fault isolation register is set; and triggering the on-chip controller to send a fault check signal to the BMC during the execution of the interrupt function.
  • the fault isolation register is configured as an interrupt source during BIOS startup.
  • An interrupt handler function is triggered when the fault isolation register becomes abnormal. This interrupt function implements the function of triggering the on-chip controller to send a fault check signal to the BMC, ensuring that a fault check signal is communicated to the BMC when each unrecoverable fault is detected in real time, enabling the BMC to promptly perform the corresponding data collection and analysis process.
  • step S630 includes: during a system hot restart, the BIOS retrieves a fault analysis table from shared memory, the fault analysis table being generated by the BMC based on the location information of the faulty device; the BIOS parses the location information from the fault analysis table and masks the corresponding faulty device based on the location information.
  • the fault analysis table can be parsed according to the format corresponding to the generated fault analysis table, for example: the location information of each faulty device is separated by special symbols, and the BIOS parses the location information of each faulty device by recognizing the special symbols when parsing the fault analysis table.
  • the BIOS detects a fault, specifically by detecting that the flag bit of the fault isolation register is set. This triggers the on-chip controller (OCC) to send a fault check signal to the BMC. Upon receiving this signal, the BMC performs a data collection operation, collecting CPU register data. After data collection, the BMC analyzes the register data to obtain the location information of the faulty device. Based on this location information, it generates a fault analysis table and stores it in the system's shared memory for the BIOS to access. Subsequently, a system warm reboot is triggered. During the system warm reboot, the BIOS locates the faulty device based on the location information in the fault analysis table and disables it.
  • OCC on-chip controller
  • the function of collecting and analyzing CPU register data is performed by the out-of-band BMC.
  • the BIOS only calls CPU resources when the fault is detected and the faulty device is finally disabled. Moreover, the faulty device is disabled during the hot restart process. Therefore, the system unrecoverable fault handling method in this embodiment greatly reduces the processor's workload, ensures the processor's performance requirements for processing real user services, and improves the stability of the server system.
  • the system unrecoverable fault handling apparatus provided in this application is described below.
  • the system unrecoverable fault handling apparatus described below can be referred to in correspondence with the system unrecoverable fault handling method described above.
  • This application also provides a system unrecoverable fault handling device, as shown in FIG8, which is applied to BMC and includes the following modules.
  • the data collection module 810 is configured to collect processor register data after a fault check signal is detected.
  • the fault check signal is sent to the BMC by the on-chip controller after it detects that the flag bit of the fault isolation register is set.
  • the data analysis module 820 is configured to analyze register data to obtain the location information of the faulty device.
  • the restart trigger module 830 is set to trigger a system hot restart.
  • the location information is used to instruct the host BIOS to disable the corresponding faulty device according to the location information.
  • the register data of the processor is collected and analyzed out-of-band by the BMC.
  • the data collection and analysis process does not occupy processor resources, which greatly reduces the workload of the processor, ensures the processor's performance requirements for processing real user services, and improves the stability of the server system.
  • the data collection module 810 is configured to collect register data from registers in the register configuration table stored in the BMC after detecting a fault check signal.
  • the register configuration table contains configuration information of the processor's registers.
  • the data collection module 810 includes the following modules.
  • the configuration information acquisition module is configured to acquire configuration information from the register configuration table.
  • the configuration information includes: register offset address, access mode, CPU number, data length, output location, and register name.
  • the frame format determination module is configured to determine the frame format based on the access method.
  • the data frame generation module is configured to generate a data frame for accessing the processor according to the offset address of the register, the CPU number and the data length in a framing format, and send the data frame to the processor as write data.
  • the data frame is used to instruct the processor to read the register value with a length equal to the data length from the register corresponding to the offset address, and return the register value to the BMC, provided that the CPU number is the same as its own number.
  • the intermediate file generation module is configured to combine register names and register values into key-value pairs to form register data, generate intermediate files based on the register data, and write the intermediate files to the specified storage path in the output location for saving.
  • system unrecoverable fault handling device further includes: an intermediate file merging module, configured to, during the system hot restart process, if a fault check signal is detected again, collect the processor register data again, generate an intermediate file again, merge the regenerated intermediate file with the previously generated intermediate file, and for registers whose data has been collected previously, retain only the previous register value.
  • an intermediate file merging module configured to, during the system hot restart process, if a fault check signal is detected again, collect the processor register data again, generate an intermediate file again, merge the regenerated intermediate file with the previously generated intermediate file, and for registers whose data has been collected previously, retain only the previous register value.
  • system unrecoverable fault handling apparatus further includes: an intermediate file deletion module, configured to delete the first generated intermediate file or the merged intermediate file after the system hot restart is completed.
  • the system unrecoverable fault handling device further includes: a restart count limit module, which is configured to prompt that the system cannot start if the number of system hot restarts exceeds a preset number of restarts and the system cannot start.
  • the data analysis module 820 includes the following modules.
  • the first target register value acquisition module is configured to acquire the first target register value whose register name in the register data corresponds to the device status.
  • the second target register value acquisition module is configured to acquire the second target register value corresponding to the device address when the first target register value represents the fault state.
  • the second target register value is the address information of the faulty device, and the address information is determined as the location information.
  • the data analysis module 820 includes the following modules.
  • the first target register value acquisition module is configured to acquire the first target register value whose register name in the register data corresponds to the device status.
  • the second target register value acquisition module is configured to acquire the second target register value corresponding to the device address when the first target register value represents the fault state.
  • the second target register value is the address information of the faulty device.
  • the equipment type determination module is configured to determine the type of faulty equipment based on the asset information stored in the BMC.
  • the device identifier conversion module is configured to convert the address information of the faulty device into the device identifier of the faulty device based on the conversion relationship between the device address information and the device identifier recorded in the asset information when the faulty device is of PCIe type, and determine the device identifier as location information.
  • system unrecoverable fault handling apparatus further includes the following modules.
  • the fault analysis table generation module is configured to generate a fault analysis table based on the location information of the faulty device before triggering a system hot restart.
  • the fault analysis table storage module is configured to send the fault analysis table to shared memory for storage, so that the host BIOS can retrieve the fault analysis table from the shared memory during a system hot restart.
  • This application embodiment also provides a system unrecoverable fault handling device, as shown in FIG9, which is applied to the BIOS on the host side.
  • the device includes the following modules.
  • the fault detection module 910 is configured to monitor the status of the flag bit of the fault isolation register.
  • the fault check signal sending module 920 is configured to trigger the on-chip controller to send a fault check signal to the BMC when the flag bit of the fault isolation register is set.
  • the fault check signal is used to instruct the BMC to collect and analyze the processor's register data to obtain the location information of the faulty device and trigger a system hot restart.
  • the fault device shielding module 930 is configured to shield the corresponding fault device based on the location information during system hot restart.
  • the BIOS on the host side detects an unrecoverable system fault, it triggers the BMC to collect and analyze the processor's register data out of band.
  • the data collection and analysis process does not occupy processor resources, greatly reducing the processor's workload, ensuring the processor's performance requirements for processing real user services, and improving the stability of the server system.
  • the fault check signal sending module 920 is configured to trigger the execution of an interrupt function corresponding to an unrecoverable system fault when the flag bit of the fault isolation register is set; during the execution of the interrupt function, the on-chip controller is triggered to send a fault check signal to the BMC.
  • the fault device shielding module 930 is configured to retrieve a fault analysis table from the shared memory during a system hot restart.
  • the fault analysis table is generated by the BMC based on the location information of the fault device.
  • the location information is parsed from the fault analysis table, and the corresponding fault device is shielded based on the location information.
  • Figure 10 illustrates a schematic diagram of the physical structure of an electronic device.
  • the electronic device may include: a processor 1010, a communications interface 1020, a memory 1030, and a communication bus 1040.
  • the processor 1010, communications interface 1020, and memory 1030 communicate with each other via the communication bus 1040.
  • the processor 1010 can call logical instructions in the memory 1030 to execute a system unrecoverable fault handling method for the BMC.
  • This method includes: collecting register data from the processor after detecting a fault check signal, the fault check signal being sent to the BMC by the on-chip controller after detecting that the flag bit of the fault isolation register is set; analyzing the register data to obtain the location information of the faulty device; and triggering a system warm restart.
  • the location information is used to instruct the host BIOS to disable the corresponding faulty device based on the location information.
  • a system unrecoverable fault handling method for the host-side BIOS may be executed, comprising: monitoring the status of the flag bit of the fault isolation register; if the flag bit of the fault isolation register is set, triggering the on-chip controller to send a fault check signal to the BMC, the fault check signal being used to instruct the BMC to collect and analyze the processor's register data to obtain the location information of the faulty device, and triggering a system hot restart; during the system hot restart, shielding the corresponding faulty device according to the location information.
  • the logical instructions in the aforementioned memory 1030 can be implemented as software functional units and sold or used as independent products, they can be stored in a non-transitory computer-readable storage medium.
  • This computer software product is stored in a non-transitory readable storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods in the various embodiments of this application.
  • the aforementioned non-transitory readable storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
  • this application also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium.
  • the computer program When the computer program is executed by a processor, the computer can execute the system unrecoverable fault handling method for BMC provided by the above methods.
  • the method includes: collecting register data of the processor after detecting a fault check signal, wherein the fault check signal is sent to the BMC by the on-chip controller after detecting that the flag bit of the fault isolation register is set; analyzing the register data to obtain the location information of the faulty device; and triggering a system hot restart, wherein during the system hot restart, the location information is used to instruct the host BIOS to shield the corresponding faulty device according to the location information.
  • a system unrecoverable fault handling method for the host-side BIOS may be executed, comprising: monitoring the status of the flag bit of the fault isolation register; if the flag bit of the fault isolation register is set, triggering the on-chip controller to send a fault check signal to the BMC, the fault check signal being used to instruct the BMC to collect and analyze the processor's register data to obtain the location information of the faulty device, and triggering a system hot restart; during the system hot restart, shielding the corresponding faulty device according to the location information.
  • this application also provides a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, is implemented to perform the system unrecoverable fault handling method for BMC provided by the above methods.
  • the method includes: collecting register data of the processor after detecting a fault check signal, the fault check signal being sent to the BMC by the on-chip controller after detecting that the flag bit of the fault isolation register is set; analyzing the register data to obtain the location information of the faulty device; and triggering a system hot restart, during which the location information is used to instruct the host BIOS to shield the corresponding faulty device according to the location information.
  • a system unrecoverable fault handling method for the host-side BIOS may be executed, comprising: monitoring the status of the flag bit of the fault isolation register; if the flag bit of the fault isolation register is set, triggering the on-chip controller to send a fault check signal to the BMC, the fault check signal being used to instruct the BMC to collect and analyze the processor's register data to obtain the location information of the faulty device, and triggering a system hot restart; during the system hot restart, shielding the corresponding faulty device according to the location information.
  • the device embodiments described above are merely illustrative.
  • the units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.
  • each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware.
  • This computer software product can be stored in a non-transitory computer-readable storage medium, such as ROM/RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods of various embodiments or some parts of the embodiments.

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Abstract

本申请涉及计算机技术领域，提供一种系统不可恢复故障处理方法、装置、电子设备及非暂态可读存储介质，该方法应用于BMC，包括：在检测到故障检查信号后收集处理器的寄存器数据，故障检查信号是片上控制器在检测到故障隔离寄存器的标识位被置位后发送至BMC的；分析寄存器数据，以得到故障设备的定位信息；触发系统热重启，在系统热重启过程中，定位信息用于指示主机BIOS根据所述定位信息屏蔽对应的故障设备。本申请中，在检测到系统不可恢复故障后，通过BMC带外收集并分析处理器的寄存器数据，数据收集和分析过程不会占用处理器资源，大大减轻了处理器的工作负载，保证了处理器对真正的用户业务的处理性能需求，提高了服务器系统的稳定性。

Description

系统不可恢复故障处理方法、装置、电子设备及存储介质
相关申请的交叉引用
本申请要求于2024年06月26日提交中国专利局，申请号为2024108319964，申请名称为“系统不可恢复故障处理方法、装置、电子设备及存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及计算机技术领域，尤其涉及一种系统不可恢复故障处理方法、装置、电子设备及非暂态可读存储介质。
背景技术
对于传统的服务器架构中，例如：OpenPower架构服务器，对于RAS(可靠性Reliability、可用性Availability和可维护性Serviceability)功能(包括故障诊断和内存告警检测等故障处理过程)的实现均是由主机端的BIOS(Basic Input/Output System，基本输入输出系统)以及片上控制器(On-chip Controller，OCC)调用处理器(CPU(Central Processing Unit，中央处理器))资源完成的。即传统OpenPower架构服务器中，对不可恢复的故障处理(故障收集、分析及生成相应记录)的整个过程都是由主机端完成的，在服务器系统发生不可恢复的错误后，片上控制器收集故障数据、分析故障数据以及生成结果记录需要花费不少处理器资源，导致处理器工作负载较高，影响处理器对真正的用户业务的处理性能。
发明内容
本申请提供一种系统不可恢复故障处理方法、装置、电子设备及非暂态可读存储介质，用以解决现有技术的系统不可恢复故障处理方法中，处理器工作负载较高，影响处理器对真正的用户业务的处理性能的问题。
本申请提供一种系统不可恢复故障处理方法，应用于BMC(Baseboard Management Controller，基板管理控制器)，包括以下步骤。
在检测到故障检查信号后收集处理器的寄存器数据，故障检查信号是片上控制器在检测到故障隔离寄存器的标识位被置位后发送至BMC的。
分析寄存器数据，以得到故障设备的定位信息。
触发系统热重启，在系统热重启过程中，定位信息用于指示主机BIOS根据定位信息屏蔽对应的故障设备。
根据本申请提供的一种系统不可恢复故障处理方法，在检测到故障检查信号后收集处理器的寄存器数据，包括：在检测到故障检查信号后，根据BMC中存储的寄存器配置表收集寄存器配置表中寄存器的寄存器数据，寄存器配置表中配置了处理器的寄存器的配置信息。
根据本申请提供的一种系统不可恢复故障处理方法，根据BMC中存储的寄存器配置表收集寄存器配置表中寄存器的寄存器数据，包括以下步骤。
获取寄存器配置表中的配置信息，配置信息包括：寄存器的偏移地址、访问方式、CPU编号、数据长度、输出位置和寄存器名称。
根据访问方式确定组帧格式。
根据寄存器的偏移地址、CPU编号和数据长度按组帧格式生成用于访问处理器的数据帧，并将数据帧作为处理器的写入数据发送至处理器，数据帧用于指示处理器在确认CPU编号与自身的编号相同的情况下，读取偏移地址对应的寄存器中长度等于数据长度的寄存器值，并将寄存器值返回至BMC。
将寄存器名称和寄存器值以键值对的形式组成寄存器数据，并根据寄存器数据生成中间文件，将中间文件写入输出位置指定存储路径保存。
根据本申请提供的一种系统不可恢复故障处理方法，还包括：在系统热重启的过程中，若再次检测到故障检查信号，则再次收集处理器的寄存器数据，再次生成中间文件，将再次生成的中间文件与上一次生成的中间文件合并，且对于上一次已收集过数据的寄存器，对应的寄存器值只保留上一次的寄存器值。
根据本申请提供的一种系统不可恢复故障处理方法，在系统热重启完成之后，还包括：删除第一次生成的中间文件或合并后的中间文件。
根据本申请提供的一种系统不可恢复故障处理方法，还包括：在系统热重启次数超过预设重启次数，且无法完成系统启动的情况下，提示系统无法启动。
根据本申请提供的一种系统不可恢复故障处理方法，还包括：片上控制器拉高与BMC相连接的checkstop引脚，BMC检测到checkstop引脚被拉高后，认为是检测到故障检查信号；BMC通过I2C和可替换单元接口获取处理器的寄存器数据。
根据本申请提供的一种系统不可恢复故障处理方法，分析寄存器数据，以得到故障设备的定位信息，包括以下步骤。
获取寄存器数据中的寄存器名称为设备状态对应的第一目标寄存器值。
在第一目标寄存器值表征故障状态的情况下，获取寄存器名称为设备地址对应的第二目标寄存器值，第二目标寄存器值为故障设备的地址信息，确定地址信息作为定位信息。
根据本申请提供的一种系统不可恢复故障处理方法，分析寄存器数据，以得到故障设备的定位信息，包括以下步骤。
获取寄存器数据中的寄存器名称为设备状态对应的第一目标寄存器值。
在第一目标寄存器值表征故障状态的情况下，获取寄存器名称为设备地址对应的第二目标寄存器值，第二目标寄存器值为故障设备的地址信息。
根据BMC中存储的资产信息，确定故障设备的类型。
在故障设备的类型为PCIe(Peripheral Component Interconnect Express，一种高速串行计算机扩展总线标准)设备类型的情况下，根据资产信息中记录的设备的地址信息和设备标识符的转换关系，将故障设备的地址信息转换成故障设备的设备标识符，确定设备标识符为定位信息。
根据本申请提供的一种系统不可恢复故障处理方法，在触发系统热重启之前，还包括以下步骤。
根据故障设备的定位信息生成故障分析表。
将故障分析表发送至共享存储器中存储，使得在系统热重启过程中，主机BIOS从共享存储器中获取故障分析表。
根据本申请提供的一种系统不可恢复故障处理方法，根据故障设备的定位信息生成故障分析表，包括以下步骤：
统计历史故障分析表中目标故障设备发生故障的次数，其中，目标故障设备为当前分析出的故障设备；
按照次数大小作为每一个目标故障设备的优先级；
按照目标故障设备的优先级排列对应的定位信息，得到故障分析表。
本申请还提供一种系统不可恢复故障处理方法，应用于主机侧的BIOS，包括以下步骤。
监测故障隔离寄存器的标识位的状态。
在故障隔离寄存器的标识位被置位的情况下，触发片上控制器发送故障检查信号至BMC，故障检查信号用于指示BMC收集并分析处理器的寄存器数据，以得到故障设备的定位信息，并触发系统热重启。
在系统热重启过程中，根据定位信息屏蔽对应的故障设备。
本申请还提供一种系统不可恢复故障处理方法，在故障隔离寄存器的标识位被置位的情况下，触发片上控制器发送故障检查信号至BMC，包括以下步骤。
在故障隔离寄存器的标识位被置位的情况下，触发执行系统不可恢复故障对应的中断函数。
在中断函数执行时，触发片上控制器发送故障检查信号至BMC。
本申请还提供一种系统不可恢复故障处理方法，在系统热重启过程中，根据定位信息屏蔽对应的故障设备，包括以下步骤。
在系统热重启过程中，从共享存储器中获取故障分析表，故障分析表是BMC根据故障设备的定位信息生成的。
从故障分析表中解析出定位信息，并根据定位信息屏蔽对应的故障设备。
本申请还提供一种系统不可恢复故障处理方法，从故障分析表中解析出定位信息，还包括：通过特殊符号从故障分析表中识别出每个故障设备的定位信息，其中，定位信息在故障分析表中通过特殊符号分隔。
本申请还提供一种系统不可恢复故障处理方法，还包括：片上控制器拉高与BMC相连接的checkstop引脚，BMC检测到checkstop引脚被拉高后，认为是检测到故障检查信号；BMC通过I2C和可替换单元接口获取处理器的寄存器数据。
本申请还提供一种系统不可恢复故障处理装置，应用于BMC，包括以下模块。
数据收集模块，被设置为在检测到故障检查信号后收集处理器的寄存器数据，故障检查信号是片上控制器在检测到故障隔离寄存器的标识位被置位后发送至BMC的。
数据分析模块，被设置为分析寄存器数据，以得到故障设备的定位信息。
重启触发模块，被设置为触发系统热重启，在系统热重启过程中，定位信息用于指示主机BIOS根据定位信息屏蔽对应的故障设备。
本申请还提供一种系统不可恢复故障处理装置，应用于主机侧的BIOS，包括以下模块。
故障检测模块，被设置为监测故障隔离寄存器的标识位的状态。
故障检查信号发送模块，被设置为在故障隔离寄存器的标识位被置位的情况下，触发片上控制器发送故障检查信号至BMC，故障检查信号用于指示BMC收集并分析处理器的寄存器数据，以得到故障设备的定位信息，并触发系统热重启。
故障设备屏蔽模块，被设置为在系统热重启过程中，根据定位信息屏蔽对应的故障设备。
本申请还提供一种电子设备，包括存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，处理器执行程序时实现如上述任一种应用于BMC的系统不可恢复故障处理方法，或实现如上述任一种应用于主机侧的BIOS的系统不可恢复故障处理方法。
本申请还提供一种非暂态计算机可读存储介质，其上存储有计算机程序，该计算机程序被处理器执行时实现如上述任一种应用于BMC的系统不可恢复故障处理方法，或实现如上述任一种应用于主机侧的BIOS的系统不可恢复故障处理方法。
本申请提供的系统不可恢复故障处理方法、装置、电子设备及非暂态可读存储介质，通过在检测到故障检查信号后，由BMC收集处理器的寄存器数据，故障检查信号是片上控制器在检测到故障隔离寄存器的标识位被置位后发送至BMC的；且由BMC分析寄存器数据，以得到故障设备的定位信息；触发系统热重启，在系统热重启过程中，定位信息用于指示主机BIOS根据定位信息屏蔽对应的故障设备。本申请中，在检测到系统不可恢复故障后，通过BMC带外收集并分析处理器的寄存器数据，数据收集和分析过程不会占用处理器资源，大大减轻了处理器的工作负载，保证了处理器对真正的用户业务的处理性能需求，提高了服务器系统的稳定性。
附图说明
为了更清楚地说明本申请或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请提供的系统不可恢复故障处理方法中采用的一种系统硬件结构示意图。
图2是本申请提供的系统不可恢复故障处理方法的流程示意图之一。
图3是本申请提供的系统不可恢复故障处理方法的流程示意图之二。
图4是本申请提供的系统不可恢复故障处理方法的流程示意图之三。
图5是本申请提供的系统不可恢复故障处理方法的流程示意图之四。
图6是本申请提供的系统不可恢复故障处理方法的流程示意图之五。
图7是本申请提供的系统不可恢复故障处理方法中处理器、BIOS和BMC三者的交互示意图。
图8是本申请提供的系统不可恢复故障处理系统的结构示意图之一。
图9是本申请提供的系统不可恢复故障处理系统的结构示意图之二。
图10是本申请提供的电子设备的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合本申请中的附图，对本申请中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
如图1所示，为openpower服务器硬件结构示意图，对于传统的RAS检测功能，当系统硬件错误检查器检测到系统的不可恢复的错误时，置位故障隔离寄存器(FIR，Fault Isolation Register)的标识位，BIOS检测到故障隔离寄存器的标识位被置位后，触发片上控制器OCC收集故障数据并保存到系统的共享存储器(flash)中，并发出故障检查信号(即checkstop信号)至基板管理控制器(Baseboard Management Controller，BMC)。当BMC检测到checkstop信号后触发系统热重启。系统热重启后BIOS会读取并分析故障数据，生成RAS记录，并根据RAS记录去隔离异常部件，之后再触发系统热重启。由于异常部件已经被隔离，系统热重启后该异常部件不会再被启动，系统就能正常运行了。无论是片上控制器的故障数据收集，还是BIOS故障数据分析都需要占用处理器(CPU)资源，尤其是在故障数据收集阶段，会增加CPU的工作负载，影响正常的真正的用户业务的处理性能。
基于上述技术问题，本申请实施例的系统不可恢复故障处理方法，如图1和2所示，包括以下步骤S210至S230。
步骤S210：在检测到故障检查信号后收集处理器的寄存器数据，故障检查信号是片上控制器在检测到故障隔离寄存器的标识位被置位后发送至BMC的。可选的，在服务器系统运行过程中，当系统硬件错误检查器检测到系统的不可恢复的错误时，置位故障隔离寄存器的标识位，BIOS检测到故障隔离寄存器的标识位被置位后，触发片上控制器OCC将故障检查信号发送至BMC，如图1所示，即片上控制器OCC拉高与BMC相连接的checkstop引脚。BMC检测到checkstop引脚被拉高后，即认为是检测到故障检查信号，便开始收集处理器的寄存器数据，因为处理器的寄存器中记录了系统中各设备的状态及地址信息，通过收集处理器的寄存器数据可以获取到各设备的状态，以便后续分析是否为故障设备。
步骤S220：分析寄存器数据，以得到故障设备的定位信息，可选的，BMC可根据处理器的寄存器中记录了系统中各设备的状态分析设备是否故障，可直接将地址信息作为定位信息，从而得到故障设备的定位信息。
步骤S230：触发系统热重启，在系统热重启过程中，定位信息用于指示主机BIOS根据定位信息屏蔽对应的故障设备。BMC在收集和分析完处理器的寄存器数据后便触发系统热重启，使得在系统热重启过程中，BIOS根据定位信息屏蔽对应的故障设备，以保证服务器系统能够正常启动。
本实施例的系统不可恢复故障处理方法中，由BMC收集处理器的寄存器数据，且由BMC分析寄存器数据，以得到故障设备的定位信息；触发系统热重启，使得在系统热重启过程中，主机侧的BIOS根据定位信息屏蔽对应的故障设备。即在检测到系统不可恢复故障后，通过BMC带外收集并分析处理器的寄存器数据，RAS检测功能的数据收集和分析过程不会占用处理器资源，大大减轻了处理器的工作负载，保证了处理器对真正的用户业务的处理性能需求，提高了服务器系统的稳定性。另外，由BMC带外收集和分析寄存器数据，避免了传统方案中，片上控制器OCC本身异常使得故障数据无法完全收集成功，而导致的故障部件隔离失败的问题。
需要说明的是：本实施例的系统不可恢复故障处理方法并不限于应用于openpower服务器系统，也可以用于其它服务器系统。
在一些实施例中，步骤S210包括：在检测到故障检查信号后，根据BMC中存储的寄存器配置表收集寄存器配置表中寄存器的寄存器数据，寄存器配置表中配置了处理器的寄存器的配置信息。如图1所示，由于BMC属于带外设备，需要通过I2C(Inter-Integrated Circuit，互连集成电路)以及可替换单元接口(Field Replaceable Unit Service Interface，FSI)与处理器交互，本实施例中，可通过I2C和可替换单元接口获取处理器的寄存器数据。而且预先在BMC中存储的寄存器配置表，寄存器配置表中配置了处理器的寄存器的配置信息，使得BMC有目的的收集记录系统中设备状态和地址的寄存器的数据，而不是收集所有处理器的寄存器数据，从而提高数据收集效率。
在一些实施例中，如图3所示，根据BMC中存储的寄存器配置表收集寄存器配置表中寄存器的寄存器数据，包括以下步骤S310至S340。
步骤S310：获取寄存器配置表中的配置信息，配置信息包括：寄存器的偏移地址、访问方式、CPU编号、数据长度、输出位置和寄存器名称。其中，偏移地址可以唯一定位一个寄存器，访问方式为寄存器的访问方式，不同寄存器有不同的访问方式，CPU编号表示寄存器属于哪个CPU，数据长度为寄存器值的长度，输出位置为获取的寄存器值的保存位置目录。例如：寄存器配置表中的配置信息如下。
"OutputPath":"Collection_data/cpu％d_bankinfo"。
"rdmcinfo":"CpuBankInfo"。
{"Params":["Target",1,"0x123",8],"Output":{"Size":8,"Name":["mc1_status","MC1"]}}。
{"Params":["Target",1,"0x124",8],"Output":{"Size":8,"Name":["mc1_addr","MC1"]}}。
{"Params":["Target",1,"0x125",8],"Output":{"Size":8,"Name":["mc1_misc","MC1"]}}。
{"Params":["Target",2,"0x123",8],"Output":{"Size":8,"Name":["mc2_status","MC2"]}}。
{"Params":["Target",2,"0x124",8],"Output":{"Size":8,"Name":["mc2_addr","MC2"]}}。
{"Params":["Target",2,"0x125",8],"Output":{"Size":8,"Name":["mc2_misc","MC2"]}}。
其中，OutputPath表示输出位置，rdmcinfo表示访问方式，1表示CPU编号，0x123表示偏移地址，8表示数据长度，mc1_status表示寄存器名称，MC1表示寄存器值的变量，CpuBankInfo表示CPU的bank信息。
步骤S320：根据访问方式确定组帧格式，不同的寄存器具有不同访问方式，例如：访问CPU基础信息的寄存器采用ping访问方式，访问CPU的bank信息相关的寄存器采用rdmcinfo访问方式，不同的访问方式具有不同的组帧格式。
步骤S330：根据寄存器的偏移地址、CPU编号和数据长度按组帧格式生成用于访问处理器的数据帧，并将数据帧作为处理器的写入数据发送至处理器，数据帧用于指示处理器在确认CPU编号与自身的编号相同的情况下，读取偏移地址对应的寄存器中长度等于数据长度的寄存器值，并将寄存器值返回至BMC。可选的，以访问CPU的bank信息相关的寄存器为例，按rdmcinfo访问方式对应的组帧格式组成的数据帧为：i2ctest w1@0x30 0x123 r8，表示通过I2C将数据帧写(w)CPU编号为1，地址为0x30的CPU，使其读取地址偏移为0x123的寄存器，读取(r)的数据长度为8的寄存器值，该寄存器值对应寄存器名称为mc1_status，mc1_status表示设备状态。同理也可以获取到寄存器名称为mc1_addr的寄存器值，mc1_addr表示设备地址信息。
步骤S340：将寄存器名称和寄存器值以键值对的形式组成寄存器数据，并根据寄存器数据生成中间文件，将中间文件写入输出位置指定存储路径保存。例如：将mc1_status和对应的寄存器值，以及mc1_addr和对应的寄存器值组成寄存器数据。
本实施例中，在寄存器配置表的基础上通过上述四个步骤，BMC可以高效地收集RAS检测功能的数据收集过程。
在一些实施例中，系统不可恢复故障处理方法还包括：在系统热重启的过程中，若再次检测到故障检查信号，则再次收集处理器的寄存器数据，再次生成中间文件，将再次生成的中间文件与上一次生成的中间文件合并，且对于上一次已收集过数据的寄存器，对应的寄存器值只保留上一次的寄存器值。系统热重启的过程中，若再次检测到故障检查信号，说明BIOS对故障设备的屏蔽不成功，也有可能是第一次数据收集由于I2C传输原因一些寄存器数据未收集到，因此，在系统热重启的过程中，若再次检测到故障检查信号，则再次收集处理器的寄存器数据，再次生成中间文件。对于上一次已收集过数据的寄存器，由于上一次收集的寄存器数据距离第一次发生不可恢复故障的时间比较近，收集的寄存器数据更能够反映发生不可恢复故障的实际情况，因此，通过对两次数据收集对应的中间文件比较，对于上一次已收集过数据的寄存器，对应的寄存器值只保留上一次的寄存器值，即丢弃再次收集的寄存器值。
在一些实施例中，系统不可恢复故障处理方法还包括：在系统热重启完成之后，删除第一次生成的中间文件或合并后的中间文件。本实施例中，系统热重启完成说明导致系统不可恢复故障的设备已经都成功屏蔽，删除第一次生成的中间文件或合并后的中间文件，避免在系统正常运行过程中，再次发生不可恢复故障收集的寄存器数据得到中间文件与之前的中间文件冲突，同时也节省系统的flash内存空间。
在一些实施例中，系统不可恢复故障处理方法还包括：在系统热重启次数超过预设重启次数，且无法完成系统启动的情况下，提示系统无法启动，即提示维护人员无法屏蔽掉故障设备，需要人为排查故障。
在一些实施例中，步骤S220流程如图4所示，包括以下步骤S410至S420。
步骤S410：获取寄存器数据中的寄存器名称为设备状态对应的第一目标寄存器值，该第一目标寄存器值表征设备状态，可以识别该第一目标寄存器值判断设备是否故障。对于RAS故障，根据RAS故障特点BIOS工程师梳理出一套RAS诊断规则，例如：通过RAS中CPU bank状态信息来推断CPU错误还是内存错误。
步骤S420：在第一目标寄存器值表征故障状态的情况下，获取寄存器名称为设备地址对应的第二目标寄存器值，第二目标寄存器值为故障设备的地址信息，确定地址信息作为定位信息。例如：寄存器mc1_status对应的寄存器值表示设备状态，mc1_addr对应的寄存器值对应设备的地址信息，从而可以得到故障设备的地址信息。
本实施例中，BMC通过解析寄存器数据中表示设备状态和设备地址的寄存器值，可以快捷地获取故障设备的地址信息，而且直接将地址信息作为定位信息，使得BIOS可以根据地址信息屏蔽相应的故障设备。
在一些实施例中，步骤S220流程如图5所示，包括以下步骤S510至S540。
步骤S510：获取寄存器数据中的寄存器名称为设备状态对应的第一目标寄存器值。
步骤S520：在第一目标寄存器值表征故障状态的情况下，获取寄存器名称为设备地址对应的第二目标寄存器值，第二目标寄存器值为故障设备的地址信息。
步骤S530：根据BMC中存储的资产信息，确定故障设备的类型。可选的，资产信息包括系统中所有设备的地址、类型及标识符等信息，在开机启动时，系统会自动加载到BMC中。
步骤S540：在故障设备的类型为PCIe设备类型的情况下，根据资产信息中记录的设备的地址信息和设备标识符的转换关系，将故障设备的地址信息转换成故障设备的设备标识符，确定设备标识符为定位信息。其中，对于PCIe设备，设备标识符为BDF(Bus、Device、Function)，系统通常是通过BDF去定位并访问PCIe设备，因此，若故障设备为PCIe设备，BMC根据资产信息中记录的设备的地址信息和设备标识符的转换关系，将故障设备的地址信息转换成故障设备的设备标识符，BIOS可直接通过该设备标识符去屏蔽对应的PCIe设备，避免在BIOS中转换地址信息和设备标识符，降低处理器资源占用。
在一些实施例中，在触发系统热重启之前，还包括：根据故障设备的定位信息生成故障分析表；将故障分析表发送至共享存储器中存储，使得在系统热重启过程中，主机BIOS从共享存储器中获取故障分析表。共享存储器为flash存储器，系统重启时，也能够保存数据，使得在重启后BIOS也能够获取到故障分析表。可选的，可以按照预定格式根据故障设备的定位信息生成故障分析表，例如：每个故障设备的定位信息通过特殊符号分隔，BIOS在解析该故障分析表时也按该预定格式进行解析，从而得到每个故障设备的定位信息。
可选的，根据故障设备的定位信息生成故障分析表的步骤如下：将当前分析出的故障设备均作为目标故障设备，对于每个目标故障设备，统计历史故障分析表中该目标故障设备发生故障的次数，按次数大小作为每一个目标故障设备的优先级，在当前生成的故障分析表中，按目标故障设备的优先级排列对应的定位信息，即目标故障设备优先级高的定位信息排列靠前，优先级低的排列靠后。在BIOS读取故障分析表时，先读取的定位信息对应的故障设备优先级越高，将其先优先屏蔽，避免屏蔽不及时引起系统宕机或其它设备故障。
如图6所示，本申请实施例的系统不可恢复故障处理方法，应用于主机侧的BIOS，包括以下步骤S610至S630。
步骤S610：监测故障隔离寄存器的标识位的状态。可选的，在服务器系统运行过程中，当系统硬件错误检查器检测到系统的不可恢复的错误时，置位故障隔离寄存器的标识位，BIOS监测故障隔离寄存器的标识位的状态。
步骤S620：在故障隔离寄存器的标识位被置位的情况下，触发片上控制器发送故障检查信号至BMC，故障检查信号用于指示BMC收集并分析处理器的寄存器数据，以得到故障设备的定位信息，并触发系统热重启。
步骤S630：在系统热重启过程中，根据定位信息屏蔽对应的故障设备。
本申请实施例的系统不可恢复故障处理方法中，在主机侧的BIOS检测到系统不可恢复故障后，触发BMC带外收集并分析处理器的寄存器数据，数据收集和分析过程不会占用处理器资源，大大减轻了处理器的工作负载，保证了处理器对真正的用户业务的处理性能需求，提高了服务器系统的稳定性。
在一些实施例中，步骤S620包括：在故障隔离寄存器的标识位被置位的情况下，触发执行系统不可恢复故障对应的中断函数；在中断函数执行时，触发片上控制器发送故障检查信号至BMC。可选的，BIOS启动过程中将故障隔离寄存器配置成一个中断源，故障隔离寄存器状态异常后会触发中断处理函数，在该中断函数中实现触发片上控制器发送故障检查信号至BMC的功能，保证在实时监测到每一个不可恢复故障时都能够将故障检查信号告知BMC，使得BMC及时执行相应的数据收集和分析过程。
在一些实施例中，步骤S630包括：在系统热重启过程中，BIOS从共享存储器中获取故障分析表，故障分析表是BMC根据故障设备的定位信息生成的；BIOS从故障分析表中解析出定位信息，并根据定位信息屏蔽对应的故障设备。可选的，可以按照生成故障分析表相应的格式解析故障分析表，例如：每个故障设备的定位信息通过特殊符号分隔，BIOS在解析故障分析表时，通过识别特殊符号将每个故障设备的定位信息解析出来。
在一个可选的实施例中，如图7所示，服务器系统正常运行过程中，BIOS检测到故障发生，即检测到故障隔离寄存器的标识位被置位后，触发片上控制器OCC将故障检查信号发送至BMC，BMC收到该故障检查信号后，执行数据收集操作，收集CPU的寄存器数据，数据收集完成后，BMC对寄存器数据进行数据分析，得到故障设备的定位信息，根据故障设备的定位信息生成故障分析表，将故障分析表存储在系统的共享存储器中，以便BIOS获取，之后触发系统热重启。在系统热重启过程中，BIOS根据故障分析表中的定位信息定位到故障设备，并屏蔽故障设备。
从上述过程可看出，CPU的寄存器数据的收集和分析的功能由带外的BMC执行，BIOS仅在检测到故障发生和最后屏蔽故障设备阶段调用CPU资源，而且屏蔽故障设备是热重启的过程中，因此，本实施例的系统不可恢复故障处理方法大大减轻了处理器的工作负载，保证了处理器对真正的用户业务的处理性能需求，提高了服务器系统的稳定性。
下面对本申请提供的系统不可恢复故障处理装置进行描述，下文描述的系统不可恢复故障处理装置与上文描述的系统不可恢复故障处理方法可相互对应参照。
本申请实施例还提供一种系统不可恢复故障处理装置，如图8所示，应用于BMC，该装置包括以下模块。
数据收集模块810，被设置为在检测到故障检查信号后收集处理器的寄存器数据，故障检查信号是片上控制器在检测到故障隔离寄存器的标识位被置位后发送至BMC的。
数据分析模块820，被设置为分析寄存器数据，以得到故障设备的定位信息。
重启触发模块830，被设置为触发系统热重启，在系统热重启过程中，定位信息用于指示主机BIOS根据定位信息屏蔽对应的故障设备。
本申请实施例的系统不可恢复故障处理装置中，在检测到系统不可恢复故障后，通过BMC带外收集并分析处理器的寄存器数据，数据收集和分析过程不会占用处理器资源，大大减轻了处理器的工作负载，保证了处理器对真正的用户业务的处理性能需求，提高了服务器系统的稳定性。
在一些实施例中，数据收集模块810被设置为在检测到故障检查信号后，根据BMC中存储的寄存器配置表收集寄存器配置表中寄存器的寄存器数据，寄存器配置表中配置了处理器的寄存器的配置信息。
在一些实施例中，数据收集模块810包括以下模块。
配置信息获取模块，被设置为获取寄存器配置表中的配置信息，配置信息包括：寄存器的偏移地址、访问方式、CPU编号、数据长度、输出位置和寄存器名称。
组帧格式确定模块，被设置为根据访问方式确定组帧格式。
数据帧生成模块，被设置为根据寄存器的偏移地址、CPU编号和数据长度按组帧格式生成用于访问处理器的数据帧，并将数据帧作为处理器的写入数据发送至处理器，数据帧用于指示处理器在确认CPU编号与自身的编号相同的情况下，读取偏移地址对应的寄存器中长度等于数据长度的寄存器值，并将寄存器值返回至BMC。
中间文件生成模块，被设置为将寄存器名称和寄存器值以键值对的形式组成寄存器数据，并根据寄存器数据生成中间文件，将中间文件写入输出位置指定存储路径保存。
在一些实施例中，系统不可恢复故障处理装置还包括：中间文件合并模块，被设置为在系统热重启的过程中，若再次检测到故障检查信号，则再次收集处理器的寄存器数据，再次生成中间文件，将再次生成的中间文件与上一次生成的中间文件合并，且对于上一次已收集过数据的寄存器，对应的寄存器值只保留上一次的寄存器值。
在一些实施例中，系统不可恢复故障处理装置，还包括：中间文件删除模块，被设置为在系统热重启完成之后，删除第一次生成的中间文件或合并后的中间文件。
在一些实施例中，系统不可恢复故障处理装置，还包括：重启次数限制模块，被设置为在系统热重启次数超过预设重启次数，且无法完成系统启动的情况下，提示系统无法启动。
在一些实施例中，数据分析模块820包括以下模块。
第一目标寄存器值获取模块，被设置为获取寄存器数据中的寄存器名称为设备状态对应的第一目标寄存器值。
第二目标寄存器值获取模块，被设置为在第一目标寄存器值表征故障状态的情况下，获取寄存器名称为设备地址对应的第二目标寄存器值，第二目标寄存器值为故障设备的地址信息，确定地址信息作为定位信息。
在一些实施例中，数据分析模块820包括以下模块。
第一目标寄存器值获取模块，被设置为获取寄存器数据中的寄存器名称为设备状态对应的第一目标寄存器值。
第二目标寄存器值获取模块，被设置为在第一目标寄存器值表征故障状态的情况下，获取寄存器名称为设备地址对应的第二目标寄存器值，第二目标寄存器值为故障设备的地址信息。
设备类型确定模块，被设置为根据BMC中存储的资产信息，确定故障设备的类型。
设备标识符转换模块，被设置为在故障设备的类型为PCIe设备类型的情况下，根据资产信息中记录的设备的地址信息和设备标识符的转换关系，将故障设备的地址信息转换成故障设备的设备标识符，确定设备标识符为定位信息。
在一些实施例中，系统不可恢复故障处理装置还包括以下模块。
故障分析表生成模块，被设置为在触发系统热重启之前，根据故障设备的定位信息生成故障分析表。
故障分析表存储模块，被设置为将故障分析表发送至共享存储器中存储，使得在系统热重启过程中，主机BIOS从共享存储器中获取故障分析表。
本申请实施例还提供一种系统不可恢复故障处理装置，如图9所示，应用于主机侧的BIOS，该装置包括以下模块。
故障检测模块910，被设置为监测故障隔离寄存器的标识位的状态。
故障检查信号发送模块920，被设置为在故障隔离寄存器的标识位被置位的情况下，触发片上控制器发送故障检查信号至BMC，故障检查信号用于指示BMC收集并分析处理器的寄存器数据，以得到故障设备的定位信息，并触发系统热重启。
故障设备屏蔽模块930，被设置为在系统热重启过程中，根据定位信息屏蔽对应的故障设备。
本申请实施例的系统不可恢复故障处理装置中，在主机侧的BIOS检测到系统不可恢复故障后，触发BMC带外收集并分析处理器的寄存器数据，数据收集和分析过程不会占用处理器资源，大大减轻了处理器的工作负载，保证了处理器对真正的用户业务的处理性能需求，提高了服务器系统的稳定性。
在一些实施例中，故障检查信号发送模块920被设置为在故障隔离寄存器的标识位被置位的情况下，触发执行系统不可恢复故障对应的中断函数；在中断函数执行时，触发片上控制器发送故障检查信号至BMC。
在一些实施例中，故障设备屏蔽模块930被设置为在系统热重启过程中，从共享存储器中获取故障分析表，故障分析表是BMC根据故障设备的定位信息生成的；从故障分析表中解析出定位信息，并根据定位信息屏蔽对应的故障设备。
图10示例了一种电子设备的实体结构示意图，如图10所示，该电子设备可以包括：处理器(processor)1010、通信接口(Communications Interface)1020、存储器(memory)1030和通信总线1040，其中，处理器1010，通信接口1020，存储器1030通过通信总线1040完成相互间的通信。处理器1010可以调用存储器1030中的逻辑指令，以执行用于BMC的系统不可恢复故障处理方法，该方法包括：在检测到故障检查信号后收集处理器的寄存器数据，故障检查信号是片上控制器在检测到故障隔离寄存器的标识位被置位后发送至BMC的；分析寄存器数据，以得到故障设备的定位信息；触发系统热重启，在系统热重启过程中，定位信息用于指示主机BIOS根据定位信息屏蔽对应的故障设备。
或者，执行用于主机侧BIOS的系统不可恢复故障处理方法，该方法包括：监测故障隔离寄存器的标识位的状态；在故障隔离寄存器的标识位被置位的情况下，触发片上控制器发送故障检查信号至BMC，故障检查信号用于指示BMC收集并分析处理器的寄存器数据，以得到故障设备的定位信息，并触发系统热重启；在系统热重启过程中，根据定位信息屏蔽对应的故障设备。
此外，上述的存储器1030中的逻辑指令可以通过软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个非暂态计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个非暂态可读存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例方法的全部或部分步骤。而前述的非暂态可读存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
另一方面，本申请还提供一种计算机程序产品，计算机程序产品包括计算机程序，计算机程序可存储在非暂态计算机可读存储介质上，计算机程序被处理器执行时，计算机能够执行上述各方法所提供的用于BMC的系统不可恢复故障处理方法，该方法包括：在检测到故障检查信号后收集处理器的寄存器数据，故障检查信号是片上控制器在检测到故障隔离寄存器的标识位被置位后发送至BMC的；分析寄存器数据，以得到故障设备的定位信息；触发系统热重启，在系统热重启过程中，定位信息用于指示主机BIOS根据定位信息屏蔽对应的故障设备。
或者，执行用于主机侧BIOS的系统不可恢复故障处理方法，该方法包括：监测故障隔离寄存器的标识位的状态；在故障隔离寄存器的标识位被置位的情况下，触发片上控制器发送故障检查信号至BMC，故障检查信号用于指示BMC收集并分析处理器的寄存器数据，以得到故障设备的定位信息，并触发系统热重启；在系统热重启过程中，根据定位信息屏蔽对应的故障设备。
又一方面，本申请还提供一种非暂态计算机可读存储介质，其上存储有计算机程序，该计算机程序被处理器执行时实现以执行上述各方法提供的用于BMC的系统不可恢复故障处理方法，该方法包括：在检测到故障检查信号后收集处理器的寄存器数据，故障检查信号是片上控制器在检测到故障隔离寄存器的标识位被置位后发送至BMC的；分析寄存器数据，以得到故障设备的定位信息；触发系统热重启，在系统热重启过程中，定位信息用于指示主机BIOS根据定位信息屏蔽对应的故障设备。
或者，执行用于主机侧BIOS的系统不可恢复故障处理方法，该方法包括：监测故障隔离寄存器的标识位的状态；在故障隔离寄存器的标识位被置位的情况下，触发片上控制器发送故障检查信号至BMC，故障检查信号用于指示BMC收集并分析处理器的寄存器数据，以得到故障设备的定位信息，并触发系统热重启；在系统热重启过程中，根据定位信息屏蔽对应的故障设备。
以上所描述的装置实施例仅仅是示意性的，其中作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。本领域普通技术人员在不付出创造性的劳动的情况下，即可以理解并实施。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到各实施方式可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件。基于这样的理解，上述技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品可以存储在非暂态计算机可读存储介质中，如ROM/RAM、磁碟、光盘等，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行各个实施例或者实施例的某些部分方法。
最后应说明的是：以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (20)

  1. 一种系统不可恢复故障处理方法，其特征在于，应用于基板管理控制器BMC，包括：
    在检测到故障检查信号后收集处理器的寄存器数据，所述故障检查信号是片上控制器在检测到故障隔离寄存器的标识位被置位后发送至BMC的；
    分析所述寄存器数据，以得到故障设备的定位信息；
    触发系统热重启，在系统热重启过程中，所述定位信息用于指示主机基本输入输出系统BIOS根据所述定位信息屏蔽对应的故障设备。
  2. 根据权利要求1所述的系统不可恢复故障处理方法，其特征在于，所述在检测到故障检查信号后收集处理器的寄存器数据，包括：
    在检测到故障检查信号后，根据BMC中存储的寄存器配置表收集所述寄存器配置表中寄存器的寄存器数据，所述寄存器配置表中配置了处理器的寄存器的配置信息。
  3. 根据权利要求2所述的系统不可恢复故障处理方法，其特征在于，根据BMC中存储的寄存器配置表收集所述寄存器配置表中寄存器的寄存器数据，包括：
    获取所述寄存器配置表中的配置信息，所述配置信息包括：寄存器的偏移地址、访问方式、中央处理器CPU编号、数据长度、输出位置和寄存器名称；
    根据所述访问方式确定组帧格式；
    根据所述寄存器的偏移地址、CPU编号和数据长度按所述组帧格式生成用于访问处理器的数据帧，并将所述数据帧作为处理器的写入数据发送至所述处理器，所述数据帧用于指示处理器在确认所述CPU编号与自身的编号相同的情况下，读取所述偏移地址对应的寄存器中长度等于所述数据长度的寄存器值，并将所述寄存器值返回至所述BMC；
    将所述寄存器名称和寄存器值以键值对的形式组成所述寄存器数据，并根据所述寄存器数据生成中间文件，将所述中间文件写入所述输出位置指定存储路径保存。
  4. 根据权利要求3所述的系统不可恢复故障处理方法，其特征在于，还包括：在所述系统热重启的过程中，若再次检测到故障检查信号，则再次收集处理器的寄存器数据，再次生成中间文件，将再次生成的中间文件与上一次生成的中间文件合并，且对于上一次已收集过数据的寄存器，对应的寄存器值只保留上一次的寄存器值。
  5. 根据权利要求4所述的系统不可恢复故障处理方法，其特征在于，在系统热重启完成之后，还包括：删除第一次生成的中间文件或合并后的中间文件。
  6. 根据权利要求4所述的系统不可恢复故障处理方法，其特征在于，还包括：在系统热重启次数超过预设重启次数，且无法完成系统启动的情况下，提示系统无法启动。
  7. 根据权利要求1所述的系统不可恢复故障处理方法，其特征在于，所述片上控制器拉高与所述BMC相连接的checkstop引脚，所述BMC检测到所述checkstop引脚被拉高后，认为是检测到所述故障检查信号；所述BMC通过I2C和可替换单元接口获取所述处理器的所述寄存器数据。
  8. 根据权利要求1所述的系统不可恢复故障处理方法，其特征在于，分析所述寄存器数据，以得到故障设备的定位信息，包括：
    获取所述寄存器数据中的寄存器名称为设备状态对应的第一目标寄存器值；
    在所述第一目标寄存器值表征故障状态的情况下，获取寄存器名称为设备地址对应的第二目标寄存器值，所述第二目标寄存器值为所述故障设备的地址信息，确定所述地址信息作为定位信息。
  9. 根据权利要求1所述的系统不可恢复故障处理方法，其特征在于，分析所述寄存器数据，以得到故障设备的定位信息，包括：
    获取所述寄存器数据中的寄存器名称为设备状态对应的第一目标寄存器值；
    在所述第一目标寄存器值表征故障状态的情况下，获取寄存器名称为设备地址对应的第二目标寄存器值，所述第二目标寄存器值为所述故障设备的地址信息；
    根据BMC中存储的资产信息，确定所述故障设备的类型；
    在所述故障设备的类型为一种高速串行计算机扩展总线标准PCIe设备类型的情况下，根据所述资产信息中记录的设备的地址信息和设备标识符的转换关系，将所述故障设备的地址信息转换成所述故障设备的设备标识符，确定所述设备标识符为所述定位信息。
  10. 根据权利要求1至9中任一项所述的系统不可恢复故障处理方法，其特征在于，在触发系统热重启之前，还包括：
    根据所述故障设备的定位信息生成故障分析表；
    将所述故障分析表发送至共享存储器中存储，使得在系统热重启过程中，主机BIOS从所述共享存储器中获取所述故障分析表。
  11. 根据权利要求10所述的系统不可恢复故障处理方法，其特征在于，所述根据所述故障设备的定位信息生成故障分析表，包括：
    统计历史故障分析表中目标故障设备发生故障的次数，其中，所述目标故障设备为当前分析出的故障设备；
    按照次数大小作为每一个目标故障设备的优先级；
    按照所述目标故障设备的优先级排列对应的定位信息，得到所述故障分析表。
  12. 一种系统不可恢复故障处理方法，其特征在于，应用于主机侧的BIOS，包括：
    监测故障隔离寄存器的标识位的状态；
    在故障隔离寄存器的标识位被置位的情况下，触发片上控制器发送故障检查信号至BMC，所述故障检查信号用于指示所述BMC收集并分析处理器的寄存器数据，以得到故障设备的定位信息，并触发系统热重启；
    在系统热重启过程中，根据定位信息屏蔽对应的故障设备。
  13. 根据权利要求12所述的系统不可恢复故障处理方法，其特征在于，在故障隔离寄存器的标识位被置位的情况下，触发片上控制器发送故障检查信号至BMC，包括：
    在故障隔离寄存器的标识位被置位的情况下，触发执行所述系统不可恢复故障对应的中断函数；
    在中断函数执行时，触发片上控制器发送所述故障检查信号至BMC。
  14. 根据权利要求12或13所述的系统不可恢复故障处理方法，其特征在于，在系统热重启过程中，根据定位信息屏蔽对应的故障设备，包括：
    在系统热重启过程中，从共享存储器中获取故障分析表，所述故障分析表是所述BMC根据所述故障设备的定位信息生成的；
    从所述故障分析表中解析出所述定位信息，并根据所述定位信息屏蔽对应的故障设备。
  15. 根据权利要求14所述的系统不可恢复故障处理方法，其特征在于，所述从所述故障分析表中解析出所述定位信息，包括：通过特殊符号从所述故障分析表中识别出每个所述故障设备的所述定位信息，其中，所述定位信息在所述故障分析表中通过所述特殊符号分隔。
  16. 根据权利要求12所述的系统不可恢复故障处理方法，其特征在于，所述片上控制器拉高与所述BMC相连接的checkstop引脚，所述BMC检测到所述checkstop引脚被拉高后，认为是检测到所述故障检查信号；所述BMC通过I2C和可替换单元接口获取所述处理器的所述寄存器数据。
  17. 一种系统不可恢复故障处理装置，其特征在于，应用于BMC，包括：
    数据收集模块，被设置为在检测到故障检查信号后收集处理器的寄存器数据，所述故障检查信号是片上控制器在检测到故障隔离寄存器的标识位被置位后发送至BMC的；
    数据分析模块，被设置为分析所述寄存器数据，以得到故障设备的定位信息；
    重启触发模块，被设置为触发系统热重启，在系统热重启过程中，所述定位信息用于指示主机BIOS根据所述定位信息屏蔽对应的故障设备。
  18. 一种系统不可恢复故障处理装置，其特征在于，应用于主机侧的BIOS，包括：
    故障检测模块，被设置为监测故障隔离寄存器的标识位的状态；
    故障检查信号发送模块，被设置为在故障隔离寄存器的标识位被置位的情况下，触发片上控制器发送故障检查信号至BMC，所述故障检查信号用于指示所述BMC收集并分析处理器的寄存器数据，以得到故障设备的定位信息，并触发系统热重启；
    故障设备屏蔽模块，被设置为在系统热重启过程中，根据定位信息屏蔽对应的故障设备。
  19. 一种电子设备，包括存储器、处理器及存储在所述存储器上并可在所述处理器上运行的计算机程序，其特征在于，所述处理器执行所述程序时实现如权利要求1至10中任一项所述的系统不可恢复故障处理方法，或实现如权利要求12至14中任一项所述的系统不可恢复故障处理方法。
  20. 一种非暂态计算机可读存储介质，其上存储有计算机程序，其特征在于，所述计算机程序被处理器执行时实现如权利要求1至10中任一项所述的系统不可恢复故障处理方法，或实现如权利要求12至14中任一项所述的系统不可恢复故障处理方法。
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