WO2025257530A1

WO2025257530A1 - Complementary metal oxide semiconductors having gold-plated electrodes

Info

Publication number: WO2025257530A1
Application number: PCT/GB2025/051256
Authority: WO
Inventors: Sara GHOREISHIZADEH; Minghao LI; Nisha NAEEM
Original assignee: UCL Business Ltd
Current assignee: UCL Business Ltd
Priority date: 2024-06-12
Filing date: 2025-06-09
Publication date: 2025-12-18
Anticipated expiration: 2026-12-12
Also published as: GB202408389D0

Abstract

The present invention provides a method of preparing a complementary metal oxide semiconductor comprising one or more electrode, the method comprising: providing a complementary metal oxide semiconductor (CMOS) integrated circuit (IC) having one or more sensor regions, each sensor region comprising a sensing zone and a passivation zone, wherein the passivation zone encircles and directly abuts the sensing zone, and the sensing zone comprises an active layer, an optional adhesive layer and a conductive base layer; replacing at least part of the active layer with a metal sub¬ layer by electroless deposition; and pulse current electroplating a crystalline gold surface layer onto the metal sub-layer to form the one or more electrodes. The present invention further provides said complementary metal oxide semiconductors, electrochemical devices containing said complementary metal oxide semiconductors, and methods of using said electrochemical devices to detect biomolecules.

Description

COMPLEMENTARY METAL OXIDE SEMICONDUCTORS HAVING GOLD-PLATED ELECTRODES

Field of the Invention

The present invention relates to methods of preparing complementary metal oxide semiconductors having gold-plated electrodes, said complementary metal oxide semiconductors themselves, electrochemical devices containing them, and methods of using said electrochemical devices to detect biomolecules.

Background of the Invention

Electrochemical sensors have seen rapid development in the past decade and are crucial in various applications such as environmental monitoring, food safety, medical diagnosis, and clinical research due to their ability to detect gases, liquids, and biological substances [l]-[3] . The compact design of electrochemical sensors makes them portable, enabling field measurements without the need for extensive laboratory infrastructure. The monolithic integration of microsensors with complementary metal oxide semiconductor (CMOS) chips is an area of interest. By directly sensing the target signal on CMOS, the signal channel is reduced to the micron level, significantly improving the signal-to-noise ratio [1] . Additionally, the integration of sensors with low-cost semiconductor device manufacturing enables their mass production with excellent economies of scale.

One crucial aspect of incorporating an electrochemical microsensor array on CMOS involves the creation of a stable, reproducible, and cost-effective sensing surface layer on the topmost metal layer of the CMOS devices, which is typically made of aluminium. Gold is a popular choice for the base layer of biosensor electrodes, due to its excellent conductivity and biocompatibility [4], Integrated circuits (ICs) fabricated in standard CMOS technology need to be processed post-fabrication, to produce gold-coated microelectrodes. A few different techniques have been utilized to achieve this: physical vapour deposition, gold bumping, electrochemical plating and electroless plating. [2], [5]-[7],

Issues of cost, reliability, incompatibility, and stability currently prevent the widespread adoption of the techniques known in the art. Physical vapour deposition, due to the need for clean room facilities, is often costly and requires regular maintenance, which can be prohibitive for small-scale operations or research facilities [2], [5], Furthermore, it requires lithography techniques to create a mask, a step that is limited by the mask fabrication precision, and at below millimetre range also can only be carried out in a clean room.

Gold bumps for 3D electrodes offer simplicity and cost-effectiveness but encounter reliability issues like solder joint fatigue and inadequate coverage of aluminium surfaces, potentially leading to biomolecule incompatibility concerns [6], [8],

Electroless plating of metal layers is simple, affordable, and reproducible [9], However, the thickness of the deposited layer is difficult to control because it is an automatically terminated process and has limited electrochemical stability [10],

A smooth and crystalline gold surface is critical in the development of various biosensors, [11] such as molecularly assembled films and the chemical modification of the sensors. Despite being a low-cost, and saleable technique, gold electrodeposition on CMOS microelectrodes, has so far only been able to achieve rough surfaces with various types of (nano-) structures, such as Au bumps and nanoflowers [8], [12], [13],

There is therefore a need for a low-cost technique for preparing smooth, uniform, and crystalline layers on CMOS electrodes.

Summary of the Invention

The present inventors have developed a low-cost electroplating-based technique for creating uniform, and crystalline surface layers on CMOS electrodes. The technique provides control of the surface roughness and layer thickness of the surface layer and provides an affordable route for accessing gold electrodes with a low surface roughness.

Therefore, in a first aspect, there is provided a method of preparing a complementary metal oxide semiconductor having one or more electrode. The method comprises the steps of providing a complementary metal oxide semiconductor having one or more sensor region. Each sensor region comprises a sensing zone and a passivation zone. The passivation zone encircles and directly abuts the sensing zone. The sensing zone comprises an active layer, an optional adhesive layer and a conductive base layer. The method further comprises the step of replacing at least part of the active layer with a metal sub-layer by electroless deposition. The method then comprises the step of pulse current electroplating a crystalline gold surface layer onto the metal sub-layer to form the one or more electrode.

In some embodiments the metal sub-layer is a gold sub-layer, a platinum sub-layer or a silver sub-layer.

The method produces gold electroplated electrodes with a crystalline surface layer. The crystalline surface layer which is uniform and has high stability. For example, the surface layer may have a surface roughness of about 600 nm or less.

The pulse current electroplating may be performed at a current density of from 1.5 to 5 mA/cm², with a deposition time of 1200s or less and a pulse frequency of greater than 10 Hz. Electrodes produced under these conditions have a low surface roughness. For example, the surface layer may have a surface roughness of about 600 nm rms or less.

Gold is the optimal choice for the surface layer of biosensor electrodes, due to its excellent conductivity and biocompatibility. The gold surface layer may have a purity of 95% gold or more, such as 97% gold or more or 99% gold or more.

The surface layer of gold may have a thickness of 2.5 micrometre or less. In some embodiments, the surface layer of gold has a thickness of 1 micrometre or less, such as 800 nm or less. The greater the current density and the longer the deposition time, the greater the thickness of the surface layer. Thicker surface layers have been found by the present inventors to be more stable. However, some sensing applications may require thinner surface layers so as to capture a cell or bead on top of the electrode, in the cavity formed by the height difference between the surface layer and the passivation zone.

The active layer is one that can be displaced by gold during the electroless deposition of gold. In some embodiments, the active layer is selected from a layer of copper, nickel phosphorous, nickel-boron, nickel, cobalt, palladium or iron. The skilled person will be aware of other suitable active layers. In some preferred embodiments, the active layer is nickel phosphorus (Ni-P). Ni-P layers achieve an active layer with lower surface roughness and finer nucleation sites. This in turn provides a metal sub-layer following electroless deposition with low surface roughness. The lower the surface roughness of the sub-layer, the lower the surface roughness of the electroplated gold surface layer. In some embodiments the active layer is palladium. Where the active layer is palladium there is no need for an additional adhesive layer.

The sub-layer protects the adhesive and conducive base layer from corrosion during the electroplating step. The sub-layer is formed by electroless deposition may be amorphous. In some embodiments, the metal sub-layer comprises at least 90% of the metal by weight of the layer, such as at least 95%, or at least 97%. In some preferred embodiments, the sub-layer is a gold sub layer. In some embodiments the gold sub-layer comprises at least 90% gold by weight of the layer, such as at least 95%, at least 97%, at least 98%, at least 99%, at least 99.5% or at least 99.9% by weight.

The conductive base layer is formed from the conductive substrate of the CMOS and is exposed when the CMOS is etched. Commonly, the conductive base layer is aluminium. However, the skilled person will be aware of CMOS with alternative conductive substrates, such as copper, which would be equally applicable to the present invention.

The optional adhesive layer, when present, improves adhesion between the conductive base layer and the active layer or metal sub-layer, compared with disposing the active layer directly onto the conductive base layer. In some embodiments, the adhesive layer is zinc. The skilled person will be aware of other suitable adhesive layers. Where the adhesive layer is zinc, is may be disposed on the conductive base layer by the double zincation process.

In some embodiments, the method comprises forming a reaction reservoir around the sensor region before electroplating occurs. The formation of a reaction reservoir protects wires and other parts of the CMOS from corrosion during the electroplating process.

In some embodiments of the method, the complementary metal oxide semiconductor integrated circuit having a sensor region is provided by etching a complementary metal oxide semiconductor to expose the conductive base layer, depositing an adhesive layer onto the conductive base layer by an electroless method, and then depositing the active layer onto the adhesive layer by an electroless method.

In a second aspect of the invention, there is provided a complementary metal oxide semiconductor having one or more electrode prepared according to a method of the first aspect.

In some embodiments the one or more electrodes of the complementary metal oxide semiconductor of the second aspect have a surface layer of gold with a roughness of less than 600 nm rms. In some embodiments of the second aspect, the sub-layer is an amorphous sub-layer. In some embodiments of the second aspect, the sub-layer is a gold, platinum or silver sub-layer. In some embodiments, the sub-layer is a gold sublayer. In some embodiments, the sub-layer is an amorphous gold sub-layer.

In a third aspect of the invention, there is provided a complementary metal oxide semiconductor integrated circuit having a sensor region comprising a sensing zone and a passivation zone, wherein the passivation zone encircles and directly abuts the sensing zone, and the sensing zone comprises an amorphous metal sub-layer adjacent to a crystalline gold surface layer.

In some embodiments of the third aspect the gold surface layer is crystalline with a surface roughness of 600 nanometres rms or less and/or and a thickness of 2.5 micrometres or less.

In some embodiments of the second and third aspects the surface layer of gold has a thickness of 1 micrometre or less, such as 800 nm or less.

In some embodiments of the second and third aspects, the sub-layer is a gold, platinum or silver sub-layer. In some embodiments, the sub-layer is a gold sub-layer. In some embodiments the sub-layer is amorphous. In some embodiments, the sub-layer is an amorphous gold sub-layer.

The surface layer of the second and third aspect has a roughness of 600 nm rms or less. Surface roughness alfects the assembly and performance of molecular films on electrode surfaces, which are critical for the sensitivity and reproducibility of sensor responses. Lower surface roughness promotes the assembly or molecular films for label-free electrochemical capacitive biosensors. In some embodiments the second or third aspect has a surface roughness of less than 200 nm rms, or less than 100 nm rms.

In a fourth aspect of the invention, there is provided an electrochemical apparatus comprising the complementary metal oxide semiconductor having one or more electrode of the second or third aspect.

In a fifth aspect, there is provided a method for detecting a biomolecule, comprising the steps of: i) providing a sample; ii) providing the electrochemical apparatus of the fourth aspect; iii) exposing the electrode of the electrochemical apparatus to the sample; iv) using a voltametric technique to assess the presence of the biomolecule.

In some embodiments, the voltametric technique is cyclic voltammetry.

Detailed Description of the Invention

The present invention provides a method of preparing a complementary metal oxide semiconductor having one or more electrode.

The method comprises the steps of providing a complementary metal oxide semiconductor having one or more sensor region. Each sensor region comprises a sensing zone and a passivation zone. The passivation zone encircles and directly abuts the sensing zone. The sensing zone comprises an active layer, an optional adhesive layer and a conductive base layer. The method further comprises the step of replacing at least part of the active layer with a metal sub-layer by electroless deposition. The method then comprises the step of pulse current electroplating a crystalline gold surface layer onto the metal sub-layer to form the electrode.

Complementary Metal Oxide Semiconductor Integrated Circuit The method comprises the steps of providing a complementary metal oxide semiconductor (CMOS) integrated circuit (IC) having one or more sensor region comprising a sensing zone and a passivation zone.

Following the method, the sensing region, comprising the passivation layer and the gold plated sensing zone, forms an electrode suitable for use in detecting biomolecules.

The CMOS IC may have two or more sensor regions, such as three or more, four or more. The CMOS IC may have one hundred sensor regions or less, such as 80 sensor regions or less, 50 sensor regions or less, or 20 sensor regions or less.

The passivation zone is a non-conductive zone that encircles and directly abuts the sensing zone. The passivation zone may be formed from the passivation layer of the CMOS. For example, the passivation zone may comprise one or more of a layer of polyimide, a layer of silicon nitride, or a layer of silicon dioxide.

The sensing zone comprises an active layer, an optional adhesive layer and a conductive base layer. The active layer is disposed on the adhesive layer when present. Where the adhesive layer is not present the active layer is disposed on the conductive base layer. When present, the adhesive layer is disposed on the conductive base layer.

The sensing zone is where the gold surface layer is formed by the method of the present invention to provide the sensing surface layer of the electrode.

In some embodiments of the method of the present invention, the complementary metal oxide semiconductor having a sensor region is provided by etching a complementary metal oxide semiconductor to expose the conductive base layer, depositing an adhesive layer onto the conductive base layer by an electroless method, and then depositing the active layer onto the adhesive layer by an electroless method. Alternatively, the complementary metal oxide semiconductor may be provided to the method pre-made.

The sensing zone may be formed by etching through the passivation layer of a CMOS to uncover the conductive substrate of the CMOS and disposing the further layers of the sensing zone onto this conductive substrate. The sensing zone may have a surface area suitable for the intended application. In some preferred embodiments the electrode is a microelectrode or a nanoelectrode and the sensing zone may have a surface area of less than 1 mm². For example, the sensing zone may have a surface area 900 pm² or less, 800 pm² or less, 700 pm² or less, 600 pm² or less, 500 pm² or less. In some embodiments, the sensing zone may have a surface area of 1 nm² or greater, 10 nm² or greater, 100 nm² or greater, 200 nm² or greater, or 400 nm² or greater. In some embodiments, the sensing zone may have a surface area of from 1 pm² to 999 pm², such as from 10 pm² to 900 pm² or from 100 nm² to 900 pm².

The sensing zone comprises an active layer, an adhesive layer and a conductive base layer. The active layer is disposed on the adhesive layer. The adhesive layer is disposed on the conductive base layer.

The conductive base layer may be formed from the conductive substrate of the CMOS. The conductive base layer may be aluminium. Other conductive base layers are known in the art. The conductive base layer may have a thickness of from 500 pm to 3000 pm, such as from 1000 pm to 2500 pm, or from 1500 pm to 2500 pm. The conductive base layer may have a roughness of from 10 nm to 300 nm. In some embodiments the conductive base layer may be an aluminium base layer with a thickness of from 500 pm to 3000 pm.

The direct deposition of gold films over conductive base layers such as aluminium base layers is not recommended due to the poor adhesion of gold to aluminium. The conductive base layer has poor adhesion with the active layer required for electroless deposition of the gold sub-layer. The conductive base layer may also lack the inner vacant electron orbit, for example where the conductive base layer is aluminium. An inner vacant electron orbit is generally required for auto-catalytic deposition of the active metal layer. An adhesive layer addresses these issues.

The adhesive layer may be a zinc layer. The zinc adhesive layer may be applied using a zincation process, preferably a double zincation process. During the zincation process, a thin layer of the conductive base layer, which may be an aluminium conductive base layer, is replaced with zinc. A double zincation process achieves a more uniform and dense zinc layer without any large zinc grains compared with a single zincation process, which improves the adhesion of the active layer at the next stage. For example, each zincation step may be carried out by exposing the sensing zone to a Zinc electroless plating solution for a period of 10 seconds to 5 minutes, such as from 30 seconds to 90 seconds, at a temperature of from 15°C to 55 °C, such as from 20°C to 50 °C. After the first zincation step, the sensing zone may be exposed to nitric acid, such as 20% nitric acid at a temperature of from 15°C to 35 °C for a period of 1 minute or less, such as from 10 seconds to 50 seconds, before the zincation step is repeated to complete the double zincation process.

The adhesive layer may have a thickness of from 10 nm to 300 nm, such as from 30 nm to 200 nm, from 50 nm to 150 nm, or from 80 nm to 120 nm. The adhesive layer may have a roughness of less than 300 nm, such as less than 250 nm, such as less than 200 nm, such as less than 150 nm. In some embodiments, the adhesive layer is a zinc layer deposited by a double zincation process and having a thickness of 10 nm to 300 nm. In some embodiments, the adhesive layer is a zinc layer deposited by a double zincation process and having a thickness of 10 nm to 300 nm and a roughness of less than 200 nm.

The active layer is one that can be displaced by a metal during the electroless deposition of the metal sub-layer. The active layer provides a layer with a low surface roughness, which in turn provides a sub-layer with low surface roughness following electroless deposition. Providing a sub-layer with low surface roughness means the surface layer electroplated onto the sub-layer may also have low surface roughness, as the electroplated layer cannot be less rough than the sub-layer.

A remnant of the active layer may remain to provide good adhesion between the adhesive layer and the metal sub-layer.

In some embodiments, the active layer may be a copper layer, a nickel phosphorous layer, a nickel layer, a cobalt layer or an iron layer. In some preferred embodiments, the active layer is a nickel layer or a nickel phosphorus (Ni-P) layer. Most preferably the adhesive layer is a Ni-P layer. Ni-P layers in particular achieve an active layer with lower surface roughness and finer nucleation sites which in turn provides a metal sublayer with lower surface roughness following electroless deposition and therefore a surface layer with lower surface roughness following electroplating. The active layer may have a thickness of 1000 nm or less, such as 900nm or less, or 800 nm or less. The active layer may have a thickness of from 100 nm to lOOOnm, such as from 200 nm to 900 nm or from 300 nm to 800 nm. The active layer may have a roughness of less than 300 nm, such as less than 200 nm or less than 100 nm.

In some embodiments, the active layer may be a nickel phosphorus (Ni-P) active layer with a thickness of from 100 nm to lOOOnm and a roughness of less than 100 nm.

The active layer may be deposited onto the adhesive layer by electroless deposition. Where the active layer is Ni-P, the process may comprise exposing the sensing zone to Ni electroless plating solution for a period of from 5 to 60 minutes, such as from 10 to 40 minutes or from 15 minutes to 35 minutes at a temperature of from 60° to 95 °C, such as from 70°C to 90°C.

The method further comprises the step of replacing at least part, and preferably 90% or more, of the active layer with a sub-layer by electroless deposition. The sub-layer may be a silver, platinum or gold sub-layer. Preferably the sub-layer is a gold sub-layer.

The presence of the sub-layer prevents the active layer from corroding during the electroplating step.

The thickness of the sub-layer is limited to the thickness of the active layer.

The sub-layer may therefore have a thickness of 1000 nm or less, such as 900nm or less, or 800 nm or less, or a thickness of from 100 nm to lOOOnm, such as from 200 nm to 900 nm or from 300 nm to 800 nm. Some of the active layer may remain following this step. The remaining active layer provides adhesion between the adhesive layer and the sub-layer.

95 % or greater of the top 100 nm, 200 nm, 300 nm or 400 nm of the gold sub-layer may be gold. Where the sub-layer has a thickness of 500 nm or greater, greater than 95% of the top 500 nm of the sub-layer may be the metal of the sub-layer, such as gold. The top of the layer is the surface furthest from the conductive base layer. Electroless deposition of metal onto the active layer may be achieved by the following process. The sensing zone having an active layer may be exposed to gold electroless solution for a period of from 5 to 45 minutes, such as from 10 to 40 minutes or from 15 to 30 minutes at a temperature of from 60° to 99 °C, such as from 80°C to 95°C. The formation of a gold sub-layer may be confirmed using SEM.

Electroless deposition of the metal sub-layer results in an amorphous sub-layer. Preferably the sub-layer is an amorphous gold sub-layer.

Electroplating

Pulse current electroplating achieves a smoother, harder, and more uniform surface compared to direct current methods. While in direct current deposition, only current density can be controlled, in pulsed current deposition, three parameters can be controlled: average current density (Iavg), pulse frequency (T = t_on + t_Off), and pulse switching duty cycle (t_on/T ) according to Formula 1.

Iavg ~ Ipton/ (ton 4“ toff')

Formula 1

Where I_avg is the average current density, I_p is the peak current density, and t_on and t_Off are the turn-on and turn-off time of one pulse respectively. Pulsed current application of the gold surface layer may be carried out by applying a pulsed current between the sensing zone and a platinised titanium electrode.

The average current density may be 5 mA/cm² or less, such as 5 mA/cm² or less, 4.5 mA/cm² or less, 4 mA/cm² or less, 3.5 mA/cm² or less, 3 mA/cm² or less or 2.5 mA/cm² or less. For example, the average current density may be from 0.5 to 5 mA/cm², from 1 to 5 mA/cm², from 1.5 to 5 mA/cm² from 1.5 to 4.5 mA/cm², from 1.5 to 4 mA/cm², from 1.5 to 3.5 mA/cm², from 1.5 to 3 mA/cm², from 1.5 to 2.5 mA/cm², or from 1.5 to 2 mA/cm². Preferably, the average current density is from 1.5 to 2 mA/cm². A low current density provides maximum control over layer thickness and avoids large nucleation sites. The avoidance of large nucleation sites promotes the formation of a uniform surface layer with low roughness. The pulse frequency may be greater than 10 Hz. For example, the pulse frequency may be greater than 20 Hz, greater than 30 Hz, greater than 40 Hz, greater than 50 Hz, greater than 60 Hz, greater than 70 Hz, greater than 80 Hz, greater than 90 Hz. In a preferred embodiment the pulse frequency is greater than 80 Hz. The pulse frequency may be less than 1000 Hz, such as less than 900 Hz, less than 800 Hz, less than 700 Hz, less than 600 Hz, or less than 500 Hz. Preferably, the pulse frequency is from 80 Hz to 500 Hz. A pulse frequency of greater than 10 Hz, and in particular greater than 80 Hz, prevents the sensing zone, which forms the working electrode during electroplating, from acting as an unintended anode during prolonged exposure to positive voltages (relative to a reference electrode).

Deposition time is the time over which the pulse current deposition is performed under the conditions outline above. The deposition time may be 3600s or less, such as 2400s or less or 1200s or less. For example, the deposition time may be 1100s or less, 1000s or less, 900s or less, 800s or less, or 700s or less. The deposition time may be from 100s to 1200s. For example, the deposition time may be from 200s to 900s, or from 300s to 900s. In a preferred embodiment the deposition time may be from 400s to 700s. The deposition time is a factor in determining the thickness and roughness of the gold surface layer. A deposition time of from 400s to 700s was found to be the deposition time range that provided surface layers with the lowest roughness.

In some embodiments the pulse current electroplating is galvanostatic. By galvanostatic it is meant that the current density during t_on is constant throughout the deposition time.

In some embodiments, the pulse current electroplating is performed at a current density of from 1.5 to 5 mA/cm², with a deposition time of 1200s or less and a pulse frequency of greater than 10 Hz.

The deposition time and the average current density can be tuned to provide a flat surface layer of gold with the desired surface roughness. At higher deposition times required to achieve a higher surface thickness or increased surface roughness for the gold surface layer, a lower average current density may be required to provide a flat surface. Therefore, in some embodiments, the deposition time is 1200s or greater, such as from 1200s to 3600s and the average current density is 2 mA/cm² or less, such as from 0.5 to 2 mA/cm² or 0.5 to 1.5 mA/cm². The present inventors have found that the deposition time and the average current density can be tuned to provide a surface layer with very low surface roughness. In this embodiment, the pulse current electroplating is performed at an average current density of from 1.5 to 5 mA/cm², preferably from 1.5 to 2.5 mA/cm², with a deposition time of 1200s or less, preferably from 400s to 700s and a pulse frequency of greater than 10 Hz, preferably of from 80 Hz to 500 Hz, provides a flat surface of electroplated gold, with a surface roughness of less than 100 nm rms.

Thickness of a layer may be calculated by measuring the dilference between the heights of the electrode and the surrounding passivation zone using atomic force microscopy (AFM) before and after the layer was deposited.

The roughness of a layer may be measured using atomic force microscopy and is expressed as a root mean square (rms). A surface described herein as smooth will have low surface roughness, for example less than 600 nm rms.

The duty cycle is the effective portion of time in a certain electroplating period with the current or potential applied. The duty cycle may be converted to pulse switching duty cycle of Formula 1 through division by 100. The pulse current electroplating of the present invention may have a duty cycle of from 40% to 60%, such as from 45% to 55%, or from 48% to 52%. This range achieves a balance between avoiding direct current methods causes by a high duty rate and achieving an acceptable rate of electroplating, which slows as the duty rate falls.

The pulse current electroplating may be performed at a temperature of from 15°C to 40°C, and preferably at room temperature.

The gold surface layer formed by the method of the present invention is crystalline.

The gold surface layer formed by the method of the present invention may have a thickness of 2.5 pm or less, such as 2 pm or less, 1.5 pm or less, 1 pm or less, 900 nm or less, 800 nm or less or 700 nm or less. The gold surface layer may have a thickness of 50 nm or more, such as 100 nm or more, 200 nm or more, 300 nm or more or 400 nm or more. The gold surface layer may have a surface roughness of about 500 nm or less, such as 400 nm or less, 300 nm or less, 200 nm or less, 150 nm or less, 100 nm or less, or 50 nm or less.

In some embodiments, the method comprises forming a reaction reservoir around the sensor region before electroplating occurs. The formation of a reaction reservoir protects wires and other parts of the CMOS from corrosion during the electroplating process. The reaction reservoir may be a glass or plastic ring that is sealed to the CMOS around the sensing zone, optionally the seal is made with epoxy resin or another appropriate resin.

Electrode

A complementary metal oxide semiconductor having one or more electrode is also provided.

In one aspect the complementary metal oxide semiconductor having one or more electrode is formed by the method of the present invention.

In another aspect, the complementary metal oxide semiconductor having one or more electrode may comprise a complementary metal oxide semiconductor integrated circuit having one or more electrode, each electrode comprising a sensing zone and a passivation zone, wherein the passivation zone encircles and directly abuts the sensing zone, and the sensing zone comprises a sub-layer adjacent to a gold surface layer, wherein the gold surface layer is crystalline and the sub-layer is amorphous.

In some embodiments, the surface layer has a surface roughness of 600 nm rms, such as 500 nm rms or less, 400 nm rms or less, 300 nm rms or less, 250 nm rms or less, 200 nm rms or less, or 100 nm rms or less.

In some embodiments, the surface layer has a thickness of 2.5 micrometres or less, such as 2 micrometres or less, 1.5 micrometres or less, 1 micrometre or less or 800 nm or less. In some embodiments, the surface layer has a surface roughness of 600 nm rms or less and a thickness of 2.5 micrometres or less. In preferred embodiments, the surface layer has a surface roughness of 300 nm rms or less and a thickness of 1.5 micrometres or less.

In some embodiments, the sub-layer is a gold, platinum or silver sub-layer. In some preferred embodiments, the sub-layer is a gold sub-layer.

The sub-layer is amorphous. The amorphous sub-layer may be formed by electroless deposition. The presence of an amorphous sub-layer facilitates the formation of a flat, electroplated surface layer with low surface roughness, such as 600 nm rms or less, at low cost and with minimal equipment requirements.

In some preferred embodiments, the sub-layer is an amorphous, gold sub-layer.

The surface layer is crystalline. The surface layer may be formed by electroplating under the conditions outlined above.

By amorphous, it is meant that the sub-layer is non-crystalline. The crystallinity of a layer may be determined using cyclic voltammetry (CV) in sulfuric acid. A crystalline gold layer will show at least two distinct oxidation peaks at between 1.14 V and 1.4 V. An amorphous gold layer will show a single broad oxidation peak between 1.14 V and 1.4 V. A distinct peak is one where the apex of the peak is at least 10% greater than the nadir adjacent to the peak.

The sub-layer is unstable when exposed to a potential difference. In contrast, a crystalline gold surface is stable under these conditions. The crystalline gold layer is therefore additionally useful in providing a stable surface layer for use in performing electrochemical measurements.

The complementary metal oxide semiconductor comprises one or more electrodes. For example, the complementary metal oxide semiconductor may comprise two or more electrodes, four or more electrodes, ten or more electrodes or one hundred or more electrodes. In some embodiments the CMOS may have additional electrical contacts allowing the CMOS chip to be electrically connected to a larger device, for example a printed circuit board.

Also provided is an electrochemical apparatus comprising the complementary metal oxide semiconductor of the present invention.

Method of Detecting a Biomolecule

Also provided is a method for detecting a biomolecule. The method comprises the steps of: i) providing a sample; ii) providing the electrochemical apparatus of the present invention; iii) exposing the electrode of the electrochemical apparatus to the sample; iv) using a voltametric or amperometric technique to assess the presence of the biomolecule.

In some embodiments the technique to assess the presence of the biomolecule is a voltametric technique selected from cyclic voltammetry or Fast Scan Cyclic voltammetry.

In some embodiments, the technique to assess the presence of the biomolecule is an amperometric technique selected from chronoamperometry.

The biomolecule may be any analyte. For example, the biomolecule may be a molecule generated by the mammalian body or by organisms within the mammalian body such as bacteria and/or viruses. In some embodiments, the biomolecule is selected from amino acids, amino acid derivatives, eicosanoids, peptides, androgens, estrogens, progestogens, secosteroids or combinations thereof. In some embodiments the biomolecule is selected from dopamine, adrenaline, melatonin, insulin, testosterone or combinations thereof.

Brief Description of Figures

Figure 1 shows a schematic of CMOS gold electrodes of the present invention. Figure 2 shows a process flow for fabricating the CMOS gold electrodes.

Figure 3 shows (a) Electroplated gold thickness (mean and standard deviation) with the electrodeposition time, (b) surface square root mean roughness (mean and standard deviation) of the fold surface layer.

Figure 4 shows cyclic voltammetry in 0.5 M sulfuric acid with a scan rate of 100 mV/s of (a) of electroplated gold microelectrode and (b) of the gold sub-layer formed by electroless deposition.

Detailed Description of the Drawings

Figure 1 shows a CMOS comprising an electrode 100, formed according to an embodiment of the present invention. The passivation zone 101 encircles and directly abuts the sensing zone 102 to form the electrode. The passivation zone and sensing zone are mounted on CMOS substrate (x). The sensing zone comprises a conductive base layer (i), an adhesive layer (ii), a sub-layer (iv) and a surface layer (v). The CMOS further comprises electrical connections 103, which may allow electrical communication between the CMOS and the electrode of the CMOS with a large system, such as a printed circuit board (PCB).

Figure 2 shows a process flow for fabricating the CMOS gold electrodes from a commercial CMOS chip according to an embodiment of the present invention. The process comprises in step a. providing a CMOS chip having passivation zones 202, conductive base layer (i) and electrical contacts 204. In step b. a zinc adhesive layer (ii) is applied on top of the conductive base layer by the double zincation process. In step c. a nickel active layer (iii) is applied onto the zinc adhesive layer by electroless nickel deposition. In step d. a gold sub-layer (iv) is deposited onto the adhesive layer by electroless deposition which displaces the nickel active layer. In step e. the electrical contacts are connected to a printed circuit board (PCB) via wires 201. In step f. the wires are encapsulated in epoxy resin 203 and a reservoir 205 is formed around the gold sub-layer, in step g. a gold layer (v) is electroplated onto the gold sub-layer at an average current density of 1.5 mA/cm'² and a frequency of 100 Hz. Examples

Chemicals

NB Au semilOO was purchased from NB Technologies. Bright Au electroless plating solution, sulfuric acid, sodium hydroxide, dopamine hydrochloride, ascorbic acid and potassium ferri/ferrocyanide were purchased from Sigma Aldrich. Nitric acid (from Honeywell research chemicals), phosphate buffer solution (PBS), acetone, isopropanol alcohol (IPA) and de-ionised (DI) water were also used.

Nickel electroless plating solution was prepared by mixing 1 mb nickel sulfate hexahydrate (28 g/L in DI water, from Sigma) and 1 mb sodium hypophosphite (27 g/L in DI water, from Sigma). Silver conductive epoxy (833 ID) was purchased from MG Chemicals. An epoxy (EP41S-5) from Masterbond was used to protect wires.

Equipment, Software and Electrode Setup

Scanning electron microscopy and energy dispersive X-ray (EDX) were carried out using the JEOL IT 100 SEM machine for surface morphology and composition analysis. The EDX was set up by applying an accelerating voltage of 15 kV, to analyze the top 0.5 pm thickness of the microelectrode surface. Atomic force microscopy (AFM) was carried out using NaioAFM (nanosurf) for surface roughness and thickness measurements. A focused ion beam (NV40, Zeiss) was used to measure the thickness of the Al and Au layers.

A pump (miniplus3, Gilson) was used for a flow injection for chronoamperometry. A semi-automatic wire-bonding machine (F & S Bondtec 5632) with 25 pm thick Au wires was used to connect the chip pads to a carrier PCB. An oven (ED056, Binder) and an ultrasound cleaner (VWR) were also used.

A potentiostat (PGSTAT204 Metrohm), was used to carry out the electrodeposition and electrochemical measurement with a three-electrode setup, with an Ag/AgCl electrode (from BASi research products) as the reference electrode, a platinized titanium rod electrode (from Ti-Shop.com) as the counter electrode. Matlab was used to calculate the result data such as the variance and standard deviation of the gold layer thickness.

CMOS Microelectrode Fabrication

A 1.77 mm x 1.77 mm CMOS IC (herein also referred to as “the chip”) was designed with a 4 x 4 array of aluminium microelectrodes in the middle and readout electronics on the sides. The IC was fabricated in a standard 180 nm CMOS technology (at Taiwan Semiconductor Manufacturing Company, TSMC). The microelectrodes measure 66 pm x 66 pm with a 40 pm edge-to-edge spacing between them, as shown in Fig. 2. (a). All but two microelectrodes were connected to the on-chip readout circuits through multiplexers.

For the purpose of this study, the two unconnected microelectrodes were used. These were directly connected to peripheral pads of the chip and thus accessible from outside to easily connect to the commercial potentiostat for electrodeposition and readout.

A 7-step process is developed to prepare the gold plated microelectrode. The steps are conceptually illustrated in Fig. 2.

The CMOS chip was prepared through surface cleaning with acetone and IPA to remove contamination as contamination severely affects the adhesion and flatness of microelectrodes. For this step (step a), the chip was placed in a beaker containing acetone, and the beaker was subsequently placed in an ultrasonic cleaner for one minute at room temperature. Then rinse the chip with deionised water. The chip was then placed in a beaker containing isopropyl alcohol, ultrasonically cleaned for one minute at room temperature, and then cleaned with deionised water.

Following the cleaning, the chip was then etched slightly with 10% sodium hydroxide (NaOH) for 2 minutes at room temperature to remove Al oxide from the Al microelectrodes and expose Al.

Step b involves a double zincation process, to achieve a Zn layer on Al to increase the adhesion of the following nickel layer [14], Each single zincate step was carried out by dipping the chip inside a beaker containing 0.5 m of Zn electroless plating solution for 1 minute at 45 °C. After the first zincate, the chip was immersed in a beaker with 20% nitric acid at room temperature for 45 seconds, followed by the second zincate process.

Electroless nickel deposit provides hardness and adhesion for the subsequent process as a barrier layer between the electroless zinc layer and gold layer. An electroless Ni deposition is then carried out (step c). The chip was immersed in 1 ml of Ni electroless plating solution for 25 minutes at 85 °C.

The electroless Au deposition was carried out for 15 minutes at 90 °C.

After depositing a thin layer of Au using the electroless plating methods, the chip was glued to a carrier printed circuit board (PCB) using silver conductive epoxy, and the peripheral pads were connected to PCB pads (step e) to allow electrical connections to the potentiostats. The wires were encapsulated using non-conductive epoxy such that the circuits, peripheral pads and wire bonds are protected while the microelectrodes in the middle of the chip remain exposed. The epoxy was left to cure overnight. A plastic or a glass ring was glued on the PCB on top of the chip using the same non-conductive epoxy, to form a reservoir to contain fluids during the following (Au deposition) step and electrochemical tests and measurements.

Final Au plating was carried out by applying a pulsed current between the microelectrode and a platinised titanium electrode. The counter electrode was cleaned with oxygen plasma prior to electroplating to prevent the electroplating process from being affected by contamination. The average current density applied was set to the minimum current density (1.5 mA/cm² ) suggested for working with the gold electroplating solution (NB Semiplate Au 100. The pulse frequency was set to 100 Hz. A duty cycle of 50% duty cycle was used. The pulsed current (average of 128 nA at a frequency of 100 Hz and 50% duty cycle) was applied to the electrode at room temperature.

The deposition time was varied between 300 s, 600 s, and 900 s. Following deposition, the chips were washed with deionised water before imaging and electrochemical characterisations were carried out. Table 1 provides a summary of the thickness and roughness of each layer.

Table 1

Layer method of deposition Thickness Roughness

(nm) (mean± std. dev.) nm rms

Al none (base layer) 2050 28.4 ± 0.3

Zn electroless 112 ± 15 125.7 ± 16.2

Ni electroless 668 ± 39 72.3 ± 7.6

1st Au electroless 527 ± 21 114.3 ± 11.2

2nd Au 0 s ED* 0 (as ref.) 114.3 ± 11.2

2nd Au 300 s ED 282 ± 31 130 ± 9.6

2nd Au 600 s ED 606 ± 45 83.6 ± 8.7

2nd Au 900 s ED 1883 ± 177 209 ± 17.3

*ED: electrodeposition

Micromorphology

Thickness

The thicknesses of the zinc and nickel layers were calculated by measuring the difference between the heights of the microelectrode and the surrounding passivation layer, before and after layer deposition. The average and standard deviation (from measurements on three electrodes) of the thickness of the zinc and nickel layers are 123 ± 7 nm and 692 ± 45 nm, respectively.

The thickness of the aluminium base layer and electrolessly deposited Au sub-layer was measured by a focus ion beam (FIB). By creating a 2 pm deep, 5 pm by 5 pm hole in the centre of the two gold microelectrodes and observing the cross-section (Fig. 3 (b)), the average and standard deviation of the thickness of aluminium and gold was measured on three microelectrodes to be 2.05 ± 0.02 pm and 527 ± 21 nm, respectively.

The thickness of the electroplated Au layer was acquired by AFM image by taking a line profile over the microelectrode part and the passivation part and comparing the height difference. The size of the AFM image of the device was set to 50 pm (the maximum size the AFM device can be set to) to include the microelectrodes and external passivation layer for reference. The line profile data of the microelectrodes is calculated to obtain their average thickness. The thickness of nine gold-plated microelectrodes with plating times of 300 s, 600 s, and 900 s (three microelectrodes were plated with each plating time) were measured. Fig. 3. (a) shows the thickness of the gold layer increases with increasing electrodeposition time.

Surface Roughness

The roughness of the gold microelectrodes is measured by selecting the area of the microelectrode in the 2-D AFM views to be the largest 50 pm. The average roughness is measured by nine gold microelectrodes with plating times of 300 s, 600 s, and 900 s (three microelectrodes were plated with each plating time), shown in Fig 3 (b).

Figure 3(b) illustrates alteration in the surface roughness of the microelectrode corresponding to the plating time. At an electroplating duration of 300s, the gold deposition uniformly coats the entire microelectrode with small grains. As the plating time extends to 600s, the grains gradually enlarge and exhibit accelerated growth, with clearly visible micrometre-sized grains by 900s. At 600s of plating time, the microelectrode achieves a minimum surface roughness of 83.6±8.7 nm with a thickness of 606±45 nm. The 600 sec is deemed as an optimum time for the electroplating and is applied to prepare all the following Au electroplated microelectronics on the CMOS chip, hereafter referred to as Au microelectrode, for simplicity.

Crystallinity

Cyclic voltammetry (CV) in sulfuric acid was employed to analyse the crystallinity of the microelectrodes.

The cyclic voltammetry measurement (in 0.5 M sulfuric acid with a scan rate of 100 mV/s) using the Au-plated microelectrodes is depicted in Fig. 4, where two sharp peaks are present in the cathodic region, as seen in Fig 4 (a). The presence of oxidative peaks in the cyclic voltammetry of sulfuric acid is indicative of the main contribution of three oriented domains of gold: Au (100), Au (110), and Au (111) progressing from low potential to high potential [15]— [18], It has also been noted in literature that the three peaks may overlap for different electrode geometries where only one or two peaks may be observable in the same region (1.14V to 1.4V) instead of three distinctive peaks [16], It was concluded that the electroplated gold microelectrodes demonstrate crystallised gold characteristics.

Cyclic voltammetry (CV) in sulfuric acid was also employed to analyse the crystallinity of the and electrolessly deposited Au sub-layer. The broad oxidative peak in the voltammogram shown in Fig 4 (b) and lack of two or more distinct peaks is indicative of an amorphous Au layer.

The present invention therefore provides a low-cost methodology for preparing a complementary metal oxide semiconductor comprising one or more electrode.

References

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Claims

1. A method of preparing a complementary metal oxide semiconductor comprising one or more electrode, the method comprising: i) providing a complementary metal oxide semiconductor (CMOS) integrated circuit (IC) having one or more sensor regions, each sensor region comprising a sensing zone and a passivation zone, wherein the passivation zone encircles and directly abuts the sensing zone, and the sensing zone comprises an active layer, an optional adhesive layer; and a conductive base layer; ii) replacing at least part of the active layer with a metal sub-layer by electroless deposition; and iii) pulse current electroplating a crystalline gold surface layer onto the metal sub-layer to form the one or more electrodes.

2. The method of claim 1, wherein the gold surface layer has a thickness of 1 micrometre or less.

3. The method of any one of claim 1 or claim 2 wherein the pulse current electroplating is performed at a current density of from 1.5 to 5 mA/cm², a deposition time of 1200s or less, and a pulse frequency of greater than 10 Hz.

4. The method of any preceding claim wherein the active layer is selected from a layer of copper, a layer of nickel phosphorous, a layer of nickel boron, a layer of nickel, a layer of cobalt or a layer of iron.

5. The method of any preceding claim wherein the active layer is a layer of nickel phosphorous.

6. The method of any preceding claim wherein the adhesive layer is a layer of zinc.

7. The method of any preceding claim wherein the conductive base layer is aluminium.

8. The method of any preceding claim, wherein the metal sub-layer is a layer of silver, platinum or gold, optionally a layer of gold.

9. The method of any preceding claim wherein the step (iii) comprises forming a reaction reservoir around the sensor region before electroplating occurs.

10. The method of any preceding claim, wherein the gold surface layer has a purity of 95% or greater by weight.

11. The method of any preceding claim wherein the complementary metal oxide semiconductor integrated circuit having a sensor region is provided by etching a complementary metal oxide semiconductor to expose the conductive base layer, depositing an adhesive layer onto the conductive base layer by an electroless method, and then depositing the active layer onto the adhesive layer by an electroless method.

12. A complementary metal oxide semiconductor prepared according to the method of any preceding claim.

13. A complementary metal oxide semiconductor having an electrode, the electrode comprising a sensing zone and a passivation zone, wherein the passivation zone encircles and directly abuts the sensing zone, and the sensing zone comprises an amorphous metal sub-layer adjacent to a surface layer, wherein the surface layer is crystalline and the metal sub-layer is amorphous.

14. The complementary metal oxide semiconductor of claims 12 or 13, wherein the surface layer has a surface roughness of 600 nm rms or less.

15. The complementary metal oxide semiconductor of claims 12, 13 or 14, wherein the sub-layer is a silver layer, a platinum layer or a gold layer.

16. The complementary metal oxide semiconductor of claim 11, wherein the surface layer has a thickness of 2.5 micrometres or less, 1 micrometre or less, or 800 nanometres or less.

17. The complementary metal oxide semiconductor of any one of claims 12 to 16, wherein the surface layer has a roughness of 200 nm rms or less, or of 100 nm rms or less.

18. The complementary metal oxide semiconductor of any one of claims 12 to 17, wherein the surface layer comprises at least 95% of gold.

19. An electrochemical apparatus comprising the complementary metal oxide semiconductor of any one of claims 12 to 18.

20. A method for detecting a biomolecule, comprising the steps of: i) providing a sample; ii) providing the electrochemical apparatus of claim 18; iii) exposing the electrode of the electrochemical apparatus to the sample; iv) using a voltametric or amperometric technique to assess the presence of the biomolecule.

21. The method of detecting a biomolecule of claim 20, wherein the technique to assess the presence of the biomolecule is a voltametric technique selected from cyclic voltammetry or Fast Scan Cyclic voltammetry.

22. The method of detecting a biomolecule of claim 20, wherein the technique to assess the presence of the biomolecule is an amperometric technique selected from chronoamperometry.