WO2025251352A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置

Info

Publication number
WO2025251352A1
WO2025251352A1 PCT/CN2024/100209 CN2024100209W WO2025251352A1 WO 2025251352 A1 WO2025251352 A1 WO 2025251352A1 CN 2024100209 W CN2024100209 W CN 2024100209W WO 2025251352 A1 WO2025251352 A1 WO 2025251352A1
Authority
WO
WIPO (PCT)
Prior art keywords
area
display panel
bonding
test
display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2024/100209
Other languages
English (en)
French (fr)
Inventor
马亮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Publication of WO2025251352A1 publication Critical patent/WO2025251352A1/zh
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers

Definitions

  • This application relates to the field of display technology, and more particularly to a display panel and display device.
  • This application provides a display panel and display device that can improve the convenience of testing the touch performance of the display panel and increase the yield rate of the display panel.
  • This application provides a display panel, which includes a display area and a non-display area adjacent to the display area;
  • the display panel also includes:
  • Touch electrodes are disposed within the display area
  • Pixel units are disposed within the display area
  • a driver chip is disposed within the non-display area, the non-display area including a bonding area located on the side of the driver chip away from the display area;
  • the display signal line is connected between the driver chip and the pixel unit;
  • Touch traces connect the touch electrodes and the driver chip
  • the display panel further includes a test trace disposed in the non-display area.
  • One end of the test trace is connected to the touch trace, and the other end of the test trace passes through the bonding area and extends to the outer boundary of the side of the display panel where the bonding area is located.
  • the test trace is located between adjacent bonding terminals.
  • embodiments of this application also provide a display device, the display device including a display panel, the display panel including a display area and a non-display area adjacent to the display area;
  • the display panel also includes:
  • Touch electrodes are disposed within the display area
  • Pixel units are disposed within the display area
  • a driver chip is disposed within the non-display area, the non-display area including a bonding area located on the side of the driver chip away from the display area;
  • the display signal line is connected between the driver chip and the pixel unit;
  • Touch traces connect the touch electrodes and the driver chip
  • the display panel further includes a test trace disposed in the non-display area.
  • One end of the test trace is connected to the touch trace, and the other end of the test trace passes through the bonding area and extends to the outer boundary of the side of the display panel where the bonding area is located.
  • the test trace is located between adjacent bonding terminals.
  • Figure 1 is a schematic diagram of a planar distribution structure of a display panel provided in an embodiment of this application;
  • FIG. 2 is a schematic diagram of another planar distribution structure of the display panel provided in an embodiment of this application.
  • Figure 3 is a schematic diagram of a display panel in a non-display area according to an embodiment of this application.
  • Figure 4 is a schematic diagram of another planar distribution structure of the display panel provided in an embodiment of this application.
  • Figure 5 is a schematic diagram of another structure of the display panel in the binding area provided in the embodiment of this application.
  • Figure 6 is a schematic diagram of another planar distribution structure of the display panel provided in an embodiment of this application.
  • Figure 7 is a schematic diagram of another planar distribution structure of the display panel provided in an embodiment of this application.
  • Figure 8 is a schematic diagram of another planar distribution structure of the display panel provided in an embodiment of this application.
  • Figure 9 is a schematic diagram of another structure of the display panel provided in the embodiment of this application in the non-display area;
  • Figure 10 is a schematic diagram of another planar distribution structure of the display panel provided in an embodiment of this application.
  • Figure 11 is a schematic diagram of a display panel in a non-display area according to an embodiment of this application.
  • Figure 13 is a schematic diagram of a display panel motherboard provided in an embodiment of this application.
  • Figure 14 is a schematic diagram of a display device provided in an embodiment of this application.
  • this application embodiment provides a display panel, which includes a display area 101 and a non-display area 102 adjacent to the display area 101.
  • the display panel also includes a touch electrode 10, a pixel unit (not shown in the figure), a driver chip 20, a display signal line 21, a touch trace 30, and multiple bonding terminals 51; the touch electrode 10 and the pixel unit are disposed within the display area 101; the driver chip 20 is disposed within the non-display area 102, and the non-display area 102 also includes a bonding area 1021 disposed on the side of the driver chip 20 away from the display area 101; the display signal line 21 is connected between the pixel unit and the driver chip 20; the touch trace 30 is connected between the touch electrode 10 and the driver chip 20, and multiple bonding terminals 51 are disposed within the bonding area 1021.
  • the display panel also includes a test trace 41 disposed in the non-display area 101.
  • One end of the test trace 41 is connected to the touch trace 30, and the other end of the test trace 41 passes through the bonding area 1021 and extends to the outer boundary of the side of the display panel where the bonding area 1021 is located.
  • the test trace 41 is located between adjacent bonding terminals 51.
  • this embodiment connects the test trace 41 to the touch trace 30, thereby enabling the test trace 41 to be used to test the touch performance of the display panel.
  • the test trace 41 can still be used to test the touch performance of the display panel, improving the convenience of touch performance testing, preventing defective products from entering subsequent stages, and improving the yield rate of the display panel.
  • the test trace 41 passes through the bonding area 1021 and extends to the outer boundary, so the test terminal connected to the test trace 41 can be cut off after the test is completed, thereby saving space in the display panel.
  • the driver chip includes a first side disposed opposite to the display area and a second side connected to the first side, the display signal line is connected to the first side of the driver chip, and the touch trace is connected to the second side of the driver chip.
  • the bonding area includes a first sub-area and a second sub-area adjacent to the first sub-area.
  • One end of the test trace is connected to the touch trace on the second side of the driver chip, and the other end of the test trace passes through the first sub-area.
  • the second sub-area is located on the side of the test trace away from the driver chip.
  • the bonding terminal includes a first type of bonding terminal disposed in the second sub-area.
  • the display panel further includes a first connecting line
  • the non-display area further includes a functional circuit area.
  • the functional circuit area and the bonding area are located on different sides of the display area.
  • One end of the first connecting line is connected to the first type of bonding terminal, and the other end of the first connecting line extends to the functional circuit area.
  • the first connecting line and the test trace are not overlapped.
  • the bonding area further includes a third sub-region disposed on the side of the first sub-region near the driver chip, and the bonding terminal further includes a second type of bonding terminal disposed in the third sub-region;
  • the display panel also includes a second connecting line, one end of which is connected to the second type of bonding terminal, and the other end of which is connected to the driver chip.
  • the second connecting line does not overlap with the test trace.
  • the display panel further includes a gate driving unit and a lamp testing unit disposed in the functional circuit area, the first connecting line is connected to the gate driving unit and the lamp testing unit, and the second connecting line is electrically connected to the display signal line and the touch trace through the driving chip.
  • the display panel includes a plurality of first-type bonding terminals and a plurality of second-type bonding terminals, wherein the spacing between two adjacent first-type bonding terminals is less than the width of the first sub-area in the direction from the first sub-area to the second sub-area, and the spacing between two adjacent second-type bonding terminals is less than the width of the first sub-area in the direction from the first sub-area to the second sub-area.
  • the display panel further includes a virtual terminal located within the first sub-area, and the virtual terminal and the test trace are arranged adjacent to each other along the direction from the first sub-area to the second sub-area.
  • the switching transistor is in an off state.
  • the display panel further includes a substrate and a gate layer and a source/drain layer disposed on the substrate, and the test trace includes a first line segment located in the bonding region, the first line segment being located in the gate layer or the source/drain layer.
  • the test trace further includes a second line segment connected to the side of the first line segment near the display area, and the distance between the first line segment and the substrate is less than the distance between the second line segment and the substrate.
  • the number of test traces is multiple, and the first segments of two adjacent test traces are set on different layers.
  • the display panel further includes a test terminal connected to the touch trace.
  • the test terminal is disposed on the side of the bonding area close to the driver chip.
  • the display panel further includes an insulating layer that covers the surface of the test terminal.
  • the display panel includes a display area 101 and a non-display area 102 adjacent to the display area 101.
  • the display panel includes a substrate 71 and a display functional layer disposed on the substrate 71.
  • FIG2 only shows a portion of the structure of the display panel located in the non-display area 102, in order to illustrate the improved portion of the display panel in the embodiments of this application.
  • the display functional layer includes a substrate 71, an inorganic stacked layer 72 disposed on the substrate 71, and an organic stacked layer disposed on the inorganic stacked layer 72; and the organic stacked layer includes a planarization layer 74, a pixel definition layer 75, a barrier layer 76, an encapsulation layer 77, and a planarization protection layer 78 disposed sequentially on the inorganic stacked layer 72.
  • the non-display area 102 includes a bending area 1022 near the display area 101, a bonding area 1021 away from the display area 101, and a device area 1023 located between the bending area 1022 and the bonding area 1021;
  • the inorganic stacked layer 72 has an opening in the bending area 1022, and the display panel also includes an organic filler layer 73 filling the opening;
  • the planarization layer 74, pixel definition layer 75, and barrier layer 76 located in the non-display area 102 can also partially cover the organic filler layer 73. Since the organic filler layer 73, pixel definition layer 75, and barrier layer 76 can all be made of organic materials, they can provide effective stress buffering for the portion of the display panel located in the bending area 1022.
  • the display panel also includes a touch electrode 10 disposed in the display area 101, a pixel unit, a driver chip 20 disposed in the non-display area 102, a touch trace 30 connecting the touch electrode 10 and the driver chip 20, and a display signal line 21 connecting the pixel unit and the driver chip 20.
  • the driver chip 20 provided in this application embodiment is a TDDI driver chip that integrates display and touch.
  • the driver chip 20 includes a first side disposed opposite to the display area 101 and a second side connected to the first side.
  • the display signal line 21 is connected to the first side of the driver chip 20, and the touch trace 30 is connected to the second side of the driver chip 20. That is, the driver chip 20 provided in this application embodiment connects the signal lines on multiple sides to avoid multiple signal lines being connected to the same side of the driver chip 20, which would cause mutual interference between different signal lines.
  • one end of the display signal line 21 is connected to a pixel unit in the display area 101, and the other end is connected to the driver chip 20.
  • the driver chip 20 can input display signals, such as data signals and timing signals, to the display signal line 21.
  • the touch electrode 10 can be disposed on the side of the encapsulation layer 77 away from the substrate 71 and covered by the planarization protective layer 78.
  • the driver chip 20 can be disposed in the device area 1023 within the non-display area 102.
  • One end of the touch trace 30 is connected to the touch electrode 10 and is located on the side of the encapsulation layer 77 away from the substrate 71, extending into the non-display area 102.
  • the touch trace 30 When passing through the bending area 1022, the touch trace 30 is located between the organic filling layer 73 and the planarization layer 74. Since both sides of the touch trace 30 are made of organic materials with buffering effect, the bending stress of the touch trace 30 in the bending area 1022 can be reduced.
  • the portion of the touch trace 30 in the device area 1023 can be located between the planarization layer 74 and the inorganic stacked layer 72 and connected to the driver chip 20.
  • the driver chip 20 can then input touch signals to the touch trace 30 and transmit them to the touch electrode 10 to realize the touch function of the display panel.
  • a via 201 is formed on the touch trace 30, and a connector 24 is formed in the via 201.
  • the driver chip 20 can be connected to the touch trace 30 through the connector 24.
  • the display panel further includes a plurality of bonding terminals 51 disposed in the bonding area 1021, which can be used to bond and connect with devices such as flexible circuit boards.
  • a test trace 41 is added to the display panel.
  • the test trace 41 is located in the non-display area 102 and is connected to the touch trace 30. It can be connected to the part of the touch trace 30 located in the device area 1023, and further connected to the part of the touch trace 30 before it enters the driver chip 20. That is, the test trace 41 is connected to the touch trace 30 on the second side of the driver chip 20.
  • the other end of the test trace 41 passes through the bonding area 1021 and extends to the outer boundary of the side of the display panel where the bonding area 1021 is located, and the test trace 41 is located between adjacent bonding terminals 51.
  • some signals can be transmitted in-plane through the driver chip 20, such as DOT trace signals, guard signals, and PCD signals. Therefore, compared with the solution where touch and display are driven by two separate ICs, the number of bonding terminals 51 in the display panel provided in this application embodiment is greatly reduced. For example, the number of bonding pads in the existing panel is about 56, while the number of bonding terminals 51 in this application embodiment can be reduced to about 8.
  • the display panel includes test traces 41. It should be noted that since the test terminals 42 are located outside the display panel and need to be cut off after the touch performance test is completed, the display panel provided in this embodiment does not have test terminals 42.
  • test trace 41 is connected to the touch trace 30, and the other end of the test trace 41 extends toward the display area 101 near the bonding area 1021, and extends through the bonding area 1021 to the outer boundary of the display panel on the side where the bonding area 1021 is located.
  • the test terminal 42 is located outside the display panel and can be located on the side of the display panel where the bonding area 1021 is provided.
  • the test trace 41 extends to one end of the outer boundary of the display panel and connects to the test terminal 42. After the touch performance test is completed, the test terminal 42 is cut along the outer boundary of the display panel to remove it.
  • the arrangement of the bonding terminals 51 in this embodiment is designed to reduce the adverse effects caused by the test trace 41 passing through the bonding area 1021.
  • the bonding area 1021 includes a first sub-area A and a second sub-area B, and the first sub-area A and the second sub-area B are arranged in a direction perpendicular to the display area 101 and close to the bonding area 1021; one end of the test trace 41 is connected to the touch trace 30 on the second side of the driver chip 20, and the other end of the test trace 41 passes through the first sub-area A.
  • the second sub-area B is located on the side of the test trace 41 away from the driver chip 20.
  • the bonding terminal 51 includes a first type of bonding terminal 511 disposed in the second sub-area B.
  • the display panel also includes a first connecting line 22, and the non-display area 102 also includes a functional circuit area 1024.
  • the functional circuit area 1024 and the bonding area 1021 are located on different sides of the display area 101.
  • One end of the first connecting line 22 is connected to the first type of bonding terminal 511, and the other end of the first connecting line 22 extends to the functional circuit area 1024.
  • the first connecting line 22 and the test trace 41 are not overlapped, that is, the first connecting line 22 is not connected to the driver chip 20.
  • the display panel further includes a gate driving unit and a lamp testing unit disposed in the functional circuit area 1024, and the first connecting line 22 is connected to the gate driving unit and the lamp testing unit.
  • the bonding area 1021 further includes a third sub-area C disposed on the side of the first sub-area A near the driver chip 20, and the bonding terminal 51 further includes a second type of bonding terminal 512 disposed in the third sub-area C; the display panel further includes a second connecting line 23, one end of the second connecting line 23 is connected to the second type of bonding terminal 512, and the other end of the second connecting line 23 is connected to the driver chip 20, and the second connecting line 23 is not overlapped with the test trace 41.
  • the second connection line 23 is electrically connected to the display signal line 21 and the touch trace 30 through the driver chip 20, that is, the signals in the display signal line 21 and the touch trace 30 can be transmitted through the second connection line 23.
  • the number of bonding terminals 51 is greatly reduced relative to the display technology, in order to facilitate the test trace 41 passing through the bonding area 1021.
  • the arrangement design of the multiple bonding terminals 51 in this application embodiment is such that the first type of bonding terminal 511 that does not need to be connected to the driver chip 20 is set on the side of the test trace 41 away from the driver chip 20, and the second type of bonding terminal 512 that needs to be connected to the driver chip 20 is set on the side of the test trace 41 close to the driver chip 20.
  • neither the first connecting line 22 nor the second connecting line 23 overlaps with the test trace 41, reducing the interference between the first connecting line 22, the second connecting line 23 and the test trace 41.
  • the display panel includes a plurality of first-type bonding terminals 511 and a plurality of second-type bonding terminals 512, and the spacing between two adjacent first-type bonding terminals 511 is less than the width of the first sub-region A in the direction from the first sub-region A to the second sub-region B, and the spacing between two adjacent second-type bonding terminals 512 is less than the width of the first sub-region A in the direction from the first sub-region A to the second sub-region B, thereby providing sufficient space for the arrangement of test traces 41.
  • multiple binding terminals 51 are located within a second sub-region B and a third sub-region C, while test terminals 42 are aligned with the first sub-region A along the direction of the display area 101 near the binding area 1021.
  • the ACF adhesive may overflow. Therefore, by not setting the bonding terminal 51 in the first sub-area A, the amount of ACF adhesive overflow in the first sub-area A can be effectively reduced, and the phenomenon of short circuit caused by the test terminal 42 connecting with the overflowing ACF adhesive can be avoided.
  • this embodiment of the application sets up a test trace 41 connected to the touch trace 30 and connects the test trace 41 to the test terminal 42.
  • This allows the test terminal 42 to be used to test the touch performance of the display panel, improving the convenience of touch performance testing of the display panel, preventing defective products from entering subsequent processes, and improving the yield rate of the display panel.
  • the test terminal 42 can be set in other areas according to actual needs, rather than being limited to the touch trace 30.
  • the arrangement of the bonding terminals 51 in this embodiment is designed to provide ample space for the test traces 41 and reduce interference between the test traces 41 and other connecting lines.
  • a first sub-region A is formed within the bonding area 1021 to align with the test terminals 42, and multiple bonding terminals 51 are located outside the first sub-region A. This effectively reduces the amount of ACF adhesive overflow in the first sub-region A, preventing short circuits caused by the test terminals 42 connecting with overflowing ACF adhesive, reducing the probability of short circuits between touch traces 30, and improving the stability of the display panel.
  • the test terminals 42 outside the display panel in this embodiment they can be removed during the manufacturing process, thereby reducing the area occupied by the test terminals 42 in the display panel and increasing the wiring space in the display panel.
  • the display panel includes test terminals 42 and test traces 41. It should be noted that since the test terminals 42 are located outside the display panel and need to be cut off after the touch performance test is completed, the display panel provided in this embodiment does not have test terminals 42.
  • test trace 41 is connected to the touch trace 30, and the other end of the test trace 41 extends toward the display area 101 near the bonding area 1021, and extends through the bonding area 1021 to the outer boundary of the display panel on the side where the bonding area 1021 is located.
  • the test terminal 42 is located outside the display panel and can be located on the side of the display panel where the bonding area 1021 is provided.
  • the test trace 41 extends to one end of the outer boundary of the display panel and connects to the test terminal 42. After the touch performance test is completed, the test terminal 42 is cut along the outer boundary of the display panel to remove it.
  • the display panel also includes a virtual terminal 52 disposed in the first sub-region A. Since the multiple bonding terminals 51 are all located outside the first sub-region A, the distribution of the multiple bonding terminals 51 is uneven. As a result, after bonding and connecting in the bonding area 1021, uneven stress distribution is likely to occur, causing the display panel to bend or deform. Therefore, this embodiment of the application improves the uneven stress distribution by forming a virtual terminal 52 in the first sub-region A, thereby improving the yield of the display panel.
  • virtual terminal 52 does not transmit signals.
  • the display panel includes a gate layer 91 and a source/drain layer 92 disposed on the substrate 71
  • the test trace 41 includes a first segment 411 located in the bonding region 1021.
  • the first segment 411 is located in the gate layer 91 or the source/drain layer 92.
  • the gate layer 91 and the source/drain layer 92 are both covered in the inorganic stacked layer 72 and are located between the film layer where the touch trace 30 is located and the substrate 71, and the gate layer 91 is located between the source/drain layer 92 and the substrate 71.
  • the test trace 41 further includes a second trace 412 connected to the side of the first trace 411 near the display area 101, and the distance between the first trace 411 and the substrate 71 is smaller than the distance between the second trace 412 and the substrate 71. It is understood that since the first trace 411 is located in the bonding area 1021, and the bonding area 1021 needs to be pressed and bonded, the film layer located in the bonding area 1021 will be squeezed and there is a risk of the film layer being squeezed and broken.
  • the first trace 411 is set closer to the substrate 71, which can reduce the probability of short circuit between the first trace 411 and the bonding terminal 51, or between the first trace 411 and the first trace 411, due to the film layer breaking, thereby improving the bonding yield of the display panel.
  • first segments 411 are set in different layers, that is, in two adjacent first segments 411, one is located in the gate layer 91 and the other is located in the source-drain layer 92. This can reduce the probability of short circuits between adjacent first segments 411 due to film layer rupture, and improve the bonding yield of the display panel.
  • the gate layer 91 can be at least two layers, and the source and drain layers 92 can also be at least two layers. Then, the adjacent first segments 411 are located in two different film layers in the at least two gate layers 91 and the at least two source and drain layers 92.
  • the test terminal 42 forms a transition layer through the same material of the source-drain layer 92 and the gate layer 91, and is connected to the test trace 41. After the touch test is completed, the test terminal 42 is cut off.
  • this embodiment of the application by setting a test trace 41 connected to the touch trace 30 and connecting the test trace 41 to the test terminal 42, allows the touch performance of the display panel to be tested using the test terminal 42. This improves the convenience of touch performance testing of the display panel, prevents defective products from entering subsequent stages, and increases the yield rate of the display panel. Furthermore, by connecting the test terminal 42 to the touch trace 30 through the test trace 41, the test terminal 42 can be placed in other areas according to actual needs, rather than being limited to the touch trace 30. In addition, a virtual terminal 52 is added in the first sub-area A to improve stress.
  • the uneven distribution phenomenon improves the yield of the display panel; in this embodiment, the test terminal 42 is set in an area outside the display panel, which can be removed during the manufacturing process, thereby reducing the area occupied by the test terminal 42 in the display panel and increasing the wiring space in the display panel; in this embodiment, by setting the first line segment 411 closer to the substrate 71 and setting adjacent first line segments 411 on different film layers, the probability of short circuit between the first line segment 411 and the bonding terminal 51 or between the first line segments 411 and the first line segments 411 due to film layer breakage can be reduced, thereby improving the bonding yield of the display panel.
  • the difference between this embodiment and Figure 4 is that the display panel further includes a switch tube 43 connected to the test trace 41.
  • the switch tube 43 is located on the side of the bonding area 1021 near the display area 101 to control the on/off state of the signal in the test trace 41.
  • the switching transistor 43 may include a MOSFET, wherein the source and drain ends of the switching transistor 43 are respectively connected to the test trace 41, and the gate end of the switching transistor 43 is connected to a test terminal 42 through a bonding terminal 51, and the test terminal 42 can be used to control the on/off state of the switching transistor 43; thereby, during the touch performance test of the display panel, the test equipment transmits test signals to the test terminal 42, including test touch signals transmitted to the test terminal 42 connected to the test trace 41, and turn-on signals to turn on the switching transistor 43 transmitted to the test terminal 42 connected to the gate end of the switching transistor 43, so that the signals in the test trace 41 can be transmitted normally; and after the test is completed, the test terminal 42 is disconnected.
  • the switch 43 is in the off state. It should be noted that in this embodiment, by adding the switch 43 in the test trace 41, and the switch 43 is in the off state after the test is completed, at the outer boundary of the side of the display panel where the bonding area 1021 is located, the cutting process can easily cause short circuits between the cross sections of adjacent test traces 41, or when the flexible circuit board 80 is pressed and bonded with the bonding terminal 51, the ACF glue may overflow, causing short circuits between adjacent test traces 41. Therefore, in this embodiment, the switch 43 is in the off state, which can reduce the probability of short circuits between adjacent test traces 41 and the probability of short circuits between adjacent touch traces 30, thereby improving the touch stability and touch effect of the display panel.
  • this embodiment of the application sets up a test trace 41 connected to the touch trace 30 and connects the test trace 41 to the test terminal 42.
  • This allows the test terminal 42 to be used to test the touch performance of the display panel, improving the convenience of touch performance testing, preventing defective products from entering subsequent stages, and increasing the yield rate of the display panel.
  • the test terminal 42 can be placed in other areas according to actual needs, rather than being limited to the touch trace 30.
  • a first sub-region A is formed within the bonding area 1021, aligned with the test terminal 42, and multiple bonding terminals 51 are located outside the first sub-region A.
  • test terminal 42 is located outside the display panel, allowing it to be cut off during the manufacturing process, thereby reducing the area occupied by the test terminal 42 in the display panel and increasing the wiring space in the display panel.
  • the probability of short circuits between the first line segment 411 and the bonding terminal 51, or between the first line segments 411 and the first line segments 411, due to film layer breakage can be reduced, thus improving the bonding yield of the display panel.
  • a switching transistor 43 is added to the path of the test line 41, thereby avoiding the phenomenon that short circuits occur between adjacent test lines 41 due to cutting at the outer boundary of the side where the bonding area 1021 is located on the display panel, which would cause short circuits in adjacent touch lines 30, thus improving the touch stability and touch effect of the display panel.
  • the test terminal 42 can also be directly disposed on the test trace 41, and the test terminal 42 needs to be disposed on the side of the bonding area 1021 close to the display area 101 to avoid the test terminal 42 affecting the bonding process; the display panel also includes an insulating layer 61 covering the surface of the test terminal 42 to provide insulation. Since the test terminal 42 does not need to be powered after the touch test is completed, the insulating layer 61 is used to cover it.
  • the material of the insulating layer 61 may include UV adhesive.
  • the display panel includes a test terminal 42, which is connected to the touch trace 30.
  • the test terminal 42 can be directly disposed on the touch trace 30; that is, a first opening 401 and a second opening 402 located in the device area 1023 can be formed in the planarization layer 74 to expose a portion of the surface of the touch trace 30 away from the substrate 71.
  • the test terminal 42 can fill the first opening 401 and be connected to the touch trace 30.
  • a chip connection terminal can be disposed in the second opening 402, and the driver chip 20 can be connected to the touch trace 30 through the chip connection terminal. It is understood that the planarization protective layer 78 above the first opening 401 and the second opening 402 can be removed to facilitate the bonding of the driver chip 20 and the connection between the test equipment and the test terminal 42 when the display panel is tested for touch performance.
  • the spacing between adjacent test terminals 42 is greater than or equal to the spacing between adjacent chip connection terminals, and less than or equal to the spacing between adjacent bonding terminals 51.
  • the display panel includes multiple touch traces 30 and multiple test traces 41, and the multiple test traces 41 can be connected one-to-one with the multiple touch traces 30.
  • the multiple test traces 41 can be connected one-to-one with the multiple touch traces 30.
  • only one touch trace 30 and one test trace 41 connected in this embodiment are used as examples for explanation.
  • touch signals can be input to the touch trace 30 through the test terminal 42 to perform touch performance testing on the display panel.
  • an insulating layer 61 can be used to cover the top of the first opening 401 to isolate the test terminal 42 from the outside world.
  • the material of the insulating layer 61 may include UV adhesive.
  • this embodiment of the application directly sets the test terminal 42 on the touch trace 30, thereby enabling the test terminal 42 to be used to test the touch performance of the display panel. This improves the convenience of touch performance testing of the display panel, prevents defective products from entering subsequent processes, and improves the yield rate of the display panel.
  • the display panel includes a test terminal 42 and a test trace 41.
  • One end of the test trace 41 is connected to the touch trace 30, and the other end of the test trace 41 extends toward the display area 101 toward the driver chip 20 and is connected to the test terminal 42.
  • the test terminal 42 is located on the side of the bonding area 1021 near the driver chip 20, that is, the test terminal 42 is located on the side of the bonding area 1021 near the display area 101, and the bonding terminals 51 can be distributed at equal intervals in the bonding area 1021, or the test terminal 42 and the bonding terminal 51 can be partially overlapped along the direction of the display area 101 near the bonding area 1021.
  • vias 201 can be formed on the planarization layer 74, and the driver chip 20 can be bonded and connected to the touch trace 30 through the vias 201, as not shown in Figure 11.
  • this embodiment of the application sets up a test trace 41 connected to the touch trace 30 and connects the test trace 41 to the test terminal 42.
  • This allows the test terminal 42 to be used to test the touch performance of the display panel, improving the convenience of touch performance testing of the display panel, preventing defective products from entering subsequent processes, and improving the yield rate of the display panel.
  • the test terminal 42 can be set in other areas according to actual needs, rather than being limited to the touch trace 30.
  • the spacing between two adjacent bonding terminals 51 is less than the width of the first sub-region A along the extension direction perpendicular to the test trace 41.
  • the bonding area 1021 needs to be bonded to the flexible circuit board 80 and can be bonded by anisotropic conductive film (ACF), when the flexible circuit board 80 is pressed and bonded to the bonding terminal 51, the ACF adhesive may overflow. Therefore, by not setting the bonding terminal 51 in the first sub-area A, the amount of ACF adhesive overflow in the first sub-area A can be effectively reduced, and the phenomenon of short circuit caused by the test terminal 42 connecting with the overflowing ACF adhesive can be avoided.
  • ACF anisotropic conductive film
  • this embodiment of the application sets up a test trace 41 connected to the touch trace 30 and connects the test trace 41 to the test terminal 42.
  • This allows the test terminal 42 to be used to test the touch performance of the display panel, improving the convenience of touch performance testing, preventing defective products from entering subsequent stages, and increasing the yield rate of the display panel.
  • the test terminal 42 can be placed in other areas according to actual needs, rather than being limited to the touch trace 30.
  • a first sub-region A is formed within the bonding area 1021, aligned with the test terminal 42, and multiple bonding terminals 51 are located outside the first sub-region A. This effectively reduces the amount of ACF adhesive overflow in the first sub-region A, preventing short circuits caused by the test terminal 42 connecting to overflowing ACF adhesive, reducing the probability of short circuits between touch traces 30, and improving the stability of the display panel.
  • this application embodiment also provides a display panel motherboard 100.
  • the display panel motherboard 100 includes at least two sub-boards 1001 and a cutting area 1002 located outside the sub-boards 1001.
  • the sub-boards 1001 include a display area 101 and a non-display area 102 adjacent to the display area 101.
  • the daughter board 1001 also includes a touch electrode 10, a driver chip 20, and touch traces 30.
  • the touch electrode 10 is disposed in the display area 101; the driver chip 20 is disposed in the non-display area 102; the touch traces 30 are connected between the touch electrode 10 and the driver chip 20; wherein, the daughter board 1001 also includes at least a test trace 41 disposed in the non-display area 102, and the test trace 41 is connected to the touch traces 30.
  • the resulting daughter board 1001 is obtained after bonding and other processes to obtain the display panel described in the above embodiment. Therefore, the setting method of the test trace 41 and the connection method between the daughter board 1001 and the touch trace 30 can be set with reference to the above embodiment.
  • the display panel includes a test trace 41 and a test terminal 42.
  • the test terminal 42 is located in the cutting area 1002.
  • One end of the test trace 41 is connected to the touch trace 30, and the other end of the test trace 41 extends to the outside of the sub-board 1001 and is connected to the test terminal 42, as shown in FIG1.
  • the non-display area 102 includes a bending area 1022 on the side close to the display area 101, a bonding area 1021 on the side away from the display area 101, and a device area 1023 located between the bending area 1022 and the bonding area 1021, and the driver chip 20 is disposed in the device area 1023.
  • the display panel includes a test terminal 42 connected to the touch trace 30, as shown in FIG8.
  • the display panel includes a test trace 41 and a test terminal 42.
  • the test terminal 42 is located on the side of the bonding area 1021 near the driver chip 20.
  • One end of the test trace 41 is connected to the touch trace 30, and the other end of the test trace 41 is connected to the test terminal 42, as shown in FIG9.
  • the display panel motherboard 100 has the same beneficial effect as the display panel described in the above embodiment, and will not be repeated here.
  • this application embodiment also provides a display device 90, which includes the display panel 901 described in the above embodiments.
  • this embodiment of the application connects the test trace 41 to the touch trace 30, thereby enabling the test trace 41 to be used to test the touch performance of the display panel.
  • the touch performance of the display panel can still be tested through the test trace 41, which improves the convenience of touch performance testing of the display panel, prevents defective products from entering subsequent processes, and improves the yield rate of the display panel.

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Position Input By Displaying (AREA)

Abstract

本申请公开了一种显示面板及显示装置；其中，显示信号线连接于驱动芯片和像素单元之间；触控走线连接于触控电极和驱动芯片之间；绑定端子设置于绑定区内；测试走线的一端连接于触控走线，测试走线的另一端穿过绑定区，并延伸至显示面板设有绑定区一侧的外边界，且测试走线位于相邻的绑定端子之间。

Description

显示面板及显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板及显示装置。
 背景技术
触控与显示驱动器集成(Touch and Display Driver Integration，TDDI)是将显示面板中的触控芯片与显示芯片整合进单一芯片中，可以提高显示面板的集成度，简化显示面板的结构。
目前，在采用TDDI技术的显示面板中，在进行触控性能测试时，集成之后的芯片来输入测试信号，因此，在芯片未绑定之前则无法完成触控性能测试，容易导致异常产品进入后续工段，不利于显示面板的良品率的提高。
 发明概述
本申请实施例提供一种显示面板及显示装置，能够提高显示面板触控性能测试的便捷性，提高显示面板的良品率。
本申请实施例提供一种显示面板，所述显示面板包括显示区以及与所述显示区相邻的非显示区；
所述显示面板还包括：
触控电极，设置于所述显示区内；
像素单元，设置于所述显示区内；
驱动芯片，设置于所述非显示区内，所述非显示区包括位于所述驱动芯片远离所述显示区一侧的绑定区；
显示信号线，连接于所述驱动芯片和所述像素单元之间；
触控走线，连接于所述触控电极和所述驱动芯片之间；
多个绑定端子，设置于所述绑定区内；
其中，所述显示面板还包括设置于所述非显示区内的测试走线，所述测试走线的一端连接于所述触控走线，所述测试走线的另一端穿过所述绑定区，并延伸至所述显示面板设有所述绑定区一侧的外边界，且所述测试走线位于相邻的所述绑定端子之间。
根据本申请的上述目的，本申请实施例还提供一种显示装置，所述显示装置包括显示面板，所述显示面板包括显示区以及与所述显示区相邻的非显示区；
所述显示面板还包括：
触控电极，设置于所述显示区内；
像素单元，设置于所述显示区内；
驱动芯片，设置于所述非显示区内，所述非显示区包括位于所述驱动芯片远离所述显示区一侧的绑定区；
显示信号线，连接于所述驱动芯片和所述像素单元之间；
触控走线，连接于所述触控电极和所述驱动芯片之间；
多个绑定端子，设置于所述绑定区内；
其中，所述显示面板还包括设置于所述非显示区内的测试走线，所述测试走线的一端连接于所述触控走线，所述测试走线的另一端穿过所述绑定区，并延伸至所述显示面板设有所述绑定区一侧的外边界，且所述测试走线位于相邻的所述绑定端子之间。
 附图说明
图1为本申请实施例提供的显示面板的一种平面分布结构示意图；
图2为本申请实施例提供的显示面板的另一种平面分布结构示意图；
图3为本申请实施例提供的显示面板在非显示区内的一种结构示意图；
图4为本申请实施例提供的显示面板的另一种平面分布结构示意图；
图5为本申请实施例提供的显示面板在绑定区内的另一种结构示意图；
图6为本申请实施例提供的显示面板的另一种平面分布结构示意图；
图7为本申请实施例提供的显示面板的另一种平面分布结构示意图；
图8为本申请实施例提供的显示面板的另一种平面分布结构示意图；
图9为本申请实施例提供的显示面板在非显示区内的另一种结构示意图；
图10为本申请实施例提供的显示面板的另一种平面分布结构示意图；
图11为本申请实施例提供的显示面板在非显示区内的一种结构示意图；
图12为本申请实施例提供的显示面板的另一种平面分布结构示意图；
图13为本申请实施例提供的显示面板母板的一种结构示意图；
图14为本申请实施例提供的显示装置的一种结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
显示面板在触控性能测试时需要驱动芯片来输入测试信号，因此，在芯片未绑定之前则无法完成触控性能测试，降低了显示面板触控性能测试的便捷性，容易导致异常产品进入后续工段，不利于显示面板的良品率的提高。
请参照图1，本申请实施例提供一种显示面板，该显示面板包括显示区101以及与显示区101相邻的非显示区102。
进一步地，显示面板还包括触控电极10、像素单元（图中未示出）、驱动芯片20、显示信号线21、触控走线30以及多个绑定端子51；触控电极10和像素单元设置于显示区101内；驱动芯片20设置于非显示区102内，非显示区102还包括设置于驱动芯片20远离显示区101一侧的绑定区1021；显示信号线21连接于像素单元和驱动芯片20之间；触控走线30连接于触控电极10和驱动芯片20之间，多个绑定端子51设置于绑定区1021内。
其中，显示面板还包括设置于非显示区101内的测试走线41，测试走线41的一端连接于触控走线30，测试走线41的另一端穿过绑定区1021，并延伸至显示面板设有绑定区1021一侧的外边界，且测试走线41位于相邻的绑定端子51之间。
在实施应用过程中，本申请实施例通过在触控走线30上连接测试走线41，进而可以采用测试走线41来对显示面板进行触控性能的测试；例如在未绑定驱动芯片20的情况下，也能通过测试走线41来对显示面板进行触控性能的测试，提高了显示面板触控性能测试的便捷性，避免了异常产品进入后续工段，提高显示面板的良品率；测试走线41穿过绑定区1021并延伸至外边界处，进而与测试走线41连接的测试端子可以在测试完成之后切除，以节省显示面板中的空间。
在本申请的一种实施例中，所述驱动芯片包括与所述显示区相对设置的第一侧以及连接于所述第一侧的第二侧，所述显示信号线连接于所述驱动芯片的所述第一侧，所述触控走线连接于所述驱动芯片的所述第二侧。
在本申请的一种实施例中，所述绑定区包括第一子区以及与所述第一子区相邻的第二子区，所述测试走线的一端在所述驱动芯片的所述第二侧连接于所述触控走线，所述测试走线的另一端穿过所述第一子区，所述第二子区位于所述测试走线远离所述驱动芯片的一侧，所述绑定端子包括设置于所述第二子区内的第一类绑定端子；
所述显示面板还包括第一连接线，所述非显示区还包括功能电路区，所述功能电路区与所述绑定区位于所述显示区的不同侧，所述第一连接线的一端连接于所述第一类绑定端子，所述第一连接线的另一端延伸至所述功能电路区，且所述第一连接线与所述测试走线不重叠设置。
在本申请的一种实施例中，所述绑定区还包括设置于所述第一子区靠近所述驱动芯片一侧的第三子区，所述绑定端子还包括设置于所述第三子区内的第二类绑定端子；
所述显示面板还包括第二连接线，所述第二连接线的一端连接于所述第二类绑定端子，所述第二连接线的另一端连接于所述驱动芯片，所述第二连接线与所述测试走线不重叠设置。
在本申请的一种实施例中，所述显示面板还包括设置于所述功能电路区内的栅极驱动单元以及点灯测试单元，所述第一连接线连接于所述栅极驱动单元以及所述点灯测试单元，所述第二连接线通过所述驱动芯片与所述显示信号线以及所述触控走线电性连接。
在本申请的一种实施例中，所述显示面板包括多个所述第一类绑定端子以及多个所述第二类绑定端子，且相邻两所述第一类绑定端子之间的间距小于所述第一子区沿所述第一子区指向所述第二子区的方向上的宽度，相邻两所述第二类绑定端子之间的间距小于所述第一子区沿所述第一子区指向所述第二子区的方向上的宽度。
在本申请的一种实施例中，所述显示面板还包括虚拟端子，所述虚拟端子位于所述第一子区内，所述虚拟端子与所述测试走线沿所述第一子区指向所述第二子区的方向上相邻设置。
在本申请的一种实施例中，所述显示面板还包括连接于所述测试走线上的开关管，所述开关管位于所述绑定区靠近所述显示区的一侧，以控制所述测试走线中信号的通断。
在本申请的一种实施例中，所述开关管处于断开状态。
在本申请的一种实施例中，所述显示面板还包括基板以及设置于所述基板上的栅极层和源漏极层，所述测试走线包括位于所述绑定区内的第一线段，所述第一线段位于所述栅极层或者所述源漏极层。
在本申请的一种实施例中，所述测试走线还包括连接于所述第一线段靠近所述显示区一侧的第二线段，且所述第一线段与所述基板之间的间距小于所述第二线段与所述基板之间的间距。
在本申请的一种实施例中，所述测试走线的数量为多根，相邻两根所述测试走线的所述第一线段不同层设置。
在本申请的一种实施例中，所述显示面板还包括测试端子，所述测试端子连接于所述触控走线。
在本申请的一种实施例中，所述测试端子设置于所述绑定区靠近所述驱动芯片的一侧。
在本申请的一种实施例中，所述显示面板还包括绝缘层，所述绝缘层覆盖于所述测试端子的表面上。
具体地，请结合图1、图2以及图3，显示面板包括显示区101以及与显示区101相邻的非显示区102。
进一步地，显示面板包括基板71以及设置于基板71上的显示功能层，图2中仅示出显示面板位于非显示区102内的部分结构，以对本申请实施例中对显示面板的改进部分进行说明。
其中，显示功能层包括基板71、设置于基板71上的无机堆叠层72、设置于无机堆叠层72上的有机堆叠层；且有机堆叠层包括依次设置于无机堆叠层72上的平坦层74、像素定义层75、挡墙层76、封装层77以及平坦保护层78。
在一种实施例中，非显示区102包括靠近显示区101一侧的弯折区1022、远离显示区101一侧的绑定区1021以及位于弯折区1022和绑定区1021之间的器件区1023；无机堆叠层72在弯折区1022内形成有开口，且显示面板还包括填充于开口内的有机填充层73，而位于非显示区102内的平坦层74、像素定义层75和挡墙层76也可以部分覆盖于有机填充层73的上方，由于有机填充层73、像素定义层75以及挡墙层76均可以采用有机材料进行制备，进而可以对显示面板位于弯折区1022内的部分提供有效的应力缓冲作用。
进一步地，显示面板还包括设置于显示区101内的触控电极10、像素单元、设置于非显示区102内的驱动芯片20、连接于触控电极10和驱动芯片20之间的触控走线30、连接于像素单元和驱动芯片20之间的显示信号线21，即本申请实施例提供的驱动芯片20为显示与触控集成的TDDI驱动芯片。
在一种实施例中，驱动芯片20包括与显示区101相对设置的第一侧以及连接于第一侧的第二侧，显示信号线21连接于驱动芯片20的第一侧，触控走线30连接于驱动芯片20的第二侧，即本申请实施例提供的驱动芯片20在多侧进行信号线的连接，避免多种信号线连接于驱动芯片20的同一侧而导致不同信号线之间相互干扰。
在一种实施例中，显示信号线21的一端连接于显示区101内的像素单元，另一端连接于驱动芯片20，驱动芯片20可以向显示信号线21输入显示信号，例如数据信号、以及时序信号等。
在一种实施例中，触控电极10可以设置于封装层77远离基板71的一侧并被平坦保护层78覆盖，驱动芯片20可以设置于非显示区102内的器件区1023内；触控走线30的一端连接于触控电极10，并位于封装层77远离基板71的一侧，且延伸至非显示区102内，在经过弯折区1022时，触控走线30位于有机填充层73和平坦层74之间，由于触控走线30两侧均为具有缓冲作用的有机材料，进而可以减小触控走线30在弯折区1022内受到的弯折应力；触控走线30在器件区1023内的部分可以位于平坦层74和无机堆叠层72之间，并与驱动芯片20相连接，进而可以通过驱动芯片20向触控走线30输入触控信号，并传输至触控电极10中，以实现显示面板的触控功能。
其中，在器件区1023内，触控走线30上形成过孔201，并在过孔201内形成连接件24，而驱动芯片20可以通过连接件24与触控走线30进行连接。
在一种实施例中，显示面板还包括设置于绑定区1021内的多个绑定端子51，可以用于与柔性线路板等器件进行绑定连接。
在本申请实施例中，为了便于显示面板进行触控性能的测试，本申请实施例在显示面板中增设测试走线41，且测试走线41设置于非显示区102内，并与触控走线30相连接，且可以连接于触控走线30位于器件区1023内的部分，进一步可以连接于触控走线30进入驱动芯片20之前的部分，即测试走线41在驱动芯片20的第二侧连接于触控走线30。
进一步地，测试走线41的另一端穿过绑定区1021，并延伸至显示面板设有绑定区1021一侧的外边界，且测试走线41位于相邻的绑定端子51之间；需要说明的是，由于本申请采用TDDI集成芯片，将触控和显示功能进行结合，进而部分信号可以通过驱动芯片20向面内进行传输，例如DOT trace信号、guard信号、以及PCD信号等；因此，本申请实施例提供的显示面板相较于触控和显示分成两个IC进行驱动的方案而言，绑定端子51的数量大大减少了，例如现有面板的bonding pad数量约56个，而本申请实施例中绑定端子51的数量可以减少至8个左右，这就为本申请实施例中的测试走线41穿过绑定区1021提供了前提条件，即为测试走线41提供了充裕的空间，使得测试走线41更容易穿过绑定区1021，并与切割前位于面板区域外的测试端子进行连接。
在本申请的一种实施例中，请结合图1以及图2，显示面板包括测试走线41，需要说明的是，由于测试端子42设置于显示面板以外的区域，且在触控性能测试完成之后，需要进行切除，因此，本实施例提供的显示面板中并不具备测试端子42。
其中，测试走线41的一端连接于触控走线30，测试走线41的另一端朝着显示区101靠近绑定区1021的方向延伸，并穿过绑定区1021延伸至显示面板设有绑定区1021一侧的外边界。
测试端子42位于显示面板以外，并可以位于显示面板设有绑定区1021的一侧，进而测试走线41延伸至显示面板外边界的一端与测试端子42相连接，且在触控性能测试完成之后，沿显示面板的外边界进行切割，以去除测试端子42。
在本实施例中，由于测试走线41需要穿过绑定区1021，且绑定区1021内设置有多个绑定端子51，因此，本申请实施例对绑定端子51的排布进行设计，以减小测试走线41穿过绑定区1021造成的不良影响。
在一种实施例中，绑定区1021包括第一子区A以及第二子区B，且第一子区A和第二子区B沿垂直于显示区101靠近绑定区1021的方向上排列；测试走线41的一端在驱动芯片20的第二侧连接于触控走线30，测试走线41的另一端穿过第一子区A，第二子区B位于测试走线41远离驱动芯片20的一侧，绑定端子51包括设置于第二子区B内的第一类绑定端子511；显示面板还包括第一连接线22，非显示区102还包括功能电路区1024，功能电路区1024与绑定区1021位于显示区101的不同侧，第一连接线22的一端连接于第一类绑定端子511，第一连接线22的另一端延伸至功能电路区1024，且第一连接线22与测试走线41不重叠设置，即第一连接线22不与驱动芯片20连接。
在一种实施例中，显示面板还包括设置于功能电路区1024内的栅极驱动单元以及点灯测试单元，第一连接线22连接于栅极驱动单元以及点灯测试单元。
在一种实施例中，绑定区1021还包括设置于第一子区A靠近驱动芯片20一侧的第三子区C，绑定端子51还包括设置于第三子区C内的第二类绑定端子512；显示面板还包括第二连接线23，第二连接线23的一端连接于第二类绑定端子512，第二连接线23的另一端连接于驱动芯片20，第二连接线23与测试走线41不重叠设置。
在一种实施例中，第二连接线23通过驱动芯片20与显示信号线21以及触控走线30电性连接，即显示信号线21和触控走线30中的信号可以通过第二连接线23进行传输。
需要说明的是，本申请实施例提供的显示面板中，绑定端子51的数量相对于显示技术而言大大减少，以为测试走线41穿过绑定区1021提供的便利，进一步地，本申请实施例对多个绑定端子51位置进行排布设计，使得不需要与驱动芯片20连接的第一类绑定端子511设置在测试走线41远离驱动芯片20的一侧，需要与驱动芯片20连接的第二类绑定端子512设置在测试走线41靠近驱动芯片20的一侧，进而第一连接线22和第二连接线23均不与测试走线41发生重叠，降低了第一连接线22、第二连接线23与测试走线41之间的干扰。
在一种实施例中，显示面板包括多个第一类绑定端子511以及多个第二类绑定端子512，且相邻两第一类绑定端子511之间的间距小于第一子区A沿第一子区A指向第二子区B的方向上的宽度，相邻两第二类绑定端子512之间的间距小于第一子区A沿第一子区A指向第二子区B的方向上的宽度，进而可以为测试走线41的排布提供充足的空间。
在一种实施例中，在多个绑定端子51位于第二子区B和第三子区C内，而测试端子42与第一子区A沿显示区101靠近绑定区1021的方向上对位设置。
当柔性线路板80与绑定端子51进行压合绑定时，ACF胶可能会溢出，因此，在第一子区A内不设置绑定端子51，可以有效减少第一子区A内ACF胶的溢出量，避免测试端子42因与溢出ACF胶连接而导致短接的现象发生。
承上，本申请实施例通过设置与触控走线30相连接的测试走线41，并将测试走线41连接至测试端子42上，进而可以采用测试端子42来对显示面板进行触控性能的测试，提高了显示面板触控性能测试的便捷性，避免了异常产品进入后续工段，提高显示面板的良品率；且通过测试走线41将测试端子42与触控走线30连接起来，进而可以根据实际需求将测试端子42设置在其他区域，而不会局限于触控走线30上。
此外，本申请实施例对绑定端子51的排布进行设计，以为测试走线41的设置提供充裕的空间，并降低测试走线41与其他连接线之间的干扰。在绑定区1021内形成与测试端子42对位设置的第一子区A，且多个绑定端子51位于第一子区A以外，进而可以有效减少第一子区A内ACF胶的溢出量，避免测试端子42因与溢出ACF胶连接而导致短接的现象发生，降低触控走线30之间发生短接的概率，提高了显示面板的稳定性；且本实施例中将测试端子42设置于显示面板以外的区域，可以在制程中进行切除，进而减少了测试端子42在显示面板中的占用面积，增加了显示面板中的布线空间。
在本申请的另一种实施例中，请结合图3、图4以及图5，在本实施例中，显示面板包括测试端子42以及测试走线41，需要说明的是，由于测试端子42设置于显示面板以外的区域，且在触控性能测试完成之后，需要进行切除，因此，本实施例提供的显示面板中并不具备测试端子42。
其中，测试走线41的一端连接于触控走线30，测试走线41的另一端朝着显示区101靠近绑定区1021的方向延伸，并穿过绑定区1021延伸至显示面板设有绑定区1021一侧的外边界。
测试端子42位于显示面板以外，并可以位于显示面板设有绑定区1021的一侧，进而测试走线41延伸至显示面板外边界的一端与测试端子42相连接，且在触控性能测试完成之后，沿显示面板的外边界进行切割，以去除测试端子42。
进一步地，显示面板还包括设置于第一子区A内的虚拟端子52，由于多个绑定端子51均位于第一子区A外，使得多个绑定端子51的分布不均匀，进而在绑定区1021进行绑定连接之后，容易发生应力分布不均的现象，导致显示面板出现弯曲或者变形，因此，本申请实施例通过在第一子区A内形成虚拟端子52，以改善应力分布不均的现象，提高显示面板的良品率。
需要说明的是，虚拟端子52不进行信号的传输。
进一步地，显示面板包括设置于基板71上的栅极层91以及源漏极层92，测试走线41包括位于绑定区1021内的第一线段411，第一线段411位于栅极层91或者源漏极层92；其中，栅极层91和源漏极层92皆包覆于无机堆叠层72中，且位于触控走线30所在膜层和基板71之间，且栅极层91位于源漏极层92和基板71之间。
在一种实施例中，测试走线41还包括连接于第一线段411靠近显示区101一侧的第二线段412，且第一线段411与基板71之间的间距小于第二线段412与基板71之间的间距；可以理解的是，由于第一线段411位于绑定区1021内，且绑定区1021需要经过压合绑定，进而位于绑定区1021内的膜层会受到挤压，且有发生膜层被挤压破裂的风险，因此，本实施例中将第一线段411设置于更靠近基板71一侧的位置，可以降低因膜层破裂而导致第一线段411与绑定端子51之间，或者第一线段411和第一线段411之间发生短接的概率，提高了显示面板的绑定良品率。
进一步地，在一种实施例中，由于测试走线41的数量为多根，进而第一线段411的数量也为多根，而相邻的两根第一线段411不同层设置，即相邻的两根第一线段411中，其中一个位于栅极层91，则另一个位于源漏极层92；可以降低因膜层破裂而导致相邻的第一线段411和第一线段411之间发生短接的概率，提高了显示面板的绑定良品率。
在一种实施例中，栅极层91可以为至少两层，源漏极层92也可以为至少两层，则相邻的第一线段411分别位于至少两层栅极层91和至少两层源漏极层92中不同的两个膜层中。
在实施应用过程中，在未切割前的显示面板中，在显示面板以外的区域内，测试端子42通过源漏极层92和栅极层91的同层材料形成转接层，并连接至测试走线41上，并在触控测试完成之后，将测试端子42切割去除。
承上，本申请实施例通过设置与触控走线30相连接的测试走线41，并将测试走线41连接至测试端子42上，进而可以采用测试端子42来对显示面板进行触控性能的测试，提高了显示面板触控性能测试的便捷性，避免了异常产品进入后续工段，提高显示面板的良品率；且通过测试走线41将测试端子42与触控走线30连接起来，进而可以根据实际需求将测试端子42设置在其他区域，而不会局限于触控走线30上；此外，在第一子区A内增设虚拟端子52，以改善应力分布不均的现象，提高显示面板的良品率；本实施例中将测试端子42设置于显示面板以外的区域，可以在制程中进行切除，进而减少了测试端子42在显示面板中的占用面积，增加了显示面板中的布线空间；本实施例通过将第一线段411设置于更靠近基板71的位置，并将相邻的第一线段411设置于不同的膜层，进而可以降低因膜层破裂而导致第一线段411与绑定端子51之间，或者第一线段411和第一线段411之间发生短接的概率，提高了显示面板的绑定良品率。
在本申请的另一种实施例中，请结合图6以及图7，本实施例与图4的区别之处在于：显示面板还包括连接于测试走线41上的开关管43，开关管43位于绑定区1021靠近显示区101的一侧，以控制测试走线41中信号的通断。
在一种实施例中，开关管43可以包括mos管，其中，开关管43的source端和Drain端分别连接于测试走线41，开关管43的gate端通过一个绑定端子51连接至一个测试端子42，且该测试端子42可以用于控制开关管43的通断；进而在显示面板进行触控性能测试过程中，测试设备向测试端子42传输测试信号，其中包括向连接测试走线41的测试端子42传输的测试触控信号、以及向连接于开关管43的gate端的测试端子42传输打开开关管43的开启信号，以实现测试走线41中的信号可以正常传输；且在测试完成之后，再将测试端子42进行切除。
因此，在显示面板中，开关管43处于断开状态；需要说明的是，本实施例中通过在测试走线41中增设开关管43，且开关管43在测试完成之后处于断开状态；在显示面板设有绑定区1021一侧的外边界处，由于切割过程容易使得相邻的测试走线41的断面发生短接，或者柔性线路板80与绑定端子51进行压合绑定时，ACF胶可能会溢出导致相邻的测试走线41之间发生短接，因此，本申请实施例中开关管43处于断开装填，而可以减小相邻测试走线41之间发生短接的概率，减小相邻的触控走线30发生短接的概率，提高了显示面板的触控稳定性和触控效果。
承上，本申请实施例通过设置与触控走线30相连接的测试走线41，并将测试走线41连接至测试端子42上，进而可以采用测试端子42来对显示面板进行触控性能的测试，提高了显示面板触控性能测试的便捷性，避免了异常产品进入后续工段，提高显示面板的良品率；且通过测试走线41将测试端子42与触控走线30连接起来，进而可以根据实际需求将测试端子42设置在其他区域，而不会局限于触控走线30上；此外，在绑定区1021内形成与测试端子42对位设置的第一子区A，且多个绑定端子51位于第一子区A以外，进而可以有效减少第一子区A内ACF胶的溢出量，避免测试端子42因与溢出ACF胶连接而导致短接的现象发生，降低触控走线30之间发生短接的概率，提高了显示面板的稳定性；且本实施例中将测试端子42设置于显示面板以外的区域，可以在制程中进行切除，进而减少了测试端子42在显示面板中的占用面积，增加了显示面板中的布线空间；本实施例通过将第一线段411设置于更靠近基板71的位置，并将相邻的第一线段411设置于不同的膜层，进而可以降低因膜层破裂而导致第一线段411与绑定端子51之间，或者第一线段411和第一线段411之间发生短接的概率，提高了显示面板的绑定良品率；进一步地，本实施例中在测试走线41的路径上增设开关管43，进而可以避免在显示面板设有绑定区1021一侧的外边界处，由于切割导致相邻的测试走线41的断面发生短接，而使得相邻的触控走线30发生短接的现象发生，提高了显示面板的触控稳定性和触控效果。
在本申请的其他实施例中，测试端子42还可以直接设置在测试走线41上，且测试端子42需要设置在绑定区1021靠近显示区101的一侧，以避免测试端子42对绑定过程造成影响；显示面板还包括覆盖于测试端子42表面上的绝缘层61，以起到绝缘作用，由于触控测试结束后，测试端子42不需要再进行通电操作，因此，采用绝缘层61对其进行覆盖，绝缘层61的材料可以包括UV胶。
在一种实施例中，请参照图8以及图9，显示面板包括测试端子42，且测试端子42连接于触控走线30。
在一种实施例中，测试端子42可以直接设置于触控走线30上；即平坦层74中可以形成位于器件区1023内的第一开口401和第二开口402，以露出触控走线30远离基板71一侧的部分表面，其中，测试端子42可以填充于第一开口401内，并与触控走线30相连接，第二开口402内可以设置芯片连接端子，驱动芯片20可以通过芯片连接端子与触控走线30相连接；可以理解的是，可以去除第一开口401和第二开口402上方的平坦保护层78，以便于驱动芯片20的绑定，以及显示面板进行触控性能测试时测试设备与测试端子42的连接。
在一种实施例中，相邻的测试端子42之间的间距大于或等于相邻的芯片连接端子之间的间距，且小于或等于相邻的绑定端子51之间的间距。
需要说明的是，显示面板包括多根触控走线30，测试走线41的数量也为多个，且多个测试走线41与多根触控走线30之间可以一一对应连接，而本申请实施例中仅一其中相连接的一根触控走线30和一个测试走线41为例，进行说明。
进而在实施应用过程中，当显示面板需要进行触控性能测试时，可以通过测试端子42向触控走线30输入触控信号，以对显示面板进行触控性能测试，且在完成触控性能测试之后，可以采用绝缘层61覆盖于第一开口401的上方，以将测试端子42与外界绝缘开来。
在一种实施例中，绝缘层61的材料可以包括UV胶。
承上，本申请实施例通过在触控走线30上直接设置测试端子42，进而可以采用测试端子42来对显示面板进行触控性能的测试，提高了显示面板触控性能测试的便捷性，避免了异常产品进入后续工段，提高显示面板的良品率。
在另一种实施例中，请结合图10以及图11，在本实施例中，显示面板包括测试端子42以及测试走线41，且测试走线41的一端连接于触控走线30，测试走线41的另一端朝着显示区101靠近驱动芯片20的方向延伸，并连接至测试端子42。
在本实施例中，测试端子42位于绑定区1021靠近驱动芯片20的一侧，即测试端子42位于绑定区1021靠近显示区101的一侧，且绑定端子51可以等间距的分布于绑定区1021内，或者测试端子42与绑定端子51沿显示区101靠近绑定区1021的方向上部分重叠设置。
其中，平坦层74上可以开设过孔201，且驱动芯片20可以通过过孔201与触控走线30绑定连接，图11中未示出。
承上，本申请实施例通过设置与触控走线30相连接的测试走线41，并将测试走线41连接至测试端子42上，进而可以采用测试端子42来对显示面板进行触控性能的测试，提高了显示面板触控性能测试的便捷性，避免了异常产品进入后续工段，提高显示面板的良品率；且通过测试走线41将测试端子42与触控走线30连接起来，进而可以根据实际需求将测试端子42设置在其他区域，而不会局限于触控走线30上。
在另一种实施例中，请参照图12，本实施例与图10、图11所示实施例的区别之处在于：多个绑定端子51不等间距分布。
其中，绑定端子51与测试端子42沿显示区101靠近绑定区1021的方向上不重叠，即绑定区1021包括第一子区A以及第二子区B，且第一子区A和第二子区B沿垂直于显示区101靠近绑定区1021的方向上排列，在多个绑定端子51位于第二子区B内，而测试端子42与第一子区A沿显示区101靠近绑定区1021的方向上对位设置。
在一种实施例中，相邻两绑定端子51之间的间距小于第一子区A沿垂直于测试走线41的延伸方向上的宽度。
需要说明的是，由于绑定区1021需要与柔性线路板80进行绑定连接，且可以通过异方性导电胶膜(Anisotropic Conductive Film，ACF)进行粘接，当柔性线路板80与绑定端子51进行压合绑定时，ACF胶可能会溢出，因此，在第一子区A内不设置绑定端子51，可以有效减少第一子区A内ACF胶的溢出量，避免测试端子42因与溢出ACF胶连接而导致短接的现象发生。
承上，本申请实施例通过设置与触控走线30相连接的测试走线41，并将测试走线41连接至测试端子42上，进而可以采用测试端子42来对显示面板进行触控性能的测试，提高了显示面板触控性能测试的便捷性，避免了异常产品进入后续工段，提高显示面板的良品率；且通过测试走线41将测试端子42与触控走线30连接起来，进而可以根据实际需求将测试端子42设置在其他区域，而不会局限于触控走线30上；此外，在绑定区1021内形成与测试端子42对位设置的第一子区A，且多个绑定端子51位于第一子区A以外，进而可以有效减少第一子区A内ACF胶的溢出量，避免测试端子42因与溢出ACF胶连接而导致短接的现象发生，降低触控走线30之间发生短接的概率，提高了显示面板的稳定性。
另外，请结合图1、图8、图10以及图13，本申请实施例还提供一种显示面板母板100，显示面板母板100包括至少两个子板1001、以及位于子板1001以外的切割区域1002，子板1001包括显示区101以及与显示区101相邻的非显示区102。
子板1001还包括触控电极10、驱动芯片20以及触控走线30。触控电极10设置于显示区101内；驱动芯片20设置于非显示区102内；触控走线30连接于触控电极10和驱动芯片20之间；其中，子板1001还包括至少设置于非显示区102内的测试走线41，测试走线41与触控走线30相连接。
需要说明的是，本申请实施例提供的显示面板母板100经过切割之后，分离得到的子板1001经过绑定等工序之后，即可得到上述实施例中所述的显示面板，因此，子板1001中关于测试走线41的设置方式以及与触控走线30之间的连接方式等皆可参照上述实施例中进行设置。
在一种实施例中，显示面板包括测试走线41以及测试端子42，测试端子42位于切割区域1002，测试走线41的一端连接于触控走线30，测试走线41的另一端延伸至子板1001外并与测试端子42连接，如图1所示。
在一种实施例中，非显示区102包括靠近显示区101一侧的弯折区1022、远离显示区101一侧的绑定区1021以及位于弯折区1022和绑定区1021之间的器件区1023，而驱动芯片20设置于器件区1023内。
在一种实施例中，显示面板包括测试端子42，测试端子42连接于触控走线30，如图8所示。
在一种实施例中，显示面板包括测试走线41以及测试端子42，测试端子42位于绑定区1021靠近驱动芯片20的一侧，测试走线41的一端连接于触控走线30，测试走线41的另一端与测试端子42连接，如图9所示。
可以理解的是，由于本申请实施例提供的显示面板母板100中测试走线41的设置方式以及与触控走线30的连接方式皆可以参照上述实施例中所述的显示面板进行设置，因此，该显示面板母板100具有与上述实施例中所述的显示面板相同的有益效果，在此不再赘述。
另外，请参照图14，本申请实施例还提供一种显示装置90，该显示装置90包括上述实施例中所述的显示面板901。
综上所述，本申请实施例通过在触控走线30上连接测试走线41，进而可以采用测试走线41来对显示面板进行触控性能的测试；例如在未绑定驱动芯片20的情况下，也能通过测试走线41来对显示面板进行触控性能的测试，提高了显示面板触控性能测试的便捷性，避免了异常产品进入后续工段，提高显示面板的良品率。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种显示面板及显示装置进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种显示面板，所述显示面板包括显示区以及与所述显示区相邻的非显示区；
    所述显示面板还包括：
    触控电极，设置于所述显示区内；
    像素单元，设置于所述显示区内；
    驱动芯片，设置于所述非显示区内，所述非显示区包括位于所述驱动芯片远离所述显示区一侧的绑定区；
    显示信号线，连接于所述驱动芯片和所述像素单元之间；
    触控走线，连接于所述触控电极和所述驱动芯片之间；
    多个绑定端子，设置于所述绑定区内；
    其中，所述显示面板还包括设置于所述非显示区内的测试走线，所述测试走线的一端连接于所述触控走线，所述测试走线的另一端穿过所述绑定区，并延伸至所述显示面板设有所述绑定区一侧的外边界，且所述测试走线位于相邻的所述绑定端子之间。
  2. 根据权利要求1所述的显示面板，其中，所述驱动芯片包括与所述显示区相对设置的第一侧以及连接于所述第一侧的第二侧，所述显示信号线连接于所述驱动芯片的所述第一侧，所述触控走线连接于所述驱动芯片的所述第二侧。
  3. 根据权利要求2所述的显示面板，其中，所述绑定区包括第一子区以及与所述第一子区相邻的第二子区，所述测试走线的一端在所述驱动芯片的所述第二侧连接于所述触控走线，所述测试走线的另一端穿过所述第一子区，所述第二子区位于所述测试走线远离所述驱动芯片的一侧，所述绑定端子包括设置于所述第二子区内的第一类绑定端子；
    所述显示面板还包括第一连接线，所述非显示区还包括功能电路区，所述功能电路区与所述绑定区位于所述显示区的不同侧，所述第一连接线的一端连接于所述第一类绑定端子，所述第一连接线的另一端延伸至所述功能电路区，且所述第一连接线与所述测试走线不重叠设置。
  4. 根据权利要求3所述的显示面板，其中，所述绑定区还包括设置于所述第一子区靠近所述驱动芯片一侧的第三子区，所述绑定端子还包括设置于所述第三子区内的第二类绑定端子；
    所述显示面板还包括第二连接线，所述第二连接线的一端连接于所述第二类绑定端子，所述第二连接线的另一端连接于所述驱动芯片，所述第二连接线与所述测试走线不重叠设置。
  5. 根据权利要求4所述的显示面板，其中，所述显示面板还包括设置于所述功能电路区内的栅极驱动单元以及点灯测试单元，所述第一连接线连接于所述栅极驱动单元以及所述点灯测试单元，所述第二连接线通过所述驱动芯片与所述显示信号线以及所述触控走线电性连接。
  6. 根据权利要求4所述的显示面板，其中，所述显示面板包括多个所述第一类绑定端子以及多个所述第二类绑定端子，且相邻两所述第一类绑定端子之间的间距小于所述第一子区沿所述第一子区指向所述第二子区的方向上的宽度，相邻两所述第二类绑定端子之间的间距小于所述第一子区沿所述第一子区指向所述第二子区的方向上的宽度。
  7. 根据权利要求3所述的显示面板，其中，所述显示面板还包括虚拟端子，所述虚拟端子位于所述第一子区内，所述虚拟端子与所述测试走线沿所述第一子区指向所述第二子区的方向上相邻设置。
  8. 根据权利要求1所述的显示面板，其中，所述显示面板还包括连接于所述测试走线上的开关管，所述开关管位于所述绑定区靠近所述显示区的一侧，以控制所述测试走线中信号的通断。
  9. 根据权利要求8所述的显示面板，其中，所述开关管处于断开状态。
  10. 根据权利要求1所述的显示面板，其中，所述显示面板还包括基板以及设置于所述基板上的栅极层和源漏极层，所述测试走线包括位于所述绑定区内的第一线段，所述第一线段位于所述栅极层或者所述源漏极层。
  11. 根据权利要求10所述的显示面板，其中，所述测试走线还包括连接于所述第一线段靠近所述显示区一侧的第二线段，且所述第一线段与所述基板之间的间距小于所述第二线段与所述基板之间的间距。
  12. 根据权利要求10所述的显示面板，其中，所述测试走线的数量为多根，相邻两根所述测试走线的所述第一线段不同层设置。
  13. 根据权利要求1所述的显示面板，其中，所述显示面板还包括测试端子，所述测试端子连接于所述触控走线。
  14. 根据权利要求13所述的显示面板，其中，所述测试端子设置于所述绑定区靠近所述驱动芯片的一侧。
  15. 根据权利要求13所述的显示面板，其中，所述显示面板还包括绝缘层，所述绝缘层覆盖于所述测试端子的表面上。
  16. 一种显示装置，所述显示装置包括显示面板，所述显示面板包括显示区以及与所述显示区相邻的非显示区；
    所述显示面板还包括：
    触控电极，设置于所述显示区内；
    像素单元，设置于所述显示区内；
    驱动芯片，设置于所述非显示区内，所述非显示区包括位于所述驱动芯片远离所述显示区一侧的绑定区；
    显示信号线，连接于所述驱动芯片和所述像素单元之间；
    触控走线，连接于所述触控电极和所述驱动芯片之间；
    多个绑定端子，设置于所述绑定区内；
    其中，所述显示面板还包括设置于所述非显示区内的测试走线，所述测试走线的一端连接于所述触控走线，所述测试走线的另一端穿过所述绑定区，并延伸至所述显示面板设有所述绑定区一侧的外边界，且所述测试走线位于相邻的所述绑定端子之间。
  17. 根据权利要求16所述的显示装置，其中，所述驱动芯片包括与所述显示区相对设置的第一侧以及连接于所述第一侧的第二侧，所述显示信号线连接于所述驱动芯片的所述第一侧，所述触控走线连接于所述驱动芯片的所述第二侧。
  18. 根据权利要求17所述的显示装置，其中，所述绑定区包括第一子区以及与所述第一子区相邻的第二子区，所述测试走线的一端在所述驱动芯片的所述第二侧连接于所述触控走线，所述测试走线的另一端穿过所述第一子区，所述第二子区位于所述测试走线远离所述驱动芯片的一侧，所述绑定端子包括设置于所述第二子区内的第一类绑定端子；
    所述显示面板还包括第一连接线，所述非显示区还包括功能电路区，所述功能电路区与所述绑定区位于所述显示区的不同侧，所述第一连接线的一端连接于所述第一类绑定端子，所述第一连接线的另一端延伸至所述功能电路区，且所述第一连接线与所述测试走线不重叠设置。
  19. 根据权利要求18所述的显示装置，其中，所述绑定区还包括设置于所述第一子区靠近所述驱动芯片一侧的第三子区，所述绑定端子还包括设置于所述第三子区内的第二类绑定端子；
    所述显示面板还包括第二连接线，所述第二连接线的一端连接于所述第二类绑定端子，所述第二连接线的另一端连接于所述驱动芯片，所述第二连接线与所述测试走线不重叠设置。
  20. 根据权利要求16所述的显示装置，其中，所述显示面板还包括连接于所述测试走线上的开关管，所述开关管位于所述绑定区靠近所述显示区的一侧，以控制所述测试走线中信号的通断。
PCT/CN2024/100209 2024-06-05 2024-06-19 显示面板及显示装置 Pending WO2025251352A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202410725912.9 2024-06-05
CN202410725912.9A CN118708078A (zh) 2024-06-05 2024-06-05 显示面板及显示装置

Publications (1)

Publication Number Publication Date
WO2025251352A1 true WO2025251352A1 (zh) 2025-12-11

Family

ID=92817031

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2024/100209 Pending WO2025251352A1 (zh) 2024-06-05 2024-06-19 显示面板及显示装置

Country Status (2)

Country Link
CN (1) CN118708078A (zh)
WO (1) WO2025251352A1 (zh)

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190023876A (ko) * 2017-08-30 2019-03-08 엘지디스플레이 주식회사 표시 장치
CN114625274A (zh) * 2022-03-14 2022-06-14 武汉华星光电半导体显示技术有限公司 显示面板和待切割显示面板
CN114721546A (zh) * 2022-04-08 2022-07-08 合肥维信诺科技有限公司 一种触控显示面板和触控显示装置
CN116113285A (zh) * 2023-01-30 2023-05-12 京东方科技集团股份有限公司 一种显示面板及其制备方法、显示模组
CN116343581A (zh) * 2023-03-30 2023-06-27 云谷（固安）科技有限公司 一种显示面板和显示装置
CN116736586A (zh) * 2023-06-05 2023-09-12 厦门天马微电子有限公司 显示面板及显示装置
CN117095624A (zh) * 2023-08-24 2023-11-21 北京京东方光电科技有限公司 一种显示面板及显示装置
CN117170148A (zh) * 2023-08-30 2023-12-05 合肥维信诺科技有限公司 显示模组和显示装置
CN117789598A (zh) * 2023-10-31 2024-03-29 上海中航光电子有限公司 显示面板和显示装置

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190023876A (ko) * 2017-08-30 2019-03-08 엘지디스플레이 주식회사 표시 장치
CN114625274A (zh) * 2022-03-14 2022-06-14 武汉华星光电半导体显示技术有限公司 显示面板和待切割显示面板
CN114721546A (zh) * 2022-04-08 2022-07-08 合肥维信诺科技有限公司 一种触控显示面板和触控显示装置
CN116113285A (zh) * 2023-01-30 2023-05-12 京东方科技集团股份有限公司 一种显示面板及其制备方法、显示模组
CN116343581A (zh) * 2023-03-30 2023-06-27 云谷（固安）科技有限公司 一种显示面板和显示装置
CN116736586A (zh) * 2023-06-05 2023-09-12 厦门天马微电子有限公司 显示面板及显示装置
CN117095624A (zh) * 2023-08-24 2023-11-21 北京京东方光电科技有限公司 一种显示面板及显示装置
CN117170148A (zh) * 2023-08-30 2023-12-05 合肥维信诺科技有限公司 显示模组和显示装置
CN117789598A (zh) * 2023-10-31 2024-03-29 上海中航光电子有限公司 显示面板和显示装置

Also Published As

Publication number Publication date
CN118708078A (zh) 2024-09-27

Similar Documents

Publication Publication Date Title
US11488987B2 (en) Display substrate, splicing screen and manufacturing method thereof
CN111919164B (zh) 具有窄下边框的显示面板及电子设备
KR101195688B1 (ko) 플렉시블 기판 및 전기 회로 구조체
CN100399126C (zh) 平面显示面板及其组装方法
KR100321883B1 (ko) 반도체소자의실장구조및실장방법과,액정표시장치
KR101015885B1 (ko) 평판 디스플레이 장치 및 그 제조 방법
US8183755B2 (en) Flat panel display apparatus and method of manufacturing the same
EP0609074A2 (en) Assembly structure of a flat type device
US7349054B2 (en) Method of mounting flexible circuit boards, and display device
JPH11305681A (ja) 表示装置
KR101000455B1 (ko) 구동 칩 및 이를 갖는 표시장치
US20080119069A1 (en) Board device and board
WO2025251352A1 (zh) 显示面板及显示装置
CN117496848B (zh) 显示面板及显示装置
CN114879421B (zh) 一种驱动电路及显示装置
CN214202334U (zh) 一种触控模组以及触控显示装置
KR20000060803A (ko) 액정 표시 장치 및 그 제조 방법
KR100816326B1 (ko) 수리선을 가지는 액정 표시 장치 및 그 수리 방법
KR102196180B1 (ko) 표시장치
KR20010056897A (ko) 액정 표시 장치용 박막 트랜지스터 기판
US12328815B2 (en) Circuit board and display device including the same
JP3601455B2 (ja) 液晶表示装置
JP2002236458A (ja) 表示装置の実装構造
CN120428489A (zh) 显示面板和显示装置
CN209281119U (zh) 栅极驱动单元及电路、阵列基板、显示面板和显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 24942262

Country of ref document: EP

Kind code of ref document: A1