WO2025237013A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置

Info

Publication number
WO2025237013A1
WO2025237013A1 PCT/CN2025/090472 CN2025090472W WO2025237013A1 WO 2025237013 A1 WO2025237013 A1 WO 2025237013A1 CN 2025090472 W CN2025090472 W CN 2025090472W WO 2025237013 A1 WO2025237013 A1 WO 2025237013A1
Authority
WO
WIPO (PCT)
Prior art keywords
pixel driving
driving circuit
initial connection
initial
connection line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2025/090472
Other languages
English (en)
French (fr)
Inventor
何庆
于子阳
张跳梅
胡明
蒋志亮
潘向南
燕青青
谷泉泳
赵攀
李子曦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Beijing BOE Technology Development Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Beijing BOE Technology Development Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd, Beijing BOE Technology Development Co Ltd filed Critical BOE Technology Group Co Ltd
Publication of WO2025237013A1 publication Critical patent/WO2025237013A1/zh
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G09F9/335—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes being organic light emitting diodes [OLED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels

Definitions

  • This article relates to the field of display technology, specifically to a display substrate and a display device.
  • OLEDs Organic light-emitting diodes
  • QLEDs quantum dot light-emitting diodes
  • TFTs thin-film transistors
  • this disclosure provides a display substrate, including: a substrate and an array of pixel driving circuits disposed on the substrate, a plurality of initial signal line groups and a plurality of initial connection lines, wherein the initial signal line groups are electrically connected to the pixel driving circuits and are configured to provide initial signals to the pixel driving circuits, and the initial connection lines are electrically connected to the initial signal line groups;
  • the plurality of initial signal line groups are arranged along a second direction, at least one initial signal line group includes at least one initial signal line, at least a portion of the at least one initial signal line extends along a first direction, the plurality of initial connecting lines are arranged along a first direction, at least a portion of the at least one initial connecting line extends along a second direction, and the first direction and the second direction intersect.
  • the distance between two adjacent initial connection lines along the first direction is greater than or equal to four times the length of the driving circuit, where the length of the driving circuit is the length of the pixel driving circuit along the first direction.
  • At least one initial signal line group includes: M initial signal lines, and the initial connection lines include: a first initial connection line to an Mth initial connection line;
  • the m-th initial connection line is electrically connected to the m-th initial signal line in the initial connection group, and multiple m-th initial connection lines and the m-th initial signal lines in the multiple initial connection groups form a mesh structure;
  • the pixel driving circuit includes: M reset transistors, each transistor including: a first electrode; the first electrode of the m-th reset transistor is electrically connected to the m-th initial signal line and the m-th initial connection line in the initial signal line group, respectively, 1 ⁇ m ⁇ M, M ⁇ 1.
  • the display substrate includes: a plurality of pixel driving circuit groups, at least one pixel driving circuit group including: a first pixel driving circuit and a second pixel driving circuit, the first pixel driving circuit and the second pixel driving circuit are at least partially symmetrically arranged with respect to a straight line extending along the second direction, and the plurality of pixel driving circuit groups are arranged in an array.
  • At least a portion of the initial connection line has its orthographic projection on the substrate located between the orthographic projection of the first pixel driving circuit and the orthographic projection of the second pixel driving circuit in at least one pixel driving circuit group on the substrate.
  • the center line of at least one initial connecting line extending along the second direction coincides with the center line of at least one pixel driving circuit group extending along the second direction.
  • the distance between two adjacent initial connection lines along the first direction is equal to the distance between the center line of the Rth column pixel driving circuit group extending along the second direction and the center line of the Sth column pixel driving circuit group extending along the second direction, where S-R ⁇ 2.
  • the pixel driving circuit group includes: a first circuit group and a second circuit group, wherein the orthographic projection of at least one initial connecting line on the substrate at least partially overlaps with the orthographic projection of the first circuit group on the substrate, and the orthographic projection of at least one initial connecting line on the substrate does not overlap with the orthographic projection of the second circuit group on the substrate.
  • the initial connecting line includes a main body, a plurality of first connecting parts, and a plurality of second connecting parts, wherein the plurality of first connecting parts and the plurality of second connecting parts are electrically connected to the main body.
  • the main body extends along the second direction, and the orthographic projection of the main body on the substrate is located between the orthographic projection of the first pixel driving circuit in the first circuit group on the substrate and the orthographic projection of the second pixel driving circuit on the substrate.
  • a plurality of first connecting parts are arranged along the second direction, at least one first connecting part extends along the first direction and is located on one side of the main body.
  • a plurality of second connecting parts are arranged along the second direction, at least one second connecting part extends along the first direction and is located on the other side of the main body.
  • the plurality of first connecting parts and the plurality of second connecting parts correspond one-to-one, and the first connecting part and the corresponding second connecting part extend along the first direction.
  • the orthographic projections of the first connecting portion and the second connecting portion on the substrate at least partially overlap with the orthographic projections of the initial signal line connected to the initial connecting line on the substrate.
  • the transistor further includes: an active layer;
  • the active layer of the reset transistor connected to the initial connection line in the first pixel driving circuit of the first circuit group is spaced apart from the active layer of the reset transistor connected to the initial connection line in the second pixel driving circuit, and is symmetrically arranged with respect to the straight line extending along the second direction.
  • the active layer of the reset transistor connected to the initial connection line in the first pixel driving circuit of the second circuit group is spaced apart from the active layer of the reset transistor connected to the initial connection line in the second pixel driving circuit, and is symmetrically arranged with respect to the straight line extending along the second direction.
  • the first electrode of the reset transistor connected to the initial connection line in the first pixel driving circuit of the first circuit group is located on the first side of the main body and is electrically connected to the first connection part.
  • the first electrode of the reset transistor connected to the initial connection line in the second pixel driving circuit of the first circuit group is located on the second side of the main body and is electrically connected to the second connection part.
  • the first electrodes of the reset transistor connected to the initial connection line in the first pixel driving circuit of the first circuit group and the first electrodes of the reset transistor connected to the initial connection line in the second pixel driving circuit of the first circuit group are arranged along a first direction.
  • the first electrode of the reset transistor connected to the initial connection line in the first pixel driving circuit of the second circuit group is spaced apart from the first electrode of the reset transistor connected to the initial connection line in the second pixel driving circuit.
  • the orthographic projection of the first electrode of the reset transistor connected to the initial connection line in at least one pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the initial signal line connected to the initial connection line on the substrate.
  • the first electrode of the reset transistor connected to the initial connection line and the first connection portion are in a zigzag shape
  • the first electrode of the reset transistor connected to the initial connection line and the second connection portion are in a zigzag shape.
  • the display substrate includes: a first insulating layer group and a second insulating layer group, wherein the first insulating layer group is an insulating layer located between the film layer where the initial interconnect line is located and the film layer where the initial signal line is located, and the second insulating layer group is a film layer located between the active layer of the transistor and the film layer where the initial interconnect line is located.
  • the first insulating layer group includes: a second via and a third via exposing the initial signal line; the first terminal of the reset transistor in the first pixel driving circuit of at least one of the first circuit group and the second circuit group, which is connected to the initial connection line, is electrically connected to the initial signal line through the second via; and the first terminal of the reset transistor in the second pixel driving circuit of at least one of the first circuit group and the second circuit group, which is connected to the initial connection line, is electrically connected to the initial signal line through the third via.
  • the second insulating layer group includes: a first via exposing the active layer of the reset transistor connected to the initial connection line in the pixel driving circuit, wherein the first electrode of the reset transistor connected to the initial connection line in the pixel driving circuit is connected to the active layer of the reset transistor through the first via, wherein the first via exposing the active layer of the reset transistor connected to the initial connection line in the first pixel driving circuit of the first circuit group is a different via from the first via exposing the active layer of the reset transistor connected to the initial connection line in the second pixel driving circuit of the first circuit group, and the first via exposing the active layer of the reset transistor connected to the initial connection line in the first pixel driving circuit of the second circuit group is a different via from the first via exposing the active layer of the reset transistor connected to the initial connection line in the second pixel driving circuit of the second circuit group.
  • the transistor further includes: an active layer;
  • the active layer of the reset transistor connected to the initial connection line in the first pixel driving circuit of the first circuit group and the active layer of the reset transistor connected to the initial connection line in the second pixel driving circuit are integral structures and are symmetrically arranged with respect to the straight line extending along the second direction.
  • the active layer of the reset transistor connected to the initial connection line in the first pixel driving circuit of the second circuit group is spaced apart from the active layer of the reset transistor connected to the initial connection line in the second pixel driving circuit, and is symmetrically arranged with respect to the straight line extending along the second direction.
  • the first electrode of the reset transistor connected to the initial connection line in the first pixel driving circuit of the first circuit group and the first electrode of the reset transistor connected to the initial connection line in the second pixel driving circuit are the same electrode and are part of the main body of the initial connection line.
  • the first electrode of the reset transistor connected to the initial connection line in the first pixel driving circuit of the second circuit group is spaced apart from the first electrode of the reset transistor connected to the initial connection line in the second pixel driving circuit.
  • the orthographic projection of the first electrode of the reset transistor connected to the initial connection line in at least one pixel driving circuit in the first circuit group on the substrate does not overlap with the orthographic projection of the initial signal line connected to the initial connection line on the substrate.
  • the orthographic projection of the first electrode of the reset transistor connected to the initial connection line in at least one pixel driving circuit in the second circuit group on the substrate at least partially overlaps with the orthographic projection of the initial signal line connected to the initial connection line on the substrate.
  • it includes: a first insulating layer group and a second insulating layer group, wherein the first insulating layer group is an insulating layer located between the film layer where the initial connection line is located and the film layer where the initial signal line is located, and the second insulating layer group is a film layer located between the active layer of the transistor and the film layer where the initial connection line is located.
  • the first insulating layer group includes: a second via and a third via exposing the initial signal line; a first connection portion is electrically connected to the initial signal line through the second via; a second connection portion is electrically connected to the initial signal line through the third via; the first terminal of the reset transistor in the first pixel driving circuit located in the second circuit group and connected to the initial connection line is electrically connected to the initial signal line through the second via; and the first terminal of the reset transistor in the second pixel driving circuit located in the second circuit group and connected to the initial connection line is electrically connected to the initial signal line through the third via.
  • the second insulating layer group includes: a first via exposing the active layer of the reset transistor connected to the initial connection line in the pixel driving circuit, wherein the first electrode of the reset transistor connected to the initial connection line in the pixel driving circuit is connected to the active layer of the reset transistor through the first via, wherein the first via exposing the active layer of the reset transistor connected to the initial connection line in the first pixel driving circuit of the first circuit group and the first via exposing the active layer of the reset transistor connected to the initial connection line in the second pixel driving circuit of the first circuit group are the same via, and the first via exposing the active layer of the reset transistor connected to the initial connection line in the first pixel driving circuit of the second circuit group and the first via exposing the active layer of the reset transistor connected to the initial connection line in the second pixel driving circuit of the second circuit group are different vias.
  • the transistor further includes: an active layer;
  • the active layer of the reset transistor connected to the initial connection line in the first pixel driving circuit of the first circuit group and the active layer of the reset transistor connected to the initial connection line in the second pixel driving circuit are integral structures and are symmetrically arranged relative to the straight line extending along the second direction.
  • the active layer of the reset transistor connected to the initial connection line in the first pixel driving circuit of the second circuit group and the active layer of the reset transistor connected to the initial connection line in the second pixel driving circuit are integral structures and are symmetrically arranged with respect to the straight line extending along the second direction.
  • the initial connecting line is a line shape extending along a second direction.
  • the first electrode of the reset transistor connected to the initial connection line in the first pixel driving circuit of the first circuit group and the first electrode of the reset transistor connected to the initial connection line in the second pixel driving circuit are the same electrode and are part of the initial connection line.
  • the first electrode of the reset transistor connected to the initial connection line in the first pixel driving circuit of the second circuit group and the first electrode of the reset transistor connected to the initial connection line in the second pixel driving circuit are integrally structured and extend along the second direction.
  • the orthographic projection of the first pole of the reset transistor connected to the initial connection line in at least one pixel driving circuit of at least one of the first and second circuit groups on the substrate at least partially overlaps with the orthographic projection of the initial signal line connected to the initial connection line on the substrate.
  • it includes: a first insulating layer group and a second insulating layer group, wherein the first insulating layer group is an insulating layer located between the film layer where the initial connection line is located and the film layer where the initial signal line is located, and the second insulating layer group is a film layer located between the active layer of the transistor and the film layer where the initial connection line is located.
  • the first insulating layer group includes: a second via exposing the initial signal line, wherein the first terminal of a reset transistor in at least one pixel driving circuit in at least one of the first and second circuit groups, which is connected to the initial connection line, is electrically connected to the initial signal line through the second via;
  • the second insulating layer group includes: a first via exposing the active layer of the reset transistor connected to the initial connection line in the pixel driving circuit, wherein the first electrode of the reset transistor connected to the initial connection line in the pixel driving circuit is connected to the active layer of the reset transistor through the first via, wherein the first via exposing the active layer of the reset transistor connected to the initial connection line in the first pixel driving circuit of the first circuit group and the first via exposing the active layer of the reset transistor connected to the initial connection line in the second pixel driving circuit of the first circuit group are the same via, and the first via exposing the active layer of the reset transistor connected to the initial connection line in the first pixel driving circuit of the second circuit group and the first via exposing the active layer of the reset transistor connected to the initial connection line in the second pixel driving circuit of the second circuit group are the same via;
  • the first via and the second via of the active layer of the pixel driving circuit which exposes the reset transistor connected to the initial connection line in at least one of the first and second circuit groups, are arranged along the second direction.
  • the initial connection line includes a first body portion and a first protrusion that are electrically connected to each other, and the initial signal line includes a second body portion and a second protrusion that are electrically connected to each other;
  • the first main body extends along the second direction, and the orthographic projection of the first main body on the substrate is located between the orthographic projection of the first pixel driving circuit and the second pixel driving circuit on the substrate in the first circuit group.
  • the first protrusion extends along the first direction and is located on one side of the first main body.
  • the second main body extends along the first direction, and the second protrusion extends along the second direction and is located on one side of the second main body;
  • the orthographic projection of the first protrusion on the substrate at least partially overlaps with the orthographic projection of the second protrusion on the substrate, and is electrically connected to the second protrusion.
  • the first electrode of the reset transistor connected to the initial connection line in the first pixel driving circuit of the first circuit group and the first electrode of the reset transistor connected to the initial connection line in the second pixel driving circuit are the same electrode and are part of the first main body of the initial connection line.
  • the first electrode of the reset transistor connected to the initial connection line in the first pixel driving circuit of the second circuit group and the first electrode of the reset transistor connected to the initial connection line in the second pixel driving circuit are integrally structured and extend along the second direction.
  • it includes: a first insulating layer group and a second insulating layer group, wherein the first insulating layer group is an insulating layer located between the film layer where the initial connection line is located and the film layer where the initial signal line is located, and the second insulating layer group is a film layer located between the active layer of the transistor and the film layer where the initial connection line is located.
  • the first insulating layer group includes: a second via of the second protrusion and a third via of the second body portion exposing the initial signal line, the first protrusion being electrically connected to the second protrusion through the second via, and the first electrode of the reset transistor connected to the initial connection line in at least one pixel driving circuit in the second circuit group being electrically connected to the second body portion of the initial signal line through the third via;
  • the second insulating layer group includes: a first via exposing the active layer of the reset transistor connected to the initial connection line in the pixel driving circuit, wherein the first electrode of the reset transistor connected to the initial connection line in the pixel driving circuit is connected to the active layer of the reset transistor through the first via, wherein the first via exposing the active layer of the reset transistor connected to the initial connection line in the first pixel driving circuit of the first circuit group and the first via exposing the active layer of the reset transistor connected to the initial connection line in the second pixel driving circuit of the first circuit group are the same via, and the first via exposing the active layer of the reset transistor connected to the initial connection line in the first pixel driving circuit of the second circuit group and the first via exposing the active layer of the reset transistor connected to the initial connection line in the second pixel driving circuit of the second circuit group are the same via;
  • the first via and the second via of the active layer of the reset transistor connected to the initial connection line in at least one pixel driving circuit in the first circuit group are arranged along a first direction
  • the first via and the third via of the active layer of the reset transistor connected to the initial connection line in at least one pixel driving circuit in the second circuit group are arranged along a second direction.
  • the pixel driving circuit further includes: a capacitor; the capacitor includes: a first electrode plate and a second electrode plate;
  • the orthographic projection of at least one initial signal line in the initial signal line group connected to the pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of at least one of the first and second plates of the capacitor on the substrate.
  • it further includes: a circuit structure layer disposed on the substrate, the circuit structure layer being provided with a pixel driving circuit, an initial signal line group and an initial connection line, the pixel driving circuit including: at least one transistor, the transistor further including: a first electrode and a second electrode;
  • the circuit structure layer includes: a semiconductor layer, a first conductive layer, and a second conductive layer sequentially stacked on a substrate;
  • the semiconductor layer includes: an active layer located in at least one transistor in at least one pixel driving circuit;
  • the first conductive layer includes at least one initial signal line in the initial signal line group
  • the second conductive layer includes: an initial connection line and a first and second electrode of at least one transistor located in at least one pixel driving circuit.
  • it further includes: a first power line, the first power line being electrically connected to the pixel driving circuit;
  • the orthographic projection of the first power line on the substrate at least partially overlaps with the orthographic projection of at least one of the initial signal lines in the initial signal line group on the substrate.
  • this disclosure also provides a display device, including: the aforementioned display substrate.
  • Figure 1 is a schematic diagram of the structure of a display device
  • Figure 2 is a schematic diagram of a planar structure of a display substrate
  • Figure 3 is a schematic diagram of the planar structure of another display substrate
  • Figure 4 is a schematic diagram of the planar structure of another display substrate
  • Figure 5 is a schematic diagram of the equivalent circuit of a pixel driving circuit
  • Figure 6 is a timing diagram of the pixel driving circuit provided in Figure 5;
  • Figure 7 is a schematic diagram of the structure of the display substrate provided in an embodiment of this disclosure.
  • Figure 8 is a second schematic diagram of the structure of the display substrate provided in an embodiment of this disclosure.
  • Figure 9 is a schematic diagram of the display substrate structure
  • Figure 10 is a schematic diagram of the structure of the display substrate (II).
  • Figure 11 is a schematic diagram of the structure of the display substrate
  • Figure 12 is a schematic diagram of the display substrate structure (IV).
  • Figure 13 is a top view of the display substrate
  • Figure 14 is a schematic diagram of part of the film layers in Figure 13.
  • Figure 15 is a schematic diagram of a portion of the film layers in Figure 13.
  • the scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto.
  • the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures.
  • the figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values shown in the figures.
  • connection should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.
  • a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
  • the channel region refers to the region through which current primarily flows.
  • the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa.
  • the functions of the "source electrode” and “drain electrode” may sometimes be interchanged. Therefore, in this specification, the "source electrode” and “drain electrode” can be interchanged.
  • electrical connection includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an “electrical function,” as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of “electrical functions” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.
  • parallel refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°.
  • perpendicular refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.
  • film and “layer” may be interchanged.
  • conductive layer may sometimes be replaced with “conductive film.”
  • insulating film may sometimes be replaced with “insulating layer.”
  • the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different.
  • the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.
  • triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.
  • Figure 1 is a schematic diagram of a display device.
  • the display device may include a timing controller, a data signal driver, a scan signal driver, a light emission signal driver, and a pixel array.
  • the timing controller is connected to the data signal driver, the scan signal driver, and the light emission signal driver.
  • the data signal driver is connected to multiple data signal lines (D1 to Dn)
  • the scan signal driver is connected to multiple scan signal lines (GATE1 to Sm)
  • the light emission signal driver is connected to multiple light emission signal lines (E1 to Eo).
  • the pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light emission device connected to the circuit unit.
  • the circuit unit may include a pixel driving circuit, which may be connected to the scan signal lines, the light emission signal lines, and the data signal lines, respectively.
  • the timing controller can provide grayscale values and control signals of specifications suitable for the data signal driver to the data signal driver, clock signals, scan start signals, etc. of specifications suitable for the scan signal driver to the scan signal driver, and clock signals, transmit stop signals, etc. of specifications suitable for the light emission signal driver to the light emission signal driver.
  • the data signal driver can use the grayscale values and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn.
  • the data signal driver can sample grayscale values using a clock signal and apply data voltages corresponding to the grayscale values to data signal lines D1 to Dn on a pixel-by-pixel basis, where n can be a natural number.
  • the scan signal driver can generate scan signals to be provided to scan signal lines GATE1, GATE2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller.
  • the scan signal driver can sequentially provide scan signals with on-level pulses to scan signal lines GATE1 to Sm.
  • a scan signal driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal, where m can be a natural number.
  • An LED signal driver can generate transmit signals to be provided to LED signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from a timing controller.
  • an LED signal driver can sequentially provide transmit signals with cutoff level pulses to LED signal lines E1 to Eo.
  • an LED signal driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals, provided in the form of cutoff level pulses, to the next stage circuit under the control of a clock signal, where o can be a natural number.
  • Figure 2 is a schematic diagram of a planar structure of a display substrate
  • Figure 3 is a schematic diagram of a planar structure of another display substrate
  • Figure 4 is a schematic diagram of a planar structure of yet another display substrate.
  • the display substrate may include multiple pixel units P arranged in a matrix. At least one of the multiple pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light.
  • Each of the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 includes a pixel driving circuit and a light-emitting device.
  • the pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line.
  • the pixel driving circuits are configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting device under the control of the scan signal line and the light-emitting signal line.
  • the light-emitting devices in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the pixel driving circuit of their respective sub-pixels.
  • the light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of their respective sub-pixels.
  • the first sub-pixel P1 can be a red sub-pixel (R) emitting red light
  • the second sub-pixel P2 can be a blue sub-pixel (B) emitting blue light
  • the third sub-pixel P3 can be a green sub-pixel (G) emitting green light.
  • the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels can be arranged horizontally side by side, vertically side by side, or in a triangular arrangement; this disclosure does not limit the specific arrangement.
  • a pixel unit may include three sub-pixels and four sub-pixels.
  • Figures 2 and 3 are illustrated using three sub-pixels as an example, and Figure 4 is illustrated using four sub-pixels as an example.
  • the three sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement, etc., and this disclosure does not limit the arrangement.
  • Figure 2 illustrates the arrangement of the three sub-pixels horizontally side-by-side as an example
  • Figure 3 illustrates the arrangement of the three sub-pixels in a triangular arrangement as an example.
  • the four sub-pixels can be arranged horizontally side by side, vertically side by side, or in a square, etc., and this disclosure does not limit the arrangement.
  • Figure 4 illustrates an example of four sub-pixels arranged in a square.
  • the light-emitting device may be an organic light-emitting diode (OLED), including a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together.
  • OLED organic light-emitting diode
  • the organic light-emitting layer may include an emissive layer (EML) and one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).
  • EML emissive layer
  • HIL hole injection layer
  • HTL hole transport layer
  • EBL electron blocking layer
  • HBL hole blocking layer
  • HBL hole blocking layer
  • HBL hole blocking layer
  • ETL electron transport layer
  • EIL electron injection layer
  • one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer, and electron injection layer of all sub-pixels may be common layers connected together, and the emissive layers of adjacent sub-pixels may have a small amount of overlap or may be isolated.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • Figure 5 is an equivalent circuit diagram of a pixel driving circuit.
  • Figure 5 illustrates the pixel driving circuit with an 8T1C structure as an example.
  • the pixel driving circuit can include 8 transistors (first transistor T1 to eighth transistor T8), 1 capacitor C, and can be connected to 11 signal lines (data signal line Data, first scan signal line Gate1, second scan signal line Gate2, first reset signal line Reset1, second reset signal line Reset2, light emission signal line EM, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, first power supply line VDD, and second power supply line VSS).
  • the control electrode of the first transistor T1 is connected to the first reset signal line Reset1, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor is connected to the third node N3.
  • the first transistor T1 can be referred to as the first reset transistor.
  • the first transistor T1 transmits the first initialization voltage of the first initial signal line INIT1 to the first node N1 to initialize the charge of the first node N1.
  • the control electrode of the second transistor T2 is connected to the second scan signal line Gate2, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the third node N3.
  • the second transistor T2 can be called a compensation transistor. When a conduction level scan signal is applied to the second scan signal line Gate2, the second transistor T2 connects the first node N1 and the third node N3.
  • the control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3.
  • the third transistor T3 can be called the driving transistor.
  • the third transistor T3 determines the magnitude of the driving current flowing between the first power line VDD and the second power line VSS based on the potential difference between its control electrode and its first electrode.
  • the control electrode of the fourth transistor T4 is connected to the first scan signal line Gate1, the first electrode of the fourth transistor T4 is connected to the data signal line Data, and the second electrode of the fourth transistor T4 is connected to the second node N2.
  • the fourth transistor T4 can be called a write transistor, scan transistor, etc. When a conduction-level scan signal is applied to the first scan signal line Gate1, the fourth transistor T4 causes the data voltage of the data signal line Data to be input to the pixel driving circuit.
  • the control electrode of the fifth transistor T5 is connected to the light-emitting signal line EM, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2.
  • the control electrode of the sixth transistor T6 is connected to the light-emitting signal line EM, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device EL.
  • the fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors.
  • the fifth transistor T5 and the sixth transistor T6 cause the light-emitting device to emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.
  • the control terminal of the seventh transistor T7 is connected to the second reset signal line Reset2, the first terminal of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second terminal of the seventh transistor T7 is connected to the first terminal of the light-emitting device EL.
  • the seventh transistor T7 can be referred to as the second reset transistor.
  • the seventh transistor T7 transmits an initialization voltage to the first terminal of the light-emitting device, thereby initializing or releasing the accumulated charge in the first terminal of the light-emitting device.
  • the control electrode of the eighth transistor T8 is connected to the second reset signal line Reset2, the first electrode of the eighth transistor T8 is connected to the third initial signal line INIT3, and the second electrode of the eighth transistor T8 is connected to the second node N2.
  • the eighth transistor T8 can be referred to as the third reset transistor.
  • the eighth transistor T8 transmits the initialization voltage to the second node N2 to initialize the charge accumulated in the second node N2.
  • the first terminal of capacitor C is connected to the first power supply line VDD, and the second terminal of capacitor C is connected to the first node N1.
  • the second electrode of the light-emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low-level signal, and the signal of the first power line VDD is a continuously high-level signal.
  • transistors can be classified into N-type transistors and P-type transistors.
  • a transistor When a transistor is P-type, its turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and its turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage).
  • a transistor When a transistor is N-type, its turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and its turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).
  • the first transistor T1 to the eighth transistor T8 can be either P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield.
  • the first reset signal line Reset1 and the second reset signal line Reset2 can be the same signal line.
  • At least two of the first initial signal lines INIT1, the second initial signal line INIT2, and the third initial signal line INIT3 are the same signal line.
  • the first transistor T1 to the eighth transistor T8 can all be P-type transistors, or the first transistor T1 to the eighth transistor T8 can include both P-type and N-type transistors.
  • Figure 5 illustrates an example where the second transistor T2 is an N-type transistor, and the first transistor T1, the third transistor T3 to the eighth transistor T8 are P-type transistors.
  • the first transistor T1 to the eighth transistor T8 can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor, or an oxide thin-film transistor, or a combination of both.
  • the active layer of the LTPS is made of low-temperature polycrystalline silicon, while the active layer of the oxide thin-film transistor is made of oxide.
  • LTPS transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating LTPS and oxide thin-film transistors onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.
  • LTPO low-temperature polycrystalline oxide
  • Figure 6 is a timing diagram of the pixel driving circuit shown in Figure 5. The exemplary embodiments of this disclosure are described below using the operation of the pixel driving circuit illustrated in Figure 5.
  • the operation of the pixel driving circuit may include:
  • the signals on the first reset signal line Reset1 and the second reset signal line Reset2 are low-level signals, while the signals on the first scan signal line Gate1, the second scan signal line Gate2, and the light emission signal line EM are high-level signals.
  • the low-level signal on the first reset signal line Reset1 turns on the first transistor T1
  • the signal on the first initialization signal line INIT1 is provided to the third node N3 to initialize (reset) the third node N3, clearing its original charge.
  • the high-level signal on the second scan signal line Gate2 turns on the second transistor T2, and the signal from the third node N3 is written to the first node N1 to initialize (reset) the first node N1, clearing its original charge.
  • the seventh transistor T7 is turned on.
  • the second initial signal line INIT2 is provided to the first terminal of the light-emitting device EL, initializing (resetting) the first terminal of the light-emitting device EL and clearing the original charge in the first terminal of the light-emitting device EL.
  • the eighth transistor T8 is turned on.
  • the third initial signal line INIT3 is provided to the second node N2, initializing (resetting) the second node N2 and clearing the original charge in the second node N2.
  • the fourth transistor T4 the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off. During this stage, the light-emitting device EL does not emit light.
  • the second stage, A2 is called the data writing stage or threshold compensation stage.
  • the first scan signal line Gate1 is low, while the second scan signal line Gate2, the light emission signal line EM, the first reset signal line Reset1, and the second reset signal line Reset2 are high.
  • the data signal line Data outputs a data voltage.
  • the third transistor T3 is turned on.
  • the low signal on the first scan signal line Gate1 turns on the fourth transistor T4, and the high signal on the second scan signal line Gate2 turns on the second transistor T2.
  • the turning on of the second transistor T2 and the fourth transistor T4 allows the data voltage output from the data signal line Data to be supplied to the first node N1 via the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2.
  • the difference between the data voltage output from the data signal line Data and the threshold voltage of the third transistor T3 is charged into capacitor C.
  • the voltage at the second terminal of capacitor C (first node N1) is Vd -
  • Vd is the data voltage output from the data signal line Data
  • Vth is the threshold voltage of the third transistor T3.
  • the third stage, A3, is called the light-emitting stage.
  • the light-emitting signal line EM and the second scan signal line Gate2 are at low levels, while the first scan signal line Gate1, the first reset signal line Reset1, and the second reset signal line Reset2 are at high levels.
  • the low level of the light-emitting signal line EM turns on the fifth transistor T5 and the sixth transistor T6.
  • the power supply voltage output from the first power line VDD then provides a driving voltage to the first terminal of the light-emitting device EL through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the light-emitting device EL to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and its first electrode. Since the voltage at the first node N1 is Vdata-
  • I is the driving current flowing through the third transistor T3, which is the driving current driving the light-emitting device EL
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the threshold voltage of the third transistor T3
  • Vd is the data voltage output by the data signal line Data
  • Vdd is the power supply voltage output by the first power supply line VDD.
  • the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current. This ensures uniform display brightness of the display product and improves the overall display effect of the display product.
  • Figure 7 is a schematic diagram of the structure of the display substrate provided in an embodiment of the present disclosure
  • Figure 8 is a schematic diagram of the structure of the display substrate provided in an embodiment of the present disclosure.
  • the display substrate provided in the embodiment of the present disclosure may include: a substrate and a pixel driving circuit P arranged in an array on the substrate, a plurality of initial signal line groups INITC and a plurality of initial connection lines CL.
  • the initial signal line groups INITC are electrically connected to the pixel driving circuit P and are configured to provide initial signals to the pixel driving circuit P.
  • the initial connection lines CL are electrically connected to the initial signal line groups INITC.
  • the display substrate includes a display area and a non-display area, and a pixel driving circuit P, a plurality of initial signal line groups INITC and a plurality of initial connection lines CL are disposed in the display area.
  • At least one initial signal line group includes at least one initial signal line. At least a portion of the at least one initial signal line extends along the first direction D1.
  • Multiple initial connecting lines (CLs) are arranged along the first direction D1. At least a portion of the at least one initial connecting line (CL) extends along the second direction D2.
  • the first direction D1 and the second direction D2 intersect.
  • Figure 7 illustrates the case where at least one initial signal line group (INITC) includes one initial signal line.
  • Figure 8 illustrates the case where at least one initial signal line group (INITC) includes three initial signal lines, namely the first initial signal line (INIT1) to the third initial signal line (INIT3). This disclosure does not limit the scope of the invention in any way.
  • the distance L between two adjacent initial connection lines CL along the first direction D1 is greater than or equal to 4 times the length W of the driving circuit, where the length W of the driving circuit is the length of the pixel driving circuit along the first direction D1.
  • the number of initial connection lines can be equal to the ratio of the total number of columns of the pixel driving circuit to K, where K is an integer multiple of 3 and greater than 3.
  • K can be 6, 9 or 12, and this disclosure does not limit it in any way.
  • This disclosure reduces the density of initial connection lines by setting the distance L between two adjacent initial connection lines CL along the first direction D1 to be greater than or equal to 4 times the length W of the driving circuit, thereby reducing the metal ratio of the display area and improving the light transmittance of the display substrate.
  • At least a portion of two adjacent pixel driving circuits located in the same row are symmetrically arranged along a straight line extending in the second direction D2.
  • At least one initial signal line group INITC includes: M initial signal lines, and initial connection lines include: a first initial connection line to an Mth initial connection line.
  • the mth initial connection line CL is electrically connected to the mth initial signal line INIT in the initial connection group, and multiple mth initial connection lines CL and multiple mth initial signal lines INIT in multiple initial connection groups form a mesh structure.
  • At least one initial signal line group INITC includes: first initial signal lines INIT1 to third initial signal lines INIT3, and initial connection lines include: first initial connection lines CL1 to third initial connection lines CL3.
  • the first initial connection lines CL1 are electrically connected to the first initial signal lines INIT1 in the plurality of initial signal line groups, and the plurality of first initial connection lines CL1 and the first initial signal lines INIT1 in the plurality of initial connection groups form a mesh structure.
  • the second initial connection lines CL2 are electrically connected to the second initial signal lines INIT2 in the plurality of initial signal line groups, and the plurality of second initial connection lines CL2 and the second initial signal lines INIT2 in the plurality of initial connection groups form a mesh structure.
  • the third initial connection lines CL3 are electrically connected to the third initial signal lines INIT3 in the plurality of initial signal line groups, and the plurality of third initial connection lines CL3 and the third initial signal lines INIT3 in the plurality of initial connection groups form a mesh structure.
  • the pixel driving circuit includes: M reset transistors, each transistor including a first terminal; the first terminal of the m-th reset transistor is electrically connected to the m-th initial signal line INIT and the m-th initial connection line CL in the initial signal line group INITC, where 1 ⁇ m ⁇ M, M ⁇ 1.
  • the pixel driving circuit may include: a first reset transistor (i.e., the first transistor T1), the first terminal of which is electrically connected to the first initial signal line INIT1 and the first initial connection line CL1 in the initial signal line group INITC; a second reset transistor (i.e., the seventh transistor T7), the first terminal of which is electrically connected to the second initial signal line INIT2 and the second initial connection line CL2 in the initial signal line group INITC; and a third reset transistor (i.e., the eighth transistor T8), the first terminal of which is electrically connected to the third initial signal line INIT3 and the third initial connection line CL3 in the initial signal line group INITC.
  • the display substrate includes: a plurality of pixel driving circuit groups PE, at least one pixel driving circuit group PE including: a first pixel driving circuit P1 and a second pixel driving circuit P2, the first pixel driving circuit P1 and the second pixel driving circuit P2 are at least partially symmetrically arranged with respect to a straight line extending along the second direction D2, and the plurality of pixel driving circuit groups PE are arranged in an array.
  • Figure 9 is a schematic diagram of the display substrate structure (one)
  • Figure 10 is a schematic diagram of the display substrate structure (two)
  • Figure 11 is a schematic diagram of the display substrate structure (three)
  • Figure 12 is a schematic diagram of the display substrate structure (four).
  • Figures 9 to 12 only show one initial signal line (INIT) and two initial connection lines (CL) connected to it.
  • the initial signal line group includes the first to third initial signal lines
  • the initial connection line in Figures 9 to 12 is the first initial connection line
  • the initial signal line is the first initial signal line
  • the reset transistor connected to the initial connection line in the pixel driving circuit is the first transistor.
  • the initial connection line is the second initial connection line
  • the initial signal line is the second initial signal line
  • the reset transistor connected to the initial connection line in the pixel driving circuit is the seventh transistor.
  • the initial connection line is the third initial connection line
  • the initial signal line is the third initial signal line
  • the reset transistor connected to the initial connection line in the pixel driving circuit is the eighth transistor.
  • At least a portion of the orthographic projection of an initial connection line CL onto the substrate lies between the orthographic projection of the first pixel driving circuit P1 and the second pixel driving circuit P2 onto the substrate in at least one pixel driving circuit group PE.
  • the center line O1 of at least one initial connecting line CL extending along the second direction D2 coincides with the center line O2 of at least one pixel driving circuit group PE extending along the second direction D2.
  • the distance between two adjacent initial connection lines along the first direction D1 is equal to the distance between the center line of the Rth column pixel driving circuit group PE extending along the second direction D2 and the center line of the Sth column pixel driving circuit group PE extending along the second direction D2, where S-R ⁇ 2.
  • the transistor includes an active layer, a first electrode, and a second electrode.
  • the display substrate may further include: a circuit structure layer disposed on the substrate, the circuit structure layer being provided with a pixel driving circuit, an initial signal line group and an initial connection line, the pixel driving circuit including: at least one transistor, the transistor further including: a first electrode and a second electrode;
  • the circuit structure layer includes: a semiconductor layer, a first conductive layer, and a second conductive layer sequentially stacked on a substrate;
  • the semiconductor layer includes: an active layer located in at least one transistor in at least one pixel driving circuit;
  • the first conductive layer includes at least one initial signal line in the initial signal line group
  • the second conductive layer includes: an initial connection line and a first and second electrode of at least one transistor located in at least one pixel driving circuit.
  • the display substrate may further include: a first insulating layer group and a second insulating layer group, wherein the first insulating layer group is an insulating layer located between the film layer where the initial interconnect line is located and the film layer where the initial signal line is located, and the second insulating layer group is a film layer located between the active layer of the transistor and the film layer where the initial interconnect line is located.
  • the first reset signal line, the second reset signal line, the light emission signal line, the first scan signal line, and the second scan signal line are all single-layer structures.
  • the circuit structure layer may further include: a third conductive layer, a fourth conductive layer, a fifth conductive layer, a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer.
  • the third conductive layer is located between the semiconductor layer and the first conductive layer; the fourth conductive layer is located between the third conductive layer and the first conductive layer; the fifth conductive layer is located on the side of the second conductive layer away from the substrate; the first insulating layer is located between the semiconductor layer and the third conductive layer; the second insulating layer is located between the third conductive layer and the fourth conductive layer; the third insulating layer is located between the fourth conductive layer and the first conductive layer; the fourth insulating layer is located between the first conductive layer and the second conductive layer; and the fifth insulating layer is located between the second conductive layer and the fifth conductive layer.
  • the first insulating layer group includes a fifth insulating layer
  • the second insulating layer group includes a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer.
  • the third conductive layer may include at least: the gate electrode of at least one transistor, a first reset signal line, a second reset signal line, a first scan signal line, a second scan signal line, and the first plate of at least one capacitor;
  • the fourth conductive layer may include at least: the second electrode of at least one capacitor;
  • the fifth conductive layer may include at least: a first power line and a data signal line.
  • the first reset signal line, the second reset signal line, the light emission signal line, and the first scan signal line are single-layer structures
  • the second scan signal line is a double-layer structure, including a first sub-line and a second sub-line, wherein the orthographic projection of the first sub-line on the substrate and the orthographic projection of the second sub-line on the substrate at least partially overlap.
  • the circuit structure layer may further include: a third conductive layer, a fourth conductive layer, a fifth conductive layer, a metal oxide layer, a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, and a sixth insulating layer.
  • the third conductive layer is located between the semiconductor layer and the first conductive layer; the fourth conductive layer is located between the third conductive layer and the first conductive layer; the fifth conductive layer is located on the side of the second conductive layer away from the substrate; the first insulating layer is located between the semiconductor layer and the third conductive layer; the second insulating layer is located between the third conductive layer and the fourth conductive layer; the third insulating layer is located between the fourth conductive layer and the metal oxide layer; the fourth insulating layer is located between the metal oxide layer and the first conductive layer; the fifth insulating layer is located between the first conductive layer and the second conductive layer; and the sixth insulating layer is located between the second conductive layer and the fifth conductive layer.
  • the first insulating layer group includes the fifth insulating layer
  • the second insulating layer group includes the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer.
  • the semiconductor layer includes: an active layer containing at least one P-type transistor;
  • the third conductive layer may include at least: the gate electrode of at least one P-type transistor, a first reset signal line, a second reset signal line, a first scan signal line, and the first plate of at least one capacitor;
  • the fourth conductive layer may include at least: the second plate of at least one capacitor and the first sub-line of the second scan signal line;
  • the first conductive layer may further include: a second sub-line of the second scan signal line;
  • the fifth conductive layer may include at least: a first power line and a data signal line.
  • the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.
  • the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer may be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They may be single-layer structures or multi-layer composite structures, such as Ti/Al/Ti.
  • the semiconductor layer may be made of at least one material selected from amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, and polythiophene.
  • the metal oxide layer may be at least one of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), and indium zinc tin oxide (IZTO).
  • a-IGZO amorphous indium gallium zinc oxide
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • the display substrate may further include a light-emitting structure layer disposed on the side of the circuit structure layer away from the substrate and an encapsulation structure layer disposed on the side of the light-emitting structure layer away from the substrate.
  • the display substrate may include other film layers, such as a touch structure layer, etc., which are not limited herein.
  • the light-emitting structure layer may include an anode, a pixel definition layer, an organic light-emitting layer, and a cathode 304.
  • the anode is connected to the pixel driving circuit through a via
  • the organic light-emitting layer is connected to the anode
  • the cathode is connected to the organic light-emitting layer.
  • the organic light-emitting layer emits light of the corresponding color under the driving of the anode and the cathode.
  • the encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together.
  • the first and third encapsulation layers may be made of inorganic materials, while the second encapsulation layer may be made of organic materials.
  • the second encapsulation layer is disposed between the first and third encapsulation layers to ensure that external moisture cannot enter the light-emitting structure layer.
  • the touch structure layer may include a first touch insulating layer disposed on the encapsulation structure layer, a first touch metal layer disposed on the first touch insulating layer, a second touch insulating layer covering the first touch metal layer, a second touch metal layer disposed on the second touch insulating layer, and a touch protective layer covering the second touch metal layer.
  • the first touch metal layer may include a plurality of bridging electrodes
  • the second touch metal layer may include a plurality of first touch electrodes and second touch electrodes. The first touch electrodes or the second touch electrodes may be connected to the bridging electrodes through vias.
  • the pixel driving circuit group PE includes: a first circuit group PE1 and a second circuit group PE2, wherein the orthographic projection of at least one initial connecting line CL on the substrate at least partially overlaps with the orthographic projection of the first circuit group PE1 on the substrate, and the orthographic projection of at least one initial connecting line CL on the substrate does not overlap with the orthographic projection of the second circuit group PE2 on the substrate.
  • the initial connecting line CL includes a main body portion CLA, a plurality of first connecting portions CLB, and a plurality of second connecting portions CLC, wherein the plurality of first connecting portions CLB and the plurality of second connecting portions CLC are electrically connected to the main body portion CLA.
  • the main body portion CLA extends along the second direction D2, and the orthographic projection of the main body portion CLA on the substrate is located between the orthographic projection of the first pixel driving circuit P1 and the second pixel driving circuit P2 on the substrate in the first circuit group PE1.
  • a plurality of first connecting portions CLB are arranged along the second direction D2, at least one first connecting portion CLB extends along the first direction D1 and is located on one side of the main body portion CLA, a plurality of second connecting portions CLC are arranged along the second direction D2, at least one second connecting portion CLC extends along the first direction D1 and is located on the other side of the main body portion CLA, the plurality of first connecting portions CLB and the plurality of second connecting portions CLC correspond one-to-one, and the first connecting portion CLB and the corresponding second connecting portion CLC extend along the first direction D1.
  • the orthographic projections of the first connecting portion CLB and the second connecting portion CLC on the substrate at least partially overlap with the orthographic projections of the initial signal line INIT connected to the initial connecting line CL on the substrate.
  • the active layer 11-1 of the reset transistor connected to the initial connection line CL in the first pixel driving circuit P1 of the first circuit group PE1 and the active layer 11-2 of the reset transistor connected to the initial connection line CL in the second pixel driving circuit P2 are spaced apart and symmetrically arranged with respect to the straight line O2 extending along the second direction D2;
  • the active layer 11-1 of the reset transistor connected to the initial connection line CL in the first pixel driving circuit P1 of the second circuit group PE2 and the active layer 11-2 of the reset transistor connected to the initial connection line CL in the second pixel driving circuit P2 are spaced apart and symmetrically arranged with respect to the straight line O extending along the second direction D2.
  • the first electrode 13-113-1 of the reset transistor connected to the initial connection line CL in the first pixel driving circuit P1 of the first circuit group PE1 is located on the first side of the main body portion CLA and is electrically connected to the first connection portion CLB.
  • the first electrode 13-2 of the reset transistor connected to the initial connection line CL in the second pixel driving circuit P2 of the first circuit group PE1 is located on the second side of the main body portion CLA and is electrically connected to the second connection portion CLC.
  • the first electrode 13-1 of the reset transistor connected to the initial connection line CL in the first pixel driving circuit P1 of the first circuit group PE1 and the first electrode 13-2 of the reset transistor connected to the initial connection line CL in the second pixel driving circuit P2 of the first circuit group PE1 are arranged along the first direction D1.
  • the first pole 13-1 of the reset transistor connected to the initial connection line CL in the first pixel driving circuit P1 of the second circuit group PE2 is spaced apart from the first pole 13-2 of the reset transistor connected to the initial connection line CL in the second pixel driving circuit P2.
  • the orthographic projection of the first electrode of the reset transistor connected to the initial connection line CL in at least one pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the initial signal line INIT connected to the initial connection line CL on the substrate.
  • the orthographic projection of the first electrode 13-1 of the reset transistor connected to the initial connection line CL in the first pixel driving circuit P1 in at least one of the first circuit groups PE1 and PE2 at least partially overlaps with the orthographic projection of the initial signal line INIT connected to the initial connection line CL on the substrate.
  • the orthographic projection of the first electrode 13-2 of the reset transistor connected to the initial connection line CL in the second pixel driving circuit P2 in at least one of the first circuit groups PE1 and PE2 at least partially overlaps with the orthographic projection of the initial signal line INIT connected to the initial connection line CL on the substrate.
  • the first terminal 13-1 of the reset transistor connected to the initial connection line CL in the first pixel driving circuit P1 of the first circuit group PE1 is in a zigzag shape with the first connection portion CLB.
  • the first terminal 13-1 of the reset transistor connected to the initial connection line CL in the first pixel driving circuit P1 of the first circuit group PE1 and the first connection portion CLB can be arranged at a right angle.
  • the first terminal 13-2 of the reset transistor connected to the initial connection line CL in the second pixel driving circuit P2 of the first circuit group PE1 is in a zigzag shape with the second connection portion CLC.
  • the first terminal 13-2 of the reset transistor connected to the initial connection line CL in the second pixel driving circuit P2 of the first circuit group PE1 and the second connection portion CLC can be arranged at a right angle.
  • the first insulating layer group may include: a second via V2 and a third via V3 exposing the initial signal line INIT; the first terminal 13-1 of the reset transistor in the first pixel driving circuit P1 of at least one circuit group in the first circuit group PE1 and the second circuit group PE2, which is connected to the initial connection line CL, is electrically connected to the initial signal line INIT through the second via V2; and the first terminal 13-2 of the reset transistor in the second pixel driving circuit P2 of at least one circuit group in the first circuit group PE1 and the second circuit group PE2, which is connected to the initial connection line CL, is electrically connected to the initial signal line INIT through the third via V3.
  • the second insulating layer group includes a first via exposing the active layer of a reset transistor connected to the initial connection line CL in the pixel driving circuit.
  • the first terminal of the reset transistor connected to the initial connection line CL in the pixel driving circuit is connected to the active layer of the reset transistor through the first via.
  • the first via V1-1 exposing the active layer 11-1 of the reset transistor connected to the initial connection line CL in the first pixel driving circuit P1 of the first circuit group PE1 is different from the first via V1-2 exposing the active layer of the reset transistor connected to the initial connection line CL in the second pixel driving circuit P2 of the first circuit group PE1.
  • the first via V1-1 exposing the active layer of the reset transistor connected to the initial connection line CL in the first pixel driving circuit P1 of the second circuit group PE2 is different from the first via V1-2 exposing the active layer of the reset transistor connected to the initial connection line CL in the second pixel driving circuit P2 of the second circuit group PE2.
  • the active layer 11-111-1 of the reset transistor connected to the initial connection line CL in the first pixel driving circuit P1 of the first circuit group PE1 and the active layer 11-2 of the reset transistor connected to the initial connection line CL in the second pixel driving circuit P2 are integral structures and are symmetrically arranged with respect to the straight line O2 extending along the second direction D2.
  • the active layer 11-1 of the reset transistor connected to the initial connection line CL in the first pixel driving circuit P1 located in the first circuit group PE1 and the active layer 11-2 of the reset transistor connected to the initial connection line CL in the second pixel driving circuit P2 are integrated in a " ⁇ " shape.
  • the active layer 11-1 of the reset transistor connected to the initial connection line CL in the first pixel driving circuit P1 of the second circuit group PE2 is spaced apart from the active layer 11-2 of the reset transistor connected to the initial connection line CL in the second pixel driving circuit P2, and is symmetrically arranged with respect to the straight line O extending along the second direction D2.
  • the first electrode 13-1 of the reset transistor connected to the initial connection line CL in the first pixel driving circuit P1 of the first circuit group PE1 and the first electrode 13-2 of the reset transistor connected to the initial connection line CL in the second pixel driving circuit P2 are the same electrode and are part of the main body CLA of the initial connection line CL.
  • the first pole 13-1 of the reset transistor connected to the initial connection line CL in the first pixel driving circuit P1 of the second circuit group PE2 is spaced apart from the first pole 13-2 of the reset transistor connected to the initial connection line CL in the second pixel driving circuit P2.
  • the orthographic projection of the first electrode of the reset transistor connected to the initial connection line CL in at least one pixel driving circuit in the first circuit group PE1 onto the substrate does not overlap with the orthographic projection of the initial signal line INIT connected to the initial connection line CL onto the substrate.
  • the orthographic projection of the first electrode 13-1 of the reset transistor connected to the initial connection line CL in the first pixel driving circuit P1 of the first circuit group PE1 onto the substrate does not overlap with the orthographic projection of the initial signal line INIT connected to the initial connection line CL onto the substrate
  • the orthographic projection of the first electrode 13-2 of the reset transistor connected to the initial connection line CL in the second pixel driving circuit P2 of the first circuit group PE1 onto the substrate does not overlap with the orthographic projection of the initial signal line INIT connected to the initial connection line CL onto the substrate.
  • the orthographic projection of the first electrode of the reset transistor connected to the initial connection line CL in at least one pixel driving circuit of the second circuit group PE2 onto the substrate at least partially overlaps with the orthographic projection of the initial signal line INIT connected to the initial connection line CL onto the substrate.
  • the orthographic projection of the first electrode 13-1 of the reset transistor connected to the initial connection line CL in the first pixel driving circuit P1 of the second circuit group PE2 onto the substrate at least partially overlaps with the orthographic projection of the initial signal line INIT connected to the initial connection line CL onto the substrate
  • the orthographic projection of the first electrode 13-2 of the reset transistor connected to the initial connection line CL in the second pixel driving circuit P2 of the second circuit group PE2 onto the substrate at least partially overlaps with the orthographic projection of the initial signal line INIT connected to the initial connection line CL onto the substrate.
  • the first insulating layer group includes: a second via V2 and a third via V3 exposing the initial signal line INIT; a first connection portion CLB is electrically connected to the initial signal line INIT through the second via V2; a second connection portion CLB is electrically connected to the initial signal line INIT through the third via V3; the first terminal 13-1 of the reset transistor in the first pixel driving circuit P1 located in the second circuit group PE2, which is connected to the initial connection line CL, is electrically connected to the initial signal line INIT through the second via V2; and the first terminal 13-2 of the reset transistor in the second pixel driving circuit P2 located in the second circuit group PE2, which is connected to the initial connection line CL, is electrically connected to the initial signal line INIT through the third via V3.
  • the second insulating layer group includes: a first via exposing the active layer of the reset transistor connected to the initial connection line CL in the pixel driving circuit, wherein the first electrode of the reset transistor connected to the initial connection line CL in the pixel driving circuit is connected to the active layer of the reset transistor through the first via, wherein the first via V1-1 exposing the active layer of the reset transistor connected to the initial connection line CL in the first pixel driving circuit P1 located in the first circuit group PE1 and the first via V1-2 exposing the active layer of the reset transistor connected to the initial connection line CL in the second pixel driving circuit P2 located in the first circuit group PE1 are the same via, and the first via V1-1 exposing the active layer of the reset transistor connected to the initial connection line CL in the first pixel driving circuit P1 located in the second circuit group PE2 and the first via V1-2 exposing the active layer of the reset transistor connected to the initial connection line CL in the second pixel driving circuit P2 located in the second circuit group PE2 are different vias.
  • the active layer 11-1 of the reset transistor connected to the initial connection line CL in the first pixel driving circuit P1 of the first circuit group PE1 and the active layer 11-2 of the reset transistor connected to the initial connection line CL in the second pixel driving circuit P2 are integral structures and are symmetrically arranged relative to the straight line extending along the second direction D2.
  • the active layer 11-1 of the reset transistor connected to the initial connection line CL in the first pixel driving circuit P1 of the first circuit group PE1 and the active layer 11-2 of the reset transistor connected to the initial connection line CL in the second pixel driving circuit P2 are integrated in a "U" shape.
  • the active layer 11-1 of the reset transistor connected to the initial connection line CL in the first pixel driving circuit P1 of the second circuit group PE2 is an integral structure with the active layer of the reset transistor connected to the initial connection line CL in the second pixel driving circuit P2, and is symmetrically arranged with respect to the straight line extending along the second direction D2.
  • the active layer 11-1 of the reset transistor connected to the initial connection line CL in the first pixel driving circuit P1 of the second circuit group PE2 and the active layer 11-2 of the reset transistor connected to the initial connection line CL in the second pixel driving circuit P2 are integrated in a " ⁇ " shape.
  • the initial connecting line CL is a line shape extending along the second direction D2.
  • the first electrode 13-1 of the reset transistor connected to the initial connection line CL in the first pixel driving circuit P1 of the first circuit group PE1 and the first electrode 13-2 of the reset transistor connected to the initial connection line CL in the second pixel driving circuit P2 are the same electrode and are part of the initial connection line CL.
  • the first electrode 13-1 of the reset transistor connected to the initial connection line CL in the first pixel driving circuit P1 of the second circuit group PE2 and the first electrode 13-2 of the reset transistor connected to the initial connection line CL in the second pixel driving circuit P2 are integral structures and extend along the second direction D2.
  • the orthographic projection of the first electrode of the reset transistor connected to the initial connection line CL in at least one pixel driving circuit of at least one circuit group in the first circuit group PE1 and the second circuit group PE2 onto the substrate at least partially overlaps with the orthographic projection of the initial signal line INIT connected to the initial connection line CL onto the substrate.
  • the orthographic projection of the first electrode 13-1 of the reset transistor connected to the initial connection line CL in the first pixel driving circuit P1 of at least one circuit group in the first circuit group PE1 and the second circuit group PE2 onto the substrate at least partially overlaps with the orthographic projection of the initial signal line INIT connected to the initial connection line CL onto the substrate.
  • the orthographic projection of the first electrode 13-2 of the reset transistor connected to the initial connection line CL in the second pixel driving circuit P2 of at least one circuit group in the first circuit group PE1 and the second circuit group PE2 onto the substrate at least partially overlaps with the orthographic projection of the initial signal line INIT connected to the initial connection line CL onto the substrate.
  • the first insulating layer group includes a second via V2 exposing the initial signal line INIT.
  • the first terminal of a reset transistor connected to the initial connection line CL in at least one pixel driving circuit in at least one of the first circuit groups PE1 and PE2 is electrically connected to the initial signal line INIT through the second via V2.
  • the first terminal 13-1 of the reset transistor 13-1 (which is also the first terminal 13-2 of the reset transistor 13-2 connected to the initial connection line CL in the first pixel driving circuit P1 in at least one of the first circuit groups PE1 and PE2) is electrically connected to the initial signal line INIT through the second via V2.
  • the second insulating layer group includes: a first via exposing the active layer of the reset transistor connected to the initial connection line CL in the pixel driving circuit, wherein the first terminal of the reset transistor connected to the initial connection line CL in the pixel driving circuit is connected to the active layer of the reset transistor through the first via, wherein the first via V1-1 exposing the active layer of the reset transistor connected to the initial connection line CL in the first pixel driving circuit P1 located in the first circuit group PE1 and the active layer exposing the reset transistor connected to the initial connection line CL in the second pixel driving circuit P2 located in the first circuit group PE1 are connected to the active layer of the reset transistor connected to the initial connection line CL in the first circuit group PE1.
  • the first via V1-2 is the same via, exposing the active layer of the reset transistor connected to the initial connection line CL in the first pixel driving circuit P1 of the second circuit group PE2.
  • the first via V1-1 and the second via V1-2 that expose the active layer of the reset transistor connected to the initial connection line CL in the second pixel driving circuit P2 of the second circuit group PE2 are the same via, and the first via and the second via V2 that expose the active layer of the reset transistor connected to the initial connection line CL in the pixel driving circuit of at least one of the first circuit group PE1 and the second circuit group PE2 are arranged along the second direction D2.
  • the initial connection line CL includes a first body portion CLE and a first protrusion CLF electrically connected to each other
  • the initial signal line INIT includes a second body portion NT1 and a second protrusion NT2 electrically connected to each other.
  • the first body portion CLE extends along the second direction D2, and the orthographic projection of the first body portion CLE on the substrate is located between the orthographic projection of the first pixel driving circuit P1 and the orthographic projection of the second pixel driving circuit P2 on the substrate in the first circuit group PE1.
  • the first protrusion CLF extends along the first direction D1 and is located on one side of the first body portion CLE.
  • the second body portion NT1 extends along the first direction D1
  • the second protrusion NT2 extends along the second direction D2 and is located on one side of the second body portion NT1.
  • the orthographic projection of the first protrusion CLF on the substrate at least partially overlaps with the orthographic projection of the second protrusion NT2 on the substrate, and is electrically connected to the second protrusion NT2.
  • the first electrode 13-1 of the reset transistor connected to the initial connection line CL in the first pixel driving circuit P1 of the first circuit group PE1 and the first electrode 13-2 of the reset transistor connected to the initial connection line CL in the second pixel driving circuit P2 are the same electrode and are part of the first main body portion CLE of the initial connection line CL.
  • the first electrode 13-1 of the reset transistor connected to the initial connection line CL in the first pixel driving circuit P1 of the second circuit group and the first electrode 13-2 of the reset transistor connected to the initial connection line CL in the second pixel driving circuit P2 are integral structures and extend along the second direction D2.
  • the first insulating layer group includes: a second via exposing a second protrusion NT2 of the initial signal line INIT and a third via exposing a second body portion NT1 of the initial signal line INIT.
  • the first protrusion CLF is electrically connected to the second protrusion NT2 through the second via V2.
  • the first terminal of the reset transistor in at least one pixel driving circuit in the second circuit group, which is connected to the initial connection line CL, is electrically connected to the second body portion NT1 of the initial signal line INIT through the third via V3.
  • the second insulating layer group includes: a first via exposing the active layer of the reset transistor connected to the initial connection line CL in the pixel driving circuit.
  • the first electrode of the reset transistor connected to the initial connection line in the pixel driving circuit is connected to the active layer of the reset transistor through the first via.
  • the first via V1-1 exposing the active layer of the reset transistor connected to the initial connection line CL in the first pixel driving circuit P1 of the first circuit group and the first via V1-2 exposing the active layer of the reset transistor connected to the initial connection line CL in the second pixel driving circuit P2 of the first circuit group are the same via.
  • the first via V1-1 of the active layer of the reset transistor connected to the initial connection line CL and the first via V1-2 of the active layer of the reset transistor connected to the initial connection line CL in the second pixel driving circuit P2 of the second circuit group are the same via; the first via V1-1 (V1-2) and the second via V2 of the active layer of the reset transistor connected to the initial connection line CL in at least one pixel driving circuit of the first circuit group PE1 are arranged along the first direction D1, and the first via V1-1 (V1-2) and the third via V3 of the active layer of the reset transistor connected to the initial connection line CL in at least one pixel driving circuit of the second circuit group PE2 are arranged along the second direction D2.
  • the second electrode 14-1 of the reset transistor connected to the initial connection line in the first pixel driving circuit P1 in at least one of the first circuit group PE1 and the second circuit group PE is a different electrode from the second electrode 14-2 of the reset transistor connected to the initial connection line in the second pixel driving circuit, and they are symmetrically arranged with respect to the straight line O2 extending along the second direction D2.
  • the display substrates shown in Figures 10 to 12 while maintaining the symmetrical structure of two adjacent sub-pixels, reduce the number of vias in the display substrate and simplify the structure of the initial signal lines, further simplifying the process of the display substrate and saving the manufacturing cost of the display substrate.
  • FIG13 is a top view of the display substrate
  • FIG14 is a schematic diagram of a portion of the film layer in FIG13
  • FIG15 is a schematic diagram of a portion of the film layer in FIG13.
  • FIG13 includes two pixel driving circuits as shown in FIG5, and the pixel driving circuit includes a P-type transistor and an N-type transistor as an example for illustration.
  • the pixel driving circuit further includes a capacitor; the capacitor includes a first plate and a second plate.
  • the orthographic projection of at least one initial signal line in the initial signal line group connected to the pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of at least one of the first plates C1 and the second plates C2 of the capacitor on the substrate.
  • Figures 13 to 15 illustrate the case where the orthographic projection of the third initial signal line INIT3 on the substrate at least partially overlaps with the orthographic projections of the first plate C1 and the second plate C2 of the capacitor on the substrate.
  • the orthographic projection of the first power line VDD on the substrate at least partially overlaps with the orthographic projection of at least one initial signal line in the initial signal line group on the substrate.
  • the orthographic projection of at least one initial signal line in the initial signal line group connected to the pixel driving circuit onto the substrate at least partially overlaps with the orthographic projection of at least one of the first plate C1 and the second plate C2 of the capacitor onto the substrate. This can reduce the space occupied by the metal in the pixel driving circuit and further improve the light transmittance of the display substrate.
  • the first power line VDD can shield the signal of at least one initial signal line in the initial signal line group connected to the pixel driving circuit, thereby preventing the signal of at least one initial signal line in the initial signal line group connected to the pixel driving circuit from being interfered with by other AC signals, and thus improving the display effect of the display substrate.
  • the control display substrate refers to a display substrate in which the distance between adjacent initial connection lines along the first direction is equal to twice the length of the driving circuit.
  • This disclosure also provides a display device, including a display substrate.
  • the display substrate is the same as the display substrate provided in any of the foregoing embodiments, and the implementation principle and effect are similar, so it will not be described again here.
  • the display device can be any product or component with display function, such as electronic paper, OLED panel, active-matrix organic light emitting diode (AMOLED) panel, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, etc.
  • display function such as electronic paper, OLED panel, active-matrix organic light emitting diode (AMOLED) panel, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, etc.

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Abstract

一种显示基板和显示装置，其中，显示基板包括：基底以及设置在基底上的阵列排布的像素驱动电路(P)、多个初始信号线组(INITC)和多条初始连接线(CL)，初始信号线组(INITC)，与像素驱动电路(P)电连接，被配置为向像素驱动电路(P)提供初始信号，初始连接线(CL)与初始信号线组(INITC)电连接；多个初始信号线组(INITC)沿第二方向(D2)排布，至少一个初始信号线组(INITC)包括至少一条初始信号线，至少一条初始信号线的至少部分沿第一方向(D1)延伸，多条初始连接线沿第一方向(D1)排布，至少一条初始连接线的至少部分沿第二方向(D2)延伸，相邻两条初始连接线(CL)沿第一方向(D1)之间的距离(L)大于或者等于驱动电路长度(W)的4倍。

Description

显示基板和显示装置
本申请要求于2024年5月15日提交的、申请号为202410606083.2、发明名称为“显示基板和显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本文涉及显示技术领域，具体涉及一种显示基板和显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开提供了一种显示基板，包括：基底以及设置在所述基底上的阵列排布的像素驱动电路、多个初始信号线组和多条初始连接线，所述初始信号线组，与所述像素驱动电路电连接，被配置为向所述像素驱动电路提供初始信号，所述初始连接线与所述初始信号线组电连接；
所述多个初始信号线组沿第二方向排布，至少一个初始信号线组包括至少一条初始信号线，至少一条初始信号线的至少部分沿第一方向延伸，所述多条初始连接线沿第一方向排布，至少一条初始连接线的至少部分沿第二方向延伸，所述第一方向和所述第二方向相交；
相邻两条初始连接线沿所述第一方向之间的距离大于或者等于驱动电路长度的4倍，所述驱动电路长度为像素驱动电路沿第一方向的长度。
在示例性实施方式中，至少一个初始信号线组包括：M条初始信号线，所述初始连接线包括：第一初始连接线至第M初始连接线；
第m初始连接线与所述初始连接组中的第m条初始信号线电连接，多条第m初始连接线与所述多个初始连接组中的第m条初始信号线形成网状结构；
所述像素驱动电路包括：M个复位晶体管，晶体管包括：第一极；第m个复位晶体管的第一极分别与初始信号线组中的第m条初始信号线和第m初始连接线电连接，1≤m≤M，M≥1。
在示例性实施方式中，所述显示基板包括：多个像素驱动电路组，至少一个像素驱动电路组包括：第一像素驱动电路和第二像素驱动电路，所述第一像素驱动电路和所述第二像素驱动电路相对于沿所述第二方向延伸的直线至少部分对称设置，多个像素驱动电路组呈阵列排布；
至少一条初始连接线的至少部分在基底上的正投影位于至少一个像素驱动电路组中的所述第一像素驱动电路在基底上的正投影和所述第二像素驱动电路在基底上的正投影之间。
在示例性实施方式中，至少一条初始连接线沿所述第二方向延伸的中线与至少一个像素驱动电路组沿第二方向延伸的中线重合。
在示例性实施方式中，相邻两条初始连接线沿所述第一方向之间的距离等于第R列像素驱动电路组沿第二方向延伸的中线与第S列像素驱动电路组沿第二方向延伸的中线之间的距离，S-R≥2。
在示例性实施方式中，所述像素驱动电路组包括：第一电路组和第二电路组，至少一条初始连接线在基底上的正投影与所述第一电路组在基底上的正投影至少部分交叠，至少一条初始连接线在基底上的正投影与所述第二电路组在基底上的正投影不存在交叠区域。
在示例性实施方式中，所述初始连接线包括主体部、多个第一连接部和多个第二连接部，所述多个第一连接部和所述多个第二连接部分别与主体部电连接；
所述主体部沿第二方向延伸，且所述主体部在基底上的正投影位于所述第一电路组中的第一像素驱动电路在基底上的正投影和所述第二像素驱动电路在基底上的正投影之间，多个第一连接部沿第二方向排布，至少一个第一连接部沿第一方向延伸，且位于所述主体部的一侧，所述多个第二连接部沿第二方向排布，至少一个第二连接部沿第一方向延伸，且位于所述主体部的另一侧，多个第一连接部和多个第二连接部一一对应，第一连接部与对应的第二连接部沿第一方向延伸；
所述第一连接部和所述第二连接部在基底上的正投影与所述初始连接线所连接的初始信号线在基底上的正投影至少部分交叠。
在示例性实施方式中，所述晶体管还包括：有源层；
对于至少一条初始连接线，位于所述第一电路组的第一像素驱动电路中的与所述初始连接线连接的复位晶体管的有源层与所述第二像素驱动电路中的与初始连接线连接的复位晶体管的有源层间隔设置，且相对于沿第二方向延伸的直线对称设置；
位于所述第二电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的有源层与所述第二像素驱动电路中的与初始连接线连接的复位晶体管的有源层间隔设置，且相对于沿第二方向延伸的直线对称设置。
在示例性实施方式中，对于至少一条初始连接线，位于第一电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的第一极位于所述主体部的第一侧，且与第一连接部电连接，位于第一电路组的第二像素驱动电路中的与初始连接线连接的复位晶体管的第一极位于所述主体部的第二侧，且与第二连接部电连接，位于第一电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的第一极和位于第一电路组的第二像素驱动电路中的与初始连接线连接的复位晶体管的第一极沿第一方向排布；
位于第二电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的第一极与第二像素驱动电路中的与初始连接线连接的复位晶体管的第一极间隔设置；
位于至少一个像素驱动电路中的与初始连接线连接的复位晶体管的第一极在基底上的正投影与初始连接线连接的初始信号线在基底上的正投影至少部分交叠；
位于第一电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的第一极与第一连接部呈折线形，位于第一电路组的第二像素驱动电路中的与初始连接线连接的复位晶体管的第一极与第二连接部呈折线形。
在示例性实施方式中，所述显示基板包括：第一绝缘层组和第二绝缘层组，所述第一绝缘层组为位于初始连接线所在的膜层和初始信号线所在的膜层之间的绝缘层，所述第二绝缘层组为位于晶体管的有源层所在的膜层和初始连接线所在的膜层；
所述第一绝缘层组包括：暴露出初始信号线的第二过孔和第三过孔，位于第一电路组和第二电路组中的至少一个电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的第一极通过第二过孔与初始信号线电连接，位于第一电路组和第二电路组中的至少一个电路组的第二像素驱动电路中的与初始连接线连接的复位晶体管的第一极通过第三过孔与初始信号线电连接；
所述第二绝缘层组包括：暴露出像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔，像素驱动电路中的与初始连接线连接的复位晶体管的第一极通过第一过孔与复位晶体管的有源层连接，其中，暴露出位于第一电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔与暴露出位于第一电路组的第二像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔为不同过孔，暴露出位于第二电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔与暴露出位于第二电路组的第二像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔为不同过孔。
在示例性实施方式中，所述晶体管还包括：有源层；
对于至少一条初始连接线，位于所述第一电路组的第一像素驱动电路中的与所述初始连接线连接的复位晶体管的有源层与所述第二像素驱动电路中的与初始连接线连接的复位晶体管的有源层为一体结构，且相对于沿第二方向延伸的直线对称设置；
位于所述第二电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的有源层与所述第二像素驱动电路中的与初始连接线连接的复位晶体管的有源层间隔设置，且相对于沿第二方向延伸的直线对称设置。
在示例性实施方式中，对于至少一条初始连接线，位于第一电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的第一极和第二像素驱动电路中的与初始连接线连接的复位晶体管的第一极为同一电极，且作为所述初始连接线的主体部的一部分；
位于第二电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的第一极与第二像素驱动电路中的与初始连接线连接的复位晶体管的第一极间隔设置；
位于第一电路组的至少一个像素驱动电路中的与初始连接线连接的复位晶体管的第一极在基底上的正投影与初始连接线连接的初始信号线在基底上的正投影不交叠，位于第二电路组的至少一个像素驱动电路中的与初始连接线连接的复位晶体管的第一极在基底上的正投影与初始连接线连接的初始信号线在基底上的正投影至少部分交叠。
在示例性实施方式中，包括：第一绝缘层组和第二绝缘层组，所述第一绝缘层组为位于初始连接线所在的膜层和初始信号线所在的膜层之间的绝缘层，第二绝缘层组为位于晶体管的有源层所在的膜层和初始连接线所在的膜层；
所述第一绝缘层组包括：暴露出初始信号线的第二过孔和第三过孔，第一连接部通过第二过孔与初始信号线电连接，第二连接部通过第三过孔与初始信号线电连接，位于第二电路组中的第一像素驱动电路中的与初始连接线连接的复位晶体管的第一极通过第二过孔与初始信号线电连接，位于第二电路组中的第二像素驱动电路中的与初始连接线连接的复位晶体管的第一极通过第三过孔与初始信号线电连接；
所述第二绝缘层组包括：暴露出像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔，像素驱动电路中的与初始连接线连接的复位晶体管的第一极通过第一过孔与复位晶体管的有源层连接，其中，暴露出位于第一电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔与暴露出位于第一电路组的第二像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔为同一过孔，暴露出位于第二电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔与暴露出位于第二电路组的第二像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔为不同过孔。
在示例性实施方式中，所述晶体管还包括：有源层；
对于至少一条初始连接线，位于第一电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的有源层与第二像素驱动电路中的与初始连接线连接的复位晶体管的有源层为一体结构，且相对于初沿第二方向延伸的直线对称设置；
位于第二电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的有源层与第二像素驱动电路中的与初始连接线连接的复位晶体管的有源层为一体结构，且相对于沿第二方向延伸的直线对称设置。
在示例性实施方式中，所述初始连接线为沿第二方向延伸的线形状。
在示例性实施方式中，对于至少一条初始连接线，位于第一电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的第一极和第二像素驱动电路中的与初始连接线连接的复位晶体管的第一极为同一电极，且作为初始连接线的一部分；
位于第二电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的第一极与第二像素驱动电路中的与初始连接线连接的复位晶体管的第一极为一体结构，且沿第二方向延伸；
位于第一电路组和第二电路组中的至少一个电路组的至少一个像素驱动电路中的与初始连接线连接的复位晶体管的第一极在基底上的正投影与初始连接线连接的初始信号线在基底上的正投影至少部分交叠。
在示例性实施方式中，包括：第一绝缘层组和第二绝缘层组，所述第一绝缘层组为位于初始连接线所在的膜层和初始信号线所在的膜层之间的绝缘层，第二绝缘层组为位于晶体管的有源层所在的膜层和初始连接线所在的膜层；
所述第一绝缘层组包括：暴露出初始信号线的第二过孔，位于第一电路组和第二电路组中的至少一个电路组中的至少一个像素驱动电路中的与初始连接线连接的复位晶体管的第一极通过第二过孔与初始信号线电连接；
所述第二绝缘层组包括：暴露出像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔，像素驱动电路中的与初始连接线连接的复位晶体管的第一极通过第一过孔与复位晶体管的有源层连接，其中，暴露出位于第一电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔与暴露出位于第一电路组的第二像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔为同一过孔，暴露出位于第二电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔与暴露出位于第二电路组的第二像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔为同一过孔；
暴露出位于第一电路组和第二电路组中的至少一个电路组的像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔与第二过孔沿第二方向排布。
在示例性实施方式中，所述初始连接线包括：相互电连接的第一主体部和第一凸起部，所述初始信号线包括：相互电连接的第二主体部和第二凸起部；
所述第一主体部沿第二方向延伸，且所述第一主体部在基底上的正投影位于所述第一电路组中的第一像素驱动电路在基底上的正投影和第二像素驱动电路在基底上的正投影之间，所述第一凸起部沿第一方向延伸，且位于第一主体部的一侧；
所述第二主体部沿第一方向延伸，所述第二凸起部沿第二方向延伸，且位于第二主体部的一侧；
所述第一凸起部在基底上的正投影与所述第二凸起部在基底上的正投影至少部分交叠，且与所述第二凸起部电连接。
在示例性实施方式中，对于至少一条初始连接线，位于第一电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的第一极和第二像素驱动电路中的与初始连接线连接的复位晶体管的第一极为同一电极，且作为初始连接线的第一主体部的一部分；
位于第二电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的第一极与第二像素驱动电路中的与初始连接线连接的复位晶体管的第一极为一体结构，且沿第二方向延伸。
在示例性实施方式中，包括：第一绝缘层组和第二绝缘层组，所述第一绝缘层组为位于初始连接线所在的膜层和初始信号线所在的膜层之间的绝缘层，第二绝缘层组为位于晶体管的有源层所在的膜层和初始连接线所在的膜层；
所述第一绝缘层组包括：第二凸起部的第二过孔和暴露出初始信号线的第二主体部的第三过孔，第一凸起部通过第二过孔与第二凸起部电连接，位于第二电路组中的至少一个像素驱动电路中的与初始连接线连接的复位晶体管的第一极通过第三过孔与初始信号线的第二主体部电连接；
所述第二绝缘层组包括：暴露出像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔，像素驱动电路中的与初始连接线连接的复位晶体管的第一极通过第一过孔与复位晶体管的有源层连接，其中，暴露出位于第一电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔与暴露出位于第一电路组的第二像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔为同一过孔，暴露出位于第二电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔与暴露出位于第二电路组的第二像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔为同一过孔；
暴露出位于第一电路组的至少一个像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔与所述第二过孔沿第一方向排布，暴露出位于第二电路组的至少一个像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔与所述第三过孔沿第二方向排布。
在示例性实施方式中，所述像素驱动电路还包括：电容；电容包括：第一极板和第二极板；
对于至少一个像素驱动电路，像素驱动电路所连接的初始信号线组中的至少一条初始信号线在基底上的正投影与电容的第一极板和第二极板中的至少一个极板在基底上的正投影至少部分交叠。
在示例性实施方式中，还包括：设置在基底上的电路结构层，所述电路结构层设置有像素驱动电路、初始信号线组和初始连接线，所述像素驱动电路包括：至少一个晶体管，晶体管还包括：第一极和第二极；
所述电路结构层包括：依次叠设在基底上的半导体层、第一导电层和第二导电层；
半导体层包括：位于至少一个像素驱动电路中的至少一个晶体管的有源层；
第一导电层包括：初始信号线组中的至少一条初始信号线；
第二导电层包括：初始连接线以及位于至少一个像素驱动电路中的至少一个晶体管的第一极和第二极。
在示例性实施方式中，还包括：第一电源线，所述第一电源线与像素驱动电路电连接；
所述第一电源线在基底上的正投影与初始信号线组中的至少一条初始信号线在基底上的正投影至少部分交叠。
第二方面，本公开还提供了一种显示装置，包括：上述显示基板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本申请技术方案的理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本申请的技术方案，并不构成对本申请技术方案的限制。
图1为一种显示装置的结构示意图；
图2为一种显示基板的平面结构示意图；
图3为另一显示基板的平面结构示意图；
图4为又一显示基板的平面结构示意图；
图5为一种像素驱动电路的等效电路示意图；
图6为图5提供的像素驱动电路的工作时序图；
图7为本公开实施例提供的显示基板的结构示意图一；
图8为本公开实施例提供的显示基板的结构示意图二；
图9为显示基板的结构示意图一；
图10为显示基板的结构示意图二；
图11为显示基板的结构示意图三；
图12为显示基板的结构示意图四；
图13为显示基板的俯视图；
图14为图13中部分膜层示意图一
图15为图13中部分膜层示意图二。
详述
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
在本说明书中，所采用的“同层设置”是指两种(或两种以上)结构通过同一次图案化工艺得以图案化而形成的结构，它们的材料可以相同或不同。例如，形成同层设置的多种结构的前驱体的材料是相同的，最终形成的材料可以相同或不同。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示装置的结构示意图。如图1所示，显示装置可以包括时序控制器、数据信号驱动器、扫描信号驱动器、发光信号驱动器和像素阵列，时序控制器分别与数据信号驱动器、扫描信号驱动器和发光信号驱动器连接，数据信号驱动器分别与多个数据信号线(D1到Dn)连接，扫描信号驱动器分别与多个扫描信号线(GATE1到Sm)连接，发光信号驱动器分别与多个发光信号线(E1到Eo)连接。像素阵列可以包括多个子像素Pxij，i和j可以是自然数，至少一个子像素Pxij可以包括电路单元和与电路单元连接的发光器件，电路单元可以包括像素驱动电路，像素驱动电路可以分别与扫描信号线、发光信号线和数据信号线连接。
在示例性实施方式中，时序控制器可以将适合于数据信号驱动器的规格的灰度值和控制信号提供到数据信号驱动器，可以将适合于扫描信号驱动器的规格的时钟信号、扫描起始信号等提供到扫描信号驱动器，可以将适合于发光信号驱动器的规格的时钟信号、发射停止信号等提供到发光信号驱动器。数据信号驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据信号驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn，n可以是自然数。扫描信号驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线GATE1、GATE2、S3、……和Sm的扫描信号。例如，扫描信号驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线GATE1至Sm。例如，扫描信号驱动器可以被构造为移位寄存器的形式，并且可以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光信号驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发射信号。例如，发光信号驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光信号驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发射停止信号传输到下一级电路的方式产生发射信号，o可以是自然数。
图2为一种显示基板的平面结构示意图，图3为另一显示基板的平面结构示意图，图4为又一显示基板的平面结构示意图。如图2至图4所示，显示基板可以包括以矩阵方式排布的多个像素单元P，多个像素单元P的至少一个包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3，第一子像素P1、第二子像素P2和第三子像素P3均包括像素驱动电路和发光器件。第一子像素P1、第二子像素P2和第三子像素P3中的像素驱动电路分别与扫描信号线、数据信号线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向发光器件输出相应的电流。第一子像素P1、第二子像素P2和第三子像素P3中的发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，第一子像素P1可以是出射红色光线的红色子像素(R)，第二子像素P2可以是出射蓝色光线的蓝色子像素(B)，第三子像素P3可以是出射绿色光线的绿色子像素(G)。在示例性实施方式中，子像素的形状可以是矩形状、菱形、五边形或六边形，三个子像素可以采用水平并列、竖直并列或品字方式排列，本公开在此不做限定。
在示例性实施方式中，像素单元可以包括三个子像素和四个子像素。图2和图3是以三个子像素为例进行说明的，图4是以四个子像素为例进行说明的。
在示例性实施方式中，三个子像素可以采用水平并列、竖直并列或品字方式等排列，本公开在此不做限定。图2是以三个子像素水平并列为例进行说明的，图3是以三个子像素为品字方式为例进行说明的。
在示例性实施方式中，四个子像素可以采用水平并列、竖直并列或正方形等方式排列，本公开在此不做限定。图4是以四个子像素采用正方形(Square)方式排列为例进行说明的。
在示例性实施方式中，发光器件可以是有机电致发光二极管(OLED)，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)。
在示例性实施方式中，有机发光层可以包括发光层(EML)以及如下任意一层或多层：空穴注入层HIL)、空穴传输层(HTL)、电子阻挡层(EBL)、空穴阻挡层(HBL)、电子传输层(ETL)和电子注入层(EIL)。在示例性实施方式中，所有子像素的空穴注入层、空穴传输层、电子阻挡层、空穴阻挡层、电子传输层和电子注入层中的一层或多层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是隔离的。
在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。
图5为一种像素驱动电路的等效电路示意图。图5是以像素驱动电路为8T1C结构为例进行说明的。如图5所示，像素驱动电路可以包括8个晶体管(第一晶体管T1到第八晶体管T8)、1个电容C，像素驱动电路可以与11个信号线(数据信号线Data、第一扫描信号线Gate1、第二扫描信号线Gate2、第一复位信号线Reset1、第二复位信号线Reset2、发光信号线EM、第一初始信号线INIT1、第二初始信号线INIT2、第三初始信号线INIT3、第一电源线VDD和第二电源线VSS)连接。
第一晶体管T1的控制极与第一复位信号线Reset1连接，第一晶体管T1的第一极与第一初始信号线INIT1连接，第一晶体管的第二极与第三节点N3连接。第一晶体管T1可以称为第一复位晶体管，当导通电平扫描信号施加到第一复位信号线Reset1时，第一晶体管T1将第一初始信号线INIT1的第一初始化电压传输到第一节点N1，以使第一节点N1的电荷量初始化。
第二晶体管T2的控制极与第二扫描信号线Gate2连接，第二晶体管T2的第一极与第一节点N1连接，第二晶体管T2的第二极与第三节点N3连接。第二晶体管T2可以称为补偿晶体管，当导通电平扫描信号施加到第二扫描信号线Gate2时，第二晶体管T2将第一节点N1和第三节点N3连通。
第三晶体管T3的控制极与第一节点N1连接，第三晶体管T3的第一极与第二节点N2连接，第三晶体管T3的第二极与第三节点N3连接。第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据其控制极与第一极之间的电位差来确定在第一电源线VDD与第二电源线VSS之间流动的驱动电流的大小。
第四晶体管T4的控制极与第一扫描信号线Gate1连接，第四晶体管T4的第一极与数据信号线Data连接，第四晶体管T4的第二极与第二节点N2连接。第四晶体管T4可以称为写入晶体管、扫描晶体管等，当导通电平扫描信号施加到第一扫描信号线Gate1时，第四晶体管T4使数据信号线Data的数据电压输入到像素驱动电路。
第五晶体管T5的控制极与发光信号线EM连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第二节点N2连接。第六晶体管T6的控制极与发光信号线EM连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与发光器件EL的第一极连接。第五晶体管T5和第六晶体管T6可以称为发光晶体管。当导通电平发光信号施加到发光信号线EM时，第五晶体管T5和第六晶体管T6通过在第一电源线VDD与第二电源线VSS之间形成驱动电流路径而使发光器件发光。
第七晶体管T7的控制极与第二复位信号线Reset2连接，第七晶体管T7的第一极与第二初始信号线INIT2连接，第七晶体管T7的第二极与发光器件EL的第一极连接。第七晶体管T7可以称为第二复位晶体管。当导通电平扫描信号施加到第二复位信号线Reset2时，第七晶体管T7将初始化电压传输到发光器件的第一极，以使发光器件的第一极中累积的电荷量初始化或释放发光器件的第一极中累积的电荷量。
第八晶体管T8的控制极与第二复位信号线Reset2连接，第八晶体管T8的第一极与第三初始信号线INIT3连接，第八晶体管T8的第二极与第二节点N2连接。第八晶体管T8可以称为第三复位晶体管。当导通电平扫描信号施加到第二复位信号线Reset2时，第八晶体管T8将初始化电压传输到第二节点N2，以使第二节点N2中累积的电荷量初始化。
电容C的第一端与第一电源线VDD连接，电容C的第二端与第一节点N1连接，
在示例性实施方式中，发光器件的第二极与第二电源线VSS连接，第二电源线VSS的信号为低电平信号，第一电源线VDD的信号为持续提供高电平信号。
按照晶体管的特性区分可以将晶体管分为N型晶体管和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其它合适的电压)，关闭电压为高电平电压(例如，5V、10V或其它合适的电压)。当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其它合适的电压)，关闭电压为低电平电压(例如，0V、-5V、-10V或其它合适的电压)。
在示例性实施方式中，第一晶体管T1到第八晶体管T8可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。
在示例性实施方式中，第一复位信号线Reset1和第二复位信号线Reset2可以为同一信号线。
在示例性实施方式中，第一初始信号线INIT1、第二初始信号线INIT2和第三初始信号线INIT3中的至少两条初始信号线为同一信号线。
在示例性实施方式中，第一晶体管T1到第八晶体管T8可以均为P型晶体管，或者第一晶体管T1到第八晶体管T8可以包括P型晶体管和N型晶体管。图5是以第二晶体管T2为N型晶体管，第一晶体管T1、第三晶体管T3至第八晶体管T8为P型晶体管为例进行说明的。
在示例性实施方式中，第一晶体管T1到第八晶体管T8可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
图6为图5提供的像素驱动电路的工作时序图。下面通过图5示例的像素驱动电路的工作过程说明本公开示例性实施例。
在示例性实施方式中，像素驱动电路的工作过程可以包括：
第一阶段A1，称为复位阶段，第一复位信号线Reset1和第二复位信号线Reset2的信号为低电平信号，第一扫描信号线Gate1、第二扫描信号线Gate2和发光信号线EM的信号为高电平信号。第一复位信号线Reset1的信号为低电平信号，使第一晶体管T1导通，第一初始信号线INIT1的信号提供至第三节点N3，对第三节点N3进行初始化(复位)，清除第三节点N3中原有电荷。第二扫描信号线Gate2的信号为高电平信号，第二晶体管T2打通，第三节点N3的信号写入第一节点N1，对第一节点N1进行初始化(复位)，清除第一节点N1中原有电荷。第二复位信号线Reset2的信号为低电平信号，第七晶体管T7导通，第二初始信号线INIT2的信号提供至发光器件EL的第一极，对发光器件EL的第一极进行初始化(复位)，清除发光器件EL的第一极中原有电荷，第八晶体管T8导通，第三初始信号线INIT3的信号提供至第二节点N2，对第二节点N2进行初始化(复位)，清除第二节点N2中原有电荷。第一扫描信号线Gate1和发光信号线EM的信号为高电平信号，使第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7断开，此阶段发光器件EL不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，第一扫描信号线Gate1的信号为低电平信号、第二扫描信号线Gate2、发光信号线EM、第一复位信号线Reset1和第二复位信号线Reset2的信号为高电平信号，数据信号线Data输出数据电压。此阶段由于电容C的第二端为低电平，因此第三晶体管T3导通。第一扫描信号线Gate1的信号为低电平信号，使第四晶体管T4导通，第二扫描信号线Gate2的信号为高电平信号，使第二晶体管T2导通，第二晶体管T2和第四晶体管T4导通使得数据信号线Data输出的数据电压经过第二节点N2、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第一节点N1，并将数据信号线Data输出的数据电压与第三晶体管T3的阈值电压之差充入电容C，电容C的第二端(第一节点N1)的电压为Vd-|Vth|，Vd为数据信号线Data输出的数据电压，Vth为第三晶体管T3的阈值电压。第一复位信号线Reset1和第二复位信号线Reset2的信号为高电平信号，使第一晶体管T1、第七晶体管T7和第八晶体管T8断开。发光信号线EM的信号为高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段A3、称为发光阶段，发光信号线EM和第二扫描信号线Gate2的信号为低电平信号，第一扫描信号线Gate1、第一复位信号线Reset1和第二复位信号线Reset2的信号为高电平信号。发光信号线EM的信号为低电平信号，使第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向发光器件EL的第一极提供驱动电压，驱动发光器件EL发光。
在像素驱动电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由其栅电极和第一极之间的电压差决定。由于第一节点N1的电压为Vdata-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth)2＝K*[(Vdd-Vd+|Vth|)-Vth]2＝K*(Vdd-Vd)2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动发光器件EL的驱动电流，K为常数，Vgs为第三晶体管T3的栅电极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vd为数据信号线Data输出的数据电压，Vdd为第一电源线VDD输出的电源电压。
由上述电流公式的推导结果可以看出，在发光阶段，第三晶体管T3的驱动电流已经不受第三晶体管T3的阈值电压的影响，从而消除了第三晶体管T3的阈值电压对驱动电流的影响，可以保证显示产品的显示亮度均匀，提升了整个显示产品的显示效果。
图7为本公开实施例提供的显示基板的结构示意图一，图8为本公开实施例提供的显示基板的结构示意图二。如图7和图8所示，本公开实施例提供的显示基板可以包括：基底以及设置在基底上的阵列排布的像素驱动电路P、多个初始信号线组INITC和多条初始连接线CL，初始信号线组INITC，与像素驱动电路P电连接，被配置为向像素驱动电路P提供初始信号，初始连接线CL与初始信号线组INITC电连接。
在示例性实施方式中，显示基板包括显示区和非显示区，像素驱动电路P、多个初始信号线组INITC和多条初始连接线CL设置在显示区。
如图7和图8所示，多个初始信号线组INITC沿第二方向D2排布，至少一个初始信号线组INITC包括至少一条初始信号线，至少一条初始信号线的至少部分沿第一方向D1延伸，多条初始连接线CL沿第一方向D1排布，至少一条初始连接线CL的至少部分沿第二方向D2延伸，第一方向D1和第二方向D2相交。图7是以至少一个初始信号线组INITC包括一条初始信号线为例进行说明的，图8是以至少一个初始信号线组INITC包括三条初始信号线分别为第一初始信号线INIT1至第三初始信号线INIT3为例进行说明的，本公开对此不做任何限定。
如图7和图8所示，相邻两条初始连接线CL沿第一方向D1之间的距离L大于或者等于驱动电路长度W的4倍，驱动电路长度W为像素驱动电路沿第一方向D1的长度。
在示例性实施方式中，初始连接线的数量可以等于像素驱动电路的总列数与K的比值，其中，K为3的整数倍，且大于3，示例性地，K可以为6、9或者12，本公开对此不做任何限定。
本公开通过设置相邻两条初始连接线CL沿第一方向D1之间的距离L大于或者等于驱动电路长度W的4倍减少了初始连接线的密度，减少了显示区的金属占比，可以提升显示基板的透光率。
在示例性实施方式中，位于同一行的相邻两个像素驱动电路的至少部分沿第二方向D2延伸的直线对称设置。
在示例性实施方式中，如图7和图8所示，至少一个初始信号线组INITC包括：M条初始信号线，初始连接线包括：第一初始连接线至第M初始连接线。第m初始连接线CL与初始连接组中的第m条初始信号线INIT电连接，多条第m初始连接线CL与多个初始连接组中的第m条初始信号线INIT形成网状结构。示例性地，M＝1时，至少一个初始信号线组INITC包括：一条初始信号线，初始连接线与初始信号线电连接，且多条初始连接线与多条初始信号线呈网状。当M＝3时，至少一个初始信号线组INITC包括：第一初始信号线INIT1至第三INIT3，初始连接线包括：第一初始连接线CL1至第三初始连接线CL3，第一初始连接线CL1与多个初始信号线组中的第一初始信号线INIT1电连接，且多条第一初始连接线CL1与多个初始连接组中的第一初始信号线INIT1形成网状结构，第二初始连接线CL2与多个初始信号线组中的第二初始信号线INIT2电连接，且多条第二初始连接线CL2与多个初始连接组中的第二初始信号线INIT2形成网状结构，第三初始连接线CL3与多个初始信号线组中的第三初始信号线INIT3电连接，且多条第三初始连接线CL3与多个初始连接组中的第三初始信号线INIT3形成网状结构。图7是以M＝1为例进行说明的，图8是以M＝3为例进行说明的。
在示例性实施方式中，像素驱动电路包括：M个复位晶体管，晶体管包括：第一极；第m个复位晶体管的第一极分别与初始信号线组INITC中的第m条初始信号线INIT和第m初始连接线CL电连接，1≤m≤M，M≥1。示例性地，以图5提供的像素驱动电路为例，结合图5和图8，像素驱动电路可以包括：第一复位晶体管(也就是第一晶体管T1)，第一复位晶体管的第一极与初始信号线组INITC中的第一条初始信号线INIT1和第一初始连接线CL1电连接，第二复位晶体管(也就是第七晶体管T7)，第二复位晶体管的第一极与初始信号线组INITC中的第二条初始信号线INIT2和第二初始连接线CL2电连接，第三复位晶体管(也就是第八晶体管T8)，第三复位晶体管的第一极与初始信号线组INITC中的第三条初始信号线INIT3和第三初始连接线CL3电连接，
在示例性实施方式中，如图7和图8所示，显示基板包括：多个像素驱动电路组PE，至少一个像素驱动电路组PE包括：第一像素驱动电路P1和第二像素驱动电路P2，第一像素驱动电路P1和第二像素驱动电路P2相对于沿第二方向D2延伸的直线至少部分对称设置，多个像素驱动电路组PE呈阵列排布。
图9为显示基板的结构示意图一，图10为显示基板的结构示意图二，图11为显示基板的结构示意图三，图12为显示基板的结构示意图四。图9至图12中仅示出了一条初始信号线INIT和与一条初始信号线连接的两条初始连接线CL。当初始信号线组包括：第一初始信号线至第三初始信号线时，图9至图12中的初始连接线为第一初始连接线时，初始信号线就是第一初始信号线，且像素驱动电路中与初始连接线连接的复位晶体管为第一晶体管，初始连接线为第二初始连接线时，初始信号线就是第二初始信号线，且像素驱动电路中与初始连接线连接的复位晶体管为第七晶体管，初始连接线为第三初始连接线时，初始信号线就是第三初始信号线，且像素驱动电路中与初始连接线连接的复位晶体管为第八晶体管。
在示例性实施方式中，如图9至图12所示，至少一条初始连接线CL的至少部分在基底上的正投影位于至少一个像素驱动电路组PE中的第一像素驱动电路P1在基底上的正投影和第二像素驱动电路P2在基底上的正投影之间。
在示例性实施方式中，如图9至图12所示，至少一条初始连接线CL沿第二方向D2延伸的中线O1与至少一个像素驱动电路组PE沿第二方向D2延伸的中线O2重合。
在示例性实施方式中，相邻两条初始连接线沿第一方向D1之间的距离等于第R列像素驱动电路组PE沿第二方向D2延伸的中线与第S列像素驱动电路组PE沿第二方向D2延伸的中线之间的距离，S-R≥2。图7至图12是以S-R＝2为例进行说明的。
在示例性实施方式中，晶体管包括：有源层、第一极和第二极。
在示例性实施方式中，显示基板还可以包括：设置在基底上的电路结构层，电路结构层设置有像素驱动电路、初始信号线组和初始连接线，像素驱动电路包括：至少一个晶体管，晶体管还包括：第一极和第二极；
电路结构层包括：依次叠设在基底上的半导体层、第一导电层和第二导电层；
半导体层包括：位于至少一个像素驱动电路中的至少一个晶体管的有源层；
第一导电层包括：初始信号线组中的至少一条初始信号线；
第二导电层包括：初始连接线以及位于至少一个像素驱动电路中的至少一个晶体管的第一极和第二极。
在示例性实施方式中，显示基板还可以包括：第一绝缘层组和第二绝缘层组，第一绝缘层组为位于初始连接线所在的膜层和初始信号线所在的膜层之间的绝缘层，第二绝缘层组为位于晶体管的有源层所在的膜层和初始连接线所在的膜层；
在示例性实施方式中，像素驱动电路中的至少一个晶体管均为P型晶体管时，第一复位信号线、第二复位信号线、发光信号线、第一扫描信号线和第二扫描信号线均为单层结构。
在示例性实施方式中，像素驱动电路中的至少一个晶体管均为P型晶体管时，电路结构层还可以包括：第三导电层，第四导电层、第五导电层、第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层。第三导电层位于半导体层和第一导电层之间，第四导电层位于第三导电层和第一导电层之间，第五导电层位于第二导电层远离基底的一侧，第一绝缘层为半导体层和第三导电层之间，第二绝缘层位于第三导电层和第四导电层之间，第三绝缘层位于第四导电层和第一导电层之间，第四绝缘层位于第一导电层和第二导电层之间，第五绝缘层位于第二导电层和第五导电层之间。其中，第一绝缘层组包括：第五绝缘层，第二绝缘层组包括：第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层；
第三导电层至少可以包括：至少一个晶体管的栅电极、第一复位信号线、第二复位信号线、第一扫描信号线、第二扫描信号线和至少一个电容的第一极板；
第四导电层至少可以包括：至少一个电容的第二极板；
第五导电层至少可以包括：第一电源线和数据信号线。
在示例性实施方式中，像素驱动电路中的至少一个晶体管包括P型晶体管和N型晶体管时，第一复位信号线、第二复位信号线、发光信号线、第一扫描信号线为单层结构，第二扫描信号线为双层结构，且包括第一子线和第二子线，其中，第一子线在基底上的正投影与第二子线在基底上的正投影至少部分交叠。
在示例性实施方式中，像素驱动电路中的至少一个晶体管包括P型晶体管和N型晶体管时，电路结构层还可以包括：第三导电层，第四导电层、第五导电层、金属氧化物层、第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层、第五绝缘层和第六绝缘层。第三导电层位于半导体层和第一导电层之间，第四导电层位于第三导电层和第一导电层之间，第五导电层位于第二导电层远离基底的一侧，第一绝缘层为半导体层和第三导电层之间，第二绝缘层位于第三导电层和第四导电层之间，第三绝缘层位于第四导电层和金属氧化物层之间，第四绝缘层位于金属氧化物层和第一导电层之间，第五绝缘层位于第一导电层和第二导电层之间，第六绝缘层位于第二导电层和第五导电层之间。其中，第一绝缘层组包括：第五绝缘层，第二绝缘层组包括：第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层；
半导体层包括：至少一个P型晶体管的有源层；
第三导电层至少可以包括：至少一个P型晶体管的栅电极、第一复位信号线、第二复位信号线、第一扫描信号线和至少一个电容的第一极板；
第四导电层至少可以包括：至少一个电容的第二极板以及第二扫描信号线的第一子线；
第一导电层还可以包括：第二扫描信号线的第二子线；
第五导电层至少可以包括：第一电源线和数据信号线。
在示例性实施方式中，第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层、第五绝缘层和第六绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。
在示例性实施方式中，第一导电层、第二导电层、第三导电层、第四导电层和第五导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Ti/Al/Ti等。
在示例性实施方式中，半导体层可以采用非晶硅(a-Si)、多晶硅(p-Si)、六噻吩、聚噻吩中的至少一种材料。
在示例性实施方式中，金属氧化物层可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)中的至少一种材料。
在示例性实施方式中，在垂直于显示基板的平面上，显示基板还可以包括设置在电路结构层远离基底一侧的发光结构层以及设置在发光结构层远离基底一侧的封装结构层。
在示例性实施方式中，显示基板可以包括其它膜层，如触控结构层等，本公开在此不做限定。
在示例性实施方式中，发光结构层可以包括阳极、像素定义层、有机发光层和阴极304，阳极通过过孔与像素驱动电路连接，有机发光层与阳极连接，阴极与有机发光层连接，有机发光层在阳极和阴极驱动下出射相应颜色的光线。
在示例性实施方式中，封装结构层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层。
在示例性实施方式中，触控结构层可以包括设置在封装结构层上的第一触控绝缘层、设置在第一触控绝缘层上的第一触控金属层、覆盖第一触控金属层的第二触控绝缘层、设置在第二触控绝缘层上的第二触控金属层和覆盖第二触控金属层的触控保护层，第一触控金属层可以包括多个桥接电极，第二触控金属层可以包括多个第一触控电极和第二触控电极，第一触控电极或第二触控电极可以通过过孔与桥接电极连接。
在示例性实施方式中，如图9至图12所示，像素驱动电路组PE包括：第一电路组PE1和第二电路组PE2，至少一条初始连接线CL在基底上的正投影与第一电路组PE1在基底上的正投影至少部分交叠，至少一条初始连接线CL在基底上的正投影与第二电路组PE2在基底上的正投影不存在交叠区域。
在示例性实施方式中，如图9和图10所示，初始连接线CL包括主体部CLA、多个第一连接部CLB和多个第二连接部CLC，多个第一连接部CLB和多个第二连接部CLC分别与主体部CLA电连接。
在示例性实施方式中，如图9和图10所示，主体部CLA沿第二方向D2延伸，且主体部CLA在基底上的正投影位于第一电路组PE1中的第一像素驱动电路P1在基底上的正投影和第二像素驱动电路P2在基底上的正投影之间。
在示例性实施方式中，如图9和图10所示，多个第一连接部CLB沿第二方向D2排布，至少一个第一连接部CLB沿第一方向D1延伸，且位于主体部CLA的一侧，多个第二连接部CLC沿第二方向D2排布，至少一个第二连接部CLC沿第一方向D1延伸，且位于主体部CLA的另一侧，多个第一连接部CLB和多个第二连接部CLC一一对应，第一连接部CLB与对应的第二连接部CLC沿第一方向D1延伸。
在示例性实施方式中，如图9和图10所示，第一连接部CLB和第二连接部CLC在基底上的正投影与初始连接线CL所连接的初始信号线INIT在基底上的正投影至少部分交叠。
在示例性实施方式中，如图9所示，对于至少一条初始连接线CL，位于第一电路组PE1的第一像素驱动电路P1中的与初始连接线CL连接的复位晶体管的有源层11-1与第二像素驱动电路P2中的与初始连接线CL连接的复位晶体管的有源层11-2间隔设置，且相对于沿第二方向D2延伸的直线O2对称设置；位于第二电路组PE2的第一像素驱动电路P1中的与初始连接线CL连接的复位晶体管的有源层11-1与第二像素驱动电路P2中的与初始连接线CL连接的复位晶体管的有源层11-2间隔设置，且相对于沿第二方向D2延伸的直线O对称设置。
在示例性实施方式中，如图9所示，对于至少一条初始连接线CL，位于第一电路组PE1的第一像素驱动电路P1中的与初始连接线CL连接的复位晶体管的第一极13-113-1位于主体部CLA的第一侧，且与第一连接部CLB电连接，位于第一电路组PE1的第二像素驱动电路P2中的与初始连接线CL连接的复位晶体管的第一极13-2位于主体部CLA的第二侧，且与第二连接部CLC电连接，位于第一电路组PE1的第一像素驱动电路P1中的与初始连接线CL连接的复位晶体管的第一极13-1和位于第一电路组PE1的第二像素驱动电路P2中的与初始连接线CL连接的复位晶体管的第一极13-2沿第一方向D1排布。
在示例性实施方式中，如图9所示，位于第二电路组PE2的第一像素驱动电路P1中的与初始连接线CL连接的复位晶体管的第一极13-1与第二像素驱动电路P2中的与初始连接线CL连接的复位晶体管的第一极13-2间隔设置。
在示例性实施方式中，如图9所示，位于至少一个像素驱动电路中的与初始连接线CL连接的复位晶体管的第一极在基底上的正投影与初始连接线CL连接的初始信号线INIT在基底上的正投影至少部分交叠。位于第一电路组PE1和第二电路组PE2中的至少一个电路组中的第一像素驱动电路P1中的初始连接线CL连接的复位晶体管的第一极13-1在基底上的正投影与初始连接线CL连接的初始信号线INIT在基底上的正投影至少部分交叠，位于第一电路组PE1和第二电路组PE2中的至少一个电路组中的第二像素驱动电路P2中的初始连接线CL连接的复位晶体管的第一极13-2在基底上的正投影与初始连接线CL连接的初始信号线INIT在基底上的正投影至少部分交叠。
在示例性实施方式中，如图9所示，位于第一电路组PE1的第一像素驱动电路P1中的与初始连接线CL连接的复位晶体管的第一极13-1与第一连接部CLB呈折线形。示例性地，位于第一电路组PE1的第一像素驱动电路P1中的与初始连接线CL连接的复位晶体管的第一极13-1与第一连接部CLB可以呈直角设置。
在示例性实施方式中，如图9所示，位于第一电路组PE1的第二像素驱动电路P2中的与初始连接线CL连接的复位晶体管的第一极13-2与第二连接部CLC呈折线形。示例性地，位于第一电路组PE1的第二像素驱动电路P2中的与初始连接线CL连接的复位晶体管的第一极13-2与第二连接部CLC可以呈直角设置。
在示例性实施方式中，如图9所示，第一绝缘层组可以包括：暴露出初始信号线INIT的第二过孔V2和第三过孔V3，位于第一电路组PE1和第二电路组PE2中的至少一个电路组的第一像素驱动电路P1中的与初始连接线CL连接的复位晶体管的第一极13-1通过第二过孔V2与初始信号线INIT电连接，位于第一电路组PE1和第二电路组PE2中的至少一个电路组的第二像素驱动电路P2中的与初始连接线CL连接的复位晶体管的第一极13-2通过第三过孔V3与初始信号线INIT电连接。
在示例性实施方式中，如图9所示，第二绝缘层组包括：暴露出像素驱动电路中的与初始连接线CL连接的复位晶体管的有源层的第一过孔。像素驱动电路中的与初始连接线CL连接的复位晶体管的第一极通过第一过孔与复位晶体管的有源层连接，
其中，暴露出位于第一电路组PE1的第一像素驱动电路P1中的与初始连接线CL连接的复位晶体管的有源层11-1的第一过孔V1-1与暴露出位于第一电路组PE1的第二像素驱动电路P2中的与初始连接线CL连接的复位晶体管的有源层的第一过孔V1-2为不同过孔，暴露出位于第二电路组PE2的第一像素驱动电路P1中的与初始连接线CL连接的复位晶体管的有源层的第一过孔V1-1与暴露出位于第二电路组PE2的第二像素驱动电路P2中的与初始连接线CL连接的复位晶体管的有源层的第一过孔V1-2为不同过孔。
在示例性实施方式中，如图10所示，对于至少一条初始连接线CL，位于第一电路组PE1的第一像素驱动电路P1中的与初始连接线CL连接的复位晶体管的有源层11-111-1与第二像素驱动电路P2中的与初始连接线CL连接的复位晶体管的有源层11-2为一体结构，且相对于沿第二方向D2延伸的直线O2对称设置。
在示例性实施方式中，如图10所示，位于第一电路组PE1的第一像素驱动电路P1中的与初始连接线CL连接的复位晶体管的有源层11-1与第二像素驱动电路P2中的与初始连接线CL连接的复位晶体管的有源层11-2的一体结构呈“几”字型。
在示例性实施方式中，如图10所示，位于第二电路组PE2的第一像素驱动电路P1中的与初始连接线CL连接的复位晶体管的有源层11-1与第二像素驱动电路P2中的与初始连接线CL连接的复位晶体管的有源层11-2间隔设置，且相对于沿第二方向D2延伸的直线O对称设置。
在示例性实施方式中，如图10所示，对于至少一条初始连接线CL，位于第一电路组PE1的第一像素驱动电路P1中的与初始连接线CL连接的复位晶体管的第一极13-1和第二像素驱动电路P2中的与初始连接线CL连接的复位晶体管的第一极13-2为同一电极，且作为初始连接线CL的主体部CLA的一部分。
在示例性实施方式中，如图10所示，位于第二电路组PE2的第一像素驱动电路P1中的与初始连接线CL连接的复位晶体管的第一极13-1与第二像素驱动电路P2中的与初始连接线CL连接的复位晶体管的第一极13-2间隔设置。
在示例性实施方式中，如图10所示，位于第一电路组PE1的至少一个像素驱动电路中的与初始连接线CL连接的复位晶体管的第一极在基底上的正投影与初始连接线CL连接的初始信号线INIT在基底上的正投影不交叠。示例性地，位于第一电路组PE1的第一像素驱动电路P1中的与初始连接线CL连接的复位晶体管的第一极13-1在基底上的正投影与初始连接线CL连接的初始信号线INIT在基底上的正投影不交叠，位于第一电路组PE1的第二像素驱动电路P2中的与初始连接线CL连接的复位晶体管的第一极13-2在基底上的正投影与初始连接线CL连接的初始信号线INIT在基底上的正投影不交叠。
在示例性实施方式中，如图10所示，位于第二电路组PE2的至少一个像素驱动电路中的与初始连接线CL连接的复位晶体管的第一极在基底上的正投影与初始连接线CL连接的初始信号线INIT在基底上的正投影至少部分交叠。示例性地，位于第二电路组PE2的第一像素驱动电路P1中的与初始连接线CL连接的复位晶体管的第一极13-1在基底上的正投影与初始连接线CL连接的初始信号线INIT在基底上的正投影至少部分交叠，位于第二电路组PE2的第二像素驱动电路P2中的与初始连接线CL连接的复位晶体管的第一极13-2在基底上的正投影与初始连接线CL连接的初始信号线INIT在基底上的正投影至少部分交叠。
在示例性实施方式中，如图10所示，第一绝缘层组包括：暴露出初始信号线INIT的第二过孔V2和第三过孔V3，第一连接部CLB通过第二过孔V2与初始信号线INIT电连接，第二连接部CLB通过第三过孔V3与初始信号线INIT电连接，位于第二电路组PE2中的第一像素驱动电路P1中的与初始连接线CL连接的复位晶体管的第一极13-1通过第二过孔V2与初始信号线INIT电连接，位于第二电路组PE2中的第二像素驱动电路P2中的与初始连接线CL连接的复位晶体管的第一极13-2通过第三过孔V3与初始信号线INIT电连接。
在示例性实施方式中，如图10所示，第二绝缘层组包括：暴露出像素驱动电路中的与初始连接线CL连接的复位晶体管的有源层的第一过孔，像素驱动电路中的与初始连接线CL连接的复位晶体管的第一极通过第一过孔与复位晶体管的有源层连接，其中，暴露出位于第一电路组PE1的第一像素驱动电路P1中的与初始连接线CL连接的复位晶体管的有源层的第一过孔V1-1与暴露出位于第一电路组PE1的第二像素驱动电路P2中的与初始连接线CL连接的复位晶体管的有源层的第一过孔V1-2为同一过孔，暴露出位于第二电路组PE2的第一像素驱动电路P1中的与初始连接线CL连接的复位晶体管的有源层的第一过孔V1-1与暴露出位于第二电路组PE2的第二像素驱动电路P2中的与初始连接线CL连接的复位晶体管的有源层的第一过孔V1-2为不同过孔。
在示例性实施方式中，如图11和图12所示，对于至少一条初始连接线CL，位于第一电路组PE1的第一像素驱动电路P1中的与初始连接线CL连接的复位晶体管的有源层11-1与第二像素驱动电路P2中的与初始连接线CL连接的复位晶体管的有源层11-2为一体结构，且相对于初沿第二方向D2延伸的直线对称设置。
在示例性实施方式中，如图11和图12所示，位于第一电路组PE1的第一像素驱动电路P1中的与初始连接线CL连接的复位晶体管的有源层11-1与第二像素驱动电路P2中的与初始连接线CL连接的复位晶体管的有源层11-2的一体结构呈“几”字型。
在示例性实施方式中，如图11和图12所示，位于第二电路组PE2的第一像素驱动电路P1中的与初始连接线CL连接的复位晶体管的有源层11-1与第二像素驱动电路P2中的与初始连接线CL连接的复位晶体管的有源层为一体结构，且相对于沿第二方向D2延伸的直线对称设置。
在示例性实施方式中，如图11和图12所示，位于第二电路组PE2的第一像素驱动电路P1中的与初始连接线CL连接的复位晶体管的有源层11-1与第二像素驱动电路P2中的与初始连接线CL连接的复位晶体管的有源层11-2的一体结构呈“几”字型。
在示例性实施方式中，如图11所示，初始连接线CL为沿第二方向D2延伸的线形状。
在示例性实施方式中，如图11所示，对于至少一条初始连接线CL，位于第一电路组PE1的第一像素驱动电路P1中的与初始连接线CL连接的复位晶体管的第一极13-1和第二像素驱动电路P2中的与初始连接线CL连接的复位晶体管的第一极13-2为同一电极，且作为初始连接线CL的一部分。
在示例性实施方式中，如图11所示，位于第二电路组PE2的第一像素驱动电路P1中的与初始连接线CL连接的复位晶体管的第一极13-1与第二像素驱动电路P2中的与初始连接线CL连接的复位晶体管的第一极13-2为一体结构，且沿第二方向D2延伸。
在示例性实施方式中，如图11所示，位于第一电路组PE1和第二电路组PE2中的至少一个电路组的至少一个像素驱动电路中的与初始连接线CL连接的复位晶体管的第一极在基底上的正投影与初始连接线CL连接的初始信号线INIT在基底上的正投影至少部分交叠。示例性地，位于第一电路组PE1和第二电路组PE2中的至少一个电路组的第一像素驱动电路P1中的与初始连接线CL连接的复位晶体管的第一极13-1在基底上的正投影与初始连接线CL连接的初始信号线INIT在基底上的正投影至少部分交叠，示例性地，位于第一电路组PE1和第二电路组PE2中的至少一个电路组的第二像素驱动电路P2中的与初始连接线CL连接的复位晶体管的第一极13-2在基底上的正投影与初始连接线CL连接的初始信号线INIT在基底上的正投影至少部分交叠。
在示例性实施方式中，如图11所示，第一绝缘层组包括：暴露出初始信号线INIT的第二过孔V2，位于第一电路组PE1和第二电路组PE2中的至少一个电路组中的至少一个像素驱动电路中的与初始连接线CL连接的复位晶体管的第一极通过第二过孔V2与初始信号线INIT电连接。示例性地，位于第一电路组PE1和第二电路组PE2中的至少一个电路组中的第一像素驱动电路P1中的与初始连接线CL连接的复位晶体管的第一极13-1(也是第二像素驱动电路P2中的与初始连接线CL连接的复位晶体管的第一极13-2)通过第二过孔V2与初始信号线INIT电连接。
在示例性实施方式中，如图11所示，第二绝缘层组包括：暴露出像素驱动电路中的与初始连接线CL连接的复位晶体管的有源层的第一过孔，像素驱动电路中的与初始连接线CL连接的复位晶体管的第一极通过第一过孔与复位晶体管的有源层连接，其中，暴露出位于第一电路组PE1的第一像素驱动电路P1中的与初始连接线CL连接的复位晶体管的有源层的第一过孔V1-1与暴露出位于第一电路组PE1的第二像素驱动电路P2中的与初始连接线CL连接的复位晶体管的有源层的第一过孔V1-2为同一过孔，暴露出位于第二电路组PE2的第一像素驱动电路P1中的与初始连接线CL连接的复位晶体管的有源层的第一过孔V1-1与暴露出位于第二电路组PE2的第二像素驱动电路P2中的与初始连接线CL连接的复位晶体管的有源层的第一过孔V1-2为同一过孔，且暴露出位于第一电路组PE1和第二电路组PE2中的至少一个电路组的像素驱动电路中的与初始连接线CL连接的复位晶体管的有源层的第一过孔与第二过孔V2沿第二方向D2排布。
在示例性实施方式中，如图12所示，初始连接线CL包括：相互电连接的第一主体部CLE和第一凸起部CLF，初始信号线INIT包括：相互电连接的第二主体部NT1和第二凸起部NT2。第一主体部CLE沿第二方向D2延伸，且第一主体部CLE在基底上的正投影位于第一电路组PE1中的第一像素驱动电路P1在基底上的正投影和第二像素驱动电路P2在基底上的正投影之间，第一凸起部CLF沿第一方向D1延伸，且位于第一主体部CLE的一侧；第二主体部NT1沿第一方向D1延伸，第二凸起部NT2沿第二方向D2延伸，且位于第二主体部NT1的一侧。
在示例性实施方式中，如图12所示，第一凸起部CLF在基底上的正投影与第二凸起部NT2在基底上的正投影至少部分交叠，且与第二凸起部NT2电连接。
在示例性实施方式中，如图12所示，对于至少一条初始连接线CL，位于第一电路组PE1的第一像素驱动电路P1中的与初始连接线CL连接的复位晶体管的第一极13-1和第二像素驱动电路P2中的与初始连接线CL连接的复位晶体管的第一极13-2为同一电极，且作为初始连接线CL的第一主体部CLE的一部分；
在示例性实施方式中，如图12所示，位于第二电路组的第一像素驱动电路P1中的与初始连接线CL连接的复位晶体管的第一极13-1与第二像素驱动电路P2中的与初始连接线CL连接的复位晶体管的第一极13-2为一体结构，且沿第二方向D2延伸。
在示例性实施方式中，如图12所示，第一绝缘层组包括：暴露出初始信号线INIT的第二凸起部NT2的第二过孔和暴露出初始信号线INIT的第二主体部NT1的第三过孔，第一凸起部CLF通过第二过孔V2与第二凸起部NT2电连接，位于第二电路组中的至少一个像素驱动电路中的与初始连接线CL连接的复位晶体管的第一极通过第三过孔V3与初始信号线INIT的第二主体部NT1电连接。
在示例性实施方式中，如图12所示，第二绝缘层组包括：暴露出像素驱动电路中的与初始连接线CL连接的复位晶体管的有源层的第一过孔，像素驱动电路中的与初始连接线连接的复位晶体管的第一极通过第一过孔与复位晶体管的有源层连接，其中，暴露出位于第一电路组的第一像素驱动电路P1中的与初始连接线CL连接的复位晶体管的有源层的第一过孔V1-1与暴露出位于第一电路组的第二像素驱动电路P2中的与初始连接线CL连接的复位晶体管的有源层的第一过孔V1-2为同一过孔，暴露出位于第二电路组的第一像素驱动电路P1中的与初始连接线CL连接的复位晶体管的有源层的第一过孔V1-1与暴露出位于第二电路组的第二像素驱动电路P2中的与初始连接线CL连接的复位晶体管的有源层的第一过孔V1-2为同一过孔；暴露出位于第一电路组PE1的至少一个像素驱动电路中的与初始连接线CL连接的复位晶体管的有源层的第一过孔V1-1(V1-2)与第二过孔V2沿第一方向D1排布，暴露出位于第二电路组PE2的至少一个像素驱动电路中的与初始连接线CL连接的复位晶体管的有源层的第一过孔V1-1(V1-2)与第三过孔V3沿第二方向D2排布。
在示例性实施方式中，如图9至图12所示，位于第一电路组PE1和第二电路组PE中的至少一个电路组中的第一像素驱动电路P1中的与初始连接线连接的复位晶体管的第二极14-1与第二像素驱动电路中的与初始连接线连接的复位晶体管的第二极14-2为不同电极，且相对于沿第二方向D2延伸的直线O2对称设置。
图10至图12提供的显示基板与图9提供的显示基板相比，在保证了相邻两个子像素的对称结构的基础上，减少了显示基板中的过孔的数量并简化了初始信号线的结构，进一步简化了显示基板的工艺，并可以节约显示基板的制作成本。
在示例性实施方式中，图13为显示基板的俯视图，图14为图13中部分膜层示意图一，图15为图13中部分膜层示意图二。图13中包括两个如图5所示的像素驱动电路，且像素驱动电路包括P型晶体管和N型晶体管为例进行说明的。如图13至图15所示，像素驱动电路还包括：电容；电容包括：第一极板和第二极板。对于至少一个像素驱动电路，像素驱动电路所连接的初始信号线组中的至少一条初始信号线在基底上的正投影与电容的第一极板C1和第二极板C2中的至少一个极板在基底上的正投影至少部分交叠。图13至图15是以M＝3，且第三初始信号线INIT3在基底上的正投影与电容的第一极板C1和第二极板C2中的至少一个极板在基底上的正投影至少部分交叠。图13至图15是以第三初始信号线INIT3在基底上的正投影与电容的第一极板C1和第二极板C2在基底上的正投影均至少部分交叠为例进行说明的。
如图13所示，第一电源线VDD在基底上的正投影与初始信号线组中的至少一条初始信号线在基底上的正投影至少部分交叠。
本公开中对于至少一个像素驱动电路，像素驱动电路所连接的初始信号线组中的至少一条初始信号线在基底上的正投影与电容的第一极板C1和第二极板C2中的至少一个极板在基底上的正投影至少部分交叠可以减少像素驱动电路中的金属所占用的空间，可以进一步提升显示基板的透光率。
在示例性实施例方式中，第一电源线VDD可以对像素驱动电路所连接的初始信号线组中的至少一条初始信号线的信号进行屏蔽，避免像素驱动电路所连接的初始信号线组中的至少一条初始信号线的信号被其他交流信号干扰，进而提升显示基板的显示效果。
经实验，本公开实施例提供的显示基板与对照显示基板相比，显示基板的透光率可以提升30％。其中，对照显示基板指的是相邻初始连接线沿第一方向之间的距离等于驱动电路长度的两倍的显示基板。
本公开实施例还提供了一种显示装置，包括：显示基板。显示基板为前述任一个实施例提供的显示基板，实现原理和实现效果类似，在此不再赘述。
在示例性实施方式中，显示装置可以为：电子纸、OLED面板、有源矩阵有机发光二极管(active-matrix organic light emitting diode，简称AMOLED)面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开中的附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
为了清晰起见，在用于描述本公开的实施例的附图中，层或微结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (24)

  1. 一种显示基板，包括：基底以及设置在所述基底上的阵列排布的像素驱动电路、多个初始信号线组和多条初始连接线，所述初始信号线组，与所述像素驱动电路电连接，被配置为向所述像素驱动电路提供初始信号，所述初始连接线与所述初始信号线组电连接；
    所述多个初始信号线组沿第二方向排布，至少一个初始信号线组包括至少一条初始信号线，至少一条初始信号线的至少部分沿第一方向延伸，所述多条初始连接线沿第一方向排布，至少一条初始连接线的至少部分沿第二方向延伸，所述第一方向和所述第二方向相交；
    相邻两条初始连接线沿所述第一方向之间的距离大于或者等于驱动电路长度的4倍，所述驱动电路长度为像素驱动电路沿第一方向的长度。
  2. 根据权利要求1所述的显示基板，其中，至少一个初始信号线组包括：M条初始信号线，所述初始连接线包括：第一初始连接线至第M初始连接线；
    第m初始连接线与所述初始连接组中的第m条初始信号线电连接，多条第m初始连接线与所述多个初始连接组中的第m条初始信号线形成网状结构；
    所述像素驱动电路包括：M个复位晶体管，晶体管包括：第一极；第m个复位晶体管的第一极分别与初始信号线组中的第m条初始信号线和第m初始连接线电连接，1≤m≤M，M≥1。
  3. 根据权利要求2所述的显示基板，其中，所述显示基板包括：多个像素驱动电路组，至少一个像素驱动电路组包括：第一像素驱动电路和第二像素驱动电路，所述第一像素驱动电路和所述第二像素驱动电路相对于沿所述第二方向延伸的直线至少部分对称设置，多个像素驱动电路组呈阵列排布；
    至少一条初始连接线的至少部分在基底上的正投影位于至少一个像素驱动电路组中的所述第一像素驱动电路在基底上的正投影和所述第二像素驱动电路在基底上的正投影之间。
  4. 根据权利要求3所述的显示基板，其中，至少一条初始连接线沿所述第二方向延伸的中线与至少一个像素驱动电路组沿第二方向延伸的中线重合。
  5. 根据权利要求4所述的显示基板，其特征在于，相邻两条初始连接线沿所述第一方向之间的距离等于第R列像素驱动电路组沿第二方向延伸的中线与第S列像素驱动电路组沿第二方向延伸的中线之间的距离，S-R≥2。
  6. 根据权利要求3至5任一项所述的显示基板，其中，所述像素驱动电路组包括：第一电路组和第二电路组，至少一条初始连接线在基底上的正投影与所述第一电路组在基底上的正投影至少部分交叠，至少一条初始连接线在基底上的正投影与所述第二电路组在基底上的正投影不存在交叠区域。
  7. 根据权利要求6所述的显示基板，其中，所述初始连接线包括主体部、多个第一连接部和多个第二连接部，所述多个第一连接部和所述多个第二连接部分别与主体部电连接；
    所述主体部沿第二方向延伸，且所述主体部在基底上的正投影位于所述第一电路组中的第一像素驱动电路在基底上的正投影和所述第二像素驱动电路在基底上的正投影之间，多个第一连接部沿第二方向排布，至少一个第一连接部沿第一方向延伸，且位于所述主体部的一侧，所述多个第二连接部沿第二方向排布，至少一个第二连接部沿第一方向延伸，且位于所述主体部的另一侧，多个第一连接部和多个第二连接部一一对应，第一连接部与对应的第二连接部沿第一方向延伸；
    所述第一连接部和所述第二连接部在基底上的正投影与所述初始连接线所连接的初始信号线在基底上的正投影至少部分交叠。
  8. 根据权利要求7所述的显示基板，其中，所述晶体管还包括：有源层；
    对于至少一条初始连接线，位于所述第一电路组的第一像素驱动电路中的与所述初始连接线连接的复位晶体管的有源层与所述第二像素驱动电路中的与初始连接线连接的复位晶体管的有源层间隔设置，且相对于沿第二方向延伸的直线对称设置；
    位于所述第二电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的有源层与所述第二像素驱动电路中的与初始连接线连接的复位晶体管的有源层间隔设置，且相对于沿第二方向延伸的直线对称设置。
  9. 根据权利要求8所述的显示基板，其中，对于至少一条初始连接线，位于第一电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的第一极位于所述主体部的第一侧，且与第一连接部电连接，位于第一电路组的第二像素驱动电路中的与初始连接线连接的复位晶体管的第一极位于所述主体部的第二侧，且与第二连接部电连接，位于第一电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的第一极和位于第一电路组的第二像素驱动电路中的与初始连接线连接的复位晶体管的第一极沿第一方向排布；
    位于第二电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的第一极与第二像素驱动电路中的与初始连接线连接的复位晶体管的第一极间隔设置；
    位于至少一个像素驱动电路中的与初始连接线连接的复位晶体管的第一极在基底上的正投影与初始连接线连接的初始信号线在基底上的正投影至少部分交叠；
    位于第一电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的第一极与第一连接部呈折线形，位于第一电路组的第二像素驱动电路中的与初始连接线连接的复位晶体管的第一极与第二连接部呈折线形。
  10. 根据权利要求9所述的显示基板，其中，所述显示基板包括：第一绝缘层组和第二绝缘层组，所述第一绝缘层组为位于初始连接线所在的膜层和初始信号线所在的膜层之间的绝缘层，所述第二绝缘层组为位于晶体管的有源层所在的膜层和初始连接线所在的膜层；
    所述第一绝缘层组包括：暴露出初始信号线的第二过孔和第三过孔，位于第一电路组和第二电路组中的至少一个电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的第一极通过第二过孔与初始信号线电连接，位于第一电路组和第二电路组中的至少一个电路组的第二像素驱动电路中的与初始连接线连接的复位晶体管的第一极通过第三过孔与初始信号线电连接；
    所述第二绝缘层组包括：暴露出像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔，像素驱动电路中的与初始连接线连接的复位晶体管的第一极通过第一过孔与复位晶体管的有源层连接，其中，暴露出位于第一电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔与暴露出位于第一电路组的第二像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔为不同过孔，暴露出位于第二电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔与暴露出位于第二电路组的第二像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔为不同过孔。
  11. 根据权利要求7所述的显示基板，其中，所述晶体管还包括：有源层；
    对于至少一条初始连接线，位于所述第一电路组的第一像素驱动电路中的与所述初始连接线连接的复位晶体管的有源层与所述第二像素驱动电路中的与初始连接线连接的复位晶体管的有源层为一体结构，且相对于沿第二方向延伸的直线对称设置；
    位于所述第二电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的有源层与所述第二像素驱动电路中的与初始连接线连接的复位晶体管的有源层间隔设置，且相对于沿第二方向延伸的直线对称设置。
  12. 根据权利要求11所述的显示基板，其中，对于至少一条初始连接线，位于第一电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的第一极和第二像素驱动电路中的与初始连接线连接的复位晶体管的第一极为同一电极，且作为所述初始连接线的主体部的一部分；
    位于第二电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的第一极与第二像素驱动电路中的与初始连接线连接的复位晶体管的第一极间隔设置；
    位于第一电路组的至少一个像素驱动电路中的与初始连接线连接的复位晶体管的第一极在基底上的正投影与初始连接线连接的初始信号线在基底上的正投影不交叠，位于第二电路组的至少一个像素驱动电路中的与初始连接线连接的复位晶体管的第一极在基底上的正投影与初始连接线连接的初始信号线在基底上的正投影至少部分交叠。
  13. 根据权利要求12所述的显示基板，其中，包括：第一绝缘层组和第二绝缘层组，所述第一绝缘层组为位于初始连接线所在的膜层和初始信号线所在的膜层之间的绝缘层，第二绝缘层组为位于晶体管的有源层所在的膜层和初始连接线所在的膜层；
    所述第一绝缘层组包括：暴露出初始信号线的第二过孔和第三过孔，第一连接部通过第二过孔与初始信号线电连接，第二连接部通过第三过孔与初始信号线电连接，位于第二电路组中的第一像素驱动电路中的与初始连接线连接的复位晶体管的第一极通过第二过孔与初始信号线电连接，位于第二电路组中的第二像素驱动电路中的与初始连接线连接的复位晶体管的第一极通过第三过孔与初始信号线电连接；
    所述第二绝缘层组包括：暴露出像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔，像素驱动电路中的与初始连接线连接的复位晶体管的第一极通过第一过孔与复位晶体管的有源层连接，其中，暴露出位于第一电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔与暴露出位于第一电路组的第二像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔为同一过孔，暴露出位于第二电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔与暴露出位于第二电路组的第二像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔为不同过孔。
  14. 根据权利要求6所述的显示基板，其中，所述晶体管还包括：有源层；
    对于至少一条初始连接线，位于第一电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的有源层与第二像素驱动电路中的与初始连接线连接的复位晶体管的有源层为一体结构，且相对于初沿第二方向延伸的直线对称设置；
    位于第二电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的有源层与第二像素驱动电路中的与初始连接线连接的复位晶体管的有源层为一体结构，且相对于沿第二方向延伸的直线对称设置。
  15. 根据权利要求14所述的显示基板，其中，所述初始连接线为沿第二方向延伸的线形状。
  16. 根据权利要求15所述的显示基板，其中，对于至少一条初始连接线，位于第一电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的第一极和第二像素驱动电路中的与初始连接线连接的复位晶体管的第一极为同一电极，且作为初始连接线的一部分；
    位于第二电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的第一极与第二像素驱动电路中的与初始连接线连接的复位晶体管的第一极为一体结构，且沿第二方向延伸；
    位于第一电路组和第二电路组中的至少一个电路组的至少一个像素驱动电路中的与初始连接线连接的复位晶体管的第一极在基底上的正投影与初始连接线连接的初始信号线在基底上的正投影至少部分交叠。
  17. 根据权利要求16所述的显示基板，其中，包括：第一绝缘层组和第二绝缘层组，所述第一绝缘层组为位于初始连接线所在的膜层和初始信号线所在的膜层之间的绝缘层，第二绝缘层组为位于晶体管的有源层所在的膜层和初始连接线所在的膜层；
    所述第一绝缘层组包括：暴露出初始信号线的第二过孔，位于第一电路组和第二电路组中的至少一个电路组中的至少一个像素驱动电路中的与初始连接线连接的复位晶体管的第一极通过第二过孔与初始信号线电连接；
    所述第二绝缘层组包括：暴露出像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔，像素驱动电路中的与初始连接线连接的复位晶体管的第一极通过第一过孔与复位晶体管的有源层连接，其中，暴露出位于第一电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔与暴露出位于第一电路组的第二像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔为同一过孔，暴露出位于第二电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔与暴露出位于第二电路组的第二像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔为同一过孔；
    暴露出位于第一电路组和第二电路组中的至少一个电路组的像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔与第二过孔沿第二方向排布。
  18. 根据权利要求14所述的显示基板，其中，所述初始连接线包括：相互电连接的第一主体部和第一凸起部，所述初始信号线包括：相互电连接的第二主体部和第二凸起部；
    所述第一主体部沿第二方向延伸，且所述第一主体部在基底上的正投影位于所述第一电路组中的第一像素驱动电路在基底上的正投影和第二像素驱动电路在基底上的正投影之间，所述第一凸起部沿第一方向延伸，且位于第一主体部的一侧；
    所述第二主体部沿第一方向延伸，所述第二凸起部沿第二方向延伸，且位于第二主体部的一侧；
    所述第一凸起部在基底上的正投影与所述第二凸起部在基底上的正投影至少部分交叠，且与所述第二凸起部电连接。
  19. 根据权利要求18所述的显示基板，其中，对于至少一条初始连接线，位于第一电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的第一极和第二像素驱动电路中的与初始连接线连接的复位晶体管的第一极为同一电极，且作为初始连接线的第一主体部的一部分；
    位于第二电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的第一极与第二像素驱动电路中的与初始连接线连接的复位晶体管的第一极为一体结构，且沿第二方向延伸。
  20. 根据权利要求19所述的显示基板，其中，包括：第一绝缘层组和第二绝缘层组，所述第一绝缘层组为位于初始连接线所在的膜层和初始信号线所在的膜层之间的绝缘层，第二绝缘层组为位于晶体管的有源层所在的膜层和初始连接线所在的膜层；
    所述第一绝缘层组包括：暴露出初始信号线的第二凸起部的第二过孔和暴露出初始信号线的第二主体部的第三过孔，第一凸起部通过第二过孔与第二凸起部电连接，位于第二电路组中的至少一个像素驱动电路中的与初始连接线连接的复位晶体管的第一极通过第三过孔与初始信号线的第二主体部电连接；
    所述第二绝缘层组包括：暴露出像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔，像素驱动电路中的与初始连接线连接的复位晶体管的第一极通过第一过孔与复位晶体管的有源层连接，其中，暴露出位于第一电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔与暴露出位于第一电路组的第二像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔为同一过孔，暴露出位于第二电路组的第一像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔与暴露出位于第二电路组的第二像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔为同一过孔；
    暴露出位于第一电路组的至少一个像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔与所述第二过孔沿第一方向排布，暴露出位于第二电路组的至少一个像素驱动电路中的与初始连接线连接的复位晶体管的有源层的第一过孔与所述第三过孔沿第二方向排布。
  21. 根据权利要求2所述的显示基板，其中，所述像素驱动电路还包括：电容；电容包括：第一极板和第二极板；
    对于至少一个像素驱动电路，像素驱动电路所连接的初始信号线组中的至少一条初始信号线在基底上的正投影与电容的第一极板和第二极板中的至少一个极板在基底上的正投影至少部分交叠。
  22. 根据权利要求2所述的显示基板，还包括：设置在基底上的电路结构层，所述电路结构层设置有像素驱动电路、初始信号线组和初始连接线，所述像素驱动电路包括：至少一个晶体管，晶体管还包括：第一极和第二极；
    所述电路结构层包括：依次叠设在基底上的半导体层、第一导电层和第二导电层；
    半导体层包括：位于至少一个像素驱动电路中的至少一个晶体管的有源层；
    第一导电层包括：初始信号线组中的至少一条初始信号线；
    第二导电层包括：初始连接线以及位于至少一个像素驱动电路中的至少一个晶体管的第一极和第二极。
  23. 根据权利要求22所述的显示基板，还包括：第一电源线，所述第一电源线与像素驱动电路电连接；
    所述第一电源线在基底上的正投影与初始信号线组中的至少一条初始信号线在基底上的正投影至少部分交叠。
  24. 一种显示装置，包括：如权利要求1至23任一项所述的显示基板。
PCT/CN2025/090472 2024-05-15 2025-04-22 显示基板和显示装置 Pending WO2025237013A1 (zh)

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