WO2025232008A1 - 显示面板 - Google Patents

显示面板

Info

Publication number
WO2025232008A1
WO2025232008A1 PCT/CN2024/109564 CN2024109564W WO2025232008A1 WO 2025232008 A1 WO2025232008 A1 WO 2025232008A1 CN 2024109564 W CN2024109564 W CN 2024109564W WO 2025232008 A1 WO2025232008 A1 WO 2025232008A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
signal line
gate
electrode
control transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2024/109564
Other languages
English (en)
French (fr)
Inventor
张欢喜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to DE112024002845.4T priority Critical patent/DE112024002845T5/de
Publication of WO2025232008A1 publication Critical patent/WO2025232008A1/zh
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/30—Active-matrix LED displays
    • H10H29/32—Active-matrix LED displays characterised by the geometry or arrangement of elements within a subpixel, e.g. arrangement of the transistor within its RGB subpixel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/30—Active-matrix LED displays
    • H10H29/49—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/80—Constructional details
    • H10H29/85—Packages
    • H10H29/855—Optical field-shaping means, e.g. lenses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits

Definitions

  • This application relates to the field of display technology, and in particular to a display panel.
  • LTPO Low Temperature Polysilicon Oxide
  • GOA Gate On Array
  • CMOS Complementary Metal Oxide Semiconductor
  • CMOS GOA circuits contain oxide semiconductor transistors. To improve the stability of the metal oxide, the oxide semiconductor transistors are shielded from light. Furthermore, to reduce processing complexity, ink is used to shield the oxide semiconductor transistors. However, due to issues with ink coating precision, the ink may not achieve the desired shielding effect. To address this problem, existing display devices use an anode layer to shield the oxide semiconductor transistors in the CMOS GOA circuit. However, because the anode layer has grooves, it cannot shield all oxide semiconductor transistors, leading to degraded performance and ultimately, CMOS GOA circuit failure.
  • This application provides a display panel to solve the technical problem that existing display devices have light leakage from the anode layer to the oxide semiconductor transistor, which leads to a deterioration in the performance of the oxide semiconductor transistor.
  • This application provides a display panel, which includes a display section and a gate driving circuit located on at least one side of the display section.
  • the gate driving circuit includes a plurality of cascaded gate driving units, each gate driving unit including a plurality of oxide semiconductor transistors.
  • the display panel includes:
  • An oxide semiconductor layer is disposed on one side of the substrate, and the oxide semiconductor layer includes the active pattern of the oxide semiconductor transistor;
  • a source-drain layer is disposed on the side of the oxide semiconductor layer away from the substrate, and the source-drain layer includes a metal pattern for forming a source-drain electrode and a light-shielding pattern formed in the non-display area;
  • a pixel electrode layer is disposed on the side of the source/drain layer away from the oxide semiconductor layer.
  • the pixel electrode layer includes a conductive pattern for forming a pixel electrode and a connection trace formed in the non-display area.
  • the connection trace is provided with a via.
  • the active pattern of the oxide semiconductor transistor in at least one of the connection traces and the light-shielding pattern is completely covered.
  • Figure 1 is a schematic diagram of the first type of existing display device.
  • Figure 2 is a second schematic diagram of an existing display device.
  • Figure 3 shows a third type of schematic diagram of existing display devices.
  • Figure 4 is a first schematic diagram of a display panel provided in an embodiment of this application.
  • Figure 5 is a second schematic diagram of the display panel provided in an embodiment of this application.
  • FIG. 6 is a circuit diagram of the gate driving unit provided in an embodiment of this application.
  • Figure 7 is a third schematic diagram of the display panel provided in the embodiments of this application.
  • Figure 8 is a fourth schematic diagram of the display panel provided in the embodiments of this application.
  • Figure 9 is a stack-up diagram of the various film layers of the gate drive circuit provided in the embodiments of this application.
  • Figure 10 is an exploded view of the silicon semiconductor layer and the first metal layer in the gate drive circuit of Figure 9.
  • Figure 11 is an exploded view of the second metal layer and oxide semiconductor layer in the gate drive circuit of Figure 9.
  • Figure 12 is an exploded view of the third metal layer and the first source/drain layer in the gate drive circuit of Figure 9.
  • Figure 13 is an exploded view of the second and third source-drain layers in the gate drive circuit of Figure 9.
  • Figure 14 is an exploded view of the anode layer in the gate drive circuit of Figure 9.
  • Figure 15 is a stack-up diagram of the oxide semiconductor layer and anode layer of the gate drive circuit in Figure 9.
  • Figure 16 is an exploded view of the first and second vias in the gate drive circuit of Figure 9.
  • Figure 17 is an exploded view of the third and fourth vias in the gate drive circuit of Figure 9.
  • first and second are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with “first” and “second” may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of” means two or more, unless otherwise explicitly specified.
  • connection refers to a direct connection between two things
  • electrical connection refers to a connection that can be direct or indirect through an intermediate medium
  • the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, “above,” “over,” and “on top” of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. “Below,” “below,” and “under” the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.
  • existing display devices include a bezel area 11, within which a CMOS GOA area 121 is located.
  • existing display devices use ink to shield the oxide semiconductor transistors in the CMOS GOA area.
  • the width of the bezel area 11 is A1
  • the width of the CMOS GOA area is A2
  • the distance between the boundary of the CMOS GOA area and the display area is A3
  • the distance between the target boundary of the ink coating and the boundary of the display area is A5.
  • the ink cannot shield the oxide semiconductor transistors in the CMOS GOA area, leading to changes in the performance of the oxide semiconductor transistors in the CMOS GOA area.
  • existing display devices utilize the anode metal 122 of the anode layer to shield the oxide semiconductor transistors (OSTs) in the CMOS GOA region.
  • the distance A6 between the anode metal 122 and the boundary of the display area is greater than the distance A3 between the CMOS GOA region and the boundary of the display area.
  • This application provides a display panel to solve the above-mentioned technical problems.
  • Figure 4 is a first schematic diagram of a display panel provided in an embodiment of this application.
  • Figure 5 is a second schematic diagram of a display panel provided in an embodiment of this application.
  • Figure 6 is a circuit diagram of a gate driving unit provided in an embodiment of this application.
  • Figure 7 is a third schematic diagram of a display panel provided in an embodiment of this application.
  • Figure 8 is a fourth schematic diagram of a display panel provided in an embodiment of this application.
  • Figure 9 is a stack-up diagram of the various film layers of the gate driving circuit provided in an embodiment of this application.
  • Figure 10 is an exploded view of the silicon semiconductor layer and the first metal layer in the gate driving circuit of Figure 9; wherein, (a) in Figure 10 is an exploded view of the silicon semiconductor layer in the gate driving circuit of Figure 9, and (b) in Figure 10 is an exploded view of the first metal layer in the gate driving circuit of Figure 9.
  • Figure 11 is an exploded view of the second metal layer and the oxide semiconductor layer in the gate driving circuit of Figure 9; wherein, (a) in Figure 11 is an exploded view of the second metal layer in the gate driving circuit of Figure 9, and (b) in Figure 11 is an exploded view of the oxide semiconductor layer in the gate driving circuit of Figure 9.
  • Figure 12 is an exploded view of the third metal layer and the first source/drain layer in the gate driving circuit of Figure 9; wherein, Figure 12(a) is an exploded view of the third metal layer in the gate driving circuit of Figure 9, and Figure 12(b) is an exploded view of the first source/drain layer in the gate driving circuit of Figure 9.
  • Figure 13 is an exploded view of the second source/drain layer and the third source/drain layer in the gate driving circuit of Figure 9; wherein, Figure 13(a) is an exploded view of the second source/drain layer in the gate driving circuit of Figure 9, and Figure 13(b) is an exploded view of the third source/drain layer in the gate driving circuit of Figure 9.
  • Figure 14 is an exploded view of the anode layer in the gate driving circuit of Figure 9.
  • Figure 15 is a stack-up diagram of the oxide semiconductor layer and the anode layer in the gate driving circuit of Figure 9.
  • Figure 16 is an exploded view of the first via and the second via in the gate driving circuit of Figure 9; wherein, Figure 16(a) is an exploded view of the first via in the gate driving circuit of Figure 9, and Figure 16(b) is an exploded view of the second via in the gate driving circuit of Figure 9.
  • Figure 17 is an exploded view of the third and fourth vias in the gate drive circuit of Figure 9; Figure 17(a) is an exploded view of the third via in the gate drive circuit of Figure 9, and Figure 17(b) is an exploded view of the fourth via in the gate drive circuit of Figure 9.
  • an embodiment of this application provides a display panel 2, which includes a display section 21 and a gate driving circuit 22 located on at least one side of the display section 21.
  • the gate driving circuit 22 includes a plurality of cascaded gate driving units 120, and each gate driving unit 120 includes a plurality of oxide semiconductor transistors (e.g., a first control transistor T13 and a first output transistor T10).
  • the display panel 2 includes:
  • An oxide semiconductor layer 211 is disposed on one side of the substrate 201.
  • the oxide semiconductor layer 211 includes the active pattern of the oxide semiconductor transistor (e.g., the active pattern T13A of the first control transistor T13).
  • the source-drain layer 223 is disposed on the side of the oxide semiconductor layer 211 away from the substrate 201.
  • the source-drain layer 223 includes a metal pattern for forming the source and drain (e.g., a metal pattern for forming the first electrode T13D and the second electrode T13S of the first control transistor T13) and a light-shielding pattern 223a formed in the non-display area NA.
  • a pixel electrode layer 221 is disposed on the side of the source/drain layer 223 away from the oxide semiconductor layer 211.
  • the pixel electrode layer 221 includes a conductive pattern for forming a pixel electrode 221c and a connection trace 221a formed in the non-display area NA.
  • the connection trace 221a is provided with a via 221b.
  • the active pattern of the oxide semiconductor transistor in at least one of the connection traces 221a and the light-shielding pattern 223a is completely covered.
  • This application provides a display panel that, by changing the relative position of the vias on the connection lines and the active pattern of the oxide semiconductor transistor, and by including a light-shielding pattern in the source-drain layer, completely covers the active pattern of the oxide semiconductor transistor with one or more of the connection lines and the light-shielding pattern, thereby preventing external light from shining on the active pattern of the oxide semiconductor transistor, achieving light shielding of the oxide semiconductor transistor, and improving the performance stability of the oxide semiconductor transistor.
  • the active patterns of oxide semiconductor transistors being completely covered by one or more of the following technical solutions: the active patterns of all oxide semiconductor transistors are completely covered by the connecting lines; the active patterns of all oxide semiconductor transistors are completely covered by the light-shielding pattern; the active patterns of some oxide semiconductor transistors are covered by the connecting lines, and the active patterns of other oxide semiconductor transistors are covered by the connecting lines.
  • the embodiments of this application specify that the active pattern of the oxide semiconductor transistor in at least one gate driving unit is completely covered by one or more of the connection traces and light-shielding patterns.
  • the design in all gate driving units can be the same, adopting one of the three schemes mentioned above; or the design in some gate driving units can be different.
  • the active pattern of all oxide semiconductor transistors is completely covered by the connection traces, and in some gate driving units, the active pattern of all oxide semiconductor transistors is completely covered by the light-shielding pattern.
  • this application is not limited to this.
  • any two or three of the three schemes mentioned above can be adopted.
  • the source and drain layers do not need to have a light-shielding pattern.
  • the metal pattern forming the source/drain and the light-shielding pattern can be set in the same source/drain layer or in different source/drain layers.
  • the metal pattern forming the source/drain can be formed in the first source/drain layer, and the light-shielding pattern can be set in the second source/drain layer.
  • the metal pattern forming the source/drain and the light-shielding pattern can be designed accordingly.
  • the fact that the active pattern of the oxide semiconductor transistor in at least one gate driving unit is completely covered by the connecting trace means that the projection of the active pattern of the oxide semiconductor transistor in at least one gate driving unit onto the substrate 201 and the projection of the via 221b on the connecting trace onto the substrate 201 have a doping gap (for example, in Figure 7, there is a gap between the active pattern T13A of the first control transistor T13 and the projection of the via 221b onto the substrate 201).
  • the projection of the active pattern of any oxide semiconductor transistor onto the substrate 201 and the projection of the via 221b onto the substrate 201 can be spaced apart.
  • the gate driving unit includes two oxide semiconductor transistors
  • the projections of the active patterns of the two oxide semiconductor transistors onto the substrate and the projections of the vias onto the substrate can be spaced apart.
  • the relative positions of the active patterns of each oxide semiconductor transistor and the vias can be seen in Figure 7.
  • the gate driving unit includes multiple oxide semiconductor transistors
  • the projections of the active patterns of all oxide semiconductor transistors onto the substrate and the projections of the vias onto the substrate can be spaced apart.
  • the active pattern of the oxide semiconductor transistor in at least one gate driving unit being completely covered by the light-shielding pattern means that the active pattern of the oxide semiconductor transistor in at least one gate driving unit is set to correspond to the light-shielding pattern 223a.
  • the active pattern of the oxide semiconductor transistor (OST) when configured to correspond with the light-shielding pattern, the active pattern of the OST can be configured to correspond with the via (for example, the active pattern T13A of the first control transistor T13 in Figure 8 is configured to correspond with the via 221b), or the active pattern of the OST can be configured not to correspond with the via.
  • the active pattern of the OST is not configured to correspond with the via, there is no need to configure the light-shielding pattern, light-shielding can be achieved by using the light-shielding pattern when the active pattern of the OST is configured to correspond with the via.
  • the active pattern of any oxide semiconductor transistor can be configured to correspond with the via 221b, and the source/drain layer 223 includes a light-shielding pattern 223a, which is configured to correspond with the via 221b.
  • the gate driving unit includes two oxide semiconductor transistors
  • the projection of the active patterns of the two oxide semiconductor transistors onto the substrate corresponds to the projection of the via onto the substrate
  • the light-shielding pattern is configured to correspond with the via.
  • the relative positions of each oxide semiconductor transistor, via, and light-shielding pattern can be seen in Figure 8.
  • the gate driving unit includes multiple oxide semiconductor transistors
  • the projection of the active patterns of all oxide semiconductor transistors onto the substrate can correspond to the projection of the via onto the substrate, and the light-shielding pattern is configured to correspond with the via.
  • the fact that the active pattern of the oxide semiconductor transistor in at least one of the gate driving units is completely covered by multiple of the connection traces and the light-shielding pattern means that: there is a gap between the projection of the active pattern of a portion of the oxide semiconductor transistor on the substrate 201 and the projection of the via 221b on the substrate 201; the active pattern of a portion of the oxide semiconductor transistor is correspondingly set with the light-shielding pattern 223a.
  • the active pattern of the oxide semiconductor transistor When the active pattern of the oxide semiconductor transistor is correspondingly set with the light-shielding pattern, the active pattern of the oxide semiconductor transistor can be correspondingly set with the via (for example, the design of the active pattern of a portion of the oxide semiconductor transistor and the via is shown in Figure 7, and the design of the active pattern of a portion of the oxide semiconductor transistor and the via and the light-shielding pattern is shown in Figure 8), or the active pattern of the oxide semiconductor transistor can not be correspondingly set with the via.
  • the via for example, the design of the active pattern of a portion of the oxide semiconductor transistor and the via is shown in Figure 7, and the design of the active pattern of a portion of the oxide semiconductor transistor and the via and the light-shielding pattern is shown in Figure 8
  • the active pattern of the oxide semiconductor transistor can not be correspondingly set with the via.
  • a gap can be created between the projection of the active pattern of a portion of the oxide semiconductor transistor onto the substrate and the projection of the via 221b onto the substrate 201.
  • the active patterns of a portion of the oxide semiconductor transistor are correspondingly positioned to the via 221b, and the source/drain layer 223 includes a light-shielding pattern 223a.
  • the via 221b, corresponding to the oxide semiconductor transistor, is also correspondingly positioned to the light-shielding pattern 223a.
  • a gate driving unit includes two oxide semiconductor transistors, and the active pattern of one oxide semiconductor transistor is spaced from the projection of any via onto the substrate.
  • the active pattern of the oxide semiconductor transistor and the projection of the via are spaced apart. The positions can be seen in Figure 7; the active pattern of another oxide semiconductor transistor is arranged correspondingly to the via, and the via is arranged correspondingly to the light-shielding pattern.
  • the relative positions of the active pattern of the oxide semiconductor transistor, the via, and the light-shielding pattern can be seen in Figure 8; thereby, the active pattern of any oxide semiconductor transistor can be prevented from being illuminated, improving the stability of the oxide semiconductor transistor; similarly, when the gate driving unit includes multiple oxide semiconductor transistors, the projections of the active patterns of some oxide semiconductor transistors on the substrate and the projections of the vias on the substrate can be spaced apart, while the projections of the active patterns of other oxide semiconductor transistors on the substrate correspond to the projections of the vias on the substrate, and the light-shielding pattern is arranged correspondingly to the via.
  • the doped portion of the oxide semiconductor transistor when there is a gap between the projection of the active pattern of the oxide semiconductor transistor on the substrate and the projection of the via on the substrate, there can be a gap between the projection of the channel portion of the oxide semiconductor transistor on the substrate and the projection of the via on the substrate, and the doped portion of the oxide semiconductor transistor can overlap with the projection of the via on the substrate.
  • the doped portion of the oxide semiconductor transistor is also spaced apart from the projection of the via on the substrate.
  • the channel portion of the oxide semiconductor transistor can be set to correspond with the via, or the doped portion of the oxide semiconductor transistor can be set to correspond with the via.
  • the light-shielding pattern can be set to correspond with the via in either case to shield the oxide semiconductor transistor from light.
  • the gate of the thin-film transistor refers to the two gates of the thin-film transistor.
  • the gate of the first control transistor T13 includes the first gate T13Ga and the second gate T13Gb.
  • the gate of the first control transistor is connected to the gate of other transistors, it means that both the first gate and the second gate of the first control transistor are connected to the gates of other transistors.
  • other thin-film transistors also include dual gates, please refer to the above description, which will not be repeated here.
  • the gate driving circuit 22 includes a plurality of repeating units, each repeating unit including at least four gate driving units 120. Taking four gate driving units 120 as one repeating unit as an example, the plurality of repeating units are arranged in the first direction.
  • the repeating unit includes a first gate driving unit 321, a second gate driving unit 322, a third gate driving unit 323, and a fourth gate driving unit 324 arranged sequentially along a first direction.
  • the display panel frame has a first clock signal line PCK1, a second clock signal line PCK2, a third clock signal line PCK3, and a fourth clock signal line PCK4 arranged along a second direction. Each pair of clock signal lines is connected to a gate driving unit 120.
  • the first clock signal line PCK1, the second clock signal line PCK2, and the first gate driving unit 321 are connected.
  • the first clock signal line PCK1 is the first clock signal line CK of the first gate driving unit 321
  • the second clock signal line PCK2 is the second clock signal line XCK of the first gate driving unit 321. That is, the first clock signal line PCK1 is connected to the second electrode of the third output transistor T6 in the first gate driving unit 321, and the second clock signal line PCK2 is connected to the gate of the seventh control transistor T21 in the first gate driving unit 321.
  • the second clock signal line PCK2, the third clock signal line PCK3, and the second gate driving unit 322 are connected.
  • the second clock signal line PCK2 is the first clock signal line CK of the second gate driving unit 322
  • the third clock signal line PCK3 is the second clock signal line XCK of the second gate driving unit 322. That is, the second clock signal line PCK2 is connected to the second electrode of the third output transistor T6 in the second gate driving unit 322, and the third clock signal line PCK3 is connected to the gate of the seventh control transistor T21 in the second gate driving unit 322.
  • the third clock signal line PCK3, the fourth clock signal line PCK4, and the third gate driving unit 323 are connected.
  • the third clock signal line PCK3 is the first clock signal line CK of the third gate driving unit 323, and the fourth clock signal line PCK4 is the second clock signal line XCK of the third gate driving unit 323. That is, the third clock signal line PCK3 is connected to the second electrode of the third output transistor T6 in the third gate driving unit 323, and the fourth clock signal line PCK4 is connected to the gate of the seventh control transistor T21 in the third gate driving unit 323.
  • the fourth clock signal line PCK4, the first clock signal line PCK1, and the fourth gate driving unit 324 are connected.
  • the fourth clock signal line PCK4 is the first clock signal line CK of the fourth gate driving unit 324
  • the first clock signal line PCK1 is the second clock signal line XCK of the fourth gate driving unit 324. That is, the fourth clock signal line PCK4 is connected to the second electrode of the third output transistor T6 in the fourth gate driving unit 324, and the first clock signal line PCK1 is connected to the gate of the seventh control transistor T21 in the fourth gate driving unit 324.
  • the first source-drain layer 215 includes a third connection line L3 connected to the second electrode T6S of the third output transistor T6.
  • the third connection line L3 is arranged along the second direction.
  • the third output transistors T6 of the first gate driving unit 321, the second gate driving unit 322, the third gate driving unit 323, and the fourth gate driving unit 324 are connected to different clock signal lines, the lengths of the third connection lines L3 in each gate driving unit 120 in the repeating unit are different in the second direction.
  • the lengths of the third connection lines L3 in the first gate driving unit 321, the second gate driving unit 322, the third gate driving unit 323, and the fourth gate driving unit 324 are different; for example, the lengths of the third connection lines L3 in the first gate driving unit 321, the second gate driving unit 322, the third gate driving unit 323, and the fourth gate driving unit 324 gradually increase.
  • the first source-drain layer 215 includes a second connection line L2 connected to the gate of the seventh control transistor T21.
  • the second connection line L2 is disposed along a second direction.
  • the seventh control transistor T21 of the first gate driving unit 321, the second gate driving unit 322, the third gate driving unit 323, and the fourth gate driving unit 324 are connected to different clock signal lines, the lengths of the second connection lines L2 in each gate driving unit 120 are different in the second direction in the repeating unit.
  • the lengths of the second connection lines L2 in the first gate driving unit 321, the second gate driving unit 322, the third gate driving unit 323, and the fourth gate driving unit 324 are different; for example, the lengths of the second connection lines L2 in the fourth gate driving unit 324, the first gate driving unit 321, the second gate driving unit 322, and the third gate driving unit 323 gradually decrease.
  • the active pattern of the oxide semiconductor transistor in at least one stage of the gate driving unit 120 is completely covered by the connection trace 221a.
  • the connection trace 221a By completely covering the active pattern of the oxide semiconductor transistor in at least one stage of the gate driving unit with the connection trace, light cannot shine on the active pattern of the oxide semiconductor transistor, thereby improving the stability of the oxide semiconductor transistor without adding other structures.
  • the active pattern of the oxide semiconductor transistor in at least one stage of the gate driving unit 120 is completely covered by the light-shielding pattern 223a.
  • the light-shielding pattern 223a By completely covering the active pattern of the oxide semiconductor transistor in at least one stage of the gate driving unit with the light-shielding pattern, light cannot shine on the active pattern of the oxide semiconductor transistor, thereby improving the stability of the oxide semiconductor transistor, and without changing the structure of the interconnect wiring.
  • the active patterns of a portion of the oxide semiconductor transistors in at least one gate driving unit 120 are covered by the connection trace 221a, and the active patterns of a portion of the oxide semiconductor transistors are covered by the light-shielding pattern 223a.
  • the source-drain layer 223 includes a first source-drain layer 215, a second source-drain layer 217, and a third source-drain layer 219.
  • the second source-drain layer 217 is disposed on the side of the first source-drain layer 215 away from the oxide semiconductor layer 211
  • the third source-drain layer 219 is disposed on the side of the second source-drain layer 217 away from the first source-drain layer 215.
  • At least one of the first source-drain layer 215, the second source-drain layer 217, and the third source-drain layer 219 includes the light-shielding pattern 223a.
  • the traces in the first, second, and third source-drain layers can be used as the light-shielding pattern.
  • the traces in the first, second, and third source-drain layers can be used as the light-shielding pattern.
  • the first, second, and third source-drain layers includes a clock signal line, a high-potential signal line, and a low-potential signal line
  • at least one of the clock signal line, high-potential signal line, and low-potential signal line can be used as the light-shielding pattern without adding traces or occupying space in each film layer.
  • one of the first source-drain layer, the second source-drain layer, and the third source-drain layer may include a portion of the light-shielding pattern, and the other one or the other two may include another portion or two portions of the light-shielding pattern.
  • the first portion of the clock signal line may be used as part of the light-shielding pattern, and the second portion of the clock signal line may be used as another portion of the light-shielding pattern.
  • the first portion of the clock signal line may be used as part of the light-shielding pattern, and the first or second portion of the high-potential signal line may be used as another portion of the light-shielding pattern.
  • the above embodiments are illustrated using the example of source-drain layers including a first source-drain layer, a second source-drain layer, and a third source-drain layer.
  • the source-drain layer may only include the first source-drain layer, and correspondingly, the first source-drain layer may include a light-shielding pattern.
  • the source-drain layer may only include the first source-drain layer and the second source-drain layer, and correspondingly, at least one of the first source-drain layer and the second source-drain layer may form a light-shielding pattern.
  • the gate driving unit 120 includes:
  • the first control unit 10 includes a first control transistor T13 and a second control transistor T12.
  • the first control transistor T13 is an oxide semiconductor transistor
  • the second control transistor T12 is a silicon semiconductor transistor.
  • the gate T13G of the first control transistor T13 and the gate T12G of the second control transistor T12 are connected to the initial signal line STV.
  • the first electrode T13D of the first control transistor T13 and the first electrode T12D of the second control transistor T12 are electrically connected to the first node K.
  • the first output unit 30 includes a first output transistor T10, a second output transistor T9, a first low-potential signal line NVGL, and a first high-potential signal line NVGH.
  • the first output transistor T10 is an oxide semiconductor transistor
  • the second output transistor T9 is a silicon semiconductor transistor.
  • the gate T10G of the first output transistor T10 is connected to the first node K
  • the gate T9G of the second output transistor T9 is electrically connected to the first node K.
  • the first electrode T10D of the first output transistor T10 and the first electrode T9D of the second output transistor T9 are connected to the first signal output terminal Nout(n).
  • the second electrode of the first output transistor T10 is connected to the first low-potential signal line NVGL
  • the second electrode T9S of the second output transistor T9 is connected to the first high-potential signal line NVGH.
  • the second control unit 20 includes a third control transistor T1, a fourth control transistor T3, a second low-potential signal line PVGL, and a second high-potential signal line PVGH.
  • the third control transistor T1 is an oxide semiconductor transistor
  • the fourth control transistor T3 is a silicon semiconductor transistor.
  • the gates T1G of the third control transistor T1 and T3G of the fourth control transistor T3 are connected to the first node K.
  • the first electrode T1D of the third control transistor T1 and the first electrode T3D of the fourth control transistor T3 are connected to the internal node P(n) of this stage.
  • the second electrode T1S of the third control transistor T1 is connected to the second low-potential signal line PVGL
  • the second electrode T3S of the fourth control transistor T3 is connected to the second high-potential signal line PVGH.
  • the output control unit 60 includes a first switching transistor T4, a second switching transistor T5, and a third switching transistor T14.
  • the first switching transistor T4 and the third switching transistor T14 are oxide semiconductor transistors, and the second switching transistor T5 is a silicon semiconductor transistor.
  • the gate T4G of the first switching transistor T4 is connected to the second clock signal line XCK.
  • the first electrode T4D of the first switching transistor T4 is connected to the first electrode T5D of the second switching transistor T5.
  • the second electrode T4S of the first switching transistor T4 is connected to the first node K.
  • the gate T5G of the second switching transistor T5 and the gate T14G of the third switching transistor T14 are connected to the first electrode T1D of the third control transistor T1.
  • the second electrode T5S of the second switching transistor T5 is connected to the second high-potential signal line PVGH.
  • the first electrode T14D of the third switching transistor T14 is connected to the first node K.
  • the second electrode T14S of the third switching transistor T14 is connected to the first low-potential signal line NVGL.
  • the third control unit 801 includes a fifth control transistor T17 and a sixth control transistor T18.
  • the fifth control transistor T17 is an oxide semiconductor transistor
  • the sixth control transistor T18 is a silicon semiconductor transistor.
  • the gate T17G of the fifth control transistor T17 is connected to the second clock signal line XCK.
  • the first electrode T17D of the fifth control transistor T17 and the first electrode T18D of the sixth control transistor T18 are connected.
  • the second electrode T17S of the fifth control transistor T17 is electrically connected to the first node K.
  • the gate T18G of the sixth control transistor T18 is connected to the gate T14G of the third switching transistor T14.
  • the second electrode T18S of the sixth control transistor T18 is connected to the second high-potential signal line PVGH.
  • the fourth control unit 802 includes a seventh control transistor T21 and an eighth control transistor T22.
  • the seventh control transistor T21 is an oxide semiconductor transistor
  • the eighth control transistor T22 is a silicon semiconductor transistor.
  • the gate T21G of the seventh control transistor T21 is connected to the second clock signal line XCK.
  • the first electrode T21D of the seventh control transistor T21 and the first electrode T22D of the eighth control transistor T22 are connected.
  • the second electrode T21S of the seventh control transistor T21 is electrically connected to the first node K.
  • the gate T22G of the eighth control transistor T22 is connected to the gate T14G of the third switching transistor T14.
  • the second electrode T22S of the eighth control transistor T22 is connected to the second high-potential signal line PVGH.
  • the active pattern T13A of the first control transistor T13, the active pattern T1A of the third control transistor T1, the active pattern T4A of the first switching transistor T4, the active pattern T14A of the third switching transistor T14, the active pattern T17A of the fifth control transistor T17, and the active pattern T21A of the seventh control transistor T21 are covered by the connection trace 221a.
  • the active pattern T10A of the first output transistor T10 is covered by the connection trace 221a; or the active pattern T10A of the first output transistor T10 is covered by the light-shielding pattern 223a.
  • the active patterns of these transistors can be prevented from being illuminated. Furthermore, by covering the active pattern of the first output transistor with connecting traces or with a light-shielding pattern, the active pattern of the first output transistor can be prevented from being illuminated, thereby improving the stability of each oxide semiconductor transistor.
  • the projections of the active pattern T13A of the first control transistor T13, the active pattern T1A of the third control transistor T1, the active pattern T4A of the first switching transistor T4, the active pattern T14A of the third switching transistor T14, the active pattern T17A of the fifth control transistor T17, and the active pattern T21A of the seventh control transistor T21 on the substrate 201 are spaced apart from the projection of the via 221b on the substrate 201.
  • the active pattern T10A of the first output transistor T10 is correspondingly disposed with respect to the via 221b, and the via 221b, which is correspondingly disposed with respect to the active pattern T10A of the first output transistor T10, is correspondingly disposed with respect to the light-shielding pattern 223a.
  • the active patterns of these transistors can be prevented from being illuminated. Furthermore, by creating a gap between the projection of the active pattern of the first output transistor on the substrate and the projection of the vias on the substrate, or by having the active pattern of the first output transistor corresponding to the vias, and the vias corresponding to the active pattern of the first output transistor corresponding to the light-shielding pattern, the active pattern of the first output transistor can be prevented from being illuminated, thereby improving the stability of each oxide semiconductor transistor.
  • the relative position of the active pattern of the first output transistor and the via can be set accordingly depending on the difference between the linewidth of the source/drain layer traces and the width of the via.
  • the linewidth of the source/drain layer traces is smaller than the width of the via, for example, when the linewidth of the source/drain layer traces is 20 micrometers and the width of the via is 28 micrometers, considering that the source/drain layer traces cannot block the via, the projection of the active pattern of the first output transistor on the substrate and the via can be spaced apart, as shown in Figure 15.
  • the projections of the active patterns of the first control transistor, the third control transistor, the first switching transistor, the third switching transistor, the fifth control transistor, the seventh control transistor, and the first output transistor on the substrate and the vias are all spaced apart.
  • the linewidth of the source-drain layer is greater than or equal to the width of the via, for example, when the linewidth of the source-drain layer is 20 micrometers and the width of the via is 20 micrometers or 19 micrometers
  • the projection of the active pattern of the first output transistor on the substrate and the via can be spaced apart.
  • the active pattern of the first output transistor can be set to correspond with the via, and the via set to correspond with the active pattern of the first output transistor can be set to correspond with the light-shielding pattern.
  • the first control transistor, the third control transistor, the first switching transistor, the third switching transistor, the fifth control transistor, the seventh control transistor, and the first output transistor are N-type transistors
  • the second control transistor, the fourth control transistor, the second switching transistor, the sixth control transistor, the eighth control transistor, and the second output transistor are P-type transistors.
  • Figure 6 illustrates an example where the first control transistor, the third control transistor, the first switching transistor, the third switching transistor, the fifth control transistor, the seventh control transistor, and the first output transistor are all dual-gate designs.
  • the embodiments of this application are not limited to this, and at least one oxide semiconductor transistor can be a single-gate design.
  • a gate driving unit that includes a first control unit, a first output unit, a second control unit, an output control unit, a third control unit, and a fourth control unit, and a first control transistor, a third control transistor, a first switching transistor, a third switching transistor, a fifth control transistor, a seventh control transistor, and a first output transistor that are oxide semiconductor transistors.
  • the embodiments of this application are not limited to this.
  • the gate driving unit has other designs, corresponding designs can also be adopted.
  • the gate driving unit includes 11T1C (11 thin film transistors and 1 capacitor), the oxide semiconductor transistors therein can adopt the above design.
  • the above embodiments are illustrated by having a gap between the projections of the active patterns of the first control transistor, the third control transistor, the first switching transistor, the third switching transistor, the fifth control transistor, and the seventh control transistor and the via on the substrate; and having a gap between the active pattern of the first output transistor and the projection of the via on the substrate.
  • the active pattern of the first output transistor may be correspondingly arranged with the via, and the via may be correspondingly arranged with the light-shielding pattern.
  • the embodiments of this application are not limited to this.
  • one or more or all of the active patterns of the first control transistor, the third control transistor, the first switching transistor, the third switching transistor, the fifth control transistor, the seventh control transistor, and the first output transistor may have a gap with the via; or the active pattern of the first control transistor may have a gap with the via.
  • One or more, or all of the active patterns of the third control transistor, the first switching transistor, the fifth control transistor, the seventh control transistor, and the first output transistor correspond to the via and are configured to correspond to the light-shielding pattern; or one or more of the active patterns of the first control transistor, the third control transistor, the first switching transistor, the fifth control transistor, the seventh control transistor, and the first output transistor are spaced apart from the via; one or more of the active patterns of the first control transistor, the third control transistor, the first switching transistor, the fifth control transistor, the seventh control transistor, and the first output transistor correspond to the via and are configured to correspond to the light-shielding pattern.
  • the active pattern of the first output transistor can be set to correspond with the vias, and the vias set to correspond with the active pattern of the first output transistor can be set to correspond with the light-shielding pattern.
  • the performance stability of the first output transistor is improved.
  • the active pattern area of other oxide semiconductor transistors is relatively small, so the vias can avoid the active patterns of other oxide semiconductor transistors, thereby improving the stability of the oxide semiconductor transistors.
  • Figure 6 illustrates the example of the second electrode T13S of the first control transistor T13 being connected to the first low-potential signal line NVGL and the second electrode T12S of the second control transistor T12 being connected to the second high-potential signal line PVGH.
  • the second electrode T13S of the first control transistor T13 can be connected to the second low-potential signal line PVGL.
  • the first electrode T13D of the first control transistor T13 and the first electrode T12D of the second control transistor T12 are connected to the second node O, and the second electrode T12S of the second control transistor T12 is connected to the second high-potential signal line PVGH.
  • Figure 6 illustrates the example of the initial signal line STV being connected to the previous level internal node P(n-1), but the embodiments of this application are not limited to this.
  • the initial signal line can be connected to the first signal output terminal of the previous level gate drive unit.
  • the first control unit 10 further includes a ninth control transistor T2, the gate T2G of the ninth control transistor T2 being connected to the second clock signal line XCK, the first electrode T2D of the ninth control transistor T2 being connected to the first node K, and the second electrode T2S of the ninth control transistor T2 being connected to the second node O;
  • the gate driving unit 120 further includes:
  • the second output unit 40 includes a third output transistor T6, a fourth output transistor T7, and a first capacitor C1.
  • the gate T6G of the third output transistor T6 is connected to the third node Q.
  • the first electrode T6D of the third output transistor T6 is connected to the first electrode T7D of the fourth output transistor T7, and the first electrode T6D of the third output transistor T6 is connected to the second signal output terminal Pout(n).
  • the second electrode T6S of the third output transistor T6 is connected to the first clock signal line CK.
  • the gate T7G of the fourth output transistor T7 is connected to the internal node P(n) of this stage.
  • the second electrode T7S of the fourth output transistor T7 is connected to the second high-potential signal line PVGH.
  • the first plate C1a of the first capacitor C1 is connected to the gate of the third output transistor T6, and the second plate C1b of the first capacitor C1 is connected to the second signal output terminal Pout(n).
  • Frequency divider unit 50 includes a first frequency divider unit 501 and a second frequency divider unit 502.
  • the first frequency divider unit includes a first frequency divider transistor T16, a second frequency divider transistor T11, and a second capacitor C2.
  • the gate T16G of the first frequency divider transistor T16 is connected to the internal node P(n) of this stage.
  • the first electrode T16D of the first frequency divider transistor T16, the first plate C2a of the second capacitor C2, and the gate T11G of the second frequency divider transistor T11 are connected.
  • the second electrode T16S of the first frequency divider transistor T16 is connected to the first frequency divider signal line NLF.
  • the first electrode T11D of the second frequency divider transistor T11 and the second plate C2b of the second capacitor C2 are connected to the fourth node W.
  • the second electrode T16S of the second frequency divider transistor T11 is connected to the first frequency divider signal line NLF.
  • the first electrode T11S is connected to the first node K;
  • the second frequency divider unit 502 includes a third frequency divider transistor T20, a fourth frequency divider transistor T19, and a third capacitor C3.
  • the gate T20G of the third frequency divider transistor T20 is connected to the internal node P(n) of this stage.
  • the first electrode T20D of the third frequency divider transistor T20, the first plate C3a of the third capacitor C3, and the gate T19G of the fourth frequency divider transistor T19 are connected.
  • the second electrode T20S of the third frequency divider transistor T20 is connected to the second frequency divider signal line PLF.
  • the first electrode T19D of the fourth frequency divider transistor T19 and the second plate C3b of the third capacitor C3 are connected to the fifth node M.
  • the second electrode T19S of the fourth frequency divider transistor T19 is connected to the first node K.
  • the reset unit 70 includes a reset transistor T15, the gate T15G of the reset transistor T15 is connected to the control signal line Control, the first electrode T15D of the reset transistor T15 is connected to the first node K, and the second electrode T15S of the reset transistor T15 is connected to the high potential signal line PVGH.
  • the switching unit 90 includes a fourth switching transistor T8.
  • the gate T8G of the fourth switching transistor T8 is connected to the switching signal line SC.
  • the switching signal line SC is connected to the two internal nodes P(n-2) above.
  • the first electrode T8D of the fourth switching transistor T8 is connected to the third node Q.
  • the second electrode T8S of the fourth switching transistor T8 is connected to the fifth node M.
  • the third output transistor T6 and the fourth output transistor T7 are silicon semiconductor transistors, and both are P-type transistors.
  • the first frequency divider transistor T16 and the second frequency divider transistor T11 are silicon semiconductor transistors, and both the first frequency divider transistor T16 and the second frequency divider transistor T11 are P-type transistors.
  • the third frequency divider transistor T20 and the fourth frequency divider transistor T19 are silicon semiconductor transistors, and the third frequency divider transistor T20 and the fourth frequency divider transistor T19 are P-type transistors.
  • the reset transistor T15 is a silicon semiconductor transistor, and the reset transistor T15 is a P-type transistor.
  • the fourth switching transistor T8 is a silicon semiconductor transistor and a P-type transistor.
  • the display panel 2 further includes:
  • a silicon semiconductor layer 205 is disposed between the substrate 201 and the oxide semiconductor layer 211;
  • a first metal layer 207 is disposed between the silicon semiconductor layer 205 and the oxide semiconductor layer 211;
  • the second metal layer 209 is disposed between the first metal layer 207 and the oxide semiconductor layer 211;
  • a third metal layer 213 is disposed between the oxide semiconductor layer 211 and the first source/drain layer 215.
  • the silicon semiconductor layer 205 includes the active pattern T2A of the ninth control transistor T2, the active pattern T3A of the fourth control transistor T3, the active pattern T5A of the second switch transistor T5, the active pattern T6A of the third output transistor T6, the active pattern T7A of the fourth output transistor T7, the active pattern T8A of the fourth switch transistor T8, the active pattern T9A of the second output transistor T9, the active pattern T11A of the second frequency divider transistor T11, the active pattern T12A of the second control transistor T12, the active pattern T15A of the reset transistor T15, the active pattern T16A of the first frequency divider transistor T16, the active pattern T18A of the sixth control transistor T18, the active pattern T19A of the fourth frequency divider transistor T19, the active pattern T20A of the third frequency divider transistor T20, and the active pattern T22A of the eighth control transistor T22.
  • the first metal layer 207 includes the gate T2G of the ninth control transistor T2, the gate T3G of the fourth control transistor T3, the gate T5G of the second switching transistor T5, the gate T6G of the third output transistor T6, the gate T7G of the fourth output transistor T7, the gate T8G of the fourth switching transistor T8, the gate T9G of the second output transistor T9, the gate T11G of the second frequency divider transistor T11, the gate T12G of the second control transistor T12, and the heavy
  • the second metal layer 209 includes the first gate T1Ga of the third control transistor T1, the first gate T4Ga of the first switching transistor T4, the first gate T10Ga of the first output transistor T10, the first gate T13Ga of the first control transistor T13, the first gate T4Ga of the third switching transistor T14, the first gate T17Ga of the fifth control transistor T17, the first gate T21Ga of the seventh control transistor T21, the second plate C1b of the first capacitor C1, the second plate C2b of the second capacitor C2, and the second plate C3b of the third capacitor C3.
  • the active pattern of each oxide semiconductor transistor can be shielded, and the gate control capability of each oxide semiconductor transistor can be improved.
  • the oxide semiconductor layer 211 includes an active pattern T13A of a first control transistor T13, an active pattern T10A of a first output transistor T10, an active pattern T1A of a third control transistor T1, an active pattern T4A of a first switch transistor T4, an active pattern T14A of a third switch transistor T14, an active pattern T17A of a fifth control transistor T17, and an active pattern T21A of a seventh control transistor T21.
  • the active patterns T21A of the seventh control transistor T21, T4A of the first switch transistor T4, T17A of the fifth control transistor T17, T14A of the third switch transistor T14, T1A of the third control transistor T1, T13A of the first control transistor T13, and T10A of the first output transistor T10 are sequentially arranged.
  • the active patterns of the seventh control transistor, the first switching transistor, the fifth control transistor, the third switching transistor, the third control transistor, the first control transistor, and the first output transistor along a direction away from the display section, more oxide semiconductor transistors can be shielded by the connecting traces, thereby avoiding performance changes of the oxide semiconductor transistors caused by the connecting traces not being able to shield them.
  • the embodiments of this application can set the active patterns of all oxide semiconductor transistors away from the display section, so that the active patterns of the oxide semiconductor transistors are located in the corresponding area of the connecting lines, and the active patterns of the oxide semiconductor transistors are shielded by the connecting lines.
  • the third metal layer 213 includes the second gate T1Gb of the third control transistor T1, the second gate T4Gb of the first switching transistor T4, the second gate T10Gb of the first output transistor T10, the second gate T13Gb of the first control transistor T13, the second gate T14Gb of the third switching transistor T14, the second gate T17Gb of the fifth control transistor T17, the second gate T21Gb of the seventh control transistor T21, and the upper two-stage internal nodes P(n-2).
  • the active pattern of the oxide semiconductor transistor is changed, the setting position of its gate can be changed accordingly, and the gate control capability of the oxide semiconductor transistor can be improved through the dual-gate design.
  • the first source-drain layer 215 includes the first electrode T2D and the second electrode T2S of the ninth control transistor T2, the first electrode T3D and the second electrode T3S of the fourth control transistor T3, the first electrode T5D and the second electrode T5S of the second switching transistor T5, the first electrode T6D and the second electrode T6S of the third output transistor T6, the first electrode T7D and the second electrode T7S of the fourth output transistor T7, the first electrode T8D and the second electrode T8S of the fourth switching transistor T8, the first electrode T9D and the second electrode T9S of the second output transistor T9, the first electrode T11D and the second electrode T11S of the second frequency divider transistor T11, the first electrode T12D and the second electrode T12S of the second control transistor T12, the first electrode T15D and the second electrode T15S of the reset transistor T15, the first electrode T16D and the second electrode T16S of the first frequency divider transistor T16,
  • the second source-drain layer 217 includes a first portion NVGL-1 of a first low-potential signal line NVGL, a first portion NVGH-1 of a first high-potential signal line NVGH, a second low-potential signal line PVGL, a first portion PVGH-1 of a second high-potential signal line PVGH, a first frequency divider signal line NLF, an initial signal line STV, a control signal line Control, a second frequency divider signal line PLF, a first portion PCK1a of a first clock signal line PCK1, a first portion PCK2a of a second clock signal line PCK2, a first portion PCK3a of a third clock signal line PCK3, and a first portion PCK4a of a fourth clock signal line PCK4.
  • the third source-drain layer 219 includes a second portion NVGL-2 of a first low-potential signal line NVGL, a second portion NVGH-2 of a first high-potential signal line NVGH, a second portion PVGH-2 of a second high-potential signal line PVGH, a second portion PCK1b of a first clock signal line PCK1, a second portion PCK2b of a second clock signal line PCK2, a second portion PCK3b of a third clock signal line PCK3, and a second portion PCK4b of a fourth clock signal line PCK4.
  • the second portion NVGL-2 of the first low-potential signal line NVGL is connected to the first portion NVGL-1 of the first low-potential signal line NVGL, and the second portion NVGH-2 of the first high-potential signal line NVGH is connected to the first high-potential signal line PVGH.
  • the first part of the high potential signal line NVGH, NVGH-1 is connected; the second part of the second high potential signal line PVGH, PVGH-2, is connected to the first part of the second high potential signal line PVGH, PVGH-1; the second part of the first clock signal line PCK1, PCK1b, is connected to the first part of the first clock signal line PCK1, PCK1a; the second part of the second clock signal line PCK2, PCK2b, is connected to the first part of the second clock signal line PCK2, PCK2a; the second part of the third clock signal line PCK3, PCK3b, is connected to the first part of the third clock signal line PCK3, PCK3a; and the second part of the fourth clock signal line PCK4, PCK4b, is connected to the first part of the fourth clock signal line PCK4, PCK4a.
  • the first low-potential signal line NVGL and the first high-potential signal line NVGH include the light-shielding pattern 223a.
  • the clock signal line may include the light-shielding pattern.
  • the pixel electrode layer 221 includes a connection trace 221a, and the connection trace 221a includes a via 221b.
  • FIG16(a) shows the location of the first via 421, which refers to the via etched from the first source/drain layer to the first active layer, the first metal layer and the second metal layer.
  • FIG16(b) shows the location of the second via 422, which refers to the via etched from the first source-drain layer to the second active layer and the third metal layer.
  • FIG17(a) shows the location of the third via 423, which refers to the via etched from the second source-drain layer to the first source-drain layer.
  • FIG17(b) shows the location of the fourth via 424, which refers to the via etched from the third source-drain layer to the second source-drain layer.
  • the first and second portions of the first low-potential signal line can be configured to correspond to each other, the first low-potential signal line can be configured to correspond to the via, the first and second portions of the first high-potential signal line can be configured to correspond to each other, and the first high-potential signal line can be configured to correspond to the via.
  • the first low-potential signal line and the second high-potential signal line can be used as a light-shielding pattern to shield the oxide semiconductor transistor without adding traces or other structures.
  • the active pattern T10A of the first output transistor T10 includes a first sub-active pattern T10Aa and a second sub-active pattern T10Ab, which are spaced apart.
  • the active pattern T9A of the second output transistor T9 includes a third sub-active pattern T9Aa and a fourth sub-active pattern T9Ab, which are spaced apart.
  • the gap H1 between the projection of the oxide semiconductor transistor on the substrate 201 and the projection of the via 221b on the substrate is greater than 5 micrometers, thereby further preventing light from shining on the active pattern of the oxide semiconductor transistor and improving the performance stability of the oxide semiconductor transistor.
  • the distance H2 between the boundary of the light-shielding pattern 223a and the boundary of the via 221b can be greater than 5 micrometers, thereby further preventing light from shining on the active pattern of the oxide semiconductor transistor and improving the performance stability of the oxide semiconductor transistor.
  • the display panel also includes a common electrode layer
  • the third source-drain layer also includes a transition line, the connection trace connecting the common electrode layer and the transition line.
  • the display panel 2 includes a display area AA and a non-display area NA, the display unit 21 is disposed in the display area AA, and the gate driving circuit 22 is disposed in the non-display area NA.
  • the display panel 2 also includes a terminal portion 23.
  • the display panel 2 includes a substrate 201, a shielding layer 202, a barrier layer 203, a buffer layer 204, a silicon semiconductor layer 205, a first gate insulating layer 206, a first metal layer 207, a second gate insulating layer 208, a second metal layer 209, a third gate insulating layer 210, an oxide semiconductor layer 211, a fourth gate insulating layer 212, a third metal layer 213, a first interlayer insulating layer 214, a first source/drain layer 215, a first planarization layer 216, a second source/drain layer 217, a second planarization layer 218, a third source/drain layer 219, a third planarization layer 220, a pixel electrode layer 221, and a pixel definition layer 222.
  • the shielding layer 202 is disposed on one side of the substrate 201, the barrier layer 203 is disposed on the side of the shielding layer 202 away from the substrate 201, and the buffer layer 204 is disposed on the barrier layer 203.
  • a first gate insulating layer 206 is disposed between the silicon semiconductor layer 205 and the first metal layer 207
  • a second gate insulating layer 208 is disposed between the first metal layer 207 and the second metal layer 209
  • a third gate insulating layer 210 is disposed between the second metal layer 209 and the oxide semiconductor layer 211
  • a fourth gate insulating layer 212 is disposed between the oxide semiconductor layer 211 and the third metal layer 213
  • a first interlayer insulating layer 214 is disposed between the third metal layer 213 and the first source/drain layer 215
  • a first planarization layer 216 is disposed between the first source/drain layer 215 and the second source/drain layer 217
  • pixel electrode layer 2221c is shown in pixel electrode layer 221. Therefore, two reference numerals are used to indicate the same structure. It can be understood that pixel electrode layer may include other structures.
  • the pixel electrode is disposed in the display area, and the connecting trace is disposed in the area corresponding to the gate driving circuit. The pixel electrode and the connecting trace are insulated from each other.
  • the first electrode of the transistor in the above embodiments is the source and the second electrode is the drain; or the first electrode of the transistor in the above embodiments is the drain and the second electrode is the source.
  • oxide semiconductor transistors can be metal oxide transistors, and silicon semiconductor transistors can be low-temperature polycrystalline silicon transistors.
  • the silicon semiconductor layer is made of low-temperature polycrystalline silicon
  • the oxide semiconductor layer is made of metal oxide, specifically indium gallium zinc oxide.
  • the third metal layer includes the second gate of the third control transistor, the second gate of the first switching transistor, the second gate of the first output transistor, the second gate of the first control transistor, the second gate of the third switching transistor, the second gate of the fifth control transistor, the second gate of the seventh control transistor, and the upper two internal nodes.
  • the active pattern of the first output transistor includes a first sub-active pattern and a second sub-active pattern, and the first sub-active pattern and the second sub-active pattern are spaced apart.
  • this application provides a display device, which includes a display panel as described in any of the above embodiments.
  • This application provides a display panel, which includes a display section and a gate driving circuit located on at least one side of the display section.
  • the gate driving circuit includes a plurality of cascaded gate driving units, each gate driving unit including a plurality of oxide semiconductor transistors.
  • the display panel includes a substrate, an oxide semiconductor layer, a source-drain layer, and a pixel electrode layer.
  • the oxide semiconductor layer is disposed on one side of the substrate and includes active patterns of oxide semiconductor transistors.
  • the source-drain layer is disposed on the side of the oxide semiconductor layer away from the substrate and includes metal patterns for forming source-drain electrodes and light-shielding patterns formed in non-display areas.
  • the pixel electrode layer is disposed on the side of the source-drain layer away from the oxide semiconductor layer and includes conductive patterns for forming pixel electrodes and connection traces formed in non-display areas. Through-holes are provided on the connection traces.
  • the active patterns of oxide semiconductor transistors in at least one level of the gate driving unit are completely covered by one or more of the connection traces and light-shielding patterns.
  • This application changes the relative position of the vias on the connection lines and the active pattern of the oxide semiconductor transistor, and makes the source and drain layers include light-shielding patterns, so that the active pattern of the oxide semiconductor transistor is completely covered by one or more of the connection lines and light-shielding patterns. This prevents external light from shining on the active pattern of the oxide semiconductor transistor, achieves light shielding of the oxide semiconductor transistor, and improves the performance stability of the oxide semiconductor transistor.

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Abstract

本申请实施例提供一种显示面板，该显示面板通过改变连接走线上的通孔与氧化物半导体晶体管的有源图案的相对位置，通过使源漏极层包括遮光图案，使得氧化物半导体晶体管的有源图案被连接走线、遮光图案中的一者或者多者完全覆盖，可以防止外界光线照射到氧化物半导体晶体管的有源图案，提高氧化物半导体晶体管的性能稳定性。

Description

显示面板
本申请要求于2024年5月7日提交中国专利局、申请号为202410558113.7的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其是涉及一种显示面板。
 背景技术
随着显示技术的发展，现有显示器件对显示效果的要求越来越高。为了提高显示效果，现有显示器件会采用LTPO（Low Temperature Polysilicon Oxide，低温多晶硅氧化物）像素电路，但LTPO像素驱动电路需要更多的GOA（Gate On Array，设置于阵列基板上的栅极驱动电路）电路输出信号，这会导致显示器件的功耗增加，为了降低显示器件的功耗，会采用CMOS（Complementary Metal Oxide Semiconductor，互补金属氧化物半导体） GOA电路减少GOA电路的数量。同时，为了释放GOA区域的有机层内的水汽，降低水汽对GOA区域器件电学性能的影响，现有显示器件会将有机层上方的阳极层进行挖槽设计。
具体的，CMOS GOA电路中设有氧化物半导体晶体管，为了提高金属氧化物的稳定性，会对氧化物半导体晶体管进行遮光，且为了减少工艺，会利用油墨对氧化物半导体晶体管进行遮光，当由于油墨涂布精度的问题，导致油墨无法实现对氧化物半导体晶体管的遮光效果。现有显示器件为了解决上述问题，会采用阳极层对CMOS GOA电路中的氧化物半导体晶体管进行遮光，但由于阳极层设有挖槽，导致阳极层无法对所有的氧化物半导体晶体管进行遮光，进而导致氧化物半导体晶体管的性能变差，CMOS GOA电路失效。
所以，现有显示器件存在阳极层的挖槽漏光至氧化物半导体晶体管，导致氧化物半导体晶体管的性能变差的技术问题。
 发明概述
本申请实施例提供一种显示面板，用以解决现有显示器件存在阳极层的挖槽漏光至氧化物半导体晶体管，导致氧化物半导体晶体管的性能变差的技术问题。
本申请实施例提供一种显示面板，该显示面板包括显示部和位于所述显示部的至少一侧的栅极驱动电路，所述栅极驱动电路包括多个级联的栅极驱动单元，所述栅极驱动单元包括多个氧化物半导体晶体管，所述显示面板包括：
衬底；
氧化物半导体层，设置于所述衬底一侧，所述氧化物半导体层包括所述氧化物半导体晶体管的有源图案；
源漏极层，设置于所述氧化物半导体层远离所述衬底的一侧，所述源漏极层包括用于形成源漏极的金属图案和形成在非显示区的遮光图案；
像素电极层，设置于所述源漏极层远离所述氧化物半导体层的一侧，所述像素电极层包括用于形成像素电极的导电图案和形成在非显示区的连接走线，所述连接走线上设有通孔；
其中，至少一级所述栅极驱动单元中的所述氧化物半导体晶体管的有源图案被所述连接走线、所述遮光图案中的一者或者多者完全覆盖。
 附图说明
图1为现有显示器件的第一种示意图。
图2为现有显示器件的第二种示意图。
图3为现有显示器件的第三种示意图。
图4为本申请实施例提供的显示面板的第一种示意图。
图5为本申请实施例提供的显示面板的第二种示意图。
图6为本申请实施例提供的栅极驱动单元的电路图。
图7为本申请实施例提供的显示面板的第三种示意图。
图8为本申请实施例提供的显示面板的第四种示意图。
图9为本申请实施例提供的栅极驱动电路的各膜层的叠层图。
图10为图9中的栅极驱动电路中的硅半导体层和第一金属层的分解图。
图11为图9中的栅极驱动电路中的第二金属层和氧化物半导体层的分解图。
图12为图9中的栅极驱动电路中的第三金属层和第一源漏极层的分解图。
图13为图9中的栅极驱动电路中的第二源漏极层和第三源漏极层的分解图。
图14为图9中的栅极驱动电路中的阳极层的分解图。
图15为图9中的栅极驱动电路的氧化物半导体层和阳极层的叠层图。
图16为图9中的栅极驱动电路中的第一过孔和第二过孔的分解图。
图17为图9中的栅极驱动电路中的第三过孔和第四过孔的分解图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“连接”是指两者直接连接，“电连接”是指两者可以直接连接，也可以通过中间媒介间接连接。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
如图1所示，现有显示器件包括边框区11，边框区内设有CMOS GOA区121，为了防止CMOS GOA区的氧化物半导体晶体管受到光照导致性能发生变化，现有显示器件会利用油墨对CMOS GOA区的氧化物半导体晶体管进行遮光，以图1所示的显示器件为例，可以看到边框区11的宽度为A1，CMOS GOA区的宽度为A2，CMOS GOA区域与显示区的边界的间距为A3，油墨涂布的目标边界与显示区的边界的间距为A5，但在油墨的实际涂布过程中，油墨涂布会有宽度为A4的误差，导致油墨实际涂布位置与理论涂布位置存在一定的误差，进而导致油墨无法遮挡CMOS GOA区的氧化物半导体晶体管，导致CMOS GOA区的氧化物半导体晶体管的性能发生变化。现有显示器件为了解决上述问题，会利用阳极层的阳极金属122对CMOS GOA区的氧化物半导体晶体管进行遮光，但从图2中可以看到，阳极金属122与显示区的边界的间距为A6，大于CMOS GOA区与显示区的边界的间距A3，导致部分氧化物半导体晶体管无法被阳极金属122遮挡，且为了释放GOA区域的有机层内的水汽，降低水汽对GOA区域器件电学性能的影响，现有显示器件会将有机层上方的阳极层进行挖槽设计，如图3所示，阳极金属122的挖槽123会暴露氧化物半导体晶体管的沟道部124，导致氧化物半导体晶体管的性能变差，所以，现有显示器件存在阳极层的挖槽漏光至氧化物半导体晶体管，导致氧化物半导体晶体管的性能变差的技术问题。
本申请实施例提供一种显示面板，用以解决上述技术问题。
图4为本申请实施例提供的显示面板的第一种示意图。图5为本申请实施例提供的显示面板的第二种示意图。图6为本申请实施例提供的栅极驱动单元的电路图。图7为本申请实施例提供的显示面板的第三种示意图。图8为本申请实施例提供的显示面板的第四种示意图。图9为本申请实施例提供的栅极驱动电路的各膜层的叠层图。图10为图9中的栅极驱动电路中的硅半导体层和第一金属层的分解图；其中，图10中的（a）为图9中的栅极驱动电路中的硅半导体层的分解图，图10中的（b）为图9中的栅极驱动电路中的第一金属层的分解图。图11为图9中的栅极驱动电路中的第二金属层和氧化物半导体层的分解图；其中，图11中的（a）为图9中的栅极驱动电路中的第二金属层的分解图，图11中的（b）为图9中的栅极驱动电路中的氧化物半导体层的分解图。图12为图9中的栅极驱动电路中的第三金属层和第一源漏极层的分解图；其中，图12中的（a）为图9中的栅极驱动电路中的第三金属层的分解图，图12中的（b）为图9中的栅极驱动电路中的第一源漏极层的分解图。图13为图9中的栅极驱动电路中的第二源漏极层和第三源漏极层的分解图；图13中的（a）为图9中的栅极驱动电路中的第二源漏极层的分解图，图13中的（b）为图9中的栅极驱动电路中的第三源漏极层的分解图。图14为图9中的栅极驱动电路中的阳极层的分解图。图15为图9中的栅极驱动电路的氧化物半导体层和阳极层的叠层图。图16为图9中的栅极驱动电路中的第一过孔和第二过孔的分解图；其中，图16中的（a）为图9中的栅极驱动电路中的第一过孔的分解图，图16中的（b）为图9中的栅极驱动电路中的第二过孔的分解图。图17为图9中的栅极驱动电路中的第三过孔和第四过孔的分解图；图17中的（a）为图9中的栅极驱动电路中的第三过孔的分解图，图17中的（b）为图9中的栅极驱动电路中的第四过孔的分解图。
如图4至图17所示，本申请实施例提供一种显示面板，该显示面板2包括显示部21和位于所述显示部21的至少一侧的栅极驱动电路22，所述栅极驱动电路22包括多个级联的栅极驱动单元120，所述栅极驱动单元120包括多个氧化物半导体晶体管（例如第一控制晶体管T13和第一输出晶体管T10），所述显示面板2包括：
衬底201；
氧化物半导体层211，设置于所述衬底201一侧，所述氧化物半导体层211包括所述氧化物半导体晶体管的有源图案（例如第一控制晶体管T13的有源图案T13A）；
源漏极层223，设置于所述氧化物半导体层211远离所述衬底201的一侧，所述源漏极层223包括用于形成源漏极的金属图案（例如形成第一控制晶体管T13的第一电极T13D和第一控制晶体管T13的第二电极T13S的金属图案）和形成在非显示区NA的遮光图案223a；
像素电极层221，设置于所述源漏极层223远离所述氧化物半导体层211的一侧，所述像素电极层221包括用于形成像素电极221c的导电图案和形成在非显示区NA的连接走线221a，所述连接走线221a上设有通孔221b；
其中，至少一级所述栅极驱动单元120中的所述氧化物半导体晶体管的有源图案被所述连接走线221a、所述遮光图案223a中的一者或者多者完全覆盖。
本申请实施例提供一种显示面板，该显示面板通过改变连接走线上的通孔与氧化物半导体晶体管的有源图案的相对位置，通过使源漏极层包括遮光图案，使得氧化物半导体晶体管的有源图案被连接走线、遮光图案中的一者或者多者完全覆盖，从而可以防止外界光线照射到氧化物半导体晶体管的有源图案，实现了对氧化物半导体晶体管的遮光，提高了氧化物半导体晶体管的性能稳定性。
具体的，对于氧化物半导体晶体管的有源图案被连接走线、遮光图案中的一者或者多个完全覆盖，其包括以下几个技术方案：所有氧化物半导体晶体管的有源图案被连接走线完全覆盖；所有氧化物半导体晶体管的有源图案被遮光图案完全覆盖；部分氧化物半导体晶体管的有源图案被连接走线覆盖，另外部分氧化物半导体晶体管的有源图案被连接走线覆盖。
同时，本申请实施例限定的是至少一个栅极驱动单元中的氧化物半导体晶体管的有源图案被连接走线、遮光图案中的一者或者多个完全覆盖，那么可以理解的是，可以使所有栅极驱动单元中的设计相同，采用上述三个方案中的一种；也可以使部分栅极驱动单元中的设计不同，例如部分栅极驱动单元中，所有氧化物半导体晶体管的有源图案被连接走线完全覆盖，部分栅极驱动单元中，所有氧化物半导体晶体管的有源图案被遮光图案完全覆盖，但本申请不限于此，在各栅极驱动单元中的设计不同时，可以采用上述三种方案中的任意两种或者三种。
具体的，在氧化物半导体晶体管的有源图案被连接走线完全覆盖时，源漏极层可以不设置遮光图案。
具体的，源漏极层包括形成源漏极的金属图案和遮光图案时，在源漏极层包括多层时，例如源漏极层包括第一源漏极层和第二源漏极层时，形成源漏极的金属图案与遮光图案可以设置在同一源漏极层，也可以设置在不同源漏极层，例如形成源漏极的金属图案可以形成在第一源漏极层，遮光图案可以设置在第二源漏极层，同理，当源漏极层包括更多膜层时，可以相应设计形成源漏极的金属图案和遮光图案。
具体的，至少一级栅极驱动单元内的有氧化物半导体晶体管的有源图案被连接走线完全覆盖是指：至少一级栅极驱动单元内的氧化物半导体晶体管的有源图案在衬底201上的投影与连接走线上的通孔221b在衬底201上的投影掺杂间距（例如图7中第一控制晶体管T13的有源图案T13A与通孔221b在衬底201上的投影存在间距）。
具体的，在避免氧化物半导体晶体管受到光照导致性能变化时，可以使任一所述氧化物半导体晶体管的有源图案在所述衬底201上的投影与所述通孔221b在所述衬底201上的投影存在间距，例如栅极驱动单元包括两个氧化物半导体晶体管，则两个氧化物半导体晶体管的有源图案在衬底上的投影与通孔在衬底上的投影均存在间距，各氧化物半导体晶体管的有源图案与通孔的相对位置可以参见图7所示；同理，在栅极驱动单元包括多个氧化物半导体晶体管时，可以使所有氧化物半导体晶体管的有源图案在衬底上的投影与通孔在衬底上的投影均存在间距。
具体的，至少一级栅极驱动单元内的有氧化物半导体晶体管的有源图案被遮光图案完全覆盖是指：至少一级栅极驱动单元内的氧化物半导体晶体管的有源图案与所述遮光图案223a对应设置。
具体的，在氧化物半导体晶体管的有源图案与遮光图案对应设置时，氧化物半导体晶体管的有源图案可以与通孔对应设置（例如图8中第一控制晶体管T13的有源图案T13A与通孔221b对应设置），也可以使氧化物半导体晶体管的有源图案不与通孔对应设置。但考虑到氧化物半导体晶体管的有源图案不与通孔对应时，无需设置遮光图案，因此，可以在氧化物半导体晶体管的有源图案与通孔对应设置时，通过遮光图案进行遮光。具体的，在避免氧化物半导体晶体管受到光照导致性能变化时，还可以使任一所述氧化物半导体晶体管的有源图案与所述通孔221b对应设置，且所述源漏极层223包括遮光图案223a，所述遮光图案223a与通孔221b对应设置；例如栅极驱动单元包括两个氧化物半导体晶体管，则两个氧化物半导体晶体管的有源图案在衬底上的投影与通孔在衬底上的投影对应，且遮光图案与通孔对应设置，各氧化物半导体晶体管与通孔和遮光图案的相对位置可以参见图8；同理，在栅极驱动单元包括多个氧化物半导体晶体管时，可以使所有氧化物半导体晶体管的有源图案在衬底上的投影与通孔在衬底上的投影对应，且遮光图案与通孔对应设置。
具体的，至少一级所述栅极驱动单元中的所述氧化物半导体晶体管的有源图案被所述连接走线、所述遮光图案中的多者完全覆盖是指：部分所述氧化物半导体晶体管的有源图案在所述衬底201上的投影与所述通孔221b在所述衬底201上的投影存在间距，部分所述氧化物半导体晶体管的有源图案与所述遮光图案223a对应设置，其中，氧化物半导体晶体管的有源图案与遮光图案对应设置时，可以使氧化物半导体晶体管的有源图案可以与通孔对应设置（例如部分氧化物半导体晶体管的有源图案与通孔的设计如图7所示，部分氧化物半导体晶体管的有源图案与通孔和遮光图案的设计如图8所示），也可以使氧化物半导体晶体管的有源图案不与通孔对应设置。
具体的，在避免氧化物半导体晶体管受到光照导致性能变化时，还可以使部分氧化物半导体晶体管的有源图案在衬底上的投影与通孔221b在所述衬底201上的投影存在间距，部分所述氧化物半导体晶体管的有源图案与所述通孔221b对应设置，且所述源漏极层223包括遮光图案223a，与所述氧化物半导体晶体管对应设置的所述通孔221b与所述遮光图案223a对应设置；例如栅极驱动单元包括两个氧化物半导体晶体管，一个氧化物半导体晶体管的有源图案与任一通孔在衬底上的投影存在间距，该氧化物半导体晶体管的有源图案与通孔的相对位置可以参见图7所示；另一氧化物半导体晶体管的有源图案与通孔对应设置，且该通孔与遮光图案对应设置，该氧化物半导体晶体管的有源图案与通孔和遮光图案的相对位置可以参见图8所示；从而可以避免任一氧化物半导体晶体管的有源图案受到光照，提高氧化物半导体晶体管的稳定性；同理，在栅极驱动单元包括多个氧化物半导体晶体管时，可以使一部分氧化物半导体晶体管的有源图案在衬底上的投影与通孔在衬底上的投影均存在间距，另一部分氧化物半导体晶体管的有源图案在衬底上的投影与通孔在衬底上的投影对应，且遮光图案与通孔对应设置。
具体的，在使氧化物半导体晶体管的有源图案在衬底上的投影与通孔在衬底上的投影存在间距时，可以使氧化物半导体晶体管的沟道部在衬底上的投影与通孔在衬底上的投影存在间距，而氧化物半导体晶体管的掺杂部可以与通孔在衬底上的投影存在重合，但考虑到光线会有一定角度，使氧化物半导体晶体管的掺杂部也与通孔在衬底上的投影存在间距。
具体的，在使氧化物半导体晶体管的有源图案与通孔对应设置时，可以是氧化物半导体晶体管的沟道部与通孔对应设置，也可以是氧化物半导体晶体管的掺杂部与通孔对应设置，考虑到光线会有一定角度，则可以在任一情况下，均设置遮光图案与通孔对应设置，对氧化物半导体晶体管进行遮光。
具体的，在本申请实施例中，由于部分薄膜晶体管会采用双栅设计，则在未明确区分该薄膜晶体管的第一栅极和第二栅极时，该薄膜晶体管的栅极是指该薄膜晶体管的两个栅极，例如，在本申请实施例中的部分实施例中，第一控制晶体管T13的栅极包括第一栅极T13Ga和第二栅极T13Gb，在说明第一控制晶体管的栅极与其他晶体管的栅极连接时，是指第一控制晶体管的第一栅极和第二栅极均与其他晶体管的栅极连接，同理，在其他薄膜晶体管也包括双栅时，可以参见上述说明，在此不再赘述。
具体的，在本申请实施例提供的显示面板2中，栅极驱动电路22包括多个重复单元，每一重复单元包括至少四个栅极驱动单元120，下面以4个栅极驱动单元120为一个重复单元为例，多个重复单元在第一方向上排列。
如图9至图17所示，重复单元包括沿第一方向依次排列的第一栅极驱动单元321、第二栅极驱动单元322和第三栅极驱动单元323和第四栅极驱动单元324，显示面板边框沿第二方向排列的第一条时钟信号线PCK1、第二条时钟信号线PCK2、第三条时钟信号线PCK3、第四条时钟信号线PCK4，每两条时钟信号线与一个栅极驱动单元120连接。
在本实施例中，第一条时钟信号线PCK1、第二条时钟信号线PCK2和第一栅极驱动单元321连接，第一条时钟信号线PCK1为第一栅极驱动单元321的第一时钟信号线CK，第二条时钟信号线PCK2为第一栅极驱动单元321的第二时钟信号线XCK，即第一条时钟信号线PCK1与第一栅极驱动单元321中的第三输出晶体管T6的第二电极连接，第二条时钟信号线PCK2与第一栅极驱动单元321中的第七控制晶体管T21的栅极连接。
在本实施例中，第二条时钟信号线PCK2、第三条时钟信号线PCK3和第二栅极驱动单元322连接，第二条时钟信号线PCK2为第二栅极驱动单元322的第一时钟信号线CK，第三条时钟信号线PCK3为第二栅极驱动单元322的第二时钟信号线XCK，即第二条时钟信号线PCK2与第二栅极驱动单元322中的第三输出晶体管T6的第二电极连接，第三条时钟信号线PCK3与第二栅极驱动单元322中的第七控制晶体管T21的栅极连接。
在本实施例中，第三条时钟信号线PCK3、第四条时钟信号线PCK4和第三栅极驱动单元323连接，第三条时钟信号线PCK3为第三栅极驱动单元323的第一时钟信号线CK，第四条时钟信号线PCK4为第三栅极驱动单元323的第二时钟信号线XCK，即第三条时钟信号线PCK3与第三栅极驱动单元323中的第三输出晶体管T6的第二电极连接，第四条时钟信号线PCK4与第三栅极驱动单元323中的第七控制晶体管T21的栅极连接。
在本实施例中，第四条时钟信号线PCK4、第一条时钟信号线PCK1和第四栅极驱动单元324连接，第四条时钟信号线PCK4为第四栅极驱动单元324的第一时钟信号线CK，第一条时钟信号线PCK1为第四栅极驱动单元324的第二时钟信号线XCK，即第四条时钟信号线PCK4与第四栅极驱动单元324中的第三输出晶体管T6的第二电极连接，第一条时钟信号线PCK1与第四栅极驱动单元324中的第七控制晶体管T21的栅极连接。
如图5、图9至图17所示，第一源漏极层215包括与第三输出晶体管T6的第二电极T6S连接的第三连接线L3，第三连接线L3沿第二方向设置，在本实施例中，由于第一栅极驱动单元321、第二栅极驱动单元322和第三栅极驱动单元323和第四栅极驱动单元324的第三输出晶体管T6与不同的时钟信号线连接，因此在重复单元中，各栅极驱动单元120中的第三连接线L3在第二方向上的长度相异，即第一栅极驱动单元321、第二栅极驱动单元322和第三栅极驱动单元323和第四栅极驱动单元324中的第三连接线L3的长度具有差异；例如，第一栅极驱动单元321、第二栅极驱动单元322和第三栅极驱动单元323和第四栅极驱动单元324中的第三连接线L3的长度逐渐增加。
在本申请实施例中，第一源漏极层215包括与第七控制晶体管T21的栅极连接的第二连接线L2，第二连接线L2沿第二方向设置，在本实施例中，由于第一栅极驱动单元321、第二栅极驱动单元322和第三栅极驱动单元323和第四栅极驱动单元324的第七控制晶体管T21与不同的时钟信号线连接，因此在重复单元中，各栅极驱动单元120中的第二连接线L2在第二方向上的长度相异，即第一栅极驱动单元321、第二栅极驱动单元322和第三栅极驱动单元323和第四栅极驱动单元324中的第二连接线L2的长度具有差异；例如，第四栅极驱动单元324、第一栅极驱动单元321、第二栅极驱动单元322和第三栅极驱动单元323中的第二连接线L2的长度逐渐减小。
在一些实施例中，至少一级所述栅极驱动单元120中的所述氧化物半导体晶体管的有源图案被所述连接走线221a完全覆盖。通过使至少一级栅极驱动单元中的氧化物半导体晶体管的有源图案被连接走线完全覆盖，使得光线无法照射到氧化物半导体晶体管的有源图案上，提高氧化物半导体晶体管的稳定性，且可以不增加其他结构。
在一些实施例中，至少一级所述栅极驱动单元120中的所述氧化物半导体晶体管的有源图案被所述遮光图案223a完全覆盖。通过使至少一级栅极驱动单元中的氧化物半导体晶体管的有源图案被遮光图案完全覆盖，使得光线无法照射到氧化物半导体晶体管的有源图案上，提高氧化物半导体晶体管的稳定性，且可以不更改连接走线的结构。
在一些实施例中，至少一级栅极驱动单元120中的部分氧化物半导体晶体管的有源图案被所述连接走线221a覆盖，部分所述氧化物半导体晶体管的有源图案被所述遮光图案223a覆盖。通过使至少一级栅极驱动单元中的部分氧化物半导体晶体管的有源图案被连接走线覆盖，另外部分氧化物半导体晶体管的有源图案被遮光图案覆盖，使得光线无法照射到氧化物半导体晶体管的有源图案上，提高氧化物半导体晶体管的稳定性，且可以不更改连接走线的结构。
在一些实施例中，如图5、图7、图8所示，所述源漏极层223包括第一源漏极层215、第二源漏极层217和第三源漏极层219，所述第二源漏极层217设置于所述第一源漏极层215远离所述氧化物半导体层211的一侧，所述第三源漏极层219设置于所述第二源漏极层217远离所述第一源漏极层215的一侧，所述第一源漏极层215、所述第二源漏极层217和所述第三源漏极层219中的至少一个包括所述遮光图案223a。通过使第一源漏极层、第二源漏极层和第三源漏极层中的至少一个包括遮光图案，可以利用现有膜层形成遮光图案，无需增加工艺步骤，提高显示面板的制备效率。
具体的，在使第一源漏极层、第二源漏极层和第三源漏极层中的至少一个包括遮光图案时，可以利用第一源漏极层、第二源漏极层和第三源漏极层中的走线作为遮光图案，例如第一源漏极层、第二源漏极层和第三源漏极层中的至少一个包括时钟信号线、高电位信号线和低电位信号线，则可以将时钟信号线、高电位信号线和低电位信号线中的至少一个作为遮光图案，无需增加走线、不会占用各膜层的空间。
具体的，在使第一源漏极层、第二源漏极层和第三源漏极层中的至少一个包括遮光图案时，可以使第一源漏极层、第二源漏极层和第三源漏极层中的一个包括遮光图案的一部分，另一个或者另外两个包括遮光图案的另一部分或者另外两部分；举例来说，第二源漏极层包括时钟信号线的第一部分，第三源漏极层包括时钟信号线的第二部分，则可以将时钟信号线的第一部分作为遮光图案的一部分，时钟信号线的第二部分作为遮光图案的另一部分，还可以将时钟信号线的第一部分作为遮光图案的一部分，高电位信号线的第一部分或者第二部分作为遮光图案的另一部分。
具体的，上述实施例以源漏极层包括第一源漏极层、第二源漏极层和第三源漏极层为例进行说明，但本申请实施例不限于此，源漏极层可以仅包括第一源漏极层，相应的，使第一源漏极层包括遮光图案，或者源漏极层仅包括第一源漏极层和第二源漏极层，相应的，可以使第一源漏极层和第二源漏极层中的至少一个形成遮光图案。
在一些实施例中，如图6所示，所述栅极驱动单元120包括：
第一控制单元10，包括第一控制晶体管T13和第二控制晶体管T12，所述第一控制晶体管T13为氧化物半导体晶体管，所述第二控制晶体管T12为硅半导体晶体管，所述第一控制晶体管T13的栅极T13G和所述第二控制晶体管T12的栅极T12G与初始信号线STV连接，所述第一控制晶体管T13的第一电极T13D和所述第二控制晶体管T12的第一电极T12D电连接于第一节点K；
第一输出单元30，包括第一输出晶体管T10、第二输出晶体管T9、第一低电位信号线NVGL和第一高电位信号线NVGH，所述第一输出晶体管T10为氧化物半导体晶体管，所述第二输出晶体管T9为硅半导体晶体管，所述第一输出晶体管T10的栅极T10G连接于所述第一节点K，所述第二输出晶体管T9的栅极T9G电连接于所述第一节点K，所述第一输出晶体管T10的第一电极T10D和所述第二输出晶体管T9的第一电极T9D与所述第一信号输出端Nout（n）连接，所述第一输出晶体管T10的第二电极连接第一低电位信号线NVGL，所述第二输出晶体管T9的第二电极T9S与第一高电位信号线NVGH连接；
第二控制单元20，包括第三控制晶体管T1、第四控制晶体管T3、第二低电位信号线PVGL和第二高电位信号线PVGH，所述第三控制晶体管T1为氧化物半导体晶体管，所述第四控制晶体管T3为硅半导体晶体管，所述第三控制晶体管T1的栅极T1G和所述第四控制晶体管T3的栅极T3G连接于所述第一节点K，所述第三控制晶体管T1的第一电极T1D与所述第四控制晶体管T3的第一电极T3D连接于本级内部节点P（n），所述第三控制晶体管T1的第二电极T1S连接第二低电位信号线PVGL，所述第四控制晶体管T3的第二电极T3S与第二高电位信号线PVGH连接；
输出控制单元60，包括第一开关晶体管T4、第二开关晶体管T5和第三开关晶体管T14，所述第一开关晶体管T4和所述第三开关晶体管T14为氧化物半导体晶体管，所述第二开关晶体管T5为硅半导体晶体管，所述第一开关晶体管T4的栅极T4G与第二时钟信号线XCK连接，所述第一开关晶体管T4的第一电极T4D与所述第二开关晶体管T5的第一电极T5D连接，所述第一开关晶体管T4的第二电极T4S连接于所述第一节点K，所述第二开关晶体管T5的栅极T5G与所述第三开关晶体管T14的栅极T14G连接所述第三控制晶体管T1的第一电极T1D，所述第二开关晶体管T5的第二电极T5S连接第二高电位信号线PVGH，所述第三开关晶体管T14的第一电极T14D连接于所述第一节点K，所述第三开关晶体管T14的第二电极T14S连接第一低电位信号线NVGL；
第三控制单元801，包括第五控制晶体管T17和第六控制晶体管T18，所述第五控制晶体管T17为氧化物半导体晶体管，所述第六控制晶体管T18为硅半导体晶体管，所述第五控制晶体管T17的栅极T17G与第二时钟信号线XCK连接，所述第五控制晶体管T17的第一电极T17D和所述第六控制晶体管T18的第一电极T18D连接，所述第五控制晶体管T17的第二电极T17S电连接于所述第一节点K，所述六控制晶体管T18的栅极T18G与所述第三开关晶体管T14的栅极T14G连接，所述第六控制晶体管T18的第二电极T18S与第二高电位信号线PVGH连接；
第四控制单元802，包括第七控制晶体管T21和第八控制晶体管T22，所述第七控制晶体管T21为氧化物半导体晶体管，所述第八控制晶体管T22为硅半导体晶体管，第七控制晶体管T21的栅极T21G与第二时钟信号线XCK连接，所述第七控制晶体管T21的第一电极T21D和所述第八控制晶体管T22的第一电极T22D连接，所述第七控制晶体管T21的第二电极T21S电连接于所述第一节点K，所述第八控制晶体管T22的栅极T22G与所述第三开关晶体管T14的栅极T14G连接，所述第八控制晶体管T22的第二电极T22S与第二高电位信号线PVGH连接；
其中，所述第一控制晶体管T13的有源图案T13A、所述第三控制晶体管T1的有源图案T1A、所述第一开关晶体管T4的有源图案T4A、所述第三开关晶体管T14的有源图案T14A、所述第五控制晶体管T17的有源图案T17A和所述第七控制晶体管T21的有源图案T21A被所述连接走线221a覆盖；
所述第一输出晶体管T10的有源图案T10A被所述连接走线221a覆盖；或者所述第一输出晶体管T10的有源图案T10A被所述遮光图案223a覆盖。
通过使第一控制晶体管的有源图案、第三控制晶体管的有源图案、第一开关晶体管的有源图案、第三开关晶体管的有源图案、第五控制晶体管的有源图案和第七控制晶体管的有源图案被连接走线覆盖，可以避免第一控制晶体管的有源图案、第三控制晶体管的有源图案、第一开关晶体管的有源图案、第三开关晶体管的有源图案、第五控制晶体管的有源图案和第七控制晶体管的有源图案受到光照，且使第一输出晶体管的有源图案被连接走线覆盖，或者第一输出晶体管的有源图案被遮光图案覆盖，可以避免第一输出晶体管的有源图案受到光照，从而可以提高各氧化物半导体晶体管的稳定性。
具体的，所述第一控制晶体管T13的有源图案T13A在所述衬底201上的投影、所述第三控制晶体管T1的有源图案T1A在所述衬底201上的投影、所述第一开关晶体管T4的有源图案T4A在所述衬底201上的投影、所述第三开关晶体管T14的有源图案T14A在所述衬底201上的投影、所述第五控制晶体管T17的有源图案T17A在所述衬底201上的投影和所述第七控制晶体管T21的有源图案T21A在所述衬底201上的投影与所述通孔221b在所述衬底201上的投影存在间距；
所述第一输出晶体管T10的有源图案T10A在所述衬底201上的投影与所述通孔221b在所述衬底201上的投影存在间距；或者所述第一输出晶体管T10的有源图案T10A与所述通孔221b对应设置，且与所述第一输出晶体管T10的有源图案T10A对应设置的所述通孔221b与所述遮光图案223a对应设置。
通过使第一控制晶体管的有源图案、第三控制晶体管的有源图案、第一开关晶体管的有源图案、第三开关晶体管的有源图案、第五控制晶体管的有源图案和第七控制晶体管的有源图案与通孔在衬底上的投影存在间距，可以避免第一控制晶体管的有源图案、第三控制晶体管的有源图案、第一开关晶体管的有源图案、第三开关晶体管的有源图案、第五控制晶体管的有源图案和第七控制晶体管的有源图案受到光照，且使第一输出晶体管的有源图案在所述衬底上的投影与所述通孔在所述衬底上的投影存在间距，或者第一输出晶体管的有源图案与通孔对应设置，且第一输出晶体管的有源图案对应设置的通孔与遮光图案对应设置，可以避免第一输出晶体管的有源图案受到光照，从而可以提高各氧化物半导体晶体管的稳定性。
具体的，针对源漏极层的走线的线宽与通孔的宽度的差值的不同，可以相应的选择第一输出晶体管的有源图案与通孔的相对位置的设置方式，在源漏极层的走线的线宽小于通孔的宽度时，例如，源漏极层的走线的线宽为20微米，通孔的宽度为28微米时，考虑到源漏极层的走线无法遮挡通孔，可以使第一输出晶体管的有源图案在衬底上的投影与通孔存在间距，如图15所示，可以看到第一控制晶体管的有源图案、第三控制晶体管的有源图案、第一开关晶体管的有源图案、第三开关晶体管的有源图案、第五控制晶体管的有源图案、第七控制晶体管的有源图案和第一输出晶体管的有源图案在衬底上的投影与通孔均存在间距。在源漏极层的走线的线宽大于或者等于通孔的宽度时，例如，源漏极层的走线的线宽为20微米，通孔的宽度为20微米或者19微米时，可以使第一输出晶体管的有源图案在衬底上的投影与通孔存在间距，也可以使第一输出晶体管的有源图案与通孔对应设置，且第一输出晶体管的有源图案对应设置的通孔与遮光图案对应设置。
具体的，第一控制晶体管、第三控制晶体管、第一开关晶体管、第三开关晶体管、第五控制晶体管、第七控制晶体管和第一输出晶体管为N型晶体管，第二控制晶体管、第四控制晶体管、第二开关晶体管、第六控制晶体管、第八控制晶体管和第二输出晶体管为P型晶体管。
具体的，图6中以第一控制晶体管、第三控制晶体管、第一开关晶体管、第三开关晶体管、第五控制晶体管、第七控制晶体管和第一输出晶体管均为双栅设计为例进行说明，但本申请实施例不限于此，可以使至少一个氧化物半导体晶体管为单栅设计。
具体的，上述实施例以栅极驱动单元包括第一控制单元、第一输出单元、第二控制单元、输出控制单元、第三控制单元和第四控制单元，且第一控制晶体管、第三控制晶体管、第一开关晶体管、第三开关晶体管、第五控制晶体管、第七控制晶体管和第一输出晶体管为氧化物半导体晶体管为例进行说明，但本申请实施例不限于此，对于栅极驱动单元为其他设计时，也可以采用相应的设计，例如栅极驱动单元包括11T1C（11个薄膜晶体管和1个电容）时，其中的氧化物半导体晶体管可以采用上述设计。
具体的，上述实施例以第一控制晶体管的有源图案、第三控制晶体管的有源图案、第一开关晶体管的有源图案、第三开关晶体管的有源图案、第五控制晶体管的有源图案和第七控制晶体管的有源图案与通孔在衬底上的投影存在间距，第一输出晶体管的有源图案与通孔在衬底上的投影存在间距，或者第一输出晶体管的有源图案与通孔对应设置，且与第一输出晶体管的有源图案对应设置通孔与遮光图案对应设置为例进行说明，但本申请实施例不限于此，例如可以使第一控制晶体管的有源图案、第三控制晶体管的有源图案、第一开关晶体管的有源图案、第三开关晶体管的有源图案、第五控制晶体管的有源图案、第七控制晶体管的有源图案和第一输出晶体管的有源图案中的一个或者多个或者所有都与通孔存在间距；或者使第一控制晶体管的有源图案、第三控制晶体管的有源图案、第一开关晶体管的有源图案、第三开关晶体管的有源图案、第五控制晶体管的有源图案、第七控制晶体管的有源图案和第一输出晶体管的有源图案中的一个或者多个或者所有都与通孔对应，且与遮光图案对应设置；或者使第一控制晶体管的有源图案、第三控制晶体管的有源图案、第一开关晶体管的有源图案、第三开关晶体管的有源图案、第五控制晶体管的有源图案、第七控制晶体管的有源图案和第一输出晶体管的有源图案中的一个或者多个与通孔存在间距；第一控制晶体管的有源图案、第三控制晶体管的有源图案、第一开关晶体管的有源图案、第三开关晶体管的有源图案、第五控制晶体管的有源图案、第七控制晶体管的有源图案和第一输出晶体管的有源图案中的一个或者多个与通孔对应，且与遮光图案对应设置。
具体的，考虑到第一输出晶体管的有源图案面积较大，难以避开通孔，因此，可以使第一输出晶体管的有源图案与通孔对应设置，且与第一输出晶体管的有源图案对应设置的通孔与遮光图案对应设置，通过遮光图案遮挡通孔漏出的光线，提高第一输出晶体管的性能稳定性，而其他氧化物半导体晶体管的有源图案面积较小，可以使通孔避开其他氧化物半导体晶体管的有源图案，从而提高氧化物半导体晶体管的稳定性。
具体的，如图6所示，图6中以第一控制晶体管T13的第二电极T13S连接第一低电位信号线NVGL、第二控制晶体管T12的第二电极T12S连接第二高电位信号线PVGH为例进行说明，但本申请实施例不限于此，第一控制晶体管T13的第二电极T13S可以连接第二低电位信号线PVGL。
具体的，如图6所示，第一控制晶体管T13的第一电极T13D和第二控制晶体管T12的第一电极T12D连接于第二节点O，第二控制晶体管T12的第二电极T12S连接第二高电位信号线PVGH。
具体的，图6中以初始信号线STV连接上一级内部节点P（n-1）为例进行说明，但本申请实施例不限于此，初始信号线可以连接上一级栅极驱动单元的第一信号输出端。
在一些实施例中，如图6所示，所述第一控制单元10还包括第九控制晶体管T2，第九控制晶体管T2的栅极T2G与第二时钟信号线XCK连接，第九控制晶体管T2的第一电极T2D连接于第一节点K，第九控制晶体管T2的第二电极T2S连接于第二节点O；所述栅极驱动单元120还包括：
第二输出单元40，包括第三输出晶体管T6、第四输出晶体管T7和第一电容C1，第三输出晶体管T6的栅极T6G连接于第三节点Q，第三输出晶体管T6的第一电极T6D与第四输出晶体管T7的第一电极T7D连接，且第三输出晶体管T6的第一电极T6D与第二信号输出端Pout（n）连接，第三输出晶体管T6的第二电极T6S与第一时钟信号线CK连接，第四输出晶体管T7的栅极T7G连接于本级内部节点P（n），第四输出晶体管T7的第二电极T7S连接第二高电位信号线PVGH，第一电容C1的第一极板C1a连接第三输出晶体管T6的栅极，第一电容C1的第二极板C1b连接第二信号输出端Pout（n）；
分频单元50，包括第一分频单元501和第二分频单元502，第一分频单元包括第一分频晶体管T16、第二分频晶体管T11和第二电容C2，第一分频晶体管T16的栅极T16G连接本级内部节点P（n），第一分频晶体管T16的第一电极T16D、第二电容C2的第一极板C2a和第二分频晶体管T11的栅极T11G连接，第一分频晶体管T16的第二电极T16S与第一分频信号线NLF连接，第二分频晶体管T11的第一电极T11D与第二电容C2的第二极板C2b连接于第四节点W，第二分频晶体管T11的第二电极T11S连接于第一节点K；第二分频单元502包括第三分频晶体管T20、第四分频晶体管T19和第三电容C3，第三分频晶体管T20的栅极T20G连接本级内部节点P（n），第三分频晶体管T20的第一电极T20D、第三电容C3的第一极板C3a和第四分频晶体管T19的栅极T19G连接，第三分频晶体管T20的第二电极T20S连接第二分频信号线PLF，第四分频晶体管T19的第一电极T19D与第三电容C3的第二极板C3b连接于第五节点M，第四分频晶体管T19的第二电极T19S连接于第一节点K；
重置单元70，包括重置晶体管T15，重置晶体管T15的栅极T15G连接控制信号线Control，重置晶体管T15的第一电极T15D连接第一节点K，重置晶体管T15的第二电极T15S连接高电位信号线PVGH；
开关单元90，包括第四开关晶体管T8，第四开关晶体管T8的栅极T8G连接开关信号线SC，开关信号线SC连接上两级内部节点P（n-2），第四开关晶体管T8的第一电极T8D连接于第三节点Q，第四开关晶体管T8的第二电极T8S连接于第五节点M。
具体的，第三输出晶体管T6和第四输出晶体管T7为硅半导体晶体管，第三输出晶体管T6和第四输出晶体管T7为P型晶体管。
具体的，第一分频晶体管T16和第二分频晶体管T11为硅半导体晶体管，第一分频晶体管T16和第二分频晶体管T11为P型晶体管。
具体的，第三分频晶体管T20和第四分频晶体管T19为硅半导体晶体管，第三分频晶体管T20和第四分频晶体管T19为P型晶体管。
具体的，重置晶体管T15为硅半导体晶体管，重置晶体管T15为P型晶体管。
具体的，第四开关晶体管T8为硅半导体晶体管，第四开关晶体管T8为P型晶体管。
在一些实施例中，如图5所示，所述显示面板2还包括：
硅半导体层205，设置于所述衬底201与所述氧化物半导体层211之间；
第一金属层207，设置于所述硅半导体层205与所述氧化物半导体层211之间；
第二金属层209，设置于所述第一金属层207与所述氧化物半导体层211之间；
第三金属层213，设置于所述氧化物半导体层211与所述第一源漏极层215之间。
在一些实施例中，如图5、图10中的（a）所示，所述硅半导体层205包括第九控制晶体管T2的有源图案T2A、第四控制晶体管T3的有源图案T3A、第二开关晶体管T5的有源图案T5A、第三输出晶体管T6的有源图案T6A、第四输出晶体管T7的有源图案T7A、第四开关晶体管T8的有源图案T8A、第二输出晶体管T9的有源图案T9A、第二分频晶体管T11的有源图案T11A、第二控制晶体管T12的有源图案T12A、重置晶体管T15的有源图案T15A、第一分频晶体管T16的有源图案T16A、第六控制晶体管T18的有源图案T18A、第四分频晶体管T19的有源图案T19A、第三分频晶体管T20的有源图案T20A和第八控制晶体管T22的有源图案T22A。
在一些实施例中，如图5、图10中的（b）所示，第一金属层207包括第九控制晶体管T2的栅极T2G、第四控制晶体管T3的栅极T3G、第二开关晶体管T5的栅极T5G、第三输出晶体管T6的栅极T6G、第四输出晶体管T7的栅极T7G、第四开关晶体管T8的栅极T8G、第二输出晶体管T9的栅极T9G、第二分频晶体管T11的栅极T11G、第二控制晶体管T12的栅极T12G、重置晶体管T15的栅极T15G、第一分频晶体管T16的栅极T16G、第六控制晶体管T18的栅极T18G、第四分频晶体管T19的栅极T19G、第三分频晶体管T20的栅极T20G、第八控制晶体管T22的栅极T22G、第一电容C1的第一极板C1a、第二电容C2的第一极板C2a、第三电容C3的第一极板C3a和第一连接线L1，第一连接线L1与第一信号输出端Nout（n）连接。
在一些实施例中，如图5、图11中的（a）所示，第二金属层209包括第三控制晶体管T1的第一栅极T1Ga、第一开关晶体管T4的第一栅极T4Ga、第一输出晶体管T10的第一栅极T10Ga、第一控制晶体管T13的第一栅极T13Ga、第三开关晶体管T14的第一栅极T4Ga、第五控制晶体管T17的第一栅极T17Ga、第七控制晶体管T21的第一栅极T21Ga、第一电容C1的第二极板C1b、第二电容C2的第二极板C2b和第三电容C3的第二极板C3b。通过使第三金属层形成各氧化物半导体晶体管的第一栅极，可以对各氧化物半导体晶体管的有源图案进行遮光，且可以提高各氧化物半导体晶体管的栅控能力。
在一些实施例中，如图5、图11中的（b）所示，所述氧化物半导体层211包括第一控制晶体管T13的有源图案T13A、第一输出晶体管T10的有源图案T10A、第三控制晶体管T1的有源图案T1A、第一开关晶体管T4的有源图案T4A、第三开关晶体管T14的有源图案T14A、第五控制晶体管T17的有源图案T17A和第七控制晶体管T21的有源图案T21A，沿远离所述显示部21的方向，所述第七控制晶体管T21的有源图案T21A、第一开关晶体管T4的有源图案T4A、所述第五控制晶体管T17的有源图案T17A、所述第三开关晶体管T14的有源图案T14A、所述第三控制晶体管T1的有源图案T1A、所述第一控制晶体管T13的有源图案T13A和所述第一输出晶体管T10的有源图案T10A依次设置。通过使第七控制晶体管的有源图案、第一开关晶体管的有源图案、第五控制晶体管的有源图案、第三开关晶体管的有源图案、第三控制晶体管的有源图案、第一控制晶体管的有源图案和第一输出晶体管的有源图案沿远离显示部的方向设置，可以使更多的氧化物半导体晶体管被连接走线遮挡，从而避免连接走线无法遮挡氧化物半导体晶体管导致氧化物半导体晶体管的性能变化。
具体的，相较于当前显示器件中，部分氧化物半导体晶体管的有源图案在衬底上的投影与连接走线在衬底上的投影不重合，本申请实施例可以将所有氧化物半导体晶体管的有源图案远离显示部设置，使得氧化物半导体晶体管的有源图案位于连接走线对应区域，通过连接走线对氧化物半导体晶体管的有源图案进行遮光。
在一些实施例中，如图5、图12中的（a）所示，第三金属层213包括第三控制晶体管T1的第二栅极T1Gb、第一开关晶体管T4的第二栅极T4Gb、第一输出晶体管T10的第二栅极T10Gb、第一控制晶体管T13的第二栅极T13Gb、第三开关晶体管T14的第二栅极T14Gb、第五控制晶体管T17的第二栅极T17Gb、第七控制晶体管T21的第二栅极T21Gb和上两级内部节点P（n-2）。在改变氧化物半导体晶体管的有源图案时，可以相应的改变其栅极的设置位置，通过双栅设计提高氧化物半导体晶体管的栅控能力。
在一些实施例中，如图5、图12中的（b）所示，第一源漏极层215包括第九控制晶体管T2的第一电极T2D和第二电极T2S、第四控制晶体管T3的第一电极T3D和第二电极T3S、第二开关晶体管T5的第一电极T5D和第二电极T5S、第三输出晶体管T6的第一电极T6D和第二电极T6S、第四输出晶体管T7的第一电极T7D和第二电极T7S、第四开关晶体管T8的第一电极T8D和第二电极T8S、第二输出晶体管T9的第一电极T9D和第二电极T9S、第二分频晶体管T11的第一电极T11D和第二电极T11S、第二控制晶体管T12的第一电极T12D和第二电极T12S、重置晶体管T15的第一电极T15D和第二电极T15S、第一分频晶体管T16的第一电极T16D和第二电极T16S、第六控制晶体管T18的第一电极T18D和第二电极T18S、第四分频晶体管T19的第一电极T19D和第二电极T19S、第三分频晶体管T20的第一电极T20D和第二电极T20S、第八控制晶体管T22的第一电极T22D和第二电极T22S、第三控制晶体管T1的第一电极T1D和第二电极T1S、第一开关晶体管T4的第一电极T4D和第二电极T4S、第一输出晶体管T10的第一电极T10D和第二电极T10S、第一控制晶体管T13的第一电极T13D和第二电极T13S、第三开关晶体管T14的第一电极T14D和第二电极T14S、第五控制晶体管T17的第一电极T17D和第二电极T17S、第七控制晶体管T21的第一电极T21D和第二电极T21S、第二连接线L2、第三连接线L3、第一信号输出端Nout（n）和第二信号输出端Pout（n）。
在一些实施例中，如图5、图13中的（a）所示，第二源漏极层217包括第一低电位信号线NVGL的第一部分NVGL-1、第一高电位信号线NVGH的第一部分NVGH-1、第二低电位信号线PVGL、第二高电位信号线PVGH的第一部分PVGH-1、第一分频信号线NLF、初始信号线STV、控制信号线Control、第二分频信号线PLF、第一条时钟信号线PCK1的第一部分PCK1a、第二条时钟信号线PCK2的第一部分PCK2a、第三条时钟信号线PCK3的第一部分PCK3a和第四条时钟信号线PCK4的第一部分PCK4a。
在一些实施例中，如图5、图13中的（b）所示，所述第三源漏极层219包括第一低电位信号线NVGL的第二部分NVGL-2、第一高电位信号线NVGH的第二部分NVGH-2、第二高电位信号线PVGH的第二部分PVGH-2、第一条时钟信号线PCK1的第二部分PCK1b、第二条时钟信号线PCK2的第二部分PCK2b、第三条时钟信号线PCK3的第二部分PCK3b和第四条时钟信号线PCK4的第二部分PCK4b，所述第一低电位信号线NVGL的第二部分NVGL-2与所述第一低电位信号线NVGL的第一部分NVGL-1连接，所述第一高电位信号线NVGH的第二部分NVGH-2与所述第一高电位信号线NVGH的第一部分NVGH-1连接，所述第二高电位信号线PVGH的第二部分PVGH-2与所述第二高电位信号线PVGH的第一部分PVGH-1连接，所述第一条时钟信号线PCK1的第二部分PCK1b与所述第一条时钟信号线PCK1的第一部分PCK1a连接，所述第二条时钟信号线PCK2的第二部分PCK2b与所述第二条时钟信号线PCK2的第一部分PCK2a连接，所述第三条时钟信号线PCK3的第二部分PCK3b与所述第三条时钟信号线PCK3的第一部分PCK3a连接，所述第四条时钟信号线PCK4的第二部分PCK4b与所述第四条时钟信号线PCK4的第一部分PCK4a连接。
在一些实施例中，所述第一低电位信号线NVGL和所述第一高电位信号线NVGH包括所述遮光图案223a。但本申请实施例不限于此，可以使时钟信号线包括遮光图案。
在一些实施例中，如图5、图14所示，像素电极层221包括连接走线221a，连接走线221a包括通孔221b。
在一些实施例中，如图16中的（a）所示，图16中的（a）示出了第一过孔421的设置位置，第一过孔421是指从第一源漏极层刻蚀至第一有源层、第一金属层和第二金属层的过孔。
在一些实施例中，如图16中的（b）所示，图16中的（b）示出了第二过孔422的设置位置，第二过孔422是指从第一源漏极层刻蚀至第二有源层和第三金属层的过孔。
在一些实施例中，如图17中的（a）所示，图17中的（a）示出了第三过孔423的设置位置，第三过孔423是指从第二源漏极层刻蚀至第一源漏极层的过孔。
在一些实施例中，如图17中的（b）所示，图17中的（b）示出了第四过孔424的设置位置，第四过孔424是指从第三源漏极层刻蚀至第二源漏极层的过孔。
具体的，可以使第一低电位信号线的第一部分和第二部分对应设置，第一低电位信号线与通孔对应设置，第一高电位信号线的第一部分和第二部分对应设置，且第一高电位信号线与通孔对应设置，则可以将第一低电位信号线和第二高电位信号线作为遮光图案，从而对氧化物半导体晶体管进行遮光，且无需增加走线或者其他结构。
在一些实施例中，如图11中的（b）所示，所述第一输出晶体管T10的有源图案T10A包括第一子有源图案T10Aa和第二子有源图案T10Ab，所述第一子有源图案T10Aa和所述第二子有源图案T10Ab间隔设置。通过使第一输出晶体管的有源图案包括第一子有源图案和第二子有源图案，可以防止第一输出晶体管的有源图案自热导致性能发生变化，提高显示面板的第一输出晶体管的性能。
在一些实施例中，如图10中的（a）所示，所述第二输出晶体管T9的有源图案T9A包括第三子有源图案T9Aa和第四子有源图案T9Ab，第三子有源图案T9Aa和第四子有源图案T9Ab间隔设置。通过使第二输出晶体管的有源图案包括第三子有源图案和第四子有源图案，可以防止第二输出晶体管的有源图案自热导致性能发生变化，提高显示面板的第二输出晶体管的性能。
在一些实施例中，如图7所示，在氧化物半导体晶体管在衬底201上的投影与通孔221b在衬底201上的投影存在间距时，氧化物半导体晶体管在衬底201上的投影与通孔221b在衬底上的投影的间距H1大于5微米，从而进一步避免光线照射至氧化物半导体晶体管的有源图案上，提高氧化物半导体晶体管的性能稳定性。
在一些实施例中，如图8所示，在氧化物半导体晶体管的有源图案与所述通孔221b对应设置，且与氧化物半导体晶体管对应设置的通孔221b与所述遮光图案223a对应设置时，可以使遮光图案223a的边界与通孔221b的边界的间距H2大于5微米，从而进一步避免光线照射至氧化物半导体晶体管的有源图案上，提高氧化物半导体晶体管的性能稳定性。
具体的，显示面板还包括公共电极层，第三源漏极层还包括转接线，所述连接走线连接公共电极层与所述转接线。
具体的，如图4所示，显示面板2包括显示区AA和非显示区NA，显示部21设置于显示区AA，栅极驱动电路22设置于非显示区NA。
具体的，如图4所示，显示面板2还包括端子部23。
具体的，如图5所示，显示面板2包括衬底201、屏蔽层202、阻隔层203、缓冲层204、硅半导体层205、第一栅极绝缘层206、第一金属层207、第二栅极绝缘层208、第二金属层209、第三栅极绝缘层210、氧化物半导体层211、第四栅极绝缘层212、第三金属层213、第一层间绝缘层214、第一源漏极层215、第一平坦化层216、第二源漏极层217、第二平坦化层218、第三源漏极层219、第三平坦化层220、像素电极层221和像素定义层222，屏蔽层202设置于衬底201一侧，阻隔层203设置于屏蔽层202远离衬底201的一侧，缓冲层204设置于阻隔层203远离屏蔽层202的一侧，第一栅极绝缘层206设置于硅半导体层205和第一金属层207之间，第二栅极绝缘层208设置于第一金属层207和第二金属层209之间，第三栅极绝缘层210设置于第二金属层209和氧化物半导体层211之间，第四栅极绝缘层212设置于氧化物半导体层211和第三金属层213之间，第一层间绝缘层214设置于第三金属层213和第一源漏极层215之间，第一平坦化层216设置于第一源漏极层215和第二源漏极层217之间，第二平坦化层218设置于第二源漏极层217和第三源漏极层219之间，第三平坦化层220设置于第三源漏极层219和像素电极层221之间。
具体的，图5中像素电极层221仅示出了像素电极221c，因此，采用两个标号标示了同一结构，可以理解的是，像素电极层可以包括其他结构。像素电极设置于显示区，连接走线设置在栅极驱动电路对应的区域，像素电极与连接走线绝缘设置。
在一些实施例中，上述实施例中的晶体管的第一电极为源极、第二电极为漏极；或者上述实施例中的晶体管的第一电极为漏极、第二电极为源极。
具体的，氧化物半导体晶体管可以为金属氧化物晶体管，硅半导体晶体管可以为低温多晶硅晶体管。
在一些实施例中，硅半导体层的材料包括低温多晶硅，氧化物半导体层的材料包括金属氧化物，具体可以为氧化铟镓锌。
具体的，上述实施例分别从各个电路、各个膜层、各个结构以及其结合对显示面板进行了具体说明，可以理解的是，在各实施例不存在冲突时，可以使各实施例结合，例如，第三金属层包括第三控制晶体管的第二栅极、第一开关晶体管的第二栅极、第一输出晶体管的第二栅极、第一控制晶体管的第二栅极、第三开关晶体管的第二栅极、第五控制晶体管的第二栅极、第七控制晶体管的第二栅极和上两级内部节点，所述第一输出晶体管的有源图案包括第一子有源图案和第二子有源图案，所述第一子有源图案和所述第二子有源图案间隔设置。
同时，本申请实施例提供一种显示装置，该显示装置包括如上述实施例任一所述的显示面板。
根据上述实施例可知：
本申请实施例提供一种显示面板，该显示面板包括显示部和位于显示部的至少一侧的栅极驱动电路，栅极驱动电路包括多个级联的栅极驱动单元，栅极驱动单元包括多个氧化物半导体晶体管，显示面板包括衬底、氧化物半导体层、源漏极层和像素电极层，氧化物半导体层设置于衬底一侧，氧化物半导体层包括氧化物半导体晶体管的有源图案，源漏极层设置于氧化物半导体层远离衬底的一侧，源漏极层包括用于形成源漏极的金属图案和形成在非显示区的遮光图案，像素电极层设置于源漏极层远离氧化物半导体层的一侧，像素电极层包括用于形成像素电极的导电图案和形成在非显示区的连接走线，连接走线上设有通孔，其中，至少一级栅极驱动单元中的氧化物半导体晶体管的有源图案被连接走线、遮光图案中的一者或者多者完全覆盖。本申请通过改变连接走线上的通孔与氧化物半导体晶体管的有源图案的相对位置，通过使源漏极层包括遮光图案，使得氧化物半导体晶体管的有源图案被连接走线、遮光图案中的一者或者多者完全覆盖，从而可以防止外界光线照射到氧化物半导体晶体管的有源图案，实现了对氧化物半导体晶体管的遮光，提高了氧化物半导体晶体管的性能稳定性。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种显示面板，其包括显示部和位于所述显示部的至少一侧的栅极驱动电路，所述栅极驱动电路包括多个级联的栅极驱动单元，所述栅极驱动单元包括多个氧化物半导体晶体管，所述显示面板包括：
    衬底；
    氧化物半导体层，设置于所述衬底一侧，所述氧化物半导体层包括所述氧化物半导体晶体管的有源图案；
    源漏极层，设置于所述氧化物半导体层远离所述衬底的一侧，所述源漏极层包括用于形成源漏极的金属图案和形成在非显示区的遮光图案；
    像素电极层，设置于所述源漏极层远离所述氧化物半导体层的一侧，所述像素电极层包括用于形成像素电极的导电图案和形成在非显示区的连接走线，所述连接走线上设有通孔；
    其中，至少一级所述栅极驱动单元中的所述氧化物半导体晶体管的有源图案被所述连接走线、所述遮光图案中的一者或者多者完全覆盖。
  2. 如权利要求1所述的显示面板，其中，至少一级所述栅极驱动单元中的所述氧化物半导体晶体管的有源图案被所述连接走线完全覆盖。
  3. 如权利要求1所述的显示面板，其中，至少一级所述栅极驱动单元中的所述氧化物半导体晶体管的有源图案被所述遮光图案完全覆盖。
  4. 如权利要求1所述的显示面板，其中，至少一级栅极驱动单元中的部分氧化物半导体晶体管的有源图案被所述连接走线覆盖，部分所述氧化物半导体晶体管的有源图案被所述遮光图案覆盖。
  5. 如权利要求1所述的显示面板，其中，所述源漏极层包括第一源漏极层、第二源漏极层和第三源漏极层，所述第二源漏极层设置于所述第一源漏极层远离所述氧化物半导体层的一侧，所述第三源漏极层设置于所述第二源漏极层远离所述第一源漏极层的一侧，所述第一源漏极层、所述第二源漏极层和所述第三源漏极层中的至少一个包括所述遮光图案。
  6. 如权利要求5所述的显示面板，其中，所述栅极驱动单元包括：
    第一控制单元，包括第一控制晶体管和第二控制晶体管，所述第一控制晶体管为氧化物半导体晶体管、所述第二控制晶体管为硅半导体晶体管，所述第一控制晶体管的栅极和所述第二控制晶体管的栅极与初始信号线连接，所述第一控制晶体管的第一电极和所述第二控制晶体管的第一电极电连接于第一节点；
    第一输出单元，包括第一输出晶体管、第二输出晶体管、第一低电位信号线和第一高电位信号线，所述第一输出晶体管为氧化物半导体晶体管、所述第二输出晶体管为硅半导体晶体管，所述第一输出晶体管的栅极与所述第二输出晶体管的栅极电连接于所述第一节点，所述第一输出晶体管的第一电极与所述第二输出晶体管的第一电极连接，且所述第一输出晶体管的第一电极与第一信号输出端连接，所述第一输出晶体管的第二电极连接第一低电位信号线，所述第二输出晶体管的第二电极连接第一高电位信号线；
    第二控制单元，包括第三控制晶体管、第四控制晶体管、第二低电位信号线和第二高电位信号线，所述第三控制晶体管为氧化物半导体晶体管、所述第四控制晶体管为硅半导体晶体管，所述第三控制晶体管的栅极和所述第四控制晶体管的栅极连接于所述第一节点，所述第三控制晶体管的第一电极与所述第四控制晶体管的第一电极连接于本级内部节点，所述第三控制晶体管的第二电极连接第二低电位信号线，所述第四控制晶体管的第二电极连接第二高电位信号线；
    输出控制单元，包括第一开关晶体管、第二开关晶体管和第三开关晶体管，所述第一开关晶体管和所述第三开关晶体管为氧化物半导体晶体管，所述第二开关晶体管为硅半导体晶体管，所述第一开关晶体管的第一电极与所述第二开关晶体管的第一电极连接，所述第一开关晶体管的第二电极连接于所述第一节点，所述第二开关晶体管的栅极与所述第三开关晶体管的栅极连接所述第三控制晶体管的第一电极，所述第三开关晶体管的第一电极连接于所述第一节点；
    第三控制单元，包括第五控制晶体管和第六控制晶体管，所述第五控制晶体管为氧化物半导体晶体管，所述第六控制晶体管为硅半导体晶体管，所述第五控制晶体管的第一电极和所述第六控制晶体管的第一电极连接，所述第五控制晶体管的第二电极电连接于所述第一节点，所述六控制晶体管的栅极与所述第三开关晶体管的栅极连接；
    第四控制单元，包括第七控制晶体管和第八控制晶体管，所述第七控制晶体管为氧化物半导体晶体管，所述第八控制晶体管为硅半导体晶体管，所述第七控制晶体管的和所述第八控制晶体管的第一电极连接，所述第七控制晶体管的第二电极电连接于所述第一节点，所述第八控制晶体管的栅极与所述第三开关晶体管的栅极连接；
    其中，所述第一控制晶体管的有源图案、所述第三控制晶体管的有源图案、所述第一开关晶体管的有源图案、所述第三开关晶体管的有源图案、所述第五控制晶体管的有源图案和所述第七控制晶体管的有源图案被所述连接走线覆盖；
    所述第一输出晶体管的有源图案被所述连接走线覆盖；或者所述第一输出晶体管的有源图案被所述遮光图案覆盖。
  7. 如权利要求6所述的显示面板，其中，所述第一控制单元还包括第九控制晶体管，第九控制晶体管的第一电极连接于第一节点，第九控制晶体管的第二电极连接于第二节点；所述栅极驱动单元还包括：
    第二输出单元，包括第三输出晶体管、第四输出晶体管和第一电容，第三输出晶体管的栅极连接于第三节点，第三输出晶体管的第一电极与第四输出晶体管的第一电极连接，且第三输出晶体管的第一电极与第二信号输出端连接，第三输出晶体管的第二电极与第一时钟信号线连接，第四输出晶体管的栅极连接于本级内部节点，第四输出晶体管的第二电极连接第二高电位信号线，第一电容的第一极板连接第三输出晶体管的栅极，第一电容的第二极板连接第二信号输出端；
    分频单元，包括第一分频单元和第二分频单元，第一分频单元包括第一分频晶体管、第二分频晶体管和第二电容，第一分频晶体管的栅极连接本级内部节点，第一分频晶体管的第一电极、第二电容的第一极板和第二分频晶体管的栅极连接，第一分频晶体管的第二电极与第一分频信号线连接，第二分频晶体管的第一电极与第二电容的第二极板连接于第四节点，第二分频晶体管的第二电极连接于第一节点；第二分频单元包括第三分频晶体管、第四分频晶体管和第三电容，第三分频晶体管的栅极连接本级内部节点，第三分频晶体管的第一电极、第三电容的第一极板和第四分频晶体管的栅极连接，第三分频晶体管的第二电极连接第二分频信号线，第四分频晶体管的第一电极与第三电容的第二极板连接于第五节点，第四分频晶体管的第二电极连接于第一节点；
    重置单元，包括重置晶体管，重置晶体管的栅极连接控制信号线，重置晶体管的第一电极连接第一节点，重置晶体管的第二电极连接高电位信号线；
    开关单元，包括第四开关晶体管，第四开关晶体管的栅极连接开关信号线，开关信号线连接上两级内部节点，第四开关晶体管的第一电极连接于第三节点，第四开关晶体管的第二电极连接于第五节点。
  8. 如权利要求7所述的显示面板，其中，所述显示面板还包括：
    硅半导体层，设置于所述衬底与所述氧化物半导体层之间；
    第一金属层，设置于所述硅半导体层与所述氧化物半导体层之间；
    第二金属层，设置于所述第一金属层与所述氧化物半导体层之间；
    第三金属层，设置于所述氧化物半导体层与所述第一源漏极层之间。
  9. 如权利要求8所述的显示面板，其中，所述硅半导体层包括第九控制晶体管的有源图案、第四控制晶体管的有源图案、第二开关晶体管的有源图案、第三输出晶体管的有源图案、第四输出晶体管的有源图案、第四开关晶体管的有源图案、第二输出晶体管的有源图案、第二分频晶体管的有源图案、第二控制晶体管的有源图案、重置晶体管的有源图案、第一分频晶体管的有源图案、第六控制晶体管的有源图案、第四分频晶体管的有源图案、第三分频晶体管的有源图案和第八控制晶体管的有源图案。
  10. 如权利要求9所述的显示面板，其中，第一金属层包括第九控制晶体管的栅极、第四控制晶体管的栅极、第二开关晶体管的栅极、第三输出晶体管的栅极、第四输出晶体管的栅极、第四开关晶体管的栅极、第二输出晶体管的栅极、第二分频晶体管的栅极、第二控制晶体管的栅极、重置晶体管的栅极、第一分频晶体管的栅极、第六控制晶体管的栅极、第四分频晶体管的栅极、第三分频晶体管的栅极、第八控制晶体管的栅极、第一电容的第一极板、第二电容的第一极板、第三电容的第一极板和第一连接线，所述第一连接线与第一信号输出端连接。
  11. 如权利要求10所述的显示面板，其中，所述第二金属层包括第三控制晶体管的第一栅极、第一开关晶体管的第一栅极、第一输出晶体管的第一栅极、第一控制晶体管的第一栅极、第三开关晶体管的第一栅极、第五控制晶体管的第一栅极、第七控制晶体管的第一栅极、第一电容的第二极板、第二电容的第二极板和第三电容的第二极板。
  12. 如权利要求11所述的显示面板，其中，所述氧化物半导体层包括第一控制晶体管的有源图案、第一输出晶体管的有源图案、第三控制晶体管的有源图案、第一开关晶体管的有源图案、第三开关晶体管的有源图案和第五控制晶体管的有源图案，沿远离所述显示部的方向，所述第七控制晶体管的有源图案、第一开关晶体管的有源图案、所述第五控制晶体管的有源图案、所述第三开关晶体管的有源图案、所述第三控制晶体管的有源图案、所述第一控制晶体管的有源图案和所述第一输出晶体管的有源图案依次设置。
  13. 如权利要求12所述的显示面板，其中，第三金属层包括第三控制晶体管的第二栅极、第一开关晶体管的第二栅极、第一输出晶体管的第二栅极、第一控制晶体管的第二栅极、第三开关晶体管的第二栅极、第五控制晶体管的第二栅极、第七控制晶体管的第二栅极和上两级内部节点。
  14. 如权利要求13所述的显示面板，其中，所述第一源漏极层包括第九控制晶体管的第一电极和第二电极、第四控制晶体管的第一电极和第二电极、第二开关晶体管的第一电极和第二电极、第三输出晶体管的第一电极和第二电极、第四输出晶体管的第一电极和第二电极、第四开关晶体管的第一电极和第二电极、第二输出晶体管的第一电极和第二电极、第二分频晶体管的第一电极和第二电极、第二控制晶体管的第一电极和第二电极、重置晶体管的第一电极和第二电极、第一分频晶体管的第一电极和第二电极、第六控制晶体管的第一电极和第二电极、第四分频晶体管的第一电极和第二电极、第三分频晶体管的第一电极和第二电极、第八控制晶体管的第一电极和第二电极、第三控制晶体管的第一电极和第二电极、第一开关晶体管的第一电极和第二电极、第一输出晶体管的第一电极和第二电极、第一控制晶体管的第一电极和第二电极、第三开关晶体管的第一电极和第二电极、第五控制晶体管的第一电极和第二电极、第七控制晶体管的第一电极和第二电极、第二连接线、第三连接线、第一信号输出端和第二信号输出端。
  15. 如权利要求14所述的显示面板，其中，所述第二源漏极层包括第一低电位信号线的第一部分、第一高电位信号线的第一部分、第二低电位信号线、第二高电位信号线的第一部分、第一分频信号线、初始信号线、控制信号线、第二分频信号线、第一条时钟信号线的第一部分、第二条时钟信号线的第一部分、第三条时钟信号线的第一部分和第四条时钟信号线的第一部分。
  16. 如权利要求15所述的显示面板，其中，所述第三源漏极层包括第一低电位信号线的第二部分、第一高电位信号线的第二部分、第二高电位信号线的第二部分、第一条时钟信号线的第二部分、第二条时钟信号线的第二部分、第三条时钟信号线的第二部分和第四条时钟信号线的第二部分，所述第一低电位信号线的第二部分与所述第一低电位信号线的第一部分连接，所述第一高电位信号线的第二部分与所述第一高电位信号线的第一部分连接，所述第二高电位信号线的第二部分与所述第二高电位信号线的第一部分连接，所述第一条时钟信号线的第二部分与所述第一条时钟信号线的第一部分连接，所述第二条时钟信号线的第二部分与所述第二条时钟信号线的第一部分连接，所述第三条时钟信号线的第二部分与所述第三条时钟信号线的第一部分连接，所述第四条时钟信号线的第二部分与所述第四条时钟信号线的第一部分连接。
  17. 如权利要求16所述的显示面板，其中，所述第一低电位信号线和所述第一高电位信号线包括所述遮光图案。
  18. 如权利要求12所述的显示面板，其中，所述第一输出晶体管的有源图案包括第一子有源图案和第二子有源图案，所述第一子有源图案和所述第二子有源图案间隔设置。
  19. 如权利要求1所述的显示面板，其中，任一所述氧化物半导体晶体管的有源图案在所述衬底上的投影与所述通孔在所述衬底上的投影存在间距。
  20. 如权利要求1所述的显示面板，其中，部分所述氧化物半导体晶体管的有源图案在所述衬底上的投影与所述通孔在所述衬底上的投影存在间距，部分所述氧化物半导体晶体管的有源图案与所述通孔对应设置，与所述氧化物半导体晶体管对应设置的所述通孔与所述遮光图案对应设置。
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CN114175257A (zh) * 2021-02-10 2022-03-11 京东方科技集团股份有限公司 阵列基板及其显示面板和显示装置
CN117637760A (zh) * 2022-08-31 2024-03-01 乐金显示有限公司 包括氧化物半导体图案的薄膜晶体管阵列基板及包括其的显示设备
CN116153941A (zh) * 2022-12-28 2023-05-23 深圳市华星光电半导体显示技术有限公司 显示面板及其制作方法、显示装置

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