WO2025227993A1 - 内存分配方法、计算机设备、存储介质及产品 - Google Patents

内存分配方法、计算机设备、存储介质及产品

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Publication number
WO2025227993A1
WO2025227993A1 PCT/CN2025/084161 CN2025084161W WO2025227993A1 WO 2025227993 A1 WO2025227993 A1 WO 2025227993A1 CN 2025084161 W CN2025084161 W CN 2025084161W WO 2025227993 A1 WO2025227993 A1 WO 2025227993A1
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Prior art keywords
memory
cxl
allocation
function
region
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PCT/CN2025/084161
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English (en)
French (fr)
Inventor
李强
张海军
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Suzhou Metabrain Intelligent Technology Co Ltd
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Suzhou Metabrain Intelligent Technology Co Ltd
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Publication of WO2025227993A1 publication Critical patent/WO2025227993A1/zh
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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/50Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00Arrangements for software engineering
    • G06F8/70Software maintenance or management
    • G06F8/72Code refactoring

Definitions

  • This application relates to the field of memory management technology, specifically to memory allocation methods, computer devices, storage media, and products.
  • CXL Computer Express Link
  • CXL memory can expand memory capacity and increase memory resource access bandwidth compared to traditional local memory, but CXL memory has higher latency.
  • this application provides a memory allocation method, computer device, storage medium, and product to solve the problem of performance instability that may occur when allocating memory.
  • this application provides a memory allocation method, including:
  • the CXL memory identifier is passed to the kernel space through the memory mapping interface, and hardware resources related to the CXL memory are allocated in the kernel space.
  • a dedicated application programming interface (API) for allocating CXL memory including:
  • the function names of the standard application programming interface are modified, and the modified function names are used as function names in the dedicated API; the standard API is used for memory allocation.
  • a dedicated application programming interface is defined for allocating CXL memory, and further includes:
  • a first function for obtaining the total amount of the requested CXL memory region a second function for obtaining the total amount of the CXL memory region allocated by the client development kit, a third function for obtaining the number of available bytes in a specified CXL memory region, a fourth function for obtaining the total amount of the CXL memory region in a specified memory node, a fifth function for obtaining the number of available bytes in the CXL memory region in a specified memory node, a sixth function for obtaining the status data of multiple CXL memory regions, and a seventh function for obtaining the status data of the corresponding CXL memory regions under multiple memory nodes.
  • the method further includes:
  • the first memory allocation pool is selected
  • the memory space in the first memory allocation pool is allocated to allocate user-mode CXL memory.
  • the allocation of memory space in the first memory allocation pool according to the invocation request includes:
  • a user-mode memory mapping flag is added to the memory allocation function, and the memory mapping flag is assigned a value according to the CXL memory identifier; the memory mapping flag is used to indicate whether CXL memory is allocated;
  • the memory space in the first memory allocation pool is allocated according to the memory allocation function.
  • a user-mode memory mapping flag is added to the memory allocation function, including:
  • the method further includes:
  • a default function is provided for setting memory mapping flags
  • a setting function is called to set the memory mapping flags of the new memory allocation pool to the default value; the default value indicates that local memory is allocated.
  • the memory mapping flags are assigned values based on the CXL memory identifier, including:
  • the CXL memory identifier is passed to kernel mode via a memory mapping interface, including:
  • the function used to obtain the memory mapping flag is called to obtain the memory mapping flag
  • the memory mapping flag is passed as a parameter according to the memory mapping flag passing function, including:
  • the local variable is passed parameters according to the memory mapping flag passing function.
  • dividing a first memory allocation pool for allocating CXL memory in user mode and a second memory allocation pool for allocating local memory in user mode includes:
  • Multiple memory allocation pools are allocated for each core of the processor, with a portion of the memory allocation pool serving as the first memory allocation pool for allocating CXL memory in user mode, and another portion serving as the second memory allocation pool for allocating local memory in user mode.
  • hardware resources associated with CXL memory are allocated in kernel mode, including:
  • the memory space in the CXL memory allocation area is allocated according to the call request in order to allocate hardware resources related to CXL memory.
  • a CXL memory allocation area is partitioned for independently managing kernel space CXL memory, including:
  • the partitioning of a CXL memory allocation area for independently managing kernel space CXL memory further includes:
  • the sub-memory region structure includes memory region data, memory start address, and memory end address; among them, the memory region data is generated compatiblely based on the existing memory allocation area.
  • the partitioning of a CXL memory allocation area for independently managing kernel space CXL memory further includes:
  • the sub-memory region index structure includes a pointer to the corresponding sub-memory region, as well as the index identifier of the sub-memory region in the sub-memory region list.
  • the partitioning of a CXL memory allocation area for independently managing kernel space CXL memory further includes:
  • the new variables include: free sub-memory region queue structure, sub-memory region list, number of sub-memory regions, and index identifier of the currently allocated sub-memory region.
  • the allocation of memory space in the CXL memory allocation area according to the call request includes:
  • the method further includes:
  • CXL memory configuration options are encapsulated in macro definitions and selectively enabled in kernel configuration;
  • CXL memory configuration options include at least one of the following: modified operating system kernel code, newly added functions, and variables.
  • this application provides a computer device, including: a memory and a processor, which are communicatively connected to each other.
  • the memory stores computer instructions
  • the processor executes the computer instructions to perform the memory allocation method of the first aspect or any corresponding embodiment described above.
  • this application provides a computer non-transitory readable storage medium storing computer instructions, which are used to cause a computer to execute the memory allocation method of the first aspect or any corresponding embodiment described above.
  • this application provides a computer program product, including computer instructions for causing a computer to execute the memory allocation method described in the first aspect or any corresponding embodiment thereof.
  • This application defines a dedicated API (Application Programming Interface) for allocating CXL memory. Users can allocate CXL memory by calling the dedicated API, without allocating local memory to the user, thus ensuring stable use of CXL memory. Furthermore, by defining a dedicated API, users only need to modify the API they call when they need to allocate CXL memory, resulting in minimal code modifications on the user side and reducing the manpower costs associated with code modifications.
  • a dedicated API Application Programming Interface
  • Figure 1 is a flowchart illustrating a memory allocation method according to an embodiment of this application
  • FIG. 2 is a flowchart illustrating another memory allocation method according to an embodiment of this application.
  • Figure 3 is a schematic diagram of the memory allocation process by selecting a memory allocation pool according to an embodiment of this application;
  • Figure 4 is a schematic diagram of the process of passing a memory mapping flag to the kernel according to an embodiment of this application;
  • Figure 5 is a flowchart illustrating another memory allocation method according to an embodiment of this application.
  • Figure 6 is a hierarchical logical memory view of the operating system kernel according to an embodiment of this application.
  • Figure 7 is a schematic diagram of the overall process of memory allocation according to an embodiment of this application.
  • Figure 8 is a structural block diagram of a memory allocation device according to an embodiment of the present application.
  • Figure 9 is a schematic diagram of the hardware structure of a computer device according to an embodiment of this application.
  • CXL Computer Express Link
  • CPU-coherent Load/Store cache-coherent memory access semantics
  • GPUs Graphics Processing Units
  • smart network interface cards achieving decoupling and pooling of computing and memory resources.
  • CXL provides high-speed interconnect technology at hundreds of nanoseconds.
  • the Type 3 device defined by the CXL protocol is the CXL memory module or CXL memory allocation pool, i.e., CXL memory. This device can expand memory capacity and improve memory resource access bandwidth. Simultaneously, CXL memory modules do not occupy memory slots on the server.
  • CXL memory mainly comes in three forms: E3.S form factor memory modules, ASIC (Application Specific Integrated Circuit) memory cards, and JBOM (memory box).
  • ASIC memory cards are typically inserted into server PCIe (Peripheral Component Interconnect Express) slots, and then several DDR (Double Data Rate) memory modules, such as 4 or 8 modules, are inserted into the card.
  • PCIe Peripheral Component Interconnect Express
  • CXL memory Compared to traditional DDR memory, CXL memory has the following characteristics:
  • Latency The latency of E3.S memory modules and ASIC memory cards is twice that of local DDR memory, which is approximately 100ns, while CXL memory is approximately 200ns-250ns. This latency difference of more than double will have a real impact on application performance, necessitating tiered usage.
  • the JBOM+CXL 2.0 switch has even higher latency, reaching 500ns, approximately five times the latency of local memory.
  • CXL memory does not occupy DIMM (Dual-Inline-Memory-Modules) slots or CPU (Central Processing Unit) memory channels, thus enabling capacity expansion.
  • DIMM Dual-Inline-Memory-Modules
  • CPU Central Processing Unit
  • regular local memory e.g., DDR memory
  • CXL memory e.g., CXL memory
  • the operating system allocates memory based on its own policies.
  • access speed will be slower when the requested memory is CXL.
  • user memory access can be fast or slow, with latency exceeding twice the normal speed.
  • the memory allocation method provided in this application defines a dedicated application interface for allocating CXL memory to the user.
  • the user can request the allocation of CXL memory by calling this application interface. At this time, no local memory will be allocated to the user, thereby ensuring that the user can use CXL memory stably.
  • a memory allocation method embodiment is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.
  • FIG. 1 is a flowchart of a memory allocation method according to an embodiment of this application. As shown in Figure 1, the process includes the following steps.
  • Step S101 Define a dedicated application programming interface for allocating CXL memory.
  • API Application Programming Interface
  • this API will be referred to as the standard application programming interface, or simply the standard API.
  • local memory e.g., DDR memory
  • CXL memory e.g., DDR memory
  • the access speed is faster, while when they request CXL memory, the access speed is slower, resulting in fluctuating access speeds and unstable memory performance.
  • a dedicated application programming interface is defined for users to allocate CXL memory.
  • users can determine that CXL memory needs to be allocated.
  • allocation of memory refers to any one or more of the following operations: requesting memory, releasing (reclaiming) memory, initializing memory, expanding memory, shrinking memory, and aligning memory.
  • the specific operation may vary depending on the actual situation.
  • Step S102 Obtain the call request for calling the application interface.
  • API application programming interface
  • a dedicated API for allocating CXL memory is provided. Therefore, when a user needs to access CXL memory, they can call this dedicated API, specifically the corresponding function within it, to fulfill the required memory allocation. Furthermore, a standard API is still retained; that is, the standard API is still provided externally. When a user does not need to specifically allocate CXL memory, they can still call this standard API.
  • the user can directly request CXL memory from the operating system, that is, call the dedicated API; while when a user needs a small amount of memory and requires high performance (such as low latency), the built-in standard API can be used.
  • Step S103 In the case of a call request for calling a dedicated application interface, a CXL memory identifier representing the allocation of CXL memory is generated.
  • the system can determine whether the current call request is for a dedicated application interface by identifying which application interface the request calls. For example, if the memory allocation function currently being called by the user is a function in a dedicated API, then it can be determined that the user is currently calling a dedicated API, i.e., the user is currently requesting the allocation of CXL memory.
  • MAP_CXLMEM CXL memory identifier
  • the CXL memory identifier (MAP_CXLMEM) can be represented by a flag bit, meaning different values indicate whether CXL memory allocation is required.
  • CXL memory allocation for example, when they need to allocate regular local memory (e.g., DDR memory)—they can still call the standard API without modifying the code that calls it.
  • the memory allocated to the user is typically hybrid memory, including both local and CXL memory.
  • users need to allocate CXL memory they only need to modify the API they're calling. This involves changing the code within the application related to the API call, replacing the original standard API with this specific API. The amount of code modification on the user side is minimal.
  • Step S104 Pass the CXL memory identifier to the kernel mode through the memory mapping interface, and allocate hardware resources related to the CXL memory in the kernel mode.
  • the CXL memory identifier (MAP_CXLMEM) is generated in user space.
  • the CXL memory identifier (MAP_CXLMEM) needs to be passed to kernel space.
  • the identifier of the allocated CXL memory (i.e., the CXL memory identifier) can be brought to the operating system kernel, such as the Linux kernel, through the operating system's memory mapping interface, namely the mmap interface.
  • the operating system kernel such as the Linux kernel
  • the operating system's memory mapping interface namely the mmap interface.
  • user-mode memory management is implemented based on a memory allocator (e.g., jemalloc), and system calls can be made through the memory mapping interface to access the Linux kernel.
  • the memory allocation method provided in this embodiment defines a dedicated API for allocating CXL memory. Users can allocate CXL memory by calling the dedicated API. At this time, no local memory is allocated to the user, thus ensuring that the user can use CXL memory stably. Furthermore, by defining a dedicated API, when users need to allocate CXL memory, they only need to modify the API being called. The amount of code modification on the user side is small, which can reduce the manpower cost caused by modifying the code.
  • FIG. 2 is a flowchart of the memory allocation method according to an embodiment of this application. As shown in Figure 2, the process includes the following steps.
  • Step S201 Define a dedicated application programming interface for allocating CXL memory.
  • step S201 "defining a dedicated application programming interface for allocating CXL memory,” includes: modifying the function names of the standard application programming interface according to the same modification rules, and using the modified function names as function names in the dedicated application programming interface; the standard application programming interface is used for memory allocation.
  • the standard API provided by the memory allocator is generally called; for example, users normally access memory through the malloc function in the standard API provided by the jemalloc library.
  • the rules for modifying function names can include adding a prefix or suffix to the original function name. For example, adding the prefix "in" to the original function name can generate a function name for the dedicated API.
  • adding the prefix "in” can generate the dedicated API's memory allocation function "in_malloc”.
  • dedicated API's memory reallocation function ⁇ in_realloc ⁇ and memory deallocation function ⁇ in_free ⁇ can also be generated.
  • a user If a user is currently requesting local memory (calling the standard API), and needs to switch to requesting CXL memory, they only need to modify the function name of the API being called. That is, they can add the prefix "in" to the function name of the API they are calling to change it to calling the dedicated API, thereby requesting CXL memory. The amount of code modification on the user side is minimal.
  • retrieval functions for returning corresponding parameters are defined for the dedicated application programming interface.
  • These retrieval functions may include at least one of the following:
  • the first get function is used to obtain the total amount of the requested CXL memory region (i.e., the total number of bytes); the first get function can be in_get_memsize_total as shown in Table 2 below.
  • a second get function is used to obtain the total amount of CXL memory regions allocated through the client development kit; this second get function can be in_get_memsize_used as shown in Table 2 below.
  • a third get function is used to obtain the number of available bytes in a specified CXL memory region; this third get function can be in_get_memsize_available as shown in Table 2 below.
  • the fourth get function is used to obtain the total amount of CXL memory region in a specified memory node; this fourth get function can be in_get_memsize_node_total as shown in Table 2 below.
  • the fifth get function is used to obtain the number of available bytes in the CXL memory region of a specified memory node; this fifth get function can be in_get_memsize_node_available as shown in Table 2 below.
  • the sixth fetch function is used to obtain status data for multiple CXL memory regions; this sixth fetch function can be in_stats_print as shown in Table 2 below.
  • the status data can include total memory, number of bytes used, and number of bytes available.
  • the seventh function is used to obtain the status data of the corresponding CXL memory regions under multiple memory nodes; this seventh function can be in_stats_node_print as shown in Table 2 below.
  • the dedicated API defined in this embodiment includes functions that can be found in Table 2 below.
  • Step S202 Divide the memory into a first memory allocation pool for allocating CXL memory in user mode and a second memory allocation pool for allocating local memory in user mode.
  • the memory allocator jemalloc has only one memory allocation pool jemalloc_arena_pool.
  • the memory allocation pool is expanded into two types of memory allocation pools. One type is used to allocate user-mode CXL memory, which will be referred to as the first memory allocation pool (cxlmem_arena_pool) in the following text. The other type is used to allocate user-mode local memory, which will be referred to as the second memory allocation pool (normal_arena_pool) in the following text.
  • step S202 above "dividing the memory allocation pool into a first memory allocation pool for allocating CXL memory in user mode and a second memory allocation pool for allocating local memory in user mode,” may include: allocating multiple memory allocation pools for each core of the processor, wherein a portion of the memory allocation pool serves as the first memory allocation pool for allocating CXL memory in user mode, and another portion serves as the second memory allocation pool for allocating local memory in user mode.
  • the memory allocation pools can be evenly divided among the processor cores, meaning the number of first and second memory allocation pools is the same.
  • the number of each type of memory allocation pool can be set.
  • the original memory allocator typically configures 4 memory allocation pools per CPU core; in this embodiment, 8 memory allocation pools are configured per CPU core, with four used for allocating CXL memory (i.e., the first memory allocation pool, cxlmem_arena_pool) and the other four used for allocating local memory (i.e., the second memory allocation pool, normal_arena_pool). Therefore, for the standard API, since only one of the first and second memory allocation pools can be selected at any given time, the number of memory allocation pools at runtime is the same as that of the original memory allocator. However, for the dedicated API for CXL memory, user applications can allocate local memory and CXL memory in parallel, meaning they can use both memory allocation pools simultaneously.
  • Step S203 Obtain the call request for calling the application interface.
  • Step S204 In the case of a call request for calling a dedicated application interface, a CXL memory identifier representing the allocation of CXL memory is generated.
  • Step S205 When the call request is used to call a dedicated application interface, a first memory allocation pool is selected, and the memory space in the first memory allocation pool is allocated according to the call request to allocate user-mode CXL memory.
  • the corresponding call request can be obtained based on the memory allocator interface, and a suitable memory allocation pool can be selected based on the call request.
  • a suitable memory allocation pool can be selected based on the call request.
  • the call request initiated by the user is for calling a dedicated API, for example, if the memory allocation function called in the call request has the prefix "in”, then the first memory allocation pool is selected; conversely, if the call request is for calling a standard API, then the second memory allocation pool can be called.
  • the memory space in the selected memory allocation pool can be allocated according to the call request, such as requesting or reclaiming the corresponding memory space.
  • step S205 "allocating memory space in the first memory allocation pool according to the call request,” may include steps A1 to A3.
  • Step A1 Determine the memory allocation function corresponding to the call request.
  • the call request includes the memory allocation function for the corresponding API, which determines the memory allocation function required by the memory allocator. For example, if the call request requests a block of memory and its memory allocation function is ⁇ malloc ⁇ , then the corresponding memory allocation function in the memory allocator, such as ⁇ je_mallocx ⁇ , is the one used to request memory.
  • Step A2 Add a user-mode memory mapping flag to the memory allocation function and assign a value to the memory mapping flag according to the CXL memory identifier; the memory mapping flag is used to indicate whether to allocate CXL memory.
  • a new flag indicating whether to allocate CXL memory namely the memory mapping flag (arena_mmap_flag) is added to the memory allocation function of the memory allocator.
  • the CXL memory identifier MAP_CXLMEM
  • the CXL memory identifier MAP_CXLMEM
  • arena_mmap_flag MAP_CXLMEM.
  • MAP_NORMAL a local memory identifier indicating the allocation of local memory
  • arena_mmap_flag MAP_NORMAL
  • step A1 above "adding a user-mode memory mapping flag in the memory allocation function" includes step A11.
  • Step A11 Add a user-mode memory mapping flag to the memory allocation structure of the memory allocation pool.
  • the memory allocation pool typically has a data structure for memory allocation, namely the memory allocation structure (arena_s).
  • the data structure of the memory allocation pool is extended by adding a flag, namely the user-space memory mapping flag (arena_mmap_flag), to distinguish whether the memory allocation pool is local memory or CXL memory in user space.
  • arena_mmap_flag the user-space memory mapping flag
  • the arena_mmap_flag of arena_s is used to determine whether the current allocation is for local memory or CXL memory, and finally the flag parameter is generated for the kernel, so that the kernel can allocate the corresponding memory. This process can be seen in Figure 3.
  • a setting function for setting the memory mapping flag (arena_mmap_flag), such as arena_set_mmap_flag, may be added, as well as a getting function for retrieving the memory mapping flag (arena_mmap_flag), such as arena_get_mmap_flag.
  • the method further includes steps B1 to B2.
  • Step B1 a preset setting function is used to set the memory mapping flag.
  • Step B2 When creating a new memory allocation pool, a setting function is called to set the memory mapping flag of the new memory allocation pool to the default value; the default value indicates that local memory (MAP_NORMAL) is allocated.
  • MAP_NORMAL local memory
  • step A2 above, "assigning a value to the memory mapping flag based on the CXL memory identifier,” may include: calling a setting function to assign the CXL memory identifier to the memory mapping flag.
  • the setting function ⁇ arena_set_mmap_flag ⁇ can be called based on the initialization function ⁇ init_arena_pool ⁇ .
  • memory is allocated to the user by default based on the traditional allocation method.
  • the newly added setting function can also be used to assign a value to the memory mapping flag.
  • Step A3 Allocate memory space in the first memory allocation pool according to the memory allocation function.
  • the memory space in the first memory allocation pool can be allocated based on the memory allocation function, such as requesting or reclaiming the first memory allocation pool.
  • Step S206 Pass the CXL memory identifier to the kernel mode through the memory mapping interface, and allocate hardware resources related to the CXL memory in the kernel mode.
  • the memory allocator is modified to support new dedicated APIs and to allow the identifier of CXL memory usage to be passed to the kernel via the operating system's memory mapping interface.
  • this embodiment uses the memory management file (extent.c) to pass parameters based on which memory allocation pool is used.
  • step S206 "passing the CXL memory identifier to kernel mode via the memory mapping interface,” includes steps C1 to C3.
  • Step C1 Based on the memory allocation kernel function in the memory management file, call the acquisition function used to obtain the memory mapping flag, and obtain the memory mapping flag.
  • the memory allocator includes a memory management file, extent.c, which contains a memory allocation kernel function, extent_alloc_core. Based on the extent_alloc_core memory allocation kernel function, the corresponding memory mapping flag is obtained from the memory allocation pool.
  • a newly added retrieval function, arena_get_mmap_flag can be called to obtain the current memory mapping flag.
  • Step C2 Set the memory mapping flag passing function and pass parameters to the memory mapping flag according to the memory mapping flag passing function.
  • the memory mapping flag passing function extent_alloc_mmap_flag in the memory management file extent.c can be used to pass parameters.
  • the memory mapping flag (arena_mmap_flag) can be merged into the local variable (interleave_policy) representing the interleaving policy; and then the local variable (interleave_policy) can be passed as a parameter according to the memory mapping flag passing function extent_alloc_mmap_flag.
  • Step C3 Add a memory mapping flag to the operating system memory page mapping function in the memory page file to pass the memory mapping flag to the kernel's memory mapping interface.
  • the memory allocator includes a memory page file, namely pages.c.
  • Memory mapping flags can be merged, for example, merging local variables including memory mapping flags and other additional flags.
  • the merged flag is then passed as a parameter to the operating system's memory page mapping function, os_pages_map_flag, within pages.c.
  • the corresponding flag is added to the os_pages_map_flag function, thus passing the memory mapping flag to the kernel's mmap interface.
  • MAP_JEMALLOC_INTERNAL_MMAP can be added to the os_pages_map_flag function and passed to the kernel's mmap interface to achieve flag parameter passing. This parameter passing process is illustrated in Figure 4.
  • the memory allocation method provided in this embodiment defines a dedicated API for allocating CXL memory. Users can allocate CXL memory by calling this dedicated API, without allocating local memory to the user, thus ensuring stable use of CXL memory. Furthermore, by defining a dedicated API, the amount of code modification on the user side is minimal, reducing the manpower costs associated with code modifications. A first memory allocation pool and a second memory allocation pool are divided in user space, allowing for adaptive allocation of CXL memory. Adding a user-space memory mapping flag to the memory allocation function effectively responds to user calls to the dedicated API. Using a memory management file to pass the memory mapping flag as a parameter solves the problem of directly passing the flag to the kernel.
  • FIG. 5 is a flowchart of the memory allocation method according to an embodiment of this application. As shown in Figure 5, the process includes the following steps.
  • Step S501 Define a dedicated application programming interface for allocating CXL memory.
  • Step S502 Obtain the call request for calling the application interface.
  • Step S503 In the case of a call request for calling a dedicated application interface, a CXL memory identifier representing the allocation of CXL memory is generated.
  • Step S504 Pass the CXL memory identifier to kernel mode through the memory mapping interface.
  • Step S505 Divide the CXL memory allocation area for independent management of kernel space CXL memory.
  • CXL memory allocation zone CXLMem_zone
  • FIG. 6 illustrates a hierarchical logical memory view within the Virtual Machine Manager (VMM) of the operating system kernel.
  • VMM Virtual Machine Manager
  • This view covers various granularities, including memory nodes, memory zones, memory buddies, and memory pages.
  • the VMM extends memory zones as memory allocation areas.
  • the Linux VMM has expanded zones to better utilize physical memory, such as DMA (Direct Memory Access)/DMA32 Zones, MOVABLE Zones, and NORMAL Zones.
  • the DMA/DMA2 Zones include a series of I/O (Input/Output) device page address spaces, which are relatively limited.
  • the MOVABLE Zone aims to reduce fragmentation and support hot-swapping of memory.
  • NORMAL Zones meaning the vast majority of DRAM (Dynamic Random Access Memory) pages belong to NORMAL Zones.
  • CXLMem_zone a new CXL memory allocation area (CXLMem_zone) is added in kernel mode for the allocation and management of CXL memory.
  • the above step S505 "dividing the CXL memory allocation area for independent management of kernel space CXL memory” includes the following steps D1 to D2.
  • Step D1 Add a new type (ZONE_CXLMEM) corresponding to the CXL memory allocation area (CXLMem_zone) to the memory region type (enum zone_type) in the memory region management header file of the operating system kernel.
  • mmzone.h. mmzone.h is the header file in the Linux kernel responsible for memory region management; memory region management is the core part of Linux kernel memory management, mainly responsible for managing the system's physical memory and swap space. It defines the types of existing memory allocation zones, i.e., memory region types (enum zone_type).
  • memory region types i.e., memory region types (enum zone_type).
  • the memory region type of the local memory allocation zone NORMAL Zone is ZONE_NORMAL.
  • the memory region type corresponding to the CXL memory allocation zone (CXLMem_zone) is added to the memory region type of the mmzone.h header file, for example, ZONE_CXLMEM.
  • CXL memory configuration options such as modified operating system kernel code, newly added functions, and variables related to CXL memory are encapsulated in macro definitions, so that the corresponding macro definitions can be selectively enabled in the kernel configuration.
  • the memory region type of the CXL memory allocation area set above belongs to the modified code of the operating system kernel, so the memory region type of the CXL memory allocation area can be added based on the macro definition.
  • Step D2 Extend the kernel-mode memory-mapped system call interface by adding flags indicating mapping CXL memory and flags indicating mapping local memory.
  • the kernel-mode memory mapping (mmap) system call interface is extended by adding flags to distinguish between calling local memory and CXL memory. Specifically, flags indicating CXL memory mapping, such as the aforementioned CXL memory flag MAP_CXLMEM, and flags indicating local memory mapping, such as the aforementioned local memory flag MAP_NORMAL, can be added to the memory mapping system call interface.
  • step S505 "dividing the CXL memory allocation area for independent management of kernel space CXL memory", may also include step D3.
  • Step D3 Add a sub-memory region structure to the memory region management header file.
  • Each sub-memory region structure corresponds to a CXL memory segment.
  • This sub-memory region structure includes memory region data, memory start address, and memory end address; the memory region data is generated compatiblely based on existing memory allocation zones.
  • the hardware since the hardware generally includes multiple CXL memory modules, and the kernel-level CXL memory allocation area (CXLMem_zone) corresponds to multiple CXL memory modules, in order to enable memory allocation in units of CXL memory, the memory area corresponding to one CXL memory module is called a subzone, and a corresponding structure is added to it, namely the subzone structure (also known as the subzone structure).
  • the subzone structure also known as the subzone structure
  • a subzone structure can be added to the memory region management header file mmzone.h.
  • Each subzone structure represents a CXL memory segment, thus supporting multiple CXL memory segments.
  • this sub-memory region structure includes the memory region data ⁇ zone_dat ⁇ , the memory start address ⁇ start_pfn ⁇ , and the memory end address ⁇ end_pfn ⁇ ; it can be understood that the memory here refers to CXL memory.
  • the memory region data ⁇ zone_dat ⁇ is generated compatiblely based on existing memory allocation zones.
  • the memory region data ⁇ zone_dat ⁇ can be constructed by wrapping a subzone around the memory allocation zone in the original kernel design, thus maintaining compatibility with previous kernel designs.
  • the CXL memory to be allocated can be represented by this subzone structure, and the corresponding CXL memory can be requested, reclaimed, etc.
  • a function add_subzone can be added to add sub-memory regions, and a function remove_subzone can be added to remove sub-memory regions. This embodiment will not be described in detail.
  • this sub-memory region structure is a new CXL memory configuration option, so it can also be added to the memory region management header file mmzone.h through macro definition.
  • step S505 "dividing the CXL memory allocation area for independent management of kernel space CXL memory", may also include the following step D4.
  • Step D4 Add a sub-memory region index structure to the memory region management header file.
  • the sub-memory region index structure includes a pointer to the corresponding sub-memory region and the index identifier (subozne_idx) of the sub-memory region in the sub-memory region list (subzonelist).
  • a subzone index structure which can be simply referred to as the subzoneref structure, is also added. Similar to adding the subzone structure, this subzone index structure, i.e., the subzoneref structure, is added to the memory zone management header file mmzone.h.
  • the sub-memory region index structure includes pointers to the corresponding sub-memory regions; and, the sub-memory region list subzonelist represents all the sub-memory regions subzone.
  • the sub-memory region index structure also includes the index identifier of the corresponding sub-memory region in the sub-memory region list subzonelist; for example, if the index identifier is ID, it can be represented by the variable name of the index identifier subozne_idx.
  • this sub-memory region index structure is also a new CXL memory configuration option, so it can also be added to the memory region management header file mmzone.h through macro definition.
  • step S505 "dividing the CXL memory allocation area for independent management of kernel space CXL memory", may also include the following step D5.
  • Step D5 Add new variables to the memory region structure in the memory region management header file.
  • the new variables include: free sub-memory region queue structure, sub-memory region list (subzonelist), number of sub-memory regions (nr_subzones), and index identifier of the currently allocated sub-memory region (cur_subzone_idx).
  • the memory region management header file mmzone.h contains a memory region structure, namely struct zone, which is a key data structure representing a memory region (zone).
  • struct zone which is a key data structure representing a memory region (zone).
  • variables related to subzones are added to the memory region structure struct zone.
  • a key structure is added to the memory region structure ⁇ struct zone ⁇ , namely the free sub-memory region queue structure.
  • the original free memory queue in Linux e.g., the free queue for local memory
  • ⁇ free_area ⁇ The original free memory queue in Linux (e.g., the free queue for local memory) is called ⁇ free_area ⁇ .
  • the corresponding free memory queues ⁇ free_area ⁇ are modified to be free sub-memory region queue structures, with the variable name ⁇ free_area_subzone ⁇ .
  • a new ⁇ free_area_subzone ⁇ structure array is introduced for CXL memory, and the appropriate free memory queue is selected based on whether it is a CXL memory region. For example, where a free memory queue is needed, the choice between using ⁇ free_area ⁇ or ⁇ free_area_subzone ⁇ can be made based on whether it is a CXL memory region.
  • the memory region structure ⁇ struct zone ⁇ also adds a list of sub-memory regions ( ⁇ subzonelist ⁇ , which includes a linked list of all sub-memory regions), the number of sub-memory regions ( ⁇ nr_subzones ⁇ , which is the total number of sub-memory regions), and the index identifier of the currently allocated sub-memory region ( ⁇ cur_subzone_idx ⁇ ).
  • ⁇ subzonelist ⁇ which includes a linked list of all sub-memory regions
  • ⁇ nr_subzones ⁇ which is the total number of sub-memory regions
  • ⁇ cur_subzone_idx ⁇ index identifier of the currently allocated sub-memory region
  • the new variable can also be configured based on macro definitions.
  • Step S506 Allocate memory space in the CXL memory allocation area according to the call request to allocate hardware resources related to CXL memory.
  • Figure 7 shows the block diagram of memory allocation based on standard API and dedicated API. After the user-mode memory allocator passes parameters based on the memory mapping interface, it uses the corresponding memory allocation area in kernel mode according to the current needs, thereby allocating the corresponding type of memory, that is, allocating hardware resources related to CXL memory in kernel mode.
  • step S506 "allocate memory space in the CXL memory allocation area according to the call request" may include: obtaining the index identifier of the next sub-memory area from the linked list of free sub-memory areas; locating the free sub-memory area from the free sub-memory area queue structure according to the index identifier of the next sub-memory area, and allocating memory according to the free sub-memory area.
  • the kernel's mm_init.c file can be modified to extend zone_init_free_lists. Specifically, if the current memory allocation zone is a CXL memory allocation zone (CXLMem_zone), the newly defined free sub-memory region queue structure free_area_subzone can be used to initialize the kernel's INIT_LIST_HEAD, completing the initialization.
  • CXLMem_zone a newly added CXL memory allocation zone
  • the index of the next sub-memory region i.e., the sub-memory region following the currently allocated sub-memory region
  • a ⁇ get_next_subzone_id ⁇ function can be set for the newly added sub-memory region ⁇ subzone ⁇ . Based on this function, the index of the next sub-memory region can be retrieved from the linked list of free sub-memory regions.
  • the free sub-memory region can be located in the free sub-memory region queue structure, and memory allocation can be performed based on that free sub-memory region—that is, memory allocation is performed based on the next sub-memory region.
  • the memory allocation method provided in this embodiment defines a dedicated API for allocating CXL memory. Users can allocate CXL memory by calling this dedicated API, ensuring stable use of CXL memory with minimal code modifications on the user side, thus reducing the manpower costs associated with code modifications.
  • a new CXL memory allocation area is added in kernel mode for dedicated management of CXL memory.
  • the addition of subzone and subzoneref structures allows for allocation of CXL memory in units of a single CXL memory block, meeting user needs.
  • CXL memory configuration options, such as those for modified code are configured using macros, allowing for easy enabling or disabling of CXL memory allocation without affecting the local memory allocation process when users call the standard API.
  • module can be a combination of software and/or hardware that implements a predetermined function.
  • the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.
  • This embodiment provides a memory allocation device, as shown in Figure 8, including:
  • Interface definition module 801 is configured to define a dedicated application interface for allocating CXL memory
  • the acquisition module 802 is configured to acquire the call request for the application interface
  • Processing module 803 is configured to generate a CXL memory identifier representing the allocation of CXL memory when the call request is used to call a dedicated application interface;
  • the parameter allocation module 804 is configured to pass the CXL memory identifier to the kernel mode through the memory mapping interface and allocate hardware resources related to the CXL memory in the kernel mode.
  • the interface definition module 801 defines a dedicated application interface for allocating CXL memory, including:
  • the function names of the standard application programming interface are modified, and the modified function names are used as function names in the dedicated API; the standard API is used for memory allocation.
  • the interface definition module 801 defines a dedicated application programming interface for allocating CXL memory, and further includes:
  • a first function for obtaining the total amount of the requested CXL memory region a second function for obtaining the total amount of the CXL memory region allocated by the client development kit, a third function for obtaining the number of available bytes in a specified CXL memory region, a fourth function for obtaining the total amount of the CXL memory region in a specified memory node, a fifth function for obtaining the number of available bytes in the CXL memory region in a specified memory node, a sixth function for obtaining the status data of multiple CXL memory regions, and a seventh function for obtaining the status data of the corresponding CXL memory regions under multiple memory nodes.
  • the apparatus further includes a partitioning module configured to partition a first memory allocation pool for allocating CXL memory in user mode and a second memory allocation pool for allocating local memory in user mode.
  • the processing module 803 is also configured to select a first memory allocation pool when the call request is for calling a dedicated application interface; and to allocate memory space in the first memory allocation pool according to the call request to allocate user-mode CXL memory.
  • the processing module 803 allocates memory space in the first memory allocation pool according to the call request, including:
  • a user-mode memory mapping flag is added to the memory allocation function, and the memory mapping flag is assigned a value according to the CXL memory identifier; the memory mapping flag is used to indicate whether CXL memory is allocated;
  • the memory space in the first memory allocation pool is allocated according to the memory allocation function.
  • the processing module 803 adds a user-mode memory mapping flag to the memory allocation function, including:
  • an initialization module configured to: pre-set a setting function for setting memory mapping flags; when a new memory allocation pool is created, call the setting function to set the memory mapping flags of the new memory allocation pool to a default value; the default value indicates that local memory is allocated;
  • the processing module 803 assigns a value to the memory mapping flag based on the CXL memory identifier, including: calling the setting function to assign the CXL memory identifier to the memory mapping flag.
  • the parameter allocation module 804 passes the CXL memory identifier to the kernel mode through a memory mapping interface, including:
  • the function used to obtain the memory mapping flag is called to obtain the memory mapping flag
  • the parameter allocation module 804 passes parameters to the memory mapping flag according to the memory mapping flag passing function, including:
  • the local variable is passed parameters according to the memory mapping flag passing function.
  • the partitioning module partitions a first memory allocation pool for allocating CXL memory in user mode and a second memory allocation pool for allocating local memory in user mode, including:
  • Multiple memory allocation pools are allocated for each core of the processor, with a portion of the memory allocation pool serving as the first memory allocation pool for allocating CXL memory in user mode, and another portion serving as the second memory allocation pool for allocating local memory in user mode.
  • the parameter allocation module 804 allocates hardware resources related to CXL memory in kernel mode, including:
  • the memory space in the CXL memory allocation area is allocated according to the call request in order to allocate hardware resources related to CXL memory.
  • the parameter allocation module 804 divides a CXL memory allocation area for independently managing kernel space CXL memory, including:
  • the parameter allocation module 804 divides a CXL memory allocation area for independently managing kernel space CXL memory, and further includes:
  • the sub-memory region structure includes memory region data, memory start address, and memory end address; among them, the memory region data is generated compatiblely based on the existing memory allocation area.
  • the parameter allocation module 804 divides a CXL memory allocation area for independently managing kernel space CXL memory, and further includes:
  • the sub-memory region index structure includes a pointer to the corresponding sub-memory region, as well as the index identifier of the sub-memory region in the sub-memory region list.
  • the parameter allocation module 804 divides a CXL memory allocation area for independently managing kernel space CXL memory, and further includes:
  • the new variables include: free sub-memory region queue structure, sub-memory region list, number of sub-memory regions, and index identifier of the currently allocated sub-memory region.
  • the parameter allocation module 804 allocates memory space in the CXL memory allocation area according to the call request, including:
  • the parameter allocation module 804 is configured as follows:
  • CXL memory configuration options are encapsulated in macro definitions and selectively enabled in kernel configuration;
  • CXL memory configuration options include at least one of the following: modified operating system kernel code, newly added functions, and variables.
  • the memory allocation device is presented in the form of a functional unit.
  • a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, including a processor and memory that execute one or more software or fixed programs, and/or other devices that can provide the above functions.
  • ASIC Application Specific Integrated Circuit
  • This application also provides a computer device having the memory allocation device shown in FIG8 above.
  • Figure 9 is a schematic diagram of the structure of a computer device provided in an optional embodiment of this application.
  • the computer device includes: one or more processors 10, memory 20, and interfaces configured to connect the various components, including high-speed interfaces and low-speed interfaces.
  • the various components communicate with each other using different buses and can be installed on a common motherboard or otherwise as needed.
  • the processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI (Graphical User Interface) on an external input/output device (such as a display device coupled to the interface).
  • GUI Graphic User Interface
  • multiple processors and/or multiple buses can be used with multiple memories if needed.
  • multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system).
  • Figure 9 uses one processor 10 as an example.
  • Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include hardware chips. These hardware chips may be application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or combinations thereof. The programmable logic devices may be complex programmable logic devices (CLPs), field-programmable gate arrays (FPGAs), general-purpose array logic (GDAs), or any combination thereof.
  • ASICs application-specific integrated circuits
  • PLDs programmable logic devices
  • the programmable logic devices may be complex programmable logic devices (CLPs), field-programmable gate arrays (FPGAs), general-purpose array logic (GDAs), or any combination thereof.
  • CLPs complex programmable logic devices
  • FPGAs field-programmable gate arrays
  • GDAs general-purpose array logic
  • the memory 20 stores instructions executable by at least one processor 10 to cause at least one processor 10 to perform the method shown in the above embodiments.
  • the memory 20 may include a program storage area and a data storage area.
  • the program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device.
  • the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device.
  • the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.
  • the memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.
  • volatile memory such as random access memory
  • non-volatile memory such as flash memory, hard disk or solid-state drive
  • the memory 20 may also include a combination of the above types of memory.
  • the computer device also includes a communication interface 30, which is configured to communicate with other devices or communication networks.
  • This application also provides a computer-readable storage medium.
  • the methods described in this application can be implemented in hardware or firmware, or implemented as recordable on a storage medium, or implemented as computer code downloaded over a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and subsequently stored on a local storage medium.
  • the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware.
  • the storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; optionally, the storage medium may also include combinations of the above types of memory.
  • computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.
  • a portion of this application can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and/or technical solutions according to this application through the operation of the computer.
  • computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc.
  • ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program.
  • the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

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Abstract

本申请涉及内存管理技术领域,公开了内存分配方法、计算机设备、存储介质及产品,该方法包括:定义用于分配计算快速连接CXL内存的专用应用程序接口;获取调用应用程序接口的调用请求;在调用请求用于调用专用应用程序接口的情况下,生成表示分配CXL内存的CXL内存标识;通过内存映射接口,将CXL内存标识传递至内核态,并在内核态分配与CXL内存相关的硬件资源。本申请定义专门用于分配CXL内存的专用API,用户通过调用专用API即可实现对CXL内存的分配,从而能够稳定地使用CXL内存;用户在需要分配CXL内存时,只需修改调用的API,代码修改量较小,可以降低因修改代码带来的人力成本。

Description

内存分配方法、计算机设备、存储介质及产品
相关申请的交叉引用
本申请要求于2024年04月30日提交中国专利局,申请号为202410535902.9,申请名称为“内存分配方法、计算机设备、存储介质及产品”的中国专利申请的优先权,其全部内容通过引用结合在本申请中。
技术领域
本申请涉及内存管理技术领域,具体涉及内存分配方法、计算机设备、存储介质及产品。
背景技术
CXL(Compute Express Link,意为计算快速连接)内存与传统的普通本地内存相比,可以扩展内存容量、提高内存资源访问带宽,但CXL内存具有更高的时延。
当在服务器中同时使用普通本地内存和CXL内存时,会向用户混合分配本地内存和CXL内存,导致性能不稳定。
发明内容
有鉴于此,本申请提供了一种内存分配方法、计算机设备、存储介质及产品,以解决分配内存时可能存在性能不稳定的问题。
第一方面,本申请提供了一种内存分配方法,包括:
定义用于分配CXL内存的专用应用程序接口;
获取调用应用程序接口的调用请求;
在调用请求用于调用专用应用程序接口的情况下,生成表示分配CXL内存的CXL内存标识;
通过内存映射接口,将CXL内存标识传递至内核态,并在内核态分配与CXL内存相关的硬件资源。
在一些可选的实施方式中,定义用于分配CXL内存的专用应用程序接口,包括:
按照相同修改规则,对标准应用程序接口的函数名进行修改,将修改后的函数名作为专用应用程序接口中的函数名;标准应用程序接口用于分配内存。
在一些可选的实施方式中,定义用于分配CXL内存的专用应用程序接口,还包括:
为专用应用程序接口定义:用于获取请求的CXL内存区域总量的第一获取函数、用于获取通过客户端开发包分配的CXL内存区域总量的第二获取函数、用于获取指定CXL内存区域可用字节数的第三获取函数、用于获取指定内存节点中CXL内存区域总量的第四获取函数、用于获取指定内存节点中CXL内存区域可用字节数的第五获取函数、用于获取多个CXL内存区域的状态数据的第六获取函数、用于获取多个内存节点下、相应CXL内存区域的状态数据的第七获取函数中的至少一种。
在一些可选的实施方式中,该方法还包括:
划分用于分配用户态的CXL内存的第一内存分配池,以及用于分配用户态的本地内存的第二内存分配池;
在调用请求用于调用专用应用程序接口的情况下,选定第一内存分配池;
根据调用请求对第一内存分配池中的内存空间进行分配处理,以分配用户态的CXL内存。
在一些可选的实施方式中,根据调用请求对第一内存分配池中的内存空间进行分配处理,包括:
确定与调用请求相对应的内存分配函数;
在内存分配函数中新增用户态的内存映射标志,并根据CXL内存标识对内存映射标志进行赋值;内存映射标志用于表示是否分配CXL内存;
根据内存分配函数对第一内存分配池中的内存空间进行分配处理。
在一些可选的实施方式中,在内存分配函数中新增用户态的内存映射标志,包括:
在内存分配池的在内存分配结构体中新增用户态的内存映射标志。
在一些可选的实施方式中,该方法还包括:
预设用于设置内存映射标志的设置函数;
在新建内存分配池时,调用设置函数,为新建内存分配池的内存映射标志设为默认值;默认值表示分配本地内存;
根据CXL内存标识对内存映射标志进行赋值,包括:
调用设置函数,将CXL内存标识赋值给内存映射标志。
在一些可选的实施方式中,通过内存映射接口,将CXL内存标识传递至内核态,包括:
基于内存管理文件中的内存分配核函数,调用用于获取内存映射标志的获取函数,获取到内存映射标志;
设置内存映射标志传递函数,根据内存映射标志传递函数对内存映射标志进行传参;
在内存页文件的操作系统内存页映射函数中增加内存映射标志,以将内存映射标志传递至内核的内存映射接口。
在一些可选的实施方式中,根据内存映射标志传递函数对内存映射标志进行传参,包括:
将内存映射标志合并至表示交织策略的局部变量;
根据内存映射标志传递函数对局部变量进行传参。
在一些可选的实施方式中,划分用于分配用户态的CXL内存的第一内存分配池,以及用于分配用户态的本地内存的第二内存分配池,包括:
为处理器的每个核分配多个内存分配池,其中部分内存分配池作为用于分配用户态的CXL内存第一内存分配池,另一部分内存分配池作为用于分配用户态的本地内存的第二内存分配池。
在一些可选的实施方式中,在内核态分配与CXL内存相关的硬件资源,包括:
划分用于独立管理内核空间CXL内存的CXL内存分配区;
根据调用请求对CXL内存分配区中的内存空间进行分配处理,以分配与CXL内存相关的硬件资源。
在一些可选的实施方式中,划分用于独立管理内核空间CXL内存的CXL内存分配区,包括:
在操作系统内核的内存区域管理头文件的内存区域类型中新增CXL内存分配区对应的类型;
扩展内核态的内存映射系统调用接口,为内存映射系统调用接口增加表示映射CXL内存的标志以及表示映射本地内存的标志。
在一些可选的实施方式中,划分用于独立管理内核空间CXL内存的CXL内存分配区,还包括:
在内存区域管理头文件中新增子内存区域结构体,每个子内存区域结构体对应一条CXL内存;
子内存区域结构体包括内存区域数据、内存起始地址和内存结束地址;其中,内存区域数据是在已有内存分配区的基础上兼容生成的。
在一些可选的实施方式中,划分用于独立管理内核空间CXL内存的CXL内存分配区,还包括:
在内存区域管理头文件中新增子内存区域索引结构体;子内存区域索引结构体包括相应子内存区域的指针,以及子内存区域在子内存区域列表中的索引标识。
在一些可选的实施方式中,划分用于独立管理内核空间CXL内存的CXL内存分配区,还包括:
对内存区域管理头文件中的内存区域结构体新增变量;新增的变量包括:空闲子内存区域队列结构体、子内存区域列表、子内存区域数量和当前已分配子内存区域的索引标识。
在一些可选的实施方式中,根据调用请求对CXL内存分配区中的内存空间进行分配处理,包括:
从空闲子内存区域的链表中,拿到下一个子内存区域的索引标识;
根据下一个子内存区域的索引标识,从空闲子内存区域队列结构体中定位到空闲子内存区域,并根据空闲子内存区域进行内存分配。
在一些可选的实施方式中,该方法还包括:
将CXL内存配置选项封装在宏定义中,并在内核配置中选择性地启用宏定义;CXL内存配置选项包括对操作系统内核的修改代码、新增的函数、变量中的至少一种。
第三方面,本申请提供了一种计算机设备,包括:存储器和处理器,存储器和处理器之间互相通信连接,存储器中存储有计算机指令,处理器通过执行计算机指令,从而执行上述第一方面或其对应的任一实施方式的内存分配方法。
第三方面,本申请提供了一种计算机非暂时可读存储介质,该计算机非暂时可读存储介质上存储有计算机指令,计算机指令用于使计算机执行上述第一方面或其对应的任一实施方式的内存分配方法。
第四方面,本申请提供了一种计算机程序产品,包括计算机指令,计算机指令用于使计算机执行上述第一方面或其对应的任一实施方式的内存分配方法。
本申请定义专门用于分配CXL内存的专用API(Application Programming Interface,应用程序接口),用户通过调用专用API即可实现对CXL内存的分配,此时不会向用户分配本地内存,从而可以保证用户能够稳定地使用CXL内存;并且,通过定义专用API的方式,用户在需要分配CXL内存时,只需修改调用的API,用户侧的代码修改量较小,可以降低因修改代码带来的人力成本。
附图说明
为了更清楚地说明本申请具体实施方式或相关技术中的技术方案,下面将对具体实施方式或相关技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图是本申请的一些实施方式,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1是根据本申请实施例的内存分配方法的流程示意图;
图2是根据本申请实施例的另一内存分配方法的流程示意图;
图3是根据本申请实施例的通过选定内存分配池进行内存分配的过程示意图;
图4是根据本申请实施例的向内核传递内存映射标志的过程示意图;
图5是根据本申请实施例的再一内存分配方法的流程示意图;
图6是根据本申请实施例的操作系统内核层次化逻辑内存视图;
图7是根据本申请实施例的实现内存分配的整体过程示意图;
图8是根据本申请实施例的内存分配装置的结构框图;
图9是本申请实施例的计算机设备的硬件结构示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚,下面将结合本申请实施例中的附图,对本申请实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本申请一部分实施例,而不是全部的实施例。基于本申请中的实施例,本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本申请保护的范围。
CXL(Compute Express Link,意为计算快速连接)技术,是一种全新的设备互连技术标准。基于CXL技术可以实现计算、内存、存储和网络的解耦,并在CXL总线上提供持久内存。其中,CXL的关键特征在于,支持缓存一致的内存访问语义(Cache-coherent Load/Store,缓存一致加载/存储)。CXL不仅支持内存子系统的容量和带宽扩展,而且可用于异构处理器与GPU(Graphics Processing Unit,图形处理器)、智能网卡等外围设备之间互连,实现计算资源和内存资源解耦及池化。
CXL提供了百纳秒的高速互连技术,CXL协议规定的类型3(type 3)型设备,就是CXL内存模组或者CXL内存分配池,即CXL内存。该设备可以扩展内存容量、提高内存资源访问带宽,同时,CXL内存模组不占用服务器上的内存插槽。CXL内存的形态主要有三种:E3.S外形的内存模组、ASIC(Application Specific Integrated Circuit,专用集成电路)内存卡、JBOM(内存盒子);其中,ASIC内存卡一般插在服务器PCIe(Peripheral Component Interconnect express,一种高速串行计算机扩展总线标准)槽位上,然后再向卡上插若干条DDR(Double Data Rate,双倍速率)内存,如4条、8条等。
CXL内存相比传统的DDR内存,有以下几个特点:
1)时延:E3.S内存模组和ASIC内存卡的时延是本地DDR内存的2倍,本地内存约100ns,CXL内存约200ns-250ns。两种内存时延差了2倍以上,对应用性能会造成实际的影响,需要分层使用。而JBOM+CXL 2.0交换机的时延更高,达500ns,约是本地内存时延的5倍。
2)容量:CXL内存不占用DIMM(Dual-Inline-Memory-Modules,双列直插式存储模块)槽位和CPU(Central Processing Unit,中央处理器)的内存通道(channel),可以实现容量扩展。
3)带宽:CXL内存不占用DIMM槽位和CPU的内存通道,可以实现带宽扩展。
在一台服务器上同时使用普通本地内存(例如DDR内存)和CXL内存会存在性能不稳定的问题。可选地,当用户向操作系统申请内存空间时,例如,用户使用malloc函数(C语言,动态内存分配函数)向操作系统申请内存空间,操作系统会根据自己的策略向用户提供内存。但是,由于操作系统并不会区分普通本地内存和CXL内存,因此当用户申请到的内存是CXL内存时,访问速度会变慢。从总体上看,用户在访问内存的时候有时快有时慢,快慢的时延会超过2倍以上。
本申请实施例提供的内存分配方法,向用户定义了专门用于分配CXL内存的应用程序接口,用户通过调用该应用程序接口即可请求分配CXL内存,此时不会向用户分配本地内存,从而可以保证用户能够稳定地使用CXL内存。
根据本申请实施例,提供了一种内存分配方法实施例,需要说明的是,在附图的流程图示出的步骤可以在诸如一组计算机可执行指令的计算机系统中执行,并且,虽然在流程图中示出了逻辑顺序,但是在某些情况下,可以以不同于此处的顺序执行所示出或描述的步骤。
在本实施例中提供了一种内存分配方法,可应用于需要进行内存分配的设备,例如终端、服务器等;可选地,该方法可依托于用于进行内存分配的存储软件(例如,内存软件)实现。图1是根据本申请实施例的内存分配方法的流程图,如图1所示,该流程包括以下步骤。
步骤S101,定义用于分配CXL内存的专用应用程序接口。
在用户需要分配内存时,例如需要申请内存时,可以通过调用存储软件提供的应用程序接口(Application Programming Interface,API)实现内存分配,为方便描述,将该应用程序接口称为标准应用程序接口,后续简称为标准API。当服务器上同时存在本地内存(例如DDR内存)和CXL内存时,若基于该标准API进行内存分配,则操作系统并不会区分本地内存和CXL内存;当用户申请到本地内存时,访问速度较快,而当申请到CXL内存时,访问速度较慢,从而导致访问速度忽快忽慢的问题,导致内存性能不稳定。
本实施例中,向用户定义专门用于分配CXL内存的应用程序接口,即专用应用程序接口,后续简称为专用API。当用户使用该专用API进行内存分配时,即可确定当前需要分配CXL内存。
需要说明的是,本实施例中对内存的“分配”,指的是申请内存、释放(回收)内存、内存初始化、内存扩容、内存缩容、内存对齐等中的任意一种或多种操作,具体可基于实际情况而定。
步骤S102,获取调用应用程序接口的调用请求。
当用户需要分配内存时,即可通过调用应用程序接口,发起调用请求;例如,用户的应用程序需要申请一段内存时,则可调用应用程序接口中用于申请内存的函数。
本实施例中,由于设有用于分配CXL内存的专用API,故当用户需要调用CXL内存时,可以调用该专用API,具体可以调用专用API中相应的函数,以完成所需的内存分配需求。并且,仍然保留有标准API,即仍然对外提供标准API;当用户并不需要刻意分配CXL内存时,即可仍然调用该标准API。
例如,当用户需要大量内存空间,且对性能要求没有那么高的时候,用户可以直接向操作系统申请CXL内存,即调用专用API;而当用户需要少量内存,且要求高性能时(例如要求低时延),则可以使用自带的标准API。
步骤S103,在调用请求用于调用专用应用程序接口的情况下,生成表示分配CXL内存的CXL内存标识。
本实施例中,在用户态,基于调用请求调用哪一应用程序接口,即可确定当前的调用请求是否用于调用专用应用程序接口。例如,若用户当前调用的内存分配函数是专用API中的函数,则可确定用户当前在调用专用API,即用户当前请求分配CXL内存。
若用户发起的调用请求用于调用专用API,则可确定用户当前请求分配CXL内存,在这种情况下,生成相应的标识,以该标识表示当前需要分配CXL内存;为方便描述,将该标识称为CXL内存标识(MAP_CXLMEM)。其中,可以用某标志位表示该CXL内存标识(MAP_CXLMEM),即以不同的数值表示是否需要分配CXL内存。
可以理解,当用户并不需要制定分配的内存是CXL内存时,例如用户当前需要分配普通本地内存(例如DDR内存)时,仍然可以按照调用标准API的方式进行调用,用户不需要修改调用标准API的程序代码,此时向用户分配的内存一般是混合内存,即包括本地内存和CXL内存。当用户需要分配CXL内存时,只需要修改所调用的API即可,即修改应用程序内与API调用相关部分的代码,将原本的标准API修改为该专用API,用户侧的代码修改量较小。
步骤S104,通过内存映射接口,将CXL内存标识传递至内核态,并在内核态分配与CXL内存相关的硬件资源。
本实施例中,在用户态获取到调用请求,并确定该调用请求是否用于调用专用API时,是在用户态生成该CXL内存标识(MAP_CXLMEM),为能够操作硬件资源的CXL内存,需要将该CXL内存标识(MAP_CXLMEM)传递至内核态。
可选地,通过操作系统的内存映射接口,即mmap接口,把分配CXL内存的标识(即CXL内存标识)带到操作系统内核,例如Linux内核;一般情况下,基于内存分配器(例如,jemalloc)实现用户态的内存管理,并向下可以通过内存映射接口进行系统调用,从而可以访问Linux内核。
本实施例提供的内存分配方法,定义专门用于分配CXL内存的专用API,用户通过调用专用API即可实现对CXL内存的分配,此时不会向用户分配本地内存,从而可以保证用户能够稳定地使用CXL内存;并且,通过定义专用API的方式,用户在需要分配CXL内存时,只需修改调用的API,用户侧的代码修改量较小,可以降低因修改代码带来的人力成本。
在本实施例中提供了一种内存分配方法,可应用于需要进行内存分配的设备,图2是根据本申请实施例的内存分配方法的流程图,如图2所示,该流程包括以下步骤。
步骤S201,定义用于分配CXL内存的专用应用程序接口。
详细请参见图1所示实施例的步骤S101,在此不再赘述。
在一些可选的实施方式中,上述步骤S201“定义用于分配CXL内存的专用应用程序接口”,包括:按照相同修改规则,对标准应用程序接口的函数名进行修改,将修改后的函数名作为专用应用程序接口中的函数名;该标准应用程序接口用于分配内存。
本实施例中,当需要进行内存分配时,一般调用内存分配器提供的标准API;例如,用户正常访问内存是通过jemalloc库提供的标准API中的malloc函数。其中,正常基于C语言申请、释放内存的标准API,其部分内存分配函数可参见下表1所示。
表1
本实施例中,在定义专用API时,在标准API的基础上进行修改,以得到所需的专用API。可选地,在标准API中函数的基础上,对函数名进行修改,并将修改后的函数名作为专用API中相应函数的函数名;并且,对于不同的函数名,使用统一的修改规则进行修改,使得专用API中的函数名与标准API中的函数名相对应。
其中,修改函数名的修改规则可以是:为原函数名增加前缀或后缀。例如,可以在原有函数名的基础上增加前缀“in”,从而生成专用API中的函数名。可选地,对于标准API中的申请内存函数malloc,为其增加前缀“in”,从而可以生成专用API中的申请内存函数“in_malloc”,类似地,对于标准API中的重分配内存函数realloc、回收内存函数free等,也可生成专用API中的重分配内存函数in_realloc、回收内存函数in_free。
用户当前申请本地内存(调用标准API),若此时需要改为申请CXL内存,则只需要修改所调用API的函数名即可,即为原本调用的API的函数名增加前缀“in”,即可改为调用专用API,从而改为申请CXL内存,用户侧代码修改量较少。
此外可选地,本实施例中,还为专用应用程序接口定义多种用于返回相应参数的获取函数,这些获取函数可以包括以下获取函数中的至少一种:
用于获取请求的CXL内存区域总量(即总字节数)的第一获取函数;该第一获取函数可以为下表2所示的in_get_memsize_total。
用于获取通过客户端开发包分配的CXL内存区域总量的第二获取函数;该第二获取函数可以为下表2所示的in_get_memsize_used。
用于获取指定CXL内存区域可用字节数的第三获取函数;该第三获取函数可以为下表2所示的in_get_memsize_available。
用于获取指定内存节点中CXL内存区域总量的第四获取函数;该第四获取函数可以为下表2所示的in_get_memsize_node_total。
用于获取指定内存节点中CXL内存区域可用字节数的第五获取函数;该第五获取函数可以为下表2所示的in_get_memsize_node_available。
用于获取多个CXL内存区域的状态数据的第六获取函数;该第六获取函数可以为下表2所示的in_stats_print。其中,该状态数据可以包括内存总量、已用内阻字节数、可用内存字节数。
用于获取多个内存节点下、相应CXL内存区域的状态数据的第七获取函数;该第七获取函数可以为下表2所示的in_stats_node_print。
本实施例定义的专用API,其包括的函数可参见下表2所示。
表2
步骤S202,划分用于分配用户态的CXL内存的第一内存分配池,以及用于分配用户态的本地内存的第二内存分配池。
其中,内存分配器中的内存分配池(arena_pool)一般只有一种;例如,内存分配器jemalloc中只有一个内存分配池jemalloc_arena_pool;本实施例中,对内存分配池进行扩展,扩展成两种内存分配池,其中一种用于分配用户态的CXL内存,后续将该内存分配池称为第一内存分配池(cxlmem_arena_pool),另一种用于分配用户态的本地内存,后续将该内存分配池称为第二内存分配池(normal_arena_pool)。
可选地,上述步骤S202“划分用于分配用户态的CXL内存的第一内存分配池,以及用于分配用户态的本地内存的第二内存分配池”,可以包括:为处理器的每个核分配多个内存分配池,其中部分内存分配池作为用于分配用户态的CXL内存第一内存分配池,另一部分内存分配池作为用于分配用户态的本地内存的第二内存分配池。例如,可以平均划分为处理器核分配的多个内存分配池,即第一内存分配池和第二内存分配池的数量一致。
初始化时,可以设置每种内存分配池(arena_pool)的数量。例如,原始的内存分配器,一般为每个处理器核(CPUcore)配置4个内存分配池;本实施例中,为每个处理器核配置8个内存分配池,其中四个用于分配CXL内存,即作为第一内存分配池(cxlmem_arena_pool),另外四个用于分配本地内存,即作为第二内存分配池(normal_arena_pool)。因此,对于标准API来说,因为在同一时刻只能在第一内存分配池和第二内存分配池中二选一,所以修改后的内存分配池的运行时数量和原始内存分配器的内存分配池一样。但是对于CXL内存的专用API来说,用户应用程序可以并行分配本地内存和CXL内存,也就是可以同时使用两种内存分配池。
步骤S203,获取调用应用程序接口的调用请求。
详细请参见图1所示实施例的步骤S102,在此不再赘述。
步骤S204,在调用请求用于调用专用应用程序接口的情况下,生成表示分配CXL内存的CXL内存标识。
详细请参见图1所示实施例的步骤S103,在此不再赘述。
步骤S205,在调用请求用于调用专用应用程序接口的情况下,选定第一内存分配池,根据调用请求对第一内存分配池中的内存空间进行分配处理,以分配用户态的CXL内存。
本实施例中,可以基于内存分配器接口获取到相应的调用请求,基于该调用请求选择合适的内存分配池。可选地,若用户发起的调用请求用于调用专用API,例如调用请求中调用的内存分配函数具有前缀in,则选定第一内存分配池;相反地,若调用请求是调用标准API,则可以调用第二内存分配池。
在选定相应的内存分配池后,即可根据调用请求对选定的内存分配池中的内存空间进行分配处理,例如,申请、回收相应的内存空间。
可选地,上述步骤S205“根据调用请求对第一内存分配池中的内存空间进行分配处理”可以包括以下步骤A1至步骤A3。
步骤A1,确定与调用请求相对应的内存分配函数。
调用请求中包括相应API的内存分配函数,基于此可以确定内存分配器所需要的内存分配函数。例如,调用请求用于申请一段内存空间,其内存分配函数为malloc函数,则与其对应的是内存分配器中用于申请内存的内存分配函数,例如je_mallocx。
步骤A2,在内存分配函数中新增用户态的内存映射标志,并根据CXL内存标识对内存映射标志进行赋值;内存映射标志用于表示是否分配CXL内存。
本实施例中,在内存分配器的内存分配函数中,新增用于表示是否分配CXL内存的标志(flag),即内存映射标志(arena_mmap_flag);在生成CXL内存标识(MAP_CXLMEM)后,即可将CXL内存标识(MAP_CXLMEM)赋值给内存映射标志(arena_mmap_flag);例如,arena_mmap_flag=MAP_CXLMEM。类似地,若当前的调用请求是调用标准API,也可以设置表示分配本地内存的本地内存标识(MAP_NORMAL),并将其赋值给内存映射标志(arena_mmap_flag);例如,arena_mmap_flag=MAP_NORMAL。
可选地,上述步骤A1“在内存分配函数中新增用户态的内存映射标志”包括步骤A11。
步骤A11,在内存分配池的在内存分配结构体中新增用户态的内存映射标志。
其中,内存分配池一般设有用于进行内存分配的数据结构,即内存分配结构体(arena_s);本实施例中,对内存分配池的数据结构进行了扩展,即为其增加一个标志(flag),即用户态的内存映射标志(arena_mmap_flag),以能够在用户态区分该内存分配池是本地内存还是CXL内存。例如,在alloc_core函数中,通过arena_s的arena_mmap_flag判断本次是分配本地内存还是CXL内存,并最终生成给内核的参数flag,使得内核可以分配相应的内存。该过程可参见图3所示。
可以理解,内存分配池的其余内容是不变的,例如其余的数据结构、内存管理机制、内存分配方法等。
可选地,还可以新增用于设置内存映射标志(arena_mmap_flag)的设置函数,例如arena_set_mmap_flag,且还可以新增用于获取内存映射标志(arena_mmap_flag)的获取函数,例如arena_get_mmap_flag。可选地,该方法还包括以下步骤B1至步骤B2。
步骤B1,预设用于设置内存映射标志的设置函数。
步骤B2,在新建内存分配池时,调用设置函数,为新建内存分配池的内存映射标志设为默认值;默认值表示分配本地内存(MAP_NORMAL)。
并且,上述步骤A2“根据CXL内存标识对内存映射标志进行赋值”可以包括:调用设置函数,将CXL内存标识赋值给内存映射标志。
本实施例中,在新建内存分配池时,可以基于初始化函数init_arena_pool调用该设置函数arena_set_mmap_flag,在进行初始化时将内存映射标志(arena_mmap_flag)设为默认的本地内存标识(MAP_NORMAL),即arena_mmap_flag=MAP_NORMAL。换句话说,默认基于传统的分配方式向用户分配内存。并且,当用户基于专用API进行内存分配时,也可以使用新增的设置函数为内存映射标志进行赋值。
步骤A3,根据内存分配函数对第一内存分配池中的内存空间进行分配处理。
在确定内存分配器的内存分配函数之后,即可基于该内存分配函数对第一内存分配池中的内存空间进行分配处理,例如申请、回收第一内存分配池等。
步骤S206,通过内存映射接口,将CXL内存标识传递至内核态,并在内核态分配与CXL内存相关的硬件资源。
详细请参见图1所示实施例的步骤S104,在此不再赘述。
可选地,对内存分配器的修改,一方面使其支持新的专用API,另一方面能通过操作系统的内存映射接口,把使用CXL内存的标识带到内核。为能够将CXL内存标识传递至内核,本实施例中,基于使用哪一种内存分配池,并利用内存管理文件(extent.c)进行传参。可选地,上述步骤S206“通过内存映射接口,将CXL内存标识传递至内核态”,包括步骤C1至步骤C3。
步骤C1,基于内存管理文件中的内存分配核函数,调用用于获取内存映射标志的获取函数,获取到内存映射标志。
本实施例中,内存分配器中设有内存管理文件,即extent.c,其中设有内存分配核函数,即extent_alloc_core;基于内存分配核函数extent_alloc_core从内存分配池中获取到相应的内存映射标志。可选地,可以调用新增的获取函数arena_get_mmap_flag,基于该获取函数arena_get_mmap_flag获取到当前的内存映射标志。
步骤C2,设置内存映射标志传递函数,根据内存映射标志传递函数对内存映射标志进行传参。
本实施例中,在获取到内存映射标志后,可以利用内存管理文件extent.c中的内存映射标志传递函数extent_alloc_mmap_flag进行传参。可选地,在传递内存映射标志时,可以将内存映射标志(arena_mmap_flag)合并至表示交织策略的局部变量(interleave_policy);进而根据内存映射标志传递函数extent_alloc_mmap_flag对该局部变量(interleave_policy)进行传参。
步骤C3,在内存页文件的操作系统内存页映射函数中增加内存映射标志,以将内存映射标志传递至内核的内存映射接口。
其中,内存分配器中设有内存页文件,即pages.c。可以对内存映射标志进行合并,例如对包括内存映射标志的局部变量以及其他额外标识进行合并,之后合并后的标识传参给内存页文件pages.c中的操作系统内存页映射函数,即os_pages_map_flag,在该操作系统内存页映射函数os_pages_map_flag中增加相应的标识,从而可以将内存映射标志传递至内核的mmap接口。例如,可以在操作系统内存页映射函数os_pages_map_flag中新增MAP_JEMALLOC_INTERNAL_MMAP,并传递给内核mmap接口,实现标识传参。其中,该传参过程可参见图4所示。
本实施例提供的内存分配方法,定义专门用于分配CXL内存的专用API,用户通过调用专用API即可实现对CXL内存的分配,此时不会向用户分配本地内存,从而可以保证用户能够稳定地使用CXL内存;并且,通过定义专用API的方式,用户侧的代码修改量较小,可以降低因修改代码带来的人力成本。在用户态划分第一内存分配池和第二内存分配池,从而可以适应性地对CXL内存进行分配;在内存分配函数中新增用户态的内存映射标志,可以有效响应用户调用专用API的情况;利用内存管理文件对内存映射标志进行传参,可以解决难以直接向内核传递标识的问题。
在本实施例中提供了一种内存分配方法,可应用于需要进行内存分配的设备,图5是根据本申请实施例的内存分配方法的流程图,如图5所示,该流程包括以下步骤。
步骤S501,定义用于分配CXL内存的专用应用程序接口。
详细请参见图1所示实施例的步骤S101,在此不再赘述。
步骤S502,获取调用应用程序接口的调用请求。
详细请参见图1所示实施例的步骤S102,在此不再赘述。
步骤S503,在调用请求用于调用专用应用程序接口的情况下,生成表示分配CXL内存的CXL内存标识。
详细请参见图1所示实施例的步骤S103,在此不再赘述。
步骤S504,通过内存映射接口,将CXL内存标识传递至内核态。
详细请参见图1所示实施例的步骤S104,在此不再赘述。
步骤S505,划分用于独立管理内核空间CXL内存的CXL内存分配区。
由于本地内存和CXL内存,这两种内存设备的硬件控制器的频率范围、协议、功能等都不一样,需要对这两种内存设备进行区分。本实施例中,引入一个新的内存分配区,该内存分配区用于独立管理内核空间的CXL内存,为方便描述,将该内存分配区称为CXL内存分配区(CXLMem_zone)。
图6示出了操作系统内核的虚拟机管理器(VMM)中,一种层次化的逻辑内存视图,该视图覆盖内存节点(node)、内存区域(zone)、内存组(buddy)和内存页多种粒度。根据硬件和软件的需求,虚拟机管理器扩展了多种内存区域作为内存分配区。例如,Linux VMM已经扩展了zone,以能够更好地利用物理内存,如DMA(Direct Memory Access,直接内存存取)/DMA32 Zone、MOVABLE(可移动)Zone、NORMAL(正常)Zone等。其中,DMA/DMA2 Zone包括一些列的IO(Input/Output,输入/输出)设备页地址空间,这些地址空间比较有限;MOVABLE Zone的目标是减少碎片,并支持内存的热插拔;一般情况下,系统和应用使用的多是NORMAL Zone,即绝大多数的DRAM(动态随机存取存储器)页都属于NORMAL Zone。
本实施例中,在保留本地内存分配区(例如,NORMAL Zone)的基础上,在内核态还新增CXL内存分配区(CXLMem_zone),用于对CXL内存进行分配管理。
在一些可选的实施方式,上述步骤S505“划分用于独立管理内核空间CXL内存的CXL内存分配区”包括以下步骤D1至步骤D2。
步骤D1,在操作系统内核的内存区域管理头文件的内存区域类型(enum zone_type)中新增CXL内存分配区(CXLMem_zone)对应的类型(ZONE_CXLMEM)。
对于操作系统内核,例如Linux内核,其设有内存区域管理头文件mmzone.h;内存区域管理头文件mmzone.h是Linux内核中负责内存区域管理的头文件;其中,内存区域管理是Linux内核内存管理的核心部分,主要负责管理系统的物理内存和交换空间。其中定义有已有内存分配区的类型,即内存区域类型(enum zone_type)。例如,本地内存分配区NORMAL Zone的内存区域类型为ZONE_NORMAL。本实施例中,在该内存区域管理头文件mmzone.h的内存区域类型中,新增该CXL内存分配区(CXLMem_zone)对应的类型,例如,新增ZONE_CXLMEM。
可选地,为便于按需开启专门分配CXL的功能,本实施例中,对于与CXL内存相关的操作系统内核的修改代码、新增的函数、变量等CXL内存配置选项(CONFIG_CXLMEM),均将其封装在宏定义中,从而可以在内核配置中选择性地启用相应的宏定义。
使用宏定义来设置CXL内存配置选项的代码具体如下:
#ifdef CONFIG_CXLMEM
修改的代码、新增的函数和变量
#endif
例如,上述设置的CXL内存分配区的内存区域类型属于操作系统内核的修改代码,故可以基于宏定义新增CXL内存分配区的内存区域类型。
步骤D2,扩展内核态的内存映射系统调用接口,为内存映射系统调用接口增加表示映射CXL内存的标志以及表示映射本地内存的标志。
本实施例中,对内核态的内存映射(mmap)系统调用接口进行扩展,扩展方式是为其增加标志(flag),以区分调用本地内存还是CXL内存。其中,可以为内存映射系统调用接口增加表示映射CXL内存的标志,例如上述的CXL内存标识MAP_CXLMEM,以及表示映射本地内存的标志,例如上述的本地内存标识MAP_NORMAL。
此外可选地,上述步骤S505“划分用于独立管理内核空间CXL内存的CXL内存分配区”,还可以包括以下步骤D3。
步骤D3,在内存区域管理头文件中新增子内存区域结构体,每个子内存区域结构体对应一条CXL内存。该子内存区域结构体包括内存区域数据、内存起始地址和内存结束地址;其中,内存区域数据是在已有内存分配区(zone)的基础上兼容生成的。
本实施例中,由于在硬件层面一般包括多条CXL内存,而内核态的CXL内存分配区(CXLMem_zone),其对应多条CXL内存;为能够以CXL内存为单位进行内存分配,将一条CXL内存对应的内存区域称为子内存区域(subzone),并为其新增了相应的结构体,即子内存区域结构体(也可称为:subzone结构体)。
可选地,在内存区域管理头文件mmzone.h中新增子内存区域结构体,即subzone结构体,每个subzone结构体代表一条CXL内存,从而可以支持多条CXL内存。
并且,该子内存区域结构体包括内存区域数据zone_dat、内存起始地址start_pfn和内存结束地址end_pfn;可以理解,这里的内存指的均是CXL内存。并且,该内存区域数据zone_dat是在已有内存分配区(zone)的基础上兼容生成的,例如,可以在原来内核设计的内存分配区(zone)的基础上,通过在内存分配区(zone)外面包装一层subzone的方式,构建内存区域数据zone_dat,从而可以兼容之前内核的设计。
在基于调用请求分配CXL内存时,可以基于该subzone结构体表示需要分配的CXL内存,已对相应的CXL内存进行申请、回收等。
此外,还可以新增用于增加子内存区域的函数add_subzone,以及用于去除子内存区域的函数remove_subzone,本实施例对此不作详述。
可以理解,该子内存区域结构体是一种新增的CXL内存配置选项,故也可以通过宏定义的方式,在内存区域管理头文件mmzone.h中新增该子内存区域结构体。
可选地,上述步骤S505“划分用于独立管理内核空间CXL内存的CXL内存分配区”,还可以包括以下步骤D4。
步骤D4,在内存区域管理头文件中新增子内存区域索引结构体;该子内存区域索引结构体包括相应子内存区域的指针,以及子内存区域在子内存区域列表(subzonelist)中的索引标识(subozne_idx)。
本实施例中,为了能够比较好地指代每一个子内存区域subzone,除了新增子内存区域结构体之外,还新增子内存区域索引结构体,可简称为subzoneref结构体。其中,与新增子内存区域结构体相似,在内存区域管理头文件mmzone.h中新增该子内存区域索引结构体,即subzoneref结构体。
其中,该子内存区域索引结构体包括相应子内存区域的指针;并且,以子内存区域列表subzonelist表示所有的子内存区域subzone,该子内存区域索引结构体还包括相应子内存区域在该子内存区域列表subzonelist中的索引标识;例如,该索引标识为ID,可以以subozne_idx表示该索引标识的变量名。
可以理解,该子内存区域索引结构体也是一种新增的CXL内存配置选项,故也可以通过宏定义的方式,在内存区域管理头文件mmzone.h中新增该子内存区域索引结构体。
可选地,上述步骤S505“划分用于独立管理内核空间CXL内存的CXL内存分配区”,还可以包括以下步骤D5。
步骤D5,对内存区域管理头文件中的内存区域结构体新增变量;新增的变量包括:空闲子内存区域队列结构体、子内存区域列表(subzonelist)、子内存区域数量(nr_subzones)和当前已分配子内存区域的索引标识(cur_subzone_idx)。
内存区域管理头文件mmzone.h中设有内存区域结构体,即struct zone,其是表示内存区域(zone)的关键数据结构。本实施例中,在内存区域结构体struct zone中新增与子内存区域subzone相关的变量。
可选地,在内存区域结构体struct zone中新增一种关键结构体,即空闲子内存区域队列结构体。其中,原来Linux设计的空闲内存队列(例如本地内存的空闲队列)叫free_area,为便于实现统一的CXL内存管理,将相应的空闲内存队列free_area都配合修改为空闲子内存区域队列的结构体,其变量名为free_area_subzone。本实施例中,为CXL内存引入新的free_area_subzone结构体数组,并根据是否是CXL内存区域来选择合适的空闲内存队列。例如,在需要使用空闲内存队列的地方,可以根据是否是CXL内存区域来选择使用free_area还是free_area_subzone。
并且,该内存区域结构体struct zone还新增有子内存区域列表(subzonel ist,包括所有子内存区域的链表),子内存区域数量(nr_subzones,即所有子内存区域的数量)和当前已分配子内存区域的索引标识(cur_subzone_idx)。其中,内存区域结构体struct zone中新增的变量,可参见下表3所示。
表3
同样地,在对内存区域结构体struct zone新增变量时,也可以基于宏定义的方式配置新增的变量。
步骤S506,根据调用请求对CXL内存分配区中的内存空间进行分配处理,以分配与CXL内存相关的硬件资源。
其中,基于标准API、专用API实现内存分配的框图如图7所示;用户态的内存分配器基于内存映射接口实现传参后,在内核态基于当前需求使用相应的内存分配区,从而对相应类型的内存进行分配,即在内核态分配与CXL内存相关的硬件资源。
可选地,上述步骤S506“根据调用请求对CXL内存分配区中的内存空间进行分配处理”可以包括:从空闲子内存区域的链表中,拿到下一个子内存区域的索引标识;根据下一个子内存区域的索引标识,从空闲子内存区域队列结构体中定位到空闲子内存区域,并根据空闲子内存区域进行内存分配。
本实施例中,为实现对新增的CXL内存分配区(CXLMem_zone)的初始化,可以修改内核的mm_init.c文件,扩展zone_init_free_lists。其中,如果当前的内存分配区是CXL内存分配区(CXLMem_zone),则可以使用新定义的空闲子内存区域队列的结构体free_area_subzone,初始化内核的INIT_LIST_HEAD,完成初始化。
若用户调用的是专用API,则当前需要分配新增的CXL内存分配区(CXLMem_zone),此时,可以确定下一个子内存区域(即当前已分配子内存区域的后一个子内存区域)的索引标识;例如,可以为新增的子内存区域subzone设置get_next_subzone_id函数,基于该get_next_subzone_id函数,从空闲子内存区域的链表中拿到下一个子内存区域的索引标识。之后,即可根据下一个子内存区域的索引标识,从空闲子内存区域队列结构体中定位到空闲子内存区域,并根据该空闲子内存区域进行内存分配,即根据下一个子内存区域进行内存分配。
本实施例提供的内存分配方法,定义专门用于分配CXL内存的专用API,用户通过调用专用API即可实现对CXL内存的分配,以保证用户能够稳定地使用CXL内存且用户侧的代码修改量较小,可以降低因修改代码带来的人力成本。在内核态新增CXL内存分配区,从而可以专门对CXL内存进行管理;新增subzone结构体和subzoneref结构体,在对CXL内存进行分配时,能够以一条CXL内存为单位进行分配,可以满足用户需求;以宏定义的方式对修改的代码等CXL内存配置选项进行配置,可以方便地开启或关闭CXL内存分配功能,在用户调用标准API时,不会影响分配本地内存的过程。
在本实施例中还提供了一种内存分配装置,该装置被配置为实现上述实施例及可选实施方式,已经进行过说明的不再赘述。如以下所使用的,术语“模块”可以是实现预定功能的软件,和/或,硬件的组合。尽管以下实施例所描述的装置较佳地以软件来实现,但是硬件,或者软件和硬件的组合的实现也是可能并被构想的。
本实施例提供一种内存分配装置,如图8所示,包括:
接口定义模块801,被配置为定义用于分配CXL内存的专用应用程序接口;
获取模块802,被配置为获取调用应用程序接口的调用请求;
处理模块803,被配置为在调用请求用于调用专用应用程序接口的情况下,生成表示分配CXL内存的CXL内存标识;
传参分配模块804,被配置为通过内存映射接口,将CXL内存标识传递至内核态,并在内核态分配与CXL内存相关的硬件资源。
在一些可选的实施方式中,接口定义模块801定义用于分配CXL内存的专用应用程序接口,包括:
按照相同修改规则,对标准应用程序接口的函数名进行修改,将修改后的函数名作为专用应用程序接口中的函数名;标准应用程序接口用于分配内存。
在一些可选的实施方式中,接口定义模块801定义用于分配CXL内存的专用应用程序接口,还包括:
为专用应用程序接口定义:用于获取请求的CXL内存区域总量的第一获取函数、用于获取通过客户端开发包分配的CXL内存区域总量的第二获取函数、用于获取指定CXL内存区域可用字节数的第三获取函数、用于获取指定内存节点中CXL内存区域总量的第四获取函数、用于获取指定内存节点中CXL内存区域可用字节数的第五获取函数、用于获取多个CXL内存区域的状态数据的第六获取函数、用于获取多个内存节点下、相应CXL内存区域的状态数据的第七获取函数中的至少一种。
在一些可选的实施方式中,该装置还包括划分模块,被配置为:划分用于分配用户态的CXL内存的第一内存分配池,以及用于分配用户态的本地内存的第二内存分配池;
处理模块803还被配置为,在调用请求用于调用专用应用程序接口的情况下,选定第一内存分配池;根据调用请求对第一内存分配池中的内存空间进行分配处理,以分配用户态的CXL内存。
在一些可选的实施方式中,处理模块803根据调用请求对第一内存分配池中的内存空间进行分配处理,包括:
确定与调用请求相对应的内存分配函数;
在内存分配函数中新增用户态的内存映射标志,并根据CXL内存标识对内存映射标志进行赋值;内存映射标志用于表示是否分配CXL内存;
根据内存分配函数对第一内存分配池中的内存空间进行分配处理。
在一些可选的实施方式中,处理模块803在内存分配函数中新增用户态的内存映射标志,包括:
在内存分配池的在内存分配结构体中新增用户态的内存映射标志。
在一些可选的实施方式中,还包括初始化模块,被配置为:预设用于设置内存映射标志的设置函数;在新建内存分配池时,调用设置函数,为新建内存分配池的内存映射标志设为默认值;默认值表示分配本地内存;
处理模块803根据CXL内存标识对内存映射标志进行赋值,包括:调用设置函数,将CXL内存标识赋值给内存映射标志。
在一些可选的实施方式中,传参分配模块804通过内存映射接口,将CXL内存标识传递至内核态,包括:
基于内存管理文件中的内存分配核函数,调用用于获取内存映射标志的获取函数,获取到内存映射标志;
设置内存映射标志传递函数,根据内存映射标志传递函数对内存映射标志进行传参;
在内存页文件的操作系统内存页映射函数中增加内存映射标志,以将内存映射标志传递至内核的内存映射接口。
在一些可选的实施方式中,传参分配模块804根据内存映射标志传递函数对内存映射标志进行传参,包括:
将内存映射标志合并至表示交织策略的局部变量;
根据内存映射标志传递函数对局部变量进行传参。
在一些可选的实施方式中,划分模块划分用于分配用户态的CXL内存的第一内存分配池,以及用于分配用户态的本地内存的第二内存分配池,包括:
为处理器的每个核分配多个内存分配池,其中部分内存分配池作为用于分配用户态的CXL内存第一内存分配池,另一部分内存分配池作为用于分配用户态的本地内存的第二内存分配池。
在一些可选的实施方式中,传参分配模块804在内核态分配与CXL内存相关的硬件资源,包括:
划分用于独立管理内核空间CXL内存的CXL内存分配区;
根据调用请求对CXL内存分配区中的内存空间进行分配处理,以分配与CXL内存相关的硬件资源。
在一些可选的实施方式中,传参分配模块804划分用于独立管理内核空间CXL内存的CXL内存分配区,包括:
在操作系统内核的内存区域管理头文件的内存区域类型中新增CXL内存分配区对应的类型;
扩展内核态的内存映射系统调用接口,为内存映射系统调用接口增加表示映射CXL内存的标志以及表示映射本地内存的标志。
在一些可选的实施方式中,传参分配模块804划分用于独立管理内核空间CXL内存的CXL内存分配区,还包括:
在内存区域管理头文件中新增子内存区域结构体,每个子内存区域结构体对应一条CXL内存;
子内存区域结构体包括内存区域数据、内存起始地址和内存结束地址;其中,内存区域数据是在已有内存分配区的基础上兼容生成的。
在一些可选的实施方式中,传参分配模块804划分用于独立管理内核空间CXL内存的CXL内存分配区,还包括:
在内存区域管理头文件中新增子内存区域索引结构体;子内存区域索引结构体包括相应子内存区域的指针,以及子内存区域在子内存区域列表中的索引标识。
在一些可选的实施方式中,传参分配模块804划分用于独立管理内核空间CXL内存的CXL内存分配区,还包括:
对内存区域管理头文件中的内存区域结构体新增变量;新增的变量包括:空闲子内存区域队列结构体、子内存区域列表、子内存区域数量和当前已分配子内存区域的索引标识。
在一些可选的实施方式中,传参分配模块804根据调用请求对CXL内存分配区中的内存空间进行分配处理,包括:
从空闲子内存区域的链表中,拿到下一个子内存区域的索引标识;
根据下一个子内存区域的索引标识,从空闲子内存区域队列结构体中定位到空闲子内存区域,并根据空闲子内存区域进行内存分配。
在一些可选的实施方式中,传参分配模块804被配置为:
将CXL内存配置选项封装在宏定义中,并在内核配置中选择性地启用宏定义;CXL内存配置选项包括对操作系统内核的修改代码、新增的函数、变量中的至少一种。
上述各个模块和单元的更进一步的功能描述与上述对应实施例相同,在此不再赘述。
本实施例中的内存分配装置是以功能单元的形式来呈现,这里的单元是指ASIC(Application Specific Integrated Circuit,专用集成电路)电路,包括执行一个或多个软件或固定程序的处理器和存储器,和/或,其他可以提供上述功能的器件。
本申请实施例还提供一种计算机设备,具有上述图8所示的内存分配装置。
请参阅图9,图9是本申请可选实施例提供的一种计算机设备的结构示意图,如图9所示,该计算机设备包括:一个或多个处理器10、存储器20,以及被配置为连接各部件的接口,包括高速接口和低速接口。各个部件利用不同的总线互相通信连接,并且可以被安装在公共主板上或者根据需要以其它方式安装。处理器可以对在计算机设备内执行的指令进行处理,包括存储在存储器中或者存储器上以在外部输入/输出装置(诸如,耦合至接口的显示设备)上显示GUI(Graphical User Interface,图形用户界面)的图形信息的指令。在一些可选的实施方式中,若需要,可以将多个处理器,和/或,多条总线与多个存储器一起使用。同样,可以连接多个计算机设备,各个设备提供部分必要的操作(例如,作为服务器阵列、一组刀片式服务器、或者多处理器系统)。图9中以一个处理器10为例。
处理器10可以是中央处理器,网络处理器或其组合。其中,处理器10还可以包括硬件芯片。上述硬件芯片可以是专用集成电路,可编程逻辑器件或其组合。上述可编程逻辑器件可以是复杂可编程逻辑器件,现场可编程逻辑门阵列,通用阵列逻辑或其任意组合。
其中,存储器20存储有可由至少一个处理器10执行的指令,以使至少一个处理器10执行实现上述实施例示出的方法。
存储器20可以包括存储程序区和存储数据区,其中,存储程序区可存储操作系统、至少一个功能所需要的应用程序;存储数据区可存储根据计算机设备的使用所创建的数据等。此外,存储器20可以包括高速随机存取存储器,还可以包括非瞬时存储器,例如至少一个磁盘存储器件、闪存器件、或其他非瞬时固态存储器件。在一些可选的实施方式中,存储器20可选包括相对于处理器10远程设置的存储器,这些远程存储器可以通过网络连接至该计算机设备。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
存储器20可以包括易失性存储器,例如,随机存取存储器;存储器也可以包括非易失性存储器,例如,快闪存储器,硬盘或固态硬盘;存储器20还可以包括上述种类的存储器的组合。
该计算机设备还包括通信接口30,被配置为该计算机设备与其他设备或通信网络通信。
本申请实施例还提供了一种计算机可读存储介质,上述根据本申请实施例的方法可在硬件、固件中实现,或者被实现为可记录在存储介质,或者被实现通过网络下载的原始存储在远程存储介质或非暂时机器可读存储介质中并将被存储在本地存储介质中的计算机代码,从而在此描述的方法可被存储在使用通用计算机、专用处理器或者可编程或专用硬件的存储介质上的这样的软件处理。其中,存储介质可为磁碟、光盘、只读存储记忆体、随机存储记忆体、快闪存储器、硬盘或固态硬盘等;可选地,存储介质还可以包括上述种类的存储器的组合。可以理解,计算机、处理器、微处理器控制器或可编程硬件包括可存储或接收软件或计算机代码的存储组件,当软件或计算机代码被计算机、处理器或硬件访问且执行时,实现上述实施例示出的方法。
本申请的一部分可被应用为计算机程序产品,例如计算机程序指令,当其被计算机执行时,通过该计算机的操作,可以调用或提供根据本申请的方法,和/或,技术方案。本领域技术人员应能理解,计算机程序指令在计算机可读介质中的存在形式包括但不限于源文件、可执行文件、安装包文件等,相应地,计算机程序指令被计算机执行的方式包括但不限于:该计算机直接执行该指令,或者该计算机编译该指令后再执行对应的编译后程序,或者该计算机读取并执行该指令,或者该计算机读取并安装该指令后再执行对应的安装后程序。在此,计算机可读介质可以是可供计算机访问的任意可用的计算机可读存储介质或通信介质。
虽然结合附图描述了本申请的实施例,但是本领域技术人员可以在不脱离本申请的精神和范围的情况下做出各种修改和变型,这样的修改和变型均落入由所附权利要求所限定的范围之内。

Claims (20)

  1. 一种内存分配方法,其特征在于,所述方法包括:
    定义用于分配计算快速连接CXL内存的专用应用程序接口;
    获取调用应用程序接口的调用请求;
    在所述调用请求用于调用所述专用应用程序接口的情况下,生成表示分配CXL内存的CXL内存标识;
    通过内存映射接口,将所述CXL内存标识传递至内核态,并在所述内核态分配与CXL内存相关的硬件资源。
  2. 根据权利要求1所述的方法,其特征在于,所述定义用于分配CXL内存的专用应用程序接口,包括:
    按照相同修改规则,对标准应用程序接口的函数名进行修改,将修改后的函数名作为所述专用应用程序接口中的函数名;所述标准应用程序接口用于分配内存。
  3. 根据权利要求2所述的方法,其特征在于,所述定义用于分配CXL内存的专用应用程序接口,还包括:
    为所述专用应用程序接口定义:用于获取请求的CXL内存区域总量的第一获取函数、用于获取通过客户端开发包分配的CXL内存区域总量的第二获取函数、用于获取指定CXL内存区域可用字节数的第三获取函数、用于获取指定内存节点中CXL内存区域总量的第四获取函数、用于获取指定内存节点中CXL内存区域可用字节数的第五获取函数、用于获取多个CXL内存区域的状态数据的第六获取函数、用于获取多个内存节点下、相应CXL内存区域的状态数据的第七获取函数中的至少一种。
  4. 根据权利要求1所述的方法,其特征在于,还包括:
    划分用于分配用户态的CXL内存的第一内存分配池,以及用于分配用户态的本地内存的第二内存分配池;
    在所述调用请求用于调用所述专用应用程序接口的情况下,选定所述第一内存分配池;
    根据所述调用请求对所述第一内存分配池中的内存空间进行分配处理,以分配用户态的CXL内存。
  5. 根据权利要求4所述的方法,其特征在于,所述根据所述调用请求对所述第一内存分配池中的内存空间进行分配处理,包括:
    确定与所述调用请求相对应的内存分配函数;
    在所述内存分配函数中新增用户态的内存映射标志,并根据所述CXL内存标识对所述内存映射标志进行赋值;所述内存映射标志用于表示是否分配CXL内存;
    根据所述内存分配函数对所述第一内存分配池中的内存空间进行分配处理。
  6. 根据权利要求5所述的方法,其特征在于,所述在所述内存分配函数中新增用户态的内存映射标志,包括:
    在内存分配池的在内存分配结构体中新增用户态的内存映射标志。
  7. 根据权利要求6所述的方法,其特征在于,还包括:
    预设用于设置内存映射标志的设置函数;
    在新建内存分配池时,调用所述设置函数,为新建内存分配池的内存映射标志设为默认值;所述默认值表示分配本地内存;
    所述根据所述CXL内存标识对所述内存映射标志进行赋值,包括:
    调用所述设置函数,将所述CXL内存标识赋值给所述内存映射标志。
  8. 根据权利要求5所述的方法,其特征在于,所述通过内存映射接口,将所述CXL内存标识传递至内核态,包括:
    基于内存管理文件中的内存分配核函数,调用用于获取所述内存映射标志的获取函数,获取到所述内存映射标志;
    设置内存映射标志传递函数,根据所述内存映射标志传递函数对所述内存映射标志进行传参;
    在内存页文件的操作系统内存页映射函数中增加所述内存映射标志,以将所述内存映射标志传递至内核的内存映射接口。
  9. 根据权利要求8所述的方法,其特征在于,所述根据所述内存映射标志传递函数对所述内存映射标志进行传参,包括:
    将所述内存映射标志合并至表示交织策略的局部变量;
    根据所述内存映射标志传递函数对所述局部变量进行传参。
  10. 根据权利要求4所述的方法,其特征在于,所述划分用于分配用户态的CXL内存的第一内存分配池,以及用于分配用户态的本地内存的第二内存分配池,包括:
    为处理器的每个核分配多个内存分配池,其中部分内存分配池作为用于分配用户态的CXL内存第一内存分配池,另一部分内存分配池作为用于分配用户态的本地内存的第二内存分配池。
  11. 根据权利要求1所述的方法,其特征在于,所述在所述内核态分配与CXL内存相关的硬件资源,包括:
    划分用于独立管理内核空间CXL内存的CXL内存分配区;
    根据所述调用请求对所述CXL内存分配区中的内存空间进行分配处理,以分配与CXL内存相关的硬件资源。
  12. 根据权利要求11所述的方法,其特征在于,所述划分用于独立管理内核空间CXL内存的CXL内存分配区,包括:
    在操作系统内核的内存区域管理头文件的内存区域类型中新增所述CXL内存分配区对应的类型;
    扩展内核态的内存映射系统调用接口,为所述内存映射系统调用接口增加表示映射CXL内存的标志以及表示映射本地内存的标志。
  13. 根据权利要求12所述的方法,其特征在于,所述划分用于独立管理内核空间CXL内存的CXL内存分配区,还包括:
    在所述内存区域管理头文件中新增子内存区域结构体,每个所述子内存区域结构体对应一条CXL内存;
    所述子内存区域结构体包括内存区域数据、内存起始地址和内存结束地址;其中,所述内存区域数据是在已有内存分配区的基础上兼容生成的。
  14. 根据权利要求13所述的方法,其特征在于,所述划分用于独立管理内核空间CXL内存的CXL内存分配区,还包括:
    在内存区域管理头文件中新增子内存区域索引结构体;所述子内存区域索引结构体包括相应子内存区域的指针,以及子内存区域在子内存区域列表中的索引标识。
  15. 根据权利要求13所述的方法,其特征在于,所述划分用于独立管理内核空间CXL内存的CXL内存分配区,还包括:
    对所述内存区域管理头文件中的内存区域结构体新增变量;新增的变量包括:空闲子内存区域队列结构体、子内存区域列表、子内存区域数量和当前已分配子内存区域的索引标识。
  16. 根据权利要求15所述的方法,其特征在于,所述根据所述调用请求对所述CXL内存分配区中的内存空间进行分配处理,包括:
    从空闲子内存区域的链表中,拿到下一个子内存区域的索引标识;
    根据下一个子内存区域的索引标识,从所述空闲子内存区域队列结构体中定位到空闲子内存区域,并根据所述空闲子内存区域进行内存分配。
  17. 根据权利要求11至16中任一项所述的方法,其特征在于,还包括:
    将CXL内存配置选项封装在宏定义中,并在内核配置中选择性地启用所述宏定义;所述CXL内存配置选项包括对操作系统内核的修改代码、新增的函数、变量中的至少一种。
  18. 一种计算机设备,其特征在于,包括:
    存储器和处理器,所述存储器和所述处理器之间互相通信连接,所述存储器中存储有计算机指令,所述处理器通过执行所述计算机指令,从而执行权利要求1至17中任一项所述的内存分配方法。
  19. 一种计算机非暂时可读存储介质,其特征在于,所述计算机非暂时可读存储介质上存储有计算机指令,所述计算机指令用于使计算机执行权利要求1至17中任一项所述的内存分配方法。
  20. 一种计算机程序产品,其特征在于,包括计算机指令,所述计算机指令用于使计算机执行权利要求1至17中任一项所述的内存分配方法。
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