WO2025218809A1 - 存储装置、电子设备和存储装置的控制方法 - Google Patents

存储装置、电子设备和存储装置的控制方法

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Publication number
WO2025218809A1
WO2025218809A1 PCT/CN2025/090092 CN2025090092W WO2025218809A1 WO 2025218809 A1 WO2025218809 A1 WO 2025218809A1 CN 2025090092 W CN2025090092 W CN 2025090092W WO 2025218809 A1 WO2025218809 A1 WO 2025218809A1
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WO
WIPO (PCT)
Prior art keywords
circuit
data
sram
nvsram
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2025/090092
Other languages
English (en)
French (fr)
Inventor
潘立阳
梁英真
张均阳
赵美然
陈雷
孙华波
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tsinghua University
Beijing Microelectronic Technology Institute
Original Assignee
Tsinghua University
Beijing Microelectronic Technology Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN202410479895.5A external-priority patent/CN118335147A/zh
Priority claimed from CN202410476134.4A external-priority patent/CN118335146A/zh
Application filed by Tsinghua University, Beijing Microelectronic Technology Institute filed Critical Tsinghua University
Publication of WO2025218809A1 publication Critical patent/WO2025218809A1/zh
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction

Definitions

  • Embodiments of the present disclosure relate to a storage device, an electronic device, and a method for controlling the storage device.
  • Volatile memory refers to memory whose stored data will be lost after a power outage
  • non-volatile memory refers to memory whose stored data is not lost after a power outage.
  • volatile memory operates quickly, while non-volatile memory has a longer retention period.
  • SRAM Static Random Access Memory
  • At least one embodiment of the present disclosure provides a storage device, comprising: an NVSRAM array, an SRAM operation circuit, a nonvolatile storage operation circuit, a first input/output interface circuit, a column selection circuit, and a second input/output interface circuit, wherein the column selection circuit is coupled to the NVSRAM array, the SRAM operation circuit is coupled to the column selection circuit, and the nonvolatile storage operation circuit is coupled to the NVSRAM array;
  • the NVSRAM array comprises a plurality of NVSRAM cells arranged in an array, and each NVSRAM cell comprises an SRAM storage sub-cell and a nonvolatile storage sub-cell, the nonvolatile storage sub-cell being configured to perform data backup on data stored in the SRAM storage sub-cell;
  • the nonvolatile storage operation circuit is configured to perform data backup operation on the SRAM storage sub-cell data in the selected NVSRAM cell in the NVSRAM array;
  • the SRAM operation circuit is configured to perform data backup operation on the SRAM storage sub-cell data The first data
  • At least one embodiment of the present disclosure provides a control method for a storage device, which is used for the storage device provided by any embodiment of the present disclosure.
  • the control method includes: when it is determined that the SRAM operation circuit performs the first data read and write operation, disconnecting the coupling between the non-volatile storage operation circuit and the NVSRAM array, controlling the column selection circuit to connect the coupling between the SRAM operation circuit and the NVSRAM array, and controlling the second input and output circuit to disconnect the coupling with the NVSRAM array; or, when it is determined that the second input and output interface circuit performs the second data read and write operation, disconnecting the coupling between the non-volatile storage operation circuit and the NVSRAM array, connecting the coupling between the second input and output interface circuit and the NVSRAM array, and controlling the column selection circuit to disconnect the SRAM operation circuit from the NVSRAM array.
  • the column selection circuit is controlled to disconnect the coupling of the SRAM operation circuit and the NVSRAM array, and the second input-output circuit is controlled to disconnect the coupling with the NVSRAM array; or, when it is determined that the column selection circuit performs the data recovery operation, the coupling of the non-volatile storage operation circuit and the NVSRAM array is disconnected, the column selection circuit is controlled to disconnect the coupling of the SRAM operation circuit and the NVSRAM array, and the second input-output interface circuit is controlled to disconnect the coupling with the NVSRAM array.
  • At least one embodiment of the present disclosure provides a storage device, comprising: an NVSRAM array, an SRAM operation circuit, a nonvolatile storage operation circuit, an error correction circuit, a first input/output interface circuit, a column selection circuit, and a second input/output interface circuit, wherein the error correction circuit is coupled to the SRAM operation circuit, the SRAM operation circuit is coupled to the column selection circuit, the column selection circuit is coupled to the NVSRAM array, and the nonvolatile storage operation circuit is coupled to the NVSRAM array;
  • the NVSRAM array comprises a plurality of NVSRAM cells arranged in an array, and each NVSRAM cell comprises an SRAM storage sub-cell and a nonvolatile storage sub-cell, the nonvolatile storage sub-cell being configured to perform data backup on data stored in the SRAM storage sub-cell;
  • the nonvolatile storage operation circuit is configured to perform a data backup operation on the SRAM storage sub-cell data in the selected NVSRAM cell in the NVSRAM array;
  • At least one embodiment of the present disclosure provides a storage device control method, which is used for the storage device provided by any embodiment of the present disclosure.
  • the control method includes: controlling the error detection circuit to encode and decode the target data, determine whether the target data has errors, and correct the errors.
  • At least one embodiment of the present disclosure provides an electronic device, including the storage device provided by any embodiment of the present disclosure.
  • FIG1 shows a schematic diagram of a combination of a volatile storage sub-unit and a non-volatile storage sub-unit
  • FIG2 shows a schematic block diagram of a storage device provided by at least one embodiment of the present disclosure
  • FIG3 shows a schematic block diagram of another storage device provided by at least one embodiment of the present disclosure
  • FIG4 shows a schematic block diagram of another storage device provided by at least one embodiment of the present disclosure.
  • FIG5 is a schematic flow chart showing a method for controlling a storage device according to at least one embodiment of the present disclosure
  • FIG6 is a schematic flow chart showing another method for controlling a storage device according to at least one embodiment of the present disclosure.
  • FIG7 is a schematic flow chart showing another method for controlling a storage device according to at least one embodiment of the present disclosure.
  • FIG8 is a schematic flow chart showing another method for controlling a storage device according to at least one embodiment of the present disclosure.
  • FIG9 is a schematic diagram showing a flow chart of a storage device operating method provided by at least one embodiment of the present disclosure.
  • FIG10 is a schematic diagram showing a flow chart of a storage device data backup method provided by at least one embodiment of the present disclosure
  • FIG11 is a schematic flow chart showing a method for recovering data from a storage device according to at least one embodiment of the present disclosure
  • FIG12 shows a schematic block diagram of a storage device provided by at least one embodiment of the present disclosure
  • FIG13 shows a schematic block diagram of another storage device provided by at least one embodiment of the present disclosure.
  • FIG14 shows a schematic block diagram of another storage device provided by at least one embodiment of the present disclosure.
  • FIG15 shows a schematic block diagram of another storage device provided by at least one embodiment of the present disclosure.
  • FIG16A shows a schematic block diagram of another storage device provided by at least one embodiment of the present disclosure.
  • FIG16B shows a schematic block diagram of another storage device provided by at least one embodiment of the present disclosure.
  • FIG17 is a schematic flow chart showing a method for controlling a storage device according to at least one embodiment of the present disclosure
  • FIG18 is a schematic flow chart showing another method for controlling a storage device according to at least one embodiment of the present disclosure.
  • FIG19 is a schematic flow chart showing another method for controlling a storage device according to at least one embodiment of the present disclosure.
  • FIG20 is a schematic flow chart showing another method for controlling a storage device according to at least one embodiment of the present disclosure
  • FIG21 is a schematic flow chart showing another method for controlling a storage device according to at least one embodiment of the present disclosure.
  • FIG22 is a schematic flow chart showing another method for controlling a storage device according to at least one embodiment of the present disclosure.
  • FIG23 is a schematic flow chart showing another method for controlling a storage device according to at least one embodiment of the present disclosure.
  • FIG24 is a schematic flow chart showing another method for controlling a storage device according to at least one embodiment of the present disclosure.
  • FIG25 shows a schematic diagram of a process for backing up data on a storage device according to at least one embodiment of the present disclosure
  • FIG26 shows a schematic diagram of a process for restoring data on a storage device according to at least one embodiment of the present disclosure.
  • FIG27 shows a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure.
  • a static random access memory consists of a memory cell array, row/column address decoders, a sense amplifier, a control circuit, and a buffer/driver circuit.
  • the memory cell array includes multiple SRAM memory sub-cells, word lines, and bit lines. These memory sub-cells are arranged in multiple rows and columns, with row addressing performed via word lines and column addressing performed via bit lines.
  • SRAM excels in situations where fast data access is required, such as cache or CPU cache. Due to its fast data access speed, SRAM can be used to store data that requires fast access.
  • SRAM can be of multiple types, such as 6T-SRAM (i.e., six-transistor type SRAM), 7T-SRAM (i.e., seven-transistor type SRAM), 8T-SRAM (i.e., eight-transistor type SRAM), and other multi-transistor type SRAMs, which are not described in detail here.
  • 6T-SRAM i.e., six-transistor type SRAM
  • 7T-SRAM i.e., seven-transistor type SRAM
  • 8T-SRAM i.e., eight-transistor type SRAM
  • other multi-transistor type SRAMs which are not described in detail here.
  • SRAM loses its stored data when power is lost.
  • SRAM lacks its own independent power supply and requires external power to maintain data storage. Once power is lost, the storage subcells lose their charge, resulting in data loss. Therefore, SRAM requires continuous power to maintain its data storage state.
  • Non-Volatile Memory is a type of semiconductor memory that can retain data even after power is removed.
  • Examples of NVM include RRAM (Resistive Random Access Memory), PRAM (Phase-Change Random Access Memory), and Flash memory.
  • RRAM and PRAM store data by changing their resistance.
  • RRAM utilizes the ability of thin film materials to switch between different resistance states—high resistance (HRS) and low resistance (LRS)—under an applied voltage. These different high and low resistance states represent logical "1" and "0,” enabling data storage and maintaining data long after power is removed.
  • the process of RRAM transitioning from a high resistance state (HRS) to a low resistance state (LRS) is called a SET process, or a set process.
  • the process of transitioning from a low resistance state to a high resistance state is called a RESET process, or a reset process.
  • Non-volatile memories operate at a relatively slow speed and require a relatively large operating current or voltage.
  • NVM and SRAM are combined to form NVSRAM (Nonvolatile Static Random Access Memory), which combines the advantages of the above two types of memory and can solve the problem of data loss after SRAM power failure and operation speed problems.
  • NVSRAM Nonvolatile Static Random Access Memory
  • the main storage area consists of an array of NVSRAM cells organized into multiple rows and columns.
  • Each NVSRAM cell includes an SRAM subcell and a corresponding NVM subcell, enabling high-speed random access.
  • Data in this area can be permanently stored even after a power outage.
  • data in the SRAM subcell can be backed up to the NVM subcell before power is lost, and restored from the NVM subcell to the SRAM subcell upon power-up.
  • the data is first stored in the SRAM subcell and then backed up to the NVM subcell, achieving non-volatile storage.
  • data is directly read from the SRAM subcell.
  • the SRAM subcell offers fast read speeds and low latency.
  • NVM storage sub-units are susceptible to certain factors during data backup and recovery, resulting in high error rates. For example, when recovering data from an SRAM storage sub-unit, a large peak current may be generated, which may reduce the stability of the NVSRAM, affect the success rate of data recovery, and ultimately lead to a high error rate in the recovered data. Errors may also occur when backing up data to the NVM storage sub-unit. For example, during the data backup process, incomplete charge injection or release may occur, or the NVM storage sub-unit may be affected by voltage fluctuations, electromagnetic interference, etc., and data bit errors may occur when backing up data to the NVM storage sub-unit. All of these can lead to high error rates in the NVM storage sub-unit.
  • the RRAM storage subcell and the SRAM storage subcell may interfere with each other during data backup or data recovery using the RRAM storage subcell.
  • the read and write mechanisms of the RRAM storage subcell and the SRAM storage subcell differ, if their operations are not properly coordinated and read and write operations are performed simultaneously on the RRAM storage subcell and the SRAM storage subcell, read and write conflicts may result, leading to mutual interference.
  • data synchronization between the RRAM storage subcell and the SRAM storage subcell is not properly handled, data loss may occur, affecting the system stability of the storage device.
  • the inventors of this disclosure note that to address these issues, it is necessary to fully consider the characteristics and operational requirements of both RRAM and SRAM storage subunits when designing the storage device, and to take appropriate measures to coordinate their operations. For example, reasonable read and write strategies can be developed to avoid read and write conflicts between the two. Alternatively, the mutual impact between the two operations can be reduced by optimizing the storage device design, such as by improving circuit design, optimizing read and write timing, and using different power supplies to reduce resource conflicts and interference.
  • the inventors of this disclosure also noted that it is necessary to fully consider the characteristics and operational requirements of both RRAM and SRAM storage subunits when designing a storage device, and to take appropriate measures to coordinate their operations. For example, read/write conflicts between the two can be avoided by developing reasonable read/write strategies. Alternatively, the mutual impact between the two operations can be reduced by optimizing the storage device design. For example, resource conflicts and interference can be reduced by improving circuit design, optimizing read/write timing, and using different power supplies. Furthermore, error detection and correction technologies can be used to detect and correct erroneous stored data.
  • FIG1 shows a schematic diagram of a combination of a volatile storage sub-unit and a non-volatile storage sub-unit.
  • the NVSRAM shown combines volatile and non-volatile memory sub-cells.
  • the volatile memory sub-cell is a 6T-SRAM (i.e., a six-transistor SRAM), comprising transistors P0, P1, N0, N1, N2, and N3, as well as bit lines BL, BLN, word lines WL, power lines CVDD, and ground lines VSS for operating the memory sub-cell.
  • the SRAM memory sub-cell also includes storage nodes Q and QN. Bit lines BL and BLN are used to read and write data, while word lines WL are used to control read and write operations.
  • Transistors P0 and N0 form an inverter, while transistors P1 and N1 form another inverter.
  • the two inverters are cross-connected to provide storage nodes Q and QN.
  • the SRAM memory sub-cell has a bistable structure. When the storage node Q is at a high level, the storage node QN is at a low level, and the stored data can be selected as "1". Correspondingly, when the storage node Q is at a low level, the storage node QN is at a high level, and the stored data can be selected as "0".
  • Transistor N2 and transistor N3 are controlled by the word line WL to turn on or off the storage sub-unit.
  • the non-volatile memory sub-cell may include a resistive random access memory sub-cell (RRAM) R, a resistive random access memory sub-cell RN, a transistor N4, and a transistor N5.
  • the non-volatile memory sub-cell is connected to the volatile memory sub-cell in a differential manner.
  • the resistive random access memory sub-cell R is connected to the storage node Q through the transistor N4, and the resistive random access memory sub-cell RN is connected to the storage node QN through the transistor N5.
  • the gates of the transistors N4 and N5 are connected to the control line CWLN, and the switching states of the transistors N4 and N5 are controlled by the control line CWLN. For example, the state in which the resistance of the resistive random access memory sub-cell R is less than the resistance of the resistive random access memory sub-cell RN is set as data "1", and vice versa.
  • the volatile memory sub-cell may be another type of SRAM sub-cell.
  • the non-volatile memory sub-cell may also be connected to the volatile memory sub-cell using a single-ended connection, for example, including only the resistive random access memory sub-cell R and the transistor N4.
  • non-volatile memory sub-cells may also use PRAM sub-cells.
  • Some embodiments of the present disclosure provide a storage device, an electronic device including the storage device, and a storage device control method.
  • the storage device includes an NVSRAM array, an SRAM operation circuit, a nonvolatile storage operation circuit, a column selection circuit, a first input/output interface circuit, and a second input/output interface circuit.
  • the column selection circuit is coupled to the NVSRAM array
  • the SRAM operation circuit is coupled to the column selection circuit
  • the nonvolatile storage operation circuit is coupled to the NVSRAM array.
  • the NVSRAM array includes a plurality of NVSRAM cells arranged in an array, and each NVSRAM cell includes an SRAM storage sub-cell and a non-volatile storage sub-cell.
  • the non-volatile storage sub-cell is configured to perform data backup for data stored in the SRAM storage sub-cell.
  • the non-volatile storage operation circuit is configured to perform a data backup operation on the SRAM storage sub-cell data in the selected NVSRAM cell in the NVSRAM array;
  • the SRAM operation circuit is configured to perform a first data read and write operation on the SRAM storage sub-cell data;
  • the column selection circuit is configured to perform a data recovery operation on the non-volatile storage sub-cell data;
  • the column selection circuit is also configured to select the object cell column that needs to be operated in the NVSRAM array when performing a data recovery operation or when the SRAM operation circuit performs the first data read and write operation;
  • the column selection circuit is also configured to isolate the operation of the SRAM operation circuit and the operation of the non-volatile storage operation circuit, and to isolate the first data read and write operation, the second data read and write operation and the data recovery operation;
  • the first input-output interface circuit is coupled to the SRAM operation circuit and is configured to provide the received first input data to the SRAM operation circuit and receive the first output data to be output from the SRAM operation circuit
  • the storage device uses a non-volatile storage sub-unit to back up the data of the SRAM storage sub-unit, uses a column selection circuit to isolate the operation of the SRAM operation circuit and the operation of the non-volatile storage operation circuit, and isolates the first data read and write operation, the second data read and write operation and the data recovery operation, and transmits the data input or output of the storage device through the first input and output interface circuit or the second input and output interface circuit, thereby improving the reliability and flexibility of data reading, writing, backup and recovery.
  • FIG2 shows a schematic block diagram of a storage device provided by at least one embodiment of the present disclosure.
  • a storage device 1000 includes an NVSRAM array 120 , an SRAM operation circuit 100 , a nonvolatile storage operation circuit 130 , a column selection circuit 110 , a first input/output interface circuit 150 , and a second input/output interface circuit 160 .
  • the SRAM operation circuit 100 is coupled to the column selection circuit 110 , the column selection circuit 110 is coupled to the NVSRAM array 120 , the non-volatile memory operation circuit 130 is coupled to the NVSRAM array 120 , the first input/output interface circuit 150 is coupled to the SRAM operation circuit 100 , and the second input/output interface circuit 160 is coupled to the NVSRAM array 120 .
  • Coupler is used to refer to the signal connection between the description objects.
  • signal transmission can be carried out, and when the coupling is disconnected between the description objects, signal connection cannot be carried out.
  • Coupling can be achieved by, for example, electrical connection.
  • “coupling” can include two or more electronic components or circuits being connected together in some way so that signals between them are transmitted to each other.
  • two storage sub-units can be directly connected to achieve information transmission through the transmission of signals or energy, or the two storage sub-units can be connected through other circuit elements, such as resistors, capacitors, switches, optoelectronic elements and other elements or transmission line networks, to achieve signal transmission.
  • the NVSRAM array 120 includes a plurality of NVSRAM cells 121 arranged in an array, and each NVSRAM cell 121 includes an SRAM storage sub-cell 122 and a non-volatile storage sub-cell 131.
  • the non-volatile storage sub-cell 131 is configured to perform data backup for the data stored in the SRAM storage sub-cell 122.
  • the array formed by the plurality of NVSRAM cells 121 includes a plurality of rows and a plurality of columns.
  • the plurality of NVSRAM cells 121 can form a storage array including M rows and N columns, where M and N are integers and 1 ⁇ M, 1 ⁇ N.
  • the NVSRAM cell 121 can, for example, take the form shown in FIG. 1 , but the embodiments of the present disclosure are not limited to this specific form.
  • the NVSRAM cells 121 of the NVSRAM array 120 combine the characteristics of SRAM storage subcells and non-volatile storage subcells.
  • the SRAM storage subcells 122 can be configured to store data and can quickly read and write data.
  • the non-volatile storage subcells 131 are configured to back up the data stored in the SRAM storage subcells 122 to prevent data loss in the event of a power outage or system crash.
  • the non-volatile storage subunit 131 may include RRAM, FeRAM (Ferroelectric Random Access Memory), MRAM (Magnetic Random Access Memory), PCM (Phase Change Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), PRAM, flash memory, and other storage subunits.
  • the non-volatile storage operating circuit 130 in the embodiments of the present disclosure is adjusted accordingly to correspond to different types of non-volatile storage subunits 131, and the present disclosure is not limited to this.
  • the non-volatile storage operating circuit 130 may include an RRAM operating circuit.
  • the nonvolatile memory operation circuit 130 is configured to perform a data backup operation on the data of the SRAM memory sub-cell 122 in the selected NVSRAM cell 121 in the NVSRAM array 120 .
  • the non-volatile storage operation circuit 130 can communicate with multiple SRAM storage subunits 122.
  • the non-volatile storage operation circuit 130 can perform data backup operations on the data in the SRAM storage subunits 122 as needed. For example, when the electronic device detects a failure or abnormality in an application, the non-volatile storage operation circuit 130 performs a backup operation.
  • the non-volatile storage operation circuit 130 can also perform a data backup operation on the data in the SRAM storage subunit 122 in response to a backup instruction, perform a periodic data backup operation on the SRAM storage subunit 122 based on a preset time, or perform a real-time data backup operation on the SRAM storage subunit 122.
  • the non-volatile storage operation circuit 130 can employ a parallel processing method to simultaneously perform data backup operations on the data of multiple selected SRAM storage subunits 122.
  • the non-volatile storage operation circuit 130 can simultaneously perform data backup operations on the data in a certain row of SRAM storage subunits 122, or the non-volatile storage operation circuit 130 can simultaneously perform data backup operations on the data in multiple rows of SRAM storage subunits 122.
  • the first input/output interface circuit 150 is configured to provide received first input data to the SRAM operation circuit 100 and receive first output data to be output from the SRAM operation circuit 100.
  • the SRAM operation circuit 100 is configured to perform a first data read/write operation on the SRAM storage sub-cell 122.
  • the column selection circuit 110 is configured to perform a data recovery operation on the non-volatile storage sub-cell data.
  • the second input/output interface circuit 160 is configured to perform a second data read/write operation on the NVSRAM array 120.
  • the "first data read/write operation” refers to the SRAM operating circuit 100 performing a data read/write operation on the SRAM storage subunit 122.
  • the “second data read/write operation” refers to the second input/output interface circuit 160 performing a data read/write operation on the SRAM storage subunit 122.
  • the first input/output interface circuit 150 can be configured to receive first input data input to the storage device 1000 and provide the first input data to the SRAM operating circuit 100.
  • the first input/output interface circuit 150 can be configured to receive first output data to be output from the SRAM operating circuit 100.
  • the storage device 1000 can determine whether the data input to the storage device 1000 is input to the storage device 1000 from the first input/output interface circuit 150 or from the second input/output interface circuit 160 based on the received control instruction, the bit width or data type of the data input to the storage device 1000, the operating conditions of each circuit in the storage device 1000, etc.
  • the column selection circuit 110 performs a data recovery operation
  • the data input to the storage device 1000 can be input from the second data input/output interface circuit 160.
  • the second input/output interface circuit 160 performs a second data read/write operation
  • the data input to the storage device 1000 can be input from the second input/output interface circuit 160.
  • the bit width of the input or output data of the first input/output interface circuit 150 and the second input/output interface circuit 160 can be preset.
  • the data bit width of the input or output of the first input/output interface circuit 150 can be preset to be greater than that of the second input/output interface circuit 160.
  • the data bit width of the input or output of the first input/output interface circuit 150 is preset to be 32 bits
  • the data bit width of the input or output of the second input/output interface circuit 160 is preset to be 512 bits. Then, when the data bit width of the input storage device 1000 is 32 bits, the data can be input from the first input/output interface circuit 150.
  • the embodiments of the present disclosure are not limited to this.
  • the received read and write instructions, data bit width or data type, the working conditions of each circuit in the storage device 1000, etc. can be used to determine whether the SRAM operation circuit 100 performs a first data read and write operation on the selected SRAM storage sub-unit 122, or whether the second input and output interface circuit 150 performs a second data read and write operation on the selected SRAM storage sub-unit 122.
  • the column selection circuit 110 is configured to select a target cell column in the NVSRAM array 120 that needs to be operated on when performing a data recovery operation or when the SRAM operation circuit 100 performs a first data read/write operation. For example, when the SRAM operation circuit 100 performs the first data read/write operation or when the column selection circuit 110 performs a data recovery operation, the column selection circuit 110 responds to a received address signal and converts it into an electrical signal, thereby selecting a corresponding target cell column in the NVSRAM array 120. For example, the column selection circuit 110 may select a corresponding target cell column in the NVSRAM array 120 based on an instruction that the SRAM operation circuit 100 needs to perform the first data read/write operation or that the column selection circuit 110 needs to perform a data recovery operation.
  • target cell column refers to the memory cell column being operated on, which can be any column in a plurality of memory arrays.
  • Address signals include row select signals and column select signals.
  • the word line driver circuit (described below) uses row select signals for row addressing, while the column select circuit uses column select signals for column addressing.
  • the operation of the non-volatile storage operation circuit 130, the operation of the SRAM operation circuit 100, the operation of the second input/output interface circuit 160, and the data recovery operation of the column selection circuit 110 may affect each other, thereby affecting the stability of data backup and data recovery.
  • the column select circuit 110 may be further configured to isolate the operation of the SRAM operation circuit 100 from the operation of the non-volatile memory operation circuit 130.
  • the second input/output interface circuit 160 may be further configured to isolate the operation of the second input/output interface circuit 160 from the operation of the non-volatile memory operation circuit 130.
  • independent column selection circuits 110 may be provided for the non-volatile storage operation circuit 130 and the SRAM operation circuit 100 respectively to reduce the influence and interference between the two.
  • the independent column selection circuits 110 may have different circuit structures and components to adapt to the characteristics and operation requirements of the non-volatile storage operation circuit 130 and the SRAM operation circuit 100.
  • the column selection circuit 110 may also not perform a data recovery operation when the SRAM operation circuit 100 performs a first data read and write operation, the second input and output interface circuit 170 performs a second data read and write operation, or the non-volatile storage operation circuit 130 performs a data backup operation, so as to isolate the first data read and write operation, the second data read and write operation, the data backup operation, and the data recovery operation.
  • power supply isolation can be implemented for the non-volatile memory operating circuit 130, the SRAM operating circuit 100, or the second input/output interface circuit 160.
  • independent power supplies or power supply lines can be provided for the non-volatile memory operating circuit 130, the SRAM operating circuit 100, or the second input/output interface circuit 160.
  • a voltage regulator can be added to the non-volatile memory operating circuit 130, the SRAM operating circuit 100, or the second input/output interface circuit 160 to improve circuit power supply stability.
  • an optical coupler can be used to transmit data from the non-volatile memory operating circuit 130, the SRAM operating circuit 100, or the second input/output interface circuit 160 via optical signals.
  • the operation of the non-volatile storage operation circuit 130, the operation of the SRAM operation circuit 100, or the operation of the second input-output interface circuit 160 can also be controlled through logic design. For example, in specific circumstances, only the operation of the non-volatile storage operation circuit 130, or only the operation of the SRAM operation circuit 100, or only the operation of the second input-output interface circuit 160 can be allowed, and the non-volatile storage operation circuit 130 and the SRAM operation circuit 100 or the second input-output interface circuit 160 are prohibited from operating simultaneously.
  • FIG3 shows a schematic block diagram of another storage device provided by at least one embodiment of the present disclosure.
  • the second input/output interface circuit 160 includes a shift register operation circuit 161, an input interface circuit 162, and an output interface circuit 163.
  • the shift register operation circuit 161 is coupled to the NVSRAM array 120 and is configured to perform second data read and write operations on the NVSRAM array 120;
  • the input interface circuit 162 is coupled to the shift register operation circuit 161 and is configured to receive second input data and provide the received second input data to the shift register operation circuit 161;
  • the output interface circuit 163 is coupled to the shift register operation circuit 161 and is configured to receive second output data to be output from the shift register operation circuit 161.
  • second input data refers to data input to the storage device 1000 via the input interface circuit 162 in the second input/output interface circuit 160.
  • second output data refers to data output from the storage device 1000 via the output interface circuit 163 in the second input/output interface circuit 160.
  • the embodiments of the present disclosure do not limit the content and format of the data.
  • the shift register operation circuit 161 can input the received second input data into the SRAM storage subunit 122 of the NVSRAM array 120, or the shift register operation circuit 161 can read the second output data from the SRAM storage subunit 122 of the NVSRAM array 120 and output the data to the storage device 1000 through the output interface circuit 163.
  • the shift register operation circuit 161 may temporarily store the received second input data, and then input the second input data into the SRAM storage subunit 122 in the NVSRAM array 120 .
  • the shift register operation circuit 161 may further convert the received second input data.
  • the shift register operation circuit 161 may convert the second input data received serially into the SRAM storage sub-units 122 in the NVSRAM array 120 and input them in parallel.
  • the NVSRAM array 120 may further be configured to be coupled to a word line driver circuit 140.
  • the word line driver circuit 140 is configured to select a target cell row to be operated in the NVSRAM array 120 when the SRAM operation circuit 100 performs a first data read/write operation, when the second input/output interface circuit 160 performs a second data read/write operation, when the column selection circuit performs a data recovery operation, or when the non-volatile memory operation circuit performs a data backup operation.
  • the “object cell row” is used to refer to a storage cell row that is an operation object, which may be any row in a plurality of storage arrays.
  • the word line driver circuit 140 for the NVSRAM array 120 is configured to control the rows (word lines) of memory cells in the NVSRAM array 120.
  • each memory cell is located at the intersection of signal lines, i.e., the horizontal signal lines are word lines, and the vertical signal lines are bit lines.
  • the word line driver circuit 140 is responsible for controlling the switches connected to the word lines to determine which row of memory cells is selected for the desired operation (correspondingly, the column select circuit 110 is responsible for determining which column of memory cells is selected for the desired operation via the bit lines).
  • word line driver circuit 140 may include a decoder and a selector.
  • the decoder receives an address signal and decodes it into a row address for the corresponding word line.
  • the selector selects the corresponding word line based on the row address and applies a drive signal.
  • word line driver circuit 140 ensures correct access to the selected memory cell while avoiding interference or malfunction in other unselected memory cells.
  • the word line driver circuit 140 may be configured to select a row of memory cells in the NVSRAM array 120 to be selected for the second data read/write operation.
  • the second input/output interface circuit 160 may read data from the selected row; when performing a data write operation, the second input/output interface circuit 160 may write data to the selected row of memory cells.
  • the column selection circuit can be used to determine which column of storage cells is selected for the second data read and write operation, or the second data read and write operation can be performed on all columns of storage cells in the NVSRAM array 120.
  • the embodiments of the present disclosure are not limited to this.
  • the word line driver circuit 140 may be configured to select a row of memory cells in the NVSRAM array 120 to be selected for the first data read/write operation.
  • the SRAM operating circuit 100 may read the selected row of data during a data read operation; and may write data to the selected row of memory cells during a data write operation.
  • the word line driver circuit 140 may be configured to select a row of memory cells in the NVSRAM array 120 to be selected for the data backup operation.
  • the non-volatile storage operation circuit 130 may read the data of the selected row in the SRAM storage sub-unit 122 and back up the data of the selected row in the SRAM storage sub-unit 122 to the non-volatile storage sub-unit 131.
  • the word line driver circuit 140 may be configured to select a row of memory cells in the NVSRAM array 120 to be selected for the data recovery operation.
  • the column selection circuit 110 may restore the data of the selected row in the nonvolatile memory sub-cell 131 to the SRAM memory sub-cell 122.
  • FIG4 shows a schematic block diagram of another storage device provided by at least one embodiment of the present disclosure.
  • the second input/output interface circuit 160 may further include an isolation sub-circuit 164.
  • the isolation sub-circuit 164 is coupled between the NVSRAM array 120 and the shift register operation circuit 161.
  • the isolation sub-circuit 164 may be configured to turn on a switch coupling the shift register operation circuit 161 to the NVSRAM array 120 when the shift register operation circuit 161 performs a second data read/write operation.
  • the isolation sub-circuit 164 may be configured to turn off the switch coupling the shift register operation circuit 161 to the NVSRAM array 120 when the non-volatile storage operation circuit 130 performs a data backup operation.
  • the isolation sub-circuit 164 can couple the shift register operation circuit 161 and the NVSRAM array 120.
  • the shift register operation circuit 161 can then perform the second data read/write operation on the SRAM storage sub-units 122 in the NVSRAM array 120, thereby achieving fast data read/write transmission.
  • the non-volatile storage operation circuit 130 is disconnected from the NVSRAM array 120, the read/write operation of the shift register operation circuit 161 is not affected.
  • the isolation sub-circuit 164 can disconnect the shift register operation circuit 161 from the NVSRAM array 120, while the non-volatile storage operation circuit 130 is coupled to the NVSRAM array 120.
  • the non-volatile storage operation circuit 130 can perform a data backup operation, and the shift register operation circuit 161 will not affect the data backup operation of the non-volatile storage operation circuit 130.
  • the column selection circuit 110 when the SRAM operation circuit 100 performs a first data read and write operation, can also be configured to connect the coupling between the SRAM operation circuit 100 and the NVSRAM array 120, the non-volatile storage operation circuit 130 can be configured to disconnect the coupling with the NVSRAM array 120, and the second input-output interface circuit 160 can be configured to disconnect the coupling with the NVSRAM array 120.
  • the column selection circuit 110 can also be configured to disconnect the SRAM operation circuit 100 and the NVSRAM array 120
  • the non-volatile storage operation circuit 130 can also be configured to connect the coupling with the NVSRAM array 120
  • the second input-output interface circuit 160 can be configured to disconnect the coupling with the NVSRAM array 120.
  • the column selection circuit 110 when the column selection circuit 110 performs a data recovery operation, the column selection circuit can also be configured to disconnect the SRAM operation circuit 100 and the NVSRAM array 120, the non-volatile storage operation circuit 130 can be configured to disconnect the NVSRAM array 120, and the second input-output interface circuit 160 can be configured to disconnect the NVSRAM array 120.
  • the column selection circuit 110 when the second input-output interface circuit 160 performs a second data read and write operation, can also be configured to disconnect the SRAM operation circuit 100 and the NVSRAM array 120, and the non-volatile storage operation circuit 130 can also be configured to disconnect the NVSRAM array 120.
  • the column selection circuit 110 couples the SRAM operating circuit 100 and the NVSRAM array 120.
  • the SRAM operating circuit 100 can then perform read/write operations on the SRAM storage subunits 122 in the NVSRAM array 120, thereby achieving fast data read/write transmission.
  • the non-volatile storage operating circuit 130 is disconnected from the NVSRAM array 120 and the second input/output interface circuit 160 is disconnected from the NVSRAM array 120, the read/write operations of the SRAM operating circuit 100 are not affected.
  • the second input/output interface circuit 160 is disconnected from the NVSRAM array 120, and the column selection circuit 110 disconnects the SRAM operation circuit 100 from the NVSRAM array 120, while the non-volatile storage operation circuit 130 is coupled to the NVSRAM array 120.
  • the non-volatile storage operation circuit 130 can perform the backup operation, and the SRAM operation circuit 100 will not affect the data backup process.
  • the second input/output interface circuit 160 is disconnected from the NVSRAM array 120, the column selection circuit 110 disconnects the SRAM operation circuit 100 from the NVSRAM array 120, and the non-volatile storage operation circuit 130 is also disconnected from the NVSRAM array 120. Therefore, the SRAM operation circuit 100, the non-volatile storage operation circuit 130, and the second input/output interface circuit 160 will not affect the data recovery operation process of the column selection circuit 110.
  • the non-volatile storage operation circuit 130 is disconnected from the NVSRAM array 120, and the column selection circuit 110 disconnects the SRAM operation circuit 100 from the NVSRAM array 120. Therefore, the operations of the SRAM operation circuit 100 and the non-volatile storage operation circuit 130 will not affect the second data read/write operation process of the second input/output interface circuit 160.
  • the column selection circuit 110 further includes a data recovery operation sub-circuit 111 .
  • the data recovery operation sub-circuit 111 can be configured to perform a data recovery operation on the data in the non-volatile storage sub-unit 131 in the target unit column. For example, upon receiving a data recovery operation instruction, the data recovery operation sub-circuit 111 can restore the data stored in the selected non-volatile storage sub-unit 131 to the SRAM storage sub-unit 122.
  • the data recovery operation sub-circuit when performing a data recovery operation, the data recovery operation sub-circuit must ensure isolation from the operations of the SRAM operation circuit 100, the second input/output interface circuit 160, and the non-volatile storage operation circuit 130 to prevent conflicts between the first data read/write operation, the second data read/write operation, the data backup operation, and the data recovery operation, thereby improving data integrity and system stability.
  • the column selection circuit 110 or the isolation sub-circuit 164 may further include a switch array (not shown).
  • the column selection circuit 110 may control the coupling between the SRAM operation circuit 100 and the NVSRAM array 120 through the switch array.
  • the shift register operation circuit 161 may be coupled to the NVSRAM array 120 through the switch array of the isolation sub-circuit 164.
  • the column selection circuit 110 may be configured to turn on the switch array coupling the column selection circuit 110 to the NVSRAM array 120.
  • the column selection circuit 110 may also be configured to turn off the switch array coupling the column selection circuit 110 to the NVSRAM array 120.
  • the switch array of the column selection circuit 110 or the isolation sub-circuit 164 can be turned on or off according to the timing logic that controls the operation of the non-volatile memory operation circuit 130, the operation of the SRAM operation circuit 100, or the operation of the shift register operation circuit 161. For example, at a specific timing, when only the SRAM operation circuit 100 is allowed to operate, the switch array of the column selection circuit 110 is turned on. For example, at a specific timing, when only the non-volatile memory operation circuit 130 is allowed to operate, the switch array of the column selection circuit 110 is turned off.
  • the array width of the NVSRAM array 120 can be configured as N, i.e., having N columns of memory cells (or 2N bit lines).
  • each row in the NVSRAM array 120 may include N NVSRAM cells.
  • the NVSRAM array 120 can also be configured to have M rows of memory cells.
  • each column in the NVSRAM array 120 may include M NVSRAM cells.
  • Each memory cell has a corresponding address for locating and accessing the memory cell.
  • the NVSRAM array 120 can also be configured to have M rows of memory cells.
  • each row in the NVSRAM array 120 includes N memory cells, and each memory cell is configured with X bit lines (X is greater than or equal to 1).
  • the number of bit lines in the NVSRAM memory array is X*N. If the transmission lines are bit line pairs, X can be configured as 2, and the number of bit lines in the NVSRAM memory array can be configured as 2N. In some embodiments, for example, the NVSRAM array 120 can be configured in units of words.
  • the nonvolatile memory operation circuit 130 can be configured to be coupled to the NVSRAM array 120 through N groups of transmission lines. For example, in at least one example, when the transmission lines are bit lines or bit line pairs (e.g., bit lines BL and BLN as shown in FIG. 1 ), the nonvolatile memory operation circuit 130 can also be configured to be coupled to the NVSRAM array 120 through N or 2N bit lines.
  • the SRAM operation circuit 100 can be configured to be coupled to the column selection circuit 110 via W1 groups of transmission lines.
  • the SRAM operation circuit 100 can also be configured to be coupled to the first input/output interface circuit 150 via W1 groups of transmission lines.
  • the non-volatile storage operation circuit 130 is coupled to the NVSRAM array 120 via N groups of transmission lines.
  • the column selection circuit 110 is coupled to the NVSRAM array 120 via N groups of transmission lines.
  • W1 and N are integers, and N ⁇ W1 >1.
  • the column selection circuit 110 can also be configured to set the voltages of the 2N bit lines to the same voltage value.
  • the SRAM operation circuit 100 is connected to the column selection circuit 110 via a W1 group of transmission lines, and is used to locate and access specific storage cells in the NVSRAM array 120 according to the address provided by the column selection circuit 110, write data into the NVSRAM array 120, and read data from the NVSRAM array 120.
  • the shift register operation circuit 161 can be coupled to the NVSRAM array 120 through N groups of transmission lines
  • the input interface circuit 162 can be coupled to the shift register operation circuit 161 through W 2 groups of transmission lines
  • the output interface circuit 163 can be coupled to the shift register operation circuit 161 through W 2 groups of transmission lines, where W 2 and N are integers and N ⁇ W 2 >1.
  • the shift register operation circuit 161 is connected to the NVSRAM array 120 through N groups of transmission lines.
  • the transmission lines are bit line pairs (for example, the bit lines BL and BLN shown in Figure 1)
  • the shift register operation circuit 161 can also be connected to the NVSRAM array 120 through 2N bit lines.
  • W1 and W2 can be used to represent the operating bit width of each word in the transmitted data.
  • the storage device 1000 can select any first input-output interface circuit 150 or input interface circuit 162 to receive data input to the storage device 1000, or select any first input-output interface circuit 150 or output interface circuit 163 to output data.
  • W1 is greater than W2 and the same
  • the input interface of the data can be determined based on the bit width of the data input to the storage device 1000; for example, W1 can be 512 bits and W2 can be 32 bits.
  • the first input-output interface circuit 150 is selected to receive or output the data.
  • the word line driving circuit 140 can also be configured to select the SRAM storage sub-unit 122 data in I row NVSRAM cells 121 of the NVSRAM array 120 to perform a data backup operation, where I is an integer and M ⁇ I ⁇ 1.
  • the word line driver circuit 140 may select the SRAM storage sub-units 122 in the NVSRAM cells 121 in row 1 of the NVSRAM array 120 according to the received data backup operation instruction.
  • the word line driver circuit 140 may select the SRAM storage sub-units 122 in the NVSRAM cells 121 in rows 1 to 1
  • the non-volatile storage operation circuit 130 may be configured to perform a parallel data backup operation on the data of the SRAM storage sub-units 122 in the NVSRAM cells 121 in rows 1 to 1 selected by the word line driver circuit 140, and back up all the data of the selected SRAM storage sub-units 122 in the row 1 to 1 to the non-volatile storage sub-unit 131.
  • the word line driving circuit 140 can also be configured to select the non-volatile storage sub-unit 131 data in the J-row NVSRAM unit 121 of the NVSRM array 120 to perform a data recovery operation, where J is an integer and M ⁇ J ⁇ 1.
  • the word line driver circuit 140 may select the non-volatile storage sub-cells 131 in the Jth row of NVSRAM cells 121 in the NVSRAM array 120 according to the received data recovery operation instruction.
  • the word line driver circuit 140 may select the non-volatile storage sub-cells 131 in the 1st to the Jth rows of NVSRAM cells 121
  • the column selection circuit 110 may be configured to perform a parallel data recovery operation on the data of the non-volatile storage sub-cells 131 in the 1st to the Jth rows of NVSRAM cells 121 selected by the word line driver circuit 140, thereby restoring all the data of the non-volatile storage sub-cells 131 in the selected Jth row to the SRAM storage sub-cells 122.
  • the SRAM operation circuit 100 is further configured to, when performing the first data read/write operation, perform the first data read/write operation on the data of the SRAM storage sub-units 122 in the W 1 NVSRAM cells 121 in the i-th row of the selected NVSRAM array 120, where N ⁇ W 1 ⁇ 1 and M ⁇ i ⁇ 1.
  • the operation bit width of the first data read/write operation of the SRAM operation circuit 100 is W 1.
  • the SRAM operation circuit 100 may perform the first data read/write operation on the data of the SRAM storage sub-units 122 in W 1 NVSRAM cells 121 in a row (i-th row) of the selected NVSRAM array 120 according to the received first data read/write operation instruction.
  • the second input/output interface circuit 170 is further configured to, when performing the second data read/write operation, perform the second data read/write operation on the data of the SRAM storage sub-units 122 in the W 2 NVSRAM cells 121 in the i-th row of the selected NVSRAM array 120, where N ⁇ W 2 ⁇ 1 and M ⁇ i ⁇ 1.
  • the operation bit width of the second data read/write operation of the second input/output interface circuit 170 is W 2 .
  • the SRAM operation circuit 100 may perform the second data read/write operation on the data of the SRAM storage sub-units 122 in W 2 NVSRAM cells 121 in a selected row (row i) of the NVSRAM array 120 according to the received second data read/write operation instruction.
  • the nonvolatile storage operation circuit 130 is further configured to perform a data backup operation on the data of the SRAM storage sub-units 122 in the NVSRAM cells 121 in the selected E row and/or F column of the NVSRAM array 120 when performing a data backup operation.
  • E and F are integers and M ⁇ E ⁇ 1, and N ⁇ F ⁇ 1.
  • the operation bit width of the data backup operation of the non-volatile storage operation circuit 130 is N*M.
  • the nonvolatile storage operation circuit 130 may perform a data backup operation on the data of the SRAM storage sub-units 122 in the selected NVSRAM cells 121 in row E or column F among the NVSRAM cells 121 in the M rows and N columns in the NVSRAM array 120 according to the received data backup operation instruction.
  • the nonvolatile storage operation circuit 130 may perform a data backup operation on all the data of the SRAM storage sub-units 122 in the selected NVSRAM cells 121 in row E and column F among the NVSRAM cells 121 in the M rows and N columns in the NVSRAM array 120.
  • the column selection circuit 110 is further configured to, when performing a data recovery operation, perform a data recovery operation on the data of the nonvolatile storage sub-cell 131 in the NVSRAM cell 121 in the G row and/or H column of the selected NVSRAM array 120.
  • G and H are integers and M ⁇ G ⁇ 1, N ⁇ H ⁇ 1.
  • the operation bit width of the data recovery operation of the column selection circuit 110 is N*M.
  • the column selection circuit 110 may perform a data recovery operation on the data of the nonvolatile storage sub-cells 131 in the selected G-row or H-column NVSRAM cells 121 among the M-row and N-column NVSRAM cells 121 in the NVSRAM array 120 according to the received data recovery operation instruction.
  • the nonvolatile storage operation circuit 130 may perform a data recovery operation on all the data of the nonvolatile storage sub-cells 131 in the selected G-row or H-column NVSRAM cells 121 among the M-row and N-column NVSRAM cells 121 in the NVSRAM array 120.
  • parameters such as the number and type of these transmission lines can be flexibly adjusted according to requirements and hardware conditions to optimize the performance and efficiency of the storage device 1000.
  • the storage device 1000 may further include a control circuit 170 (not shown in the figure), and the control circuit 170 may be coupled to the SRAM operation circuit 100, the non-volatile storage operation circuit 130, the first input-output interface circuit 150, the column selection circuit 110 and the second input-output interface circuit 160.
  • the control circuit 170 may be configured to provide corresponding control signals to the SRAM operation circuit 100 , the nonvolatile memory operation circuit 130 , the first I/O interface circuit 150 , the column selection circuit 110 and the second I/O interface circuit 160 according to the selected operation mode.
  • control circuit 170 may generate a corresponding control signal according to the working mode or specific requirements of the storage device 1000 , and provide the generated control signal to the corresponding operating circuit.
  • control circuit 170 can provide a control signal for performing a first data read and write operation to the SRAM operation circuit 100 according to preset conditions, or provide a control signal for performing a second data read and write operation to the second input and output interface circuit 160.
  • control circuit 170 can provide a control signal for performing the data backup operation to the non-volatile storage operation circuit 130, and the non-volatile storage operation circuit 130 performs a data backup operation on the data in the selected SRAM storage subunit 122 based on the received data backup operation control signal.
  • control circuit 170 can provide a control signal for performing the data recovery operation to the column selection circuit 110, and the column selection circuit 110 can perform a data recovery operation on the data in the selected non-volatile storage sub-unit 131 based on the received data recovery operation control signal.
  • control circuit 170 may also monitor the operating status or health status of the storage device 1000. For example, if the first input/output interface circuit 150 fails and the storage device 1000 needs to perform a data read/write operation, the control circuit 170 may provide a second data read/write operation control signal to the second input/output interface circuit 160. The control circuit 170 may also take appropriate measures to repair the failed circuit or report error information to improve the reliability and stability of the storage device 1000.
  • control circuit 170 can improve the operating efficiency of the storage device 1000 in different operating modes by connecting or interacting with other circuits and components of the storage device 1000.
  • the control circuit 170 can also adjust the operating status and parameters of each circuit and component as needed to achieve flexible control and management of the storage device 1000.
  • Figure 5 shows a flow chart of a method for controlling a storage device according to at least one embodiment of the present disclosure. As shown in Figure 5 , the method may include steps S310 - S313 .
  • Step S310 determining that the SRAM operation circuit performs a first data read/write operation.
  • Step S311 disconnecting the nonvolatile storage operation circuit from the NVSRAM array.
  • Step S312 Control the column selection circuit to connect the SRAM operation circuit to the NVSRAM array.
  • Step S313 controlling the second input/output interface circuit to disconnect from the NVSRAM array.
  • the SRAM operation circuit When the SRAM operation circuit is determined to perform the first data read/write operation, it is necessary to isolate the operation of the non-volatile storage operation circuit from the operation of the SRAM operation circuit to prevent the two from interfering with each other and thus affecting the reliability of the first data read/write operation. Therefore, it is necessary to disconnect the non-volatile storage operation circuit from the NVSRAM array and control the column selection circuit to connect the SRAM operation circuit to the NVSRAM array to isolate the operations of the non-volatile storage operation circuit from the SRAM operation circuit.
  • the non-volatile storage operation circuit stops the operation of the non-volatile storage operation circuit according to the received instruction from the SRAM operation circuit to perform the first data read and write operation.
  • step S312 in one example, for example, when the column selection circuit includes a switch array, step S312 further includes step S3121 (not shown in the figure).
  • Step S3121 Control the column selection circuit to turn on the switch array coupled to the NVSRAM array.
  • the method of isolating the operation of the non-volatile storage operation circuit and the operation of the SRAM operation circuit can be referred to the relevant description above and will not be repeated here.
  • the second input-output interface circuit stops performing the second data read-write operation according to the instruction received from the SRAM operation circuit to perform the first data read-write operation, and controls the second input-output interface circuit to disconnect from the NVSRAM array to avoid affecting the operation of the SRAM operation circuit.
  • the method shown in FIG5 may further include step S314 (not shown in the figure).
  • Step S314 controlling the column selection circuit to stop the data recovery operation.
  • the SRAM operation circuit When the SRAM operation circuit is determined to perform the first data read/write operation, it is necessary to isolate the data recovery operation of the column selection circuit from the operation of the SRAM operation circuit to prevent the two from interfering with each other and thus affecting the reliability of data reading and writing. Therefore, it is necessary to control the column selection circuit to stop the data recovery operation to isolate the data recovery operation of the column selection circuit from the first data read/write operation of the SRAM operation circuit.
  • Figure 6 shows a flow chart of a method for controlling a storage device according to at least one embodiment of the present disclosure. As shown in Figure 6 , the method may include steps S320 - S323 .
  • Step S320 determining that the second input/output interface circuit performs a second data read/write operation.
  • Step S321 disconnecting the nonvolatile storage operation circuit from the NVSRAM array.
  • Step S322 Connecting the second input/output interface circuit to the NVSRAM array.
  • Step S323 Control the column selection circuit to disconnect the SRAM operation circuit from the NVSRAM array.
  • the second input/output interface circuit When the second input/output interface circuit is determined to perform the second data read/write operation, it is necessary to isolate the operation of the non-volatile storage operation circuit from the operation of the second input/output interface circuit to prevent the two from interfering with each other and thereby affecting the reliability of the second data read/write operation. Therefore, it is necessary to disconnect the non-volatile storage operation circuit from the NVSRAM array and connect the second input/output interface circuit to the NVSRAM array to isolate the operations of the non-volatile storage operation circuit and the second input/output interface circuit.
  • the non-volatile storage operation circuit may stop the operation of the non-volatile storage operation circuit according to the received instruction from the second input/output interface circuit to perform the second data read/write operation.
  • step S322 in one example, for example, when the second input-output interface circuit includes an isolation sub-circuit, step S322 further includes step S3221 (not shown in the figure).
  • Step S3221 Control the isolation sub-circuit to connect the second input/output interface circuit to the NVSRAM array.
  • the method for isolating the operation of the non-volatile storage operation circuit and the operation of the second input/output interface circuit can be referred to the above description and will not be repeated here.
  • the column selection circuit disconnects the SRAM operation circuit from the NVSRAM array according to the instruction received from the second input/output interface circuit to perform the second data read/write operation, so as to avoid affecting the second input/output interface circuit performing the second data read/write operation.
  • the method shown in FIG6 may further include step S234 (not shown in the figure).
  • Step S234 controlling the column selection circuit to stop the data recovery operation.
  • the second input/output interface circuit When the second input/output interface circuit is determined to perform the second data read/write operation, it is necessary to isolate the data recovery operation of the column selection circuit from the operation of the second input/output interface circuit to prevent the two from interfering with each other and thus affecting the reliability of data reading and writing. Therefore, it is necessary to control the column selection circuit to stop the data recovery operation to isolate the data recovery operation of the column selection circuit from the second data read/write operation of the second input/output interface circuit.
  • Figure 7 shows a flow chart of another method for controlling a storage device according to at least one embodiment of the present disclosure. As shown in Figure 7 , the control method may include steps S330 - S333 .
  • Step S330 determining whether the non-volatile storage operation circuit performs data backup.
  • Step S331 Connecting the non-volatile storage operation circuit to the NVSRAM array.
  • Step S332 Control the column selection circuit to disconnect the SRAM operation circuit from the NVSRAM array.
  • Step S333 controlling the second input/output interface circuit to disconnect from the NVSRAM array.
  • the non-volatile storage operation circuit When the non-volatile storage operation circuit is determined to perform a data backup operation, it is necessary to isolate the operation of the non-volatile storage operation circuit from the operation of the SRAM operation circuit and the operation of the second input/output interface circuit to prevent mutual interference and thus affect the reliability of the data backup operation. Therefore, it is necessary to connect the non-volatile storage operation circuit to the NVSRAM array, control the column selection circuit to disconnect the SRAM operation circuit from the NVSRAM array, and control the second input/output interface circuit to disconnect the NVSRAM array, thereby isolating the non-volatile storage operation circuit from the SRAM operation circuit and the second input/output interface circuit.
  • the column selection circuit stops operation of the column selection circuit based on a received instruction from the non-volatile storage operation circuit to perform a data backup operation.
  • step S332 also includes step S3321 (not shown).
  • Step S3321 Controlling the column selection circuit to disconnect the switch array coupled to the NVSRAM array. The method for isolating the operation of the non-volatile storage operation circuit from the operation of the SRAM operation circuit can be found in the relevant description above and will not be repeated here.
  • step S333 in one example, for example, the second input/output interface circuit stops the operation of the second input/output interface circuit based on the received instruction from the non-volatile storage operation circuit to perform a data backup operation.
  • step S333 also includes step S3331 (not shown in the figure).
  • Step S3331 Control the isolation sub-circuit to disconnect the second input/output interface circuit from the NVSRAM array.
  • the method shown in FIG7 may further include step S334 (not shown in the figure).
  • Step S334 controlling the column selection circuit to stop the data recovery operation.
  • step S334 may also include controlling the data recovery operation sub-circuit to stop performing the data recovery operation.
  • Figure 8 shows a flow chart of another method for controlling a storage device according to at least one embodiment of the present disclosure. As shown in Figure 8 , the control method may include steps S340 - S343 .
  • Step S340 determining that the column selection circuit performs a data recovery operation.
  • Step S341 disconnecting the nonvolatile storage operation circuit from the NVSRAM array.
  • Step S342 Control the column selection circuit to disconnect the SRAM operation circuit from the NVSRAM array.
  • Step S343 Control the second input/output interface circuit to disconnect from the NVSRAM array.
  • the column select circuit When the column select circuit is determined to perform a data recovery operation, it is necessary to isolate the operations of the nonvolatile storage operation circuit, the SRAM operation circuit, the second input/output interface circuit, and the data recovery operation of the column select circuit to prevent mutual interference and thus affect the reliability of the data recovery operation. Therefore, it is necessary to disconnect the nonvolatile storage operation circuit from the NVSRAM array, control the column select circuit to disconnect the SRAM operation circuit from the NVSRAM array, and control the second input/output interface circuit to disconnect the NVSRAM array, thereby isolating the operations of the nonvolatile storage operation circuit, the SRAM operation circuit, and the second input/output interface circuit from the data recovery operation of the column select circuit.
  • step S342 further includes step S344 (not shown).
  • Step S344 Controlling the column select circuit to disconnect the switch array coupled to the NVSRAM array. The method for isolating the operation of the nonvolatile storage operation circuit and the data recovery operation of the column select circuit can be found in the relevant description above and will not be repeated here.
  • step S343 in one example, for example, the second input/output interface circuit stops operating the second input/output interface circuit based on the received instruction from the non-volatile storage operation circuit to perform a data backup operation.
  • step S343 also includes step S345 (not shown).
  • Step S345 Controlling the isolation subcircuit to disconnect the switch coupling the second input/output interface circuit to the NVSRAM array.
  • the method for controlling a storage device may further include steps S400 - S420 (not shown in the figure).
  • Step S400 Receive a working mode signal.
  • Step S410 generating a control signal for a first data read/write operation, a data backup operation, a data recovery operation, or a second data read/write operation according to the working mode signal.
  • Step S420 providing control signals to the SRAM operation circuit, the nonvolatile memory operation circuit, the first input/output interface circuit, the column selection circuit, or the second input/output interface circuit accordingly.
  • the control circuit receives an operating mode signal, which can be used to instruct the storage device which operating mode to perform.
  • the operating mode signal can be used to instruct the storage device to perform data read and write operations, data backup operations, or data recovery operations.
  • step S410 after the control circuit receives the operating mode signal, the control circuit may generate corresponding control signals based on the received operating mode signal, for example, generating control signals for a first data read/write operation, a data backup operation, a data recovery operation, or a second data read/write operation.
  • the control signal for the first data read/write operation may include controlling the SRAM operating circuit to perform the first data read/write operation;
  • the control signal for the first data read/write operation may also include controlling the non-volatile storage operating circuit to disconnect from the NVSRAM array.
  • control signal for the data backup operation may include controlling the non-volatile storage operating circuit to perform the data backup operation;
  • control signal for the data backup operation may also include controlling the SRAM operating circuit and the second input/output interface circuit to disconnect from the NVSRAM array;
  • control signal for the data recovery operation may include controlling the column select circuit to perform the data recovery operation, controlling the non-volatile storage operating circuit to disconnect from the NVSRAM array, controlling the second input/output interface circuit to disconnect from the NVSRAM array, and controlling the column select circuit to disconnect the SRAM operating circuit from the NVSRAM array.
  • the control circuit provides the generated control signal to the corresponding operation circuit.
  • the control circuit may provide the control signal for the first data read and write operation to the SRAM operation circuit;
  • the control circuit may also provide the control signal for the first data read and write operation or the data recovery operation to the non-volatile storage operation circuit.
  • the control circuit may provide the control signal for the data backup operation to the non-volatile storage operation circuit;
  • the control circuit may also provide the control signal for the data backup operation to the SRAM operation circuit and the second input-output interface circuit.
  • control circuit may provide the control signal for the second data read and write operation to the second input-output interface circuit; Exemplarily, the control circuit may also provide the control signal for the second data read and write operation to the non-volatile storage operation circuit. Exemplarily, the control circuit may also provide the control signal for the data recovery operation to the column selection circuit.
  • control circuit generates corresponding control signals based on the received working mode signal, and provides each control signal to the corresponding operation circuit, thereby improving the reliability and efficiency of data reading, writing, backup, recovery and other operations.
  • Figure 9 shows a schematic flow diagram of a storage device operating method provided by at least one embodiment of the present disclosure.
  • the storage device operating method includes steps S500-S560. This operating method can be used, for example, for the storage device shown in Figure 2 or Figure 3.
  • Step S500 The storage device is powered on.
  • step S500 the storage device starts to be powered on, that is, the storage device is connected to a power source and starts up.
  • This process can be controlled by a power circuit, which can provide the required voltage and current to the storage device to ensure its normal operation.
  • Step S510 Determine whether data recovery is to be performed.
  • step S510 the storage device may determine whether a data recovery operation is required based on the received instruction or the state of the electronic device. If data recovery is required, step S520 is performed; otherwise, step S530 is performed.
  • Step S520 Perform data recovery.
  • step S520 for example, the data previously backed up in the RRAM storage subunit is restored to the SRAM storage subunit.
  • This step can be controlled by, for example, a column selection circuit.
  • step S520 also includes steps S700-S750 shown in FIG11 (described below).
  • Step S530 Read and write data.
  • this step can be controlled, for example, by an SRAM operation circuit or a shift register operation circuit.
  • the SRAM operation circuit (in conjunction with the selection operation of the word line driver circuit and the column select circuit) reads data from the SRAM storage sub-cells of the NVSRAM array.
  • the shift register operation circuit (in conjunction with the selection operation of the word line driver circuit) reads data from the SRAM storage sub-cells of the NVSRAM array.
  • Step S540 Determine whether to perform data backup.
  • step S540 the storage device determines whether a data backup operation is required. If data backup is required, the process proceeds to step S550; otherwise, the process proceeds to step S560.
  • Step S550 Perform data backup.
  • step S550 the storage device performs a data backup operation to back up the data in the SRAM storage subunit in the storage device to the RRAM storage subunit.
  • This step can be controlled by a non-volatile storage operation circuit.
  • step S550 also includes steps S600-S650 shown in Figure 10 (described below).
  • Step S560 Determine whether a power outage occurs.
  • step S560 the electronic device determines whether the storage device has experienced a power outage. If so, the storage device terminates operations; otherwise, the process returns to step S510 to determine whether data recovery is required. This process ensures that the storage device can continue to operate under normal operating conditions while protecting data integrity in the event of a power outage.
  • FIG10 shows a schematic flow chart of a storage device data backup method provided by at least one embodiment of the present disclosure.
  • the data backup method includes steps S600 to S650 .
  • the data backup method can be used in the storage device shown in Figure 2 or Figure 3 , for example.
  • Step S600 Read and write data.
  • step S600 when data is written, for example, data can be written to the SRAM storage subunit in the NVSRAM unit through the SRAM operation circuit, or data can be written to the SRAM storage subunit in the NVSRAM unit through the shift register operation circuit.
  • the data stored in the SRAM storage subunit can be read through the SRAM operation circuit (which can be combined with the selection operation of the word line drive circuit and the column selection circuit) and output through the first input and output interface circuit.
  • the data stored in the SRAM storage subunit can be read through the shift register operation circuit (which can be combined with the selection operation of the word line drive circuit) and output through the output interface circuit.
  • Step S610 Determine whether a data backup operation is required.
  • step S610 the storage device determines whether a data backup operation is required based on the received instruction. If data backup is required, step S620 is performed; otherwise, step S600 is continued to continue the data read and write operation.
  • Step S620 Select I row of NVSRAM cells.
  • step S620 when the storage device determines to perform a data backup operation, the word line driver circuit determines the data in row I of NVSRAM cells based on the address information.
  • I is an integer with 0 ⁇ I.
  • the word line driver circuit determines the data in rows 1 through 1 of NVSRAM cells based on the address information.
  • Step S630 backing up the data in the SRAM storage sub-units in the selected I row of storage cells to the RRAM storage sub-units simultaneously.
  • step S630 the non-volatile storage operation circuit performs a parallel operation to simultaneously back up the data in the determined row 1 of the SRAM storage sub-cells to the RRAM storage sub-cells.
  • the non-volatile storage operation circuit backs up the data in the selected rows 1 to 1 of the SRAM storage sub-cells to the RRAM storage sub-cells.
  • Step S640 Determine whether the data backup is completed.
  • step S640 the non-volatile storage operation circuit determines whether the data backup is completed. If the backup is not completed, step S650 is performed; if it is determined that the data backup is completed, the data backup operation is terminated.
  • Step S650 Increase the row address of the SRAM storage subunit by 1. Then continue with the data backup operation of steps S620-S640.
  • the wordline driver circuit updates the row address of the SRAM storage subunit, increasing the row address by one, so that the next data backup operation can proceed.
  • the nonvolatile storage operation circuit backs up the data in the determined SRAM storage subunits in rows (I+1) through (2I) to the RRAM storage subunit.
  • the data backup operation of steps S620-S640 is then continued until all data to be backed up has been backed up to the RRAM storage subunit.
  • Figure 11 shows a flow chart of a method for recovering data from a storage device according to at least one embodiment of the present disclosure. As shown in Figure 11 , the method includes steps S700 to S750. The method can be used, for example, for the storage device shown in Figure 2 or Figure 3 .
  • Step S700 Determine whether to perform a data recovery operation.
  • the storage device determines whether to perform a data recovery operation based on a received instruction or a preset instruction. If it is determined that a data recovery operation is required, step S710 will be performed; if it is determined that a data recovery operation is not required, step S740 will be directly performed.
  • Step S710 Select I row of NVSRAM cells.
  • step S710 the word line driving circuit determines the data in row I of NVSRAM cells according to the address information.
  • I is an integer and 0 ⁇ I.
  • the word line driving circuit determines the data in rows 1 to 1 of NVSRAM cells according to the address information.
  • Step S720 restoring the data of the selected I row of RRAM storage sub-units to the SRAM storage sub-units simultaneously.
  • step S720 the column selection circuit performs a parallel operation to restore the data in the determined row of RRAM storage sub-units to the SRAM storage sub-units, and then proceeds to step S730.
  • Step S730 Determine whether the data recovery operation is completed.
  • step S730 if the data recovery operation is not completed, proceed to step S750 ; if the data recovery operation is completed, proceed to step S740 .
  • Step S740 the SRAM operation circuit or the shift register operation circuit performs read and write operations on the data in the SRAM storage subunit.
  • the data in the SRAM storage subunit can be read through the SRAM operation circuit, and the read data can be input into the first input-output interface circuit for subsequent processing and use.
  • the data in the SRAM storage subunit can be read through the shift register operation circuit, and the read data can be input into the output interface circuit for subsequent processing and use.
  • the data in the SRAM storage subunit can be read through the SRAM operation circuit or the shift register operation circuit according to the bit width of the data.
  • the first input-output interface circuit can be preset to transmit high-bit-width data
  • the input interface circuit and the output interface circuit can be preset to transmit low-bit-width data.
  • the transmitted data when the transmitted data is high-bit-width data, the data in the SRAM storage subunit can be read through the SRAM operation circuit.
  • the transmitted data is low-bit-width data, the data in the SRAM storage subunit can be read through the shift register operation circuit.
  • Step S750 The row address is increased by another 1 row.
  • step S750 if the data recovery operation is not complete, the row address of the data to be recovered in the RRAM storage subunit is updated, and the row address is increased by one row to allow the next data recovery operation to proceed.
  • the column selection circuit restores the data in the RRAM storage subunits in rows (I+1) through (2I) to the SRAM storage subunit. The data recovery operation of steps S710-S730 is then continued until all data to be recovered has been restored to the SRAM storage subunit.
  • Some embodiments of the present disclosure provide a storage device, an electronic device including the storage device, and a storage device control method.
  • the storage device includes an NVSRAM array, an SRAM operating circuit, a non-volatile storage operating circuit, an error correction circuit, a first input/output interface circuit, a column selection circuit, and a second input/output interface circuit, wherein the error correction circuit is coupled to the SRAM operating circuit, the SRAM operating circuit is coupled to the column selection circuit, the column selection circuit is coupled to the NVSRAM array, and the non-volatile storage operating circuit is coupled to the NVSRAM array.
  • the NVSRAM array includes a plurality of NVSRAM cells arranged in an array, and each NVSRAM cell includes an SRAM storage sub-cell and a non-volatile storage sub-cell.
  • the non-volatile storage sub-cell is configured to perform data backup for data stored in the SRAM storage sub-cell.
  • the non-volatile storage operation circuit is configured to perform a data backup operation on the SRAM storage sub-unit data in the selected NVSRAM cell in the NVSRAM array; the SRAM operation circuit is configured to perform a first data read and write operation on the SRAM storage sub-unit data; the column selection circuit is configured to perform a data recovery operation on the non-volatile storage sub-unit data; the column selection circuit is further configured to select the object unit column to be operated in the NVSRAM array when performing the data recovery operation or when the SRAM operation circuit performs the first data read and write operation; the first input and output interface circuit is connected to the SRAM operation circuit.
  • the circuit is coupled to the SRAM operation circuit and is configured to provide the received first input data to the SRAM operation circuit and receive the first output data to be output from the SRAM operation circuit;
  • the error detection circuit is configured to encode and decode the target data and determine whether an error occurs in the target data and correct the error;
  • the column selection circuit is further configured to isolate the operation of the SRAM operation circuit and the operation of the non-volatile storage operation circuit, and to isolate the first data read and write operation, the second data read and write operation and the data recovery operation;
  • the second input and output interface circuit is coupled to the NVSRAM array and is configured to perform the second data read and write operation on the NVSRAM array.
  • the storage device uses a non-volatile storage sub-unit to back up data of an SRAM storage sub-unit, uses an error detection circuit to detect and correct erroneous storage data, uses a column selection circuit to isolate the operation of an SRAM operation circuit and the operation of a non-volatile storage operation circuit, and isolates a first data read and write operation, a second data read and write operation, and a data recovery operation.
  • the data input to or output from the storage device is transmitted through a first input and output interface circuit or a second input and output interface circuit, thereby improving the reliability and flexibility of data reading, writing, backup, and recovery.
  • FIG12 shows a schematic block diagram of a storage device provided by at least one embodiment of the present disclosure.
  • the storage device 2000 includes an NVSRAM array 220, an SRAM operation circuit 200, a non-volatile storage operation circuit 230, a column selection circuit 210, a first input-output interface circuit 250, a second input-output interface circuit 270, and an error correction circuit 260.
  • the error correction circuit 260 is coupled to the SRAM operation circuit 200, the SRAM operation circuit 200 is coupled to the column selection circuit 210, the column selection circuit 210 is coupled to the NVSRAM array 220, the non-volatile storage operation circuit 230 is coupled to the NVSRAM array 220, the first input/output interface circuit 250 is coupled to the SRAM operation circuit 200, and the second input/output interface circuit 270 is coupled to the NVSRAM array 220.
  • Coupler is used to refer to the signal connection between the description objects.
  • signal transmission can be carried out, and when the coupling is disconnected between the description objects, signal connection cannot be carried out.
  • Coupling can be achieved by, for example, electrical connection.
  • “coupling” can include two or more electronic components or circuits being connected together in some way so that signals between them are transmitted to each other.
  • two storage sub-units can be directly connected to achieve information transmission through the transmission of signals or energy, or the two storage sub-units can be connected through other circuit elements, such as resistors, capacitors, switches, optoelectronic elements and other elements or transmission line networks, to achieve signal transmission.
  • the NVSRAM array 220 includes a plurality of NVSRAM cells 221 arranged in an array, and each NVSRAM cell 221 includes an SRAM storage sub-cell 222 and a non-volatile storage sub-cell 231.
  • the non-volatile storage sub-cell 231 is configured to perform data backup for the data stored in the SRAM storage sub-cell 222.
  • the array formed by the plurality of NVSRAM cells 221 includes a plurality of rows and a plurality of columns.
  • the plurality of NVSRAM cells 221 can form a storage array including M rows and N columns, where M and N are integers and 1 ⁇ M, 1 ⁇ N.
  • the NVSRAM cell 221 can, for example, take the form shown in FIG1 , but the embodiments of the present disclosure are not limited to this specific form.
  • the NVSRAM cells 221 of the NVSRAM array 220 combine the characteristics of SRAM storage subcells and non-volatile storage subcells.
  • the SRAM storage subcells 222 can be configured to store data and quickly read and write data.
  • the non-volatile storage subcells 231 are configured to back up the data stored in the SRAM storage subcells 222 to prevent data loss in the event of a power outage or system crash.
  • the non-volatile storage subunit 231 may include RRAM, FeRAM (Ferroelectric Random Access Memory), MRAM (Magnetic Random Access Memory), PCM (Phase Change Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), PRAM, flash memory, and other storage subunits.
  • the non-volatile storage operating circuit 230 in the embodiments of the present disclosure is adjusted accordingly to correspond to different types of non-volatile storage subunits 231, and the present disclosure is not limited to this.
  • the non-volatile storage operating circuit 230 may include an RRAM operating circuit.
  • the nonvolatile memory operation circuit 230 is configured to perform a data backup operation on the data of the SRAM memory sub-cell 222 in the selected NVSRAM cell 221 in the NVSRAM array 220 .
  • the non-volatile storage operation circuit 230 can communicate with multiple SRAM storage subunits 222.
  • the non-volatile storage operation circuit 230 can perform data backup operations on the data in the SRAM storage subunits 222 as needed. For example, when the electronic device detects that an application has failed or is abnormal, the non-volatile storage operation circuit 230 performs a backup operation.
  • the non-volatile storage operation circuit 230 can also perform data backup operations on the data in the SRAM storage subunits 222 in response to a backup instruction, perform data backup operations on the SRAM storage subunits 222 periodically based on a preset time, or perform data backup operations on the SRAM storage subunits 222 in real time.
  • the non-volatile storage operation circuit 230 can employ a parallel processing method to simultaneously perform data backup operations on the data of multiple selected SRAM storage subunits 222.
  • the non-volatile storage operation circuit 230 can simultaneously perform data backup operations on the data in a certain row of SRAM storage subunits 222, or the non-volatile storage operation circuit 230 can simultaneously perform data backup operations on the data in multiple rows of SRAM storage subunits 222.
  • At least one embodiment of the present disclosure also adopts some safety designs to improve the redundancy of the non-volatile storage operation circuit 230.
  • the non-volatile storage operation circuit 230 can adopt a double backup mechanism, and the data of each SRAM storage sub-unit 222 can be backed up twice or more to reduce the risk of data loss.
  • the non-volatile storage operation circuit 230 can employ an ECC (Error Checking and Correcting) mechanism.
  • ECC Error Checking and Correcting
  • the ECC mechanism can add additional check bits to detect and correct errors when data is read.
  • the ECC mechanism can improve data reliability and reduce the risk of data loss due to hardware failure or data corruption.
  • the non-volatile storage operation circuit 230 may also adopt a CRC (Cyclic Redundancy Check) mechanism to calculate the CRC value of the data before and after the data backup operation to ensure the integrity of the data. If the CRC values do not match, the non-volatile storage operation circuit 230 may take corresponding measures to recover the data or perform error handling.
  • CRC Cyclic Redundancy Check
  • inventions of the present disclosure may also adopt other data verification and error correction mechanisms, including but not limited to parity check, SED (Single-bit Error Detection), SEC (Single-bit Error Correction), DED (Double-bit Error Detection) or FED (Fatal Error Detection), etc., and the embodiments of the present disclosure are not limited to this.
  • SED Single-bit Error Detection
  • SEC Single-bit Error Correction
  • DED Double-bit Error Detection
  • FED Total Error Detection
  • the first input/output interface circuit 250 is configured to provide received first input data to the SRAM operation circuit 200 and receive first output data to be output from the SRAM operation circuit 200.
  • the SRAM operation circuit 200 is configured to perform a first data read/write operation on the SRAM storage subunit 222.
  • the second input/output interface circuit 270 is configured to perform a second data read/write operation on the NVSRAM array 220.
  • the "first data read/write operation” refers to the SRAM operating circuit 200 performing a data read/write operation on the SRAM storage subunit 222.
  • the “second data read/write operation” refers to the second input/output interface circuit 270 performing a data read/write operation on the SRAM storage subunit 222.
  • the first input/output interface circuit 250 can be configured to receive first input data input to the storage device 2000 and provide the first input data to the SRAM operating circuit 200.
  • the first input/output interface circuit 250 can be configured to receive first output data to be output from the SRAM operating circuit 200.
  • the storage device 2000 can determine whether the data input to the storage device 2000 is input to the storage device 2000 from the first input/output interface circuit 250 or from the second input/output interface circuit 270 based on the received control instruction, the bit width or data type of the data input to the storage device 2000, the operating conditions of each circuit in the storage device 2000, etc.
  • the column selection circuit 210 performs a data recovery operation
  • the data input to the storage device 2000 can be input from the second data input/output interface circuit 260.
  • the second input/output interface circuit 270 performs a second data read/write operation
  • the data input to the storage device 2000 can be input from the second input/output interface circuit 270.
  • the bit width of the input or output data of the first input/output interface circuit 250 and the second input/output interface circuit 270 can be preset.
  • the data bit width of the input or output of the first input/output interface circuit 250 can be preset to be greater than that of the second input/output interface circuit 270.
  • the data bit width of the input or output of the first input/output interface circuit 250 is preset to be 32 bits
  • the data bit width of the input or output of the second input/output interface circuit 270 is preset to be 512 bits. Then, when the data bit width of the input storage device 2000 is 32 bits, the data can be input from the first input/output interface circuit 250.
  • the embodiments of the present disclosure are not limited to this.
  • the received read and write instructions, data bit width or data type, the working conditions of each circuit in the storage device 2000, etc. can be used to determine whether the SRAM operation circuit 200 performs a first data read and write operation on the selected SRAM storage sub-unit 222, or whether the second input and output interface circuit 250 performs a second data read and write operation on the selected SRAM storage sub-unit 222.
  • the SRAM operation circuit 200 receives the corresponding data read/write instruction and performs a first data read/write operation on the selected SRAM storage subunit 222.
  • the column selection circuit 210 performs a data restoration operation, and the SRAM operation circuit 200 reads the data in the SRAM storage subunit 222 and inputs the data into the error detection and correction circuit 260.
  • the column selection circuit 210 is configured to select a target cell column in the NVSRAM array 220 that needs to be operated on when performing a data recovery operation or when the SRAM operation circuit 200 performs a first data read/write operation. For example, when the SRAM operation circuit 200 performs the first data read/write operation or when the column selection circuit 210 performs a data recovery operation, the column selection circuit 210 responds to a received address signal and converts it into an electrical signal, thereby selecting a corresponding target cell column in the NVSRAM array 220.
  • the column selection circuit 210 may select a corresponding target cell column in the NVSRAM array 220 based on an instruction that the SRAM operation circuit 200 needs to perform the first data read/write operation or that the column selection circuit 210 needs to perform a data recovery operation.
  • target cell column refers to the memory cell column being operated on, which can be any column in a plurality of memory arrays.
  • Address signals include row select signals and column select signals.
  • the word line driver circuit (described below) uses row select signals for row addressing, while the column select circuit uses column select signals for column addressing.
  • the operation of the non-volatile storage operation circuit 230, the operation of the SRAM operation circuit 200, the second input/output interface circuit 270, and the data recovery operation of the column selection circuit 210 may affect each other, thereby affecting the stability of data backup and data recovery.
  • the column select circuit 210 may be further configured to isolate the operation of the SRAM operation circuit 200 from the operation of the non-volatile memory operation circuit 230.
  • the second input/output interface circuit 270 may be further configured to isolate the operation of the second input/output interface circuit 270 from the operation of the non-volatile memory operation circuit 230.
  • independent column selection circuits 210 may be provided for the non-volatile storage operation circuit 230 and the SRAM operation circuit 200 respectively to reduce the influence and interference between the two.
  • the independent column selection circuits 210 may have different circuit structures and components to adapt to the characteristics and operation requirements of the non-volatile storage operation circuit 230 and the SRAM operation circuit 200.
  • the column selection circuit 210 may also not perform a data recovery operation when the SRAM operation circuit 200 performs a first data read and write operation, the second input and output interface circuit 270 performs a second data read and write operation, or the non-volatile storage operation circuit 230 performs a data backup operation, so as to isolate the first data read and write operation, the second data read and write operation, the data backup operation, and the data recovery operation.
  • power supply isolation can be implemented for the non-volatile memory operating circuit 230, the SRAM operating circuit 200, or the second input/output interface circuit 270.
  • independent power supplies or power supply lines can be provided for the non-volatile memory operating circuit 230, the SRAM operating circuit 200, or the second input/output interface circuit 270.
  • a voltage regulator can be added to the non-volatile memory operating circuit 230, the SRAM operating circuit 200, or the second input/output interface circuit 270 to improve circuit power supply stability.
  • an optical coupler can be used to transmit data from the non-volatile memory operating circuit 230, the SRAM operating circuit 200, or the second input/output interface circuit 270 via optical signals.
  • the operation of the non-volatile storage operation circuit 230, the operation of the SRAM operation circuit 200, or the operation of the second input-output interface circuit 270 can also be controlled through logic design. For example, in specific circumstances, only the operation of the non-volatile storage operation circuit 230, or only the operation of the SRAM operation circuit 200, or only the operation of the second input-output interface circuit 270 can be allowed, and the non-volatile storage operation circuit 230 and the SRAM operation circuit 200 or the second input-output interface circuit 270 are prohibited from operating simultaneously.
  • the first input-output interface circuit 250 is configured to provide the received first input data to the SRAM operation circuit 200 and receive the first output data to be output from the SRAM operation circuit 200;
  • the error correction circuit 260 is configured to encode and decode the target data and determine whether an error occurs in the target data and correct the error.
  • the error detection circuit 260 can encode the data using a parity check code, and can add an additional data check bit to the data so that the number of 1s in the entire byte is an even number (even check) or an odd number (odd check).
  • the error detection circuit 260 can check the check bit.
  • the error detection circuit 260 can also encode the data using a Hamming code, divide the data into multiple groups, and add a check bit to each group so that erroneous data in each group can be detected and corrected.
  • the error detection circuit 260 can also encode the data using a cyclic redundancy check (CRC) method, add redundant check codes to the data, regard the data as a binary polynomial, use the generating polynomial to perform a modulo-2 division operation on it, and the remainder obtained is the CRC check code.
  • CRC cyclic redundancy check
  • the error correction and detection circuit 260 may further include a data encoder and a data decoder.
  • the data encoder may be configured to convert input data into a specific encoding format and add redundant information to the data, such as a parity check code, a Hamming code, a cyclic redundancy check code, etc.
  • the data decoder may be configured to decode the received encoded data into the original data and, at the same time, perform error detection on the data, such as through a parity check, a CRC check, etc.
  • the error detection and correction circuit 260 may also include error detection and correction logic and control logic.
  • the error detection and correction logic can perform error detection on the decoded data and determine whether the error can be corrected based on the encoding method. For example, if a parity check code is used, the logic will check the check bits and determine the error bits, and then correct the error bits. For some complex error situations, multiple error correction or degradation processes may be required.
  • the control logic is used to control the entire process of data encoding, transmission, decoding, and error correction, and can also be used to interact with other circuits, such as sending control signals to the column selection circuit 210 to control data transmission.
  • the error correction and detection circuit 260 may also be configured to: encode target data input from the SRAM operation circuit 200 to the error correction and detection circuit 260 when the non-volatile storage operation circuit 230 performs a data backup operation; and determine whether an error occurs in the target data read from the NVSRAM array 220 by the SRAM operation circuit 200 and input to the error correction and detection circuit 260 and correct the error when the column selection circuit 210 completes a data recovery operation.
  • the SRAM operation circuit 200 reads data from the SRAM storage subunit 222 of the NVSRAM array and inputs the data into the error correction circuit 260.
  • the error correction circuit 260 encodes the data.
  • the encoding can increase the redundancy of the data by adding additional check bits, so that after the data is written to the NVSRAM array 220 again, even if part of the data is damaged or lost, errors can be detected and corrected by the check bits.
  • the encoded data will be written into the SRAM operation circuit 200 by the error correction circuit 260.
  • the SRAM operation circuit 200 receives the encoded data from the error correction circuit 260 and writes it into the NVSRAM array 220 through the column selection circuit.
  • the error correction circuit 260 encodes the K-bit information code of the read target data to obtain an R-bit check code, and writes the R-bit check code into the SRAM storage subunit 222 of the NVSRAM array 220 through the SRAM operation circuit 200.
  • K and R are positive integers.
  • the error correction circuit 260 when encoding, obtains the K-bit information code of the target data, and then processes it through a specific encoding algorithm.
  • the algorithm can generate an R-bit check code corresponding to the content of the K-bit information code.
  • the generated R-bit check code can be used to detect and correct errors that may occur during data transmission or storage.
  • the error correction circuit 260 will write the data including the R-bit check code into the SRAM storage subunit 222 of the NVSRAM array 220 through the SRAM operation circuit 200.
  • the check code By storing the check code in the NVSRAM array 220, the data can be protected during subsequent transmission or storage. Even if a data transmission error or storage medium damage occurs, the data can be recovered and corrected through the check code, thereby improving the reliability of the data and the stability of the system.
  • the column selection circuit can turn on the coupling between the SRAM operation circuit 200 and the NVSRAM array 220.
  • the error correction circuit 260 can determine whether an error has occurred in the read data and correct the error. For example, the read data can be compared with the expected data. If an error is found, the error correction circuit 260 will use the check bit added during the encoding process to correct the error. For example, if one bit in the read data is wrong, the error correction circuit 260 can use the check bit to detect the error and use the correct value expected during the encoding process to correct the error.
  • the error detection and correction circuit 260 decodes the encoded target data read from the NVSRAM array 220 by the SRAM operation circuit 200. During decoding, the error detection and correction circuit 260 decodes and detects errors in the K-bit information code and R-bit parity check code of the read target data. In response to errors, the error detection circuit 260 performs error correction and writes the K-bit error-corrected information code into the NVSRAM array 220 via the SRAM operation circuit 200. For example, during decoding, the SRAM operation circuit 200 reads the target data, including the K-bit information code and R-bit parity check code, from the NVSRAM array 220 and passes it to the error detection and correction circuit 260.
  • the error detection and correction circuit 260 uses a specific decoding algorithm to decode and detect errors in the read data. During this process, the error detection and correction circuit 260 can check the integrity of the data and detect whether there are errors using the parity check code. If an error is detected during the decoding process, the error detection and correction circuit 260 can activate the error correction mechanism. The error detection and correction circuit 260 can then take appropriate error correction measures based on the type and severity of the error. For example, the error detection circuit 260 can write the K-bit error-corrected information code into the SRAM storage subunit 222 of the NVSRAM array 220 through the SRAM operation circuit 200 to replace the original erroneous data. This not only improves the accuracy of the data, but also improves the security and reliability of the stored data.
  • the error detection circuit 260 encodes the data including the K-bit information code input from the SRAM operation circuit 200 to obtain R-bit parity code data.
  • the error detection circuit 260 then writes the encoded data including the R-bit parity code into the SRAM operation circuit 200.
  • the SRAM operation circuit 200 writes the data including the R-bit parity code into the NVSRAM array 220 via the column selection circuit.
  • the error detection circuit 260 decodes the data including the K-bit information code and the R-bit parity code read from the NVSRAM array 220 by the SRAM operation circuit 200 and input to the error detection circuit 260, determines whether an error occurs in the decoded result, and performs error correction if an error occurs.
  • the storage device 2000 may perform error correction and detection operations when performing a data backup operation or a data recovery operation, but may not perform error correction and detection operations when performing a first data read and write operation or a second data read and write operation, thereby increasing the speed of data reading and writing.
  • the error correction and detection circuit 260 may use different encoding and decoding algorithms, such as parity check, CRC check, and other different verification methods, which are not limited by the embodiment of the present disclosure.
  • the data writing and reading process may also vary depending on the specific hardware and interface design.
  • FIG13 shows a schematic block diagram of another storage device provided by at least one embodiment of the present disclosure.
  • the second input/output interface circuit 270 includes a shift register operation circuit 271, an input interface circuit 272, and an output interface circuit 273.
  • the shift register operation circuit 271 is coupled to the NVSRAM array 220 and is configured to perform second data read and write operations on the NVSRAM array 220;
  • the input interface circuit 272 is coupled to the shift register operation circuit 271 and is configured to receive second input data and provide the received second input data to the shift register operation circuit 271;
  • the output interface circuit 273 is coupled to the shift register operation circuit 271 and is configured to receive second output data to be output from the shift register operation circuit 271.
  • second input data refers to data input to the storage device 2000 via the input interface circuit 272 in the second input/output interface circuit 270.
  • second output data refers to data output from the storage device 2000 via the output interface circuit 273 in the second input/output interface circuit 270.
  • the embodiments of the present disclosure do not limit the content and format of the data.
  • the shift register operation circuit 271 can input the received second input data into the SRAM storage subunit 222 of the NVSRAM array 220, or the shift register operation circuit 271 can read the second output data from the SRAM storage subunit 222 of the NVSRAM array 220 and output the data to the storage device 2000 through the output interface circuit 273.
  • the shift register operation circuit 271 may temporarily store the received second input data, and then input the second input data into the SRAM storage subunit 222 in the NVSRAM array 220 .
  • the shift register operation circuit 271 may further convert the received second input data.
  • the shift register operation circuit 271 may convert the second input data received serially into the SRAM storage sub-units 222 in the NVSRAM array 220 in parallel.
  • the NVSRAM array 220 may further be configured to be coupled to a word line driver circuit 240.
  • the word line driver circuit 240 is configured to select a target cell row to be operated in the NVSRAM array 220 when the SRAM operation circuit 200 performs a first data read/write operation, when the second input/output interface circuit 270 performs a second data read/write operation, when the non-volatile storage operation circuit performs a data backup operation, when the column selection circuit performs a data recovery operation, or when the non-volatile storage operation circuit performs a data backup operation.
  • the “object cell row” is used to refer to a storage cell row that is an operation object, which may be any row in a plurality of storage arrays.
  • the word line driver circuit 240 for the NVSRAM array 220 is configured to control the rows (word lines) of memory cells in the NVSRAM array 220.
  • each memory cell is located at the intersection of signal lines, i.e., the horizontal signal lines are word lines, and the vertical signal lines are bit lines.
  • the word line driver circuit 240 is responsible for controlling the switches connected to the word lines to determine which row of memory cells is selected for the desired operation (correspondingly, the column select circuit 210 is responsible for determining which column of memory cells is selected for the desired operation via the bit lines).
  • word line driver circuit 240 may include a decoder and a selector.
  • the decoder receives an address signal and decodes it into a row address for the corresponding word line.
  • the selector selects the corresponding word line based on the row address and applies a drive signal.
  • word line driver circuit 240 ensures correct access to the selected memory cell while avoiding interference or malfunction in other unselected memory cells.
  • the word line driver circuit 240 may be configured to select a row of memory cells in the NVSRAM array 220 to be selected for the second data read/write operation.
  • the second input/output interface circuit 270 may read data from the selected row; when performing a data write operation, the second input/output interface circuit 270 may write data to the selected row of memory cells.
  • the column selection circuit can be used to determine which column of storage cells is selected for the second data read and write operation, or the second data read and write operation can be performed on all columns of storage cells in the NVSRAM array 220.
  • the embodiments of the present disclosure are not limited to this.
  • the word line driver circuit 240 may be configured to select which row of memory cells in the NVSRAM array 220 is selected for the first data read/write operation or the data recovery operation.
  • the SRAM operation circuit 200 may read the selected row of data during a data read operation; and may write data to the selected row of memory cells during a data write operation.
  • the word line driver circuit 240 may be configured to select a row of memory cells in the NVSRAM array 220 to be selected for the data backup operation.
  • the non-volatile storage operation circuit 230 may read the data of the selected row in the SRAM storage sub-unit 222 and back up the data of the row in the SRAM storage sub-unit 222 to the non-volatile storage sub-unit 231.
  • the word line driver circuit 240 may be configured to select a row of memory cells in the NVSRAM array 220 to be selected for the data recovery operation. For example, when performing the data recovery operation, the column selection circuit 210 may restore the data of the selected row in the nonvolatile memory sub-cell 231 to the SRAM memory sub-cell 222.
  • FIG14 shows a schematic block diagram of another storage device provided by at least one embodiment of the present disclosure.
  • the second input/output interface circuit 270 may further include an isolation sub-circuit 274.
  • the isolation sub-circuit 274 is coupled between the NVSRAM array 220 and the shift register operation circuit 271.
  • the isolation sub-circuit 274 may be configured to turn on a switch coupling the shift register operation circuit 271 to the NVSRAM array 220 when the shift register operation circuit 271 performs a second data read/write operation.
  • the isolation sub-circuit 274 may be configured to turn off the switch coupling the shift register operation circuit 271 to the NVSRAM array 220 when the non-volatile storage operation circuit 230 performs a data backup operation.
  • the isolation sub-circuit 274 can couple the shift register operation circuit 271 and the NVSRAM array 220.
  • the shift register operation circuit 271 can then perform the second data read/write operation on the SRAM storage subunits 222 in the NVSRAM array 220, thereby achieving fast data read/write transmission.
  • the non-volatile storage operation circuit 230 is disconnected from the NVSRAM array 220, the read/write operation of the shift register operation circuit 271 is not affected.
  • the isolation sub-circuit 274 can disconnect the shift register operation circuit 271 from the NVSRAM array 220, while the non-volatile storage operation circuit 230 is coupled to the NVSRAM array 220.
  • the non-volatile storage operation circuit 230 can perform a data backup operation, and the shift register operation circuit 271 will not affect the data backup operation of the non-volatile storage operation circuit 230.
  • the column selection circuit 210 can also be configured to connect the coupling between the SRAM operation circuit 200 and the NVSRAM array 220
  • the non-volatile storage operation circuit 230 can be configured to disconnect the coupling with the NVSRAM array 220
  • the second input-output interface circuit 260 can be configured to disconnect the coupling with the NVSRAM array 220.
  • the column selection circuit 210 can also be configured to disconnect the SRAM operation circuit 200 and the NVSRAM array 220
  • the non-volatile storage operation circuit 230 can also be configured to connect the coupling with the NVSRAM array 220
  • the second input-output interface circuit 260 can be configured to disconnect the coupling with the NVSRAM array 220.
  • the column selection circuit 210 when the column selection circuit 210 performs a data recovery operation, the column selection circuit can also be configured to disconnect the SRAM operation circuit 200 and the NVSRAM array 220, the non-volatile storage operation circuit 230 can be configured to disconnect the NVSRAM array 220, and the second input-output interface circuit 260 can be configured to disconnect the NVSRAM array 220.
  • the column selection circuit 210 can also be configured to disconnect the SRAM operation circuit 200 and the NVSRAM array 220, and the non-volatile storage operation circuit 230 can also be configured to disconnect the NVSRAM array 220.
  • the column select circuit 210 couples the SRAM operating circuit 200 and the NVSRAM array 220.
  • the SRAM operating circuit 200 can then perform read/write operations on the SRAM storage subunits 222 in the NVSRAM array 220, thereby achieving fast data read/write transmission.
  • the non-volatile storage operating circuit 230 is disconnected from the NVSRAM array 220 and the second input/output interface circuit 260 is disconnected from the NVSRAM array 220, the read/write operations of the SRAM operating circuit 200 are not affected.
  • the non-volatile storage operation circuit 230 needs to perform data backup, the second input/output interface circuit 260 is disconnected from the NVSRAM array 220, and the column selection circuit 210 disconnects the SRAM operation circuit 200 from the NVSRAM array 220, while the non-volatile storage operation circuit 230 is coupled to the NVSRAM array 220.
  • the non-volatile storage operation circuit 230 can perform the backup operation, and the SRAM operation circuit 200 will not affect the data backup process.
  • the second input/output interface circuit 260 is disconnected from the NVSRAM array 220, the column selection circuit 210 disconnects the SRAM operation circuit 200 from the NVSRAM array 220, and the non-volatile storage operation circuit 230 is also disconnected from the NVSRAM array 220. Therefore, the SRAM operation circuit 200, the non-volatile storage operation circuit 230, and the second input/output interface circuit 260 will not affect the data recovery operation process of the column selection circuit 210.
  • the non-volatile storage operation circuit 230 is disconnected from the NVSRAM array 220, and the column selection circuit 210 disconnects the SRAM operation circuit 200 from the NVSRAM array 220. Therefore, the operations of the SRAM operation circuit 200 and the non-volatile storage operation circuit 230 will not affect the second data read/write operation process of the second input/output interface circuit 260.
  • the column selection circuit 210 further includes a data recovery operation sub-circuit 211 .
  • the data recovery operation subcircuit 211 can be configured to perform a data recovery operation on the data in the non-volatile storage sub-unit 231 in the target cell column. For example, upon receiving a data recovery operation instruction, the data recovery operation subcircuit 211 can restore the data stored in the selected non-volatile storage sub-unit 231 to the SRAM storage sub-unit 222.
  • the data recovery operation subcircuit when performing a data recovery operation, the data recovery operation subcircuit must ensure isolation from the operations of the SRAM operation circuit 200, the second input/output interface circuit 260, and the non-volatile storage operation circuit 230 to prevent conflicts between the first data read/write operation, the second data read/write operation, the data backup operation, and the data recovery operation, thereby improving data integrity and system stability.
  • the column selection circuit 210 or the isolation sub-circuit 264 may further include a switch array (not shown).
  • the column selection circuit 210 may control the coupling between the SRAM operation circuit 200 and the NVSRAM array 220 through the switch array.
  • the shift register operation circuit 261 may be coupled to the NVSRAM array 220 through the switch array of the isolation sub-circuit 264.
  • the column selection circuit 210 may be configured to turn on the switch array coupling the column selection circuit 210 to the NVSRAM array 220.
  • the column selection circuit 210 may also be configured to turn off the switch array coupling the column selection circuit 210 to the NVSRAM array 220.
  • the switch array of the column selection circuit 210 or the isolation sub-circuit 264 can be turned on or off according to the timing logic that controls the operation of the non-volatile memory operation circuit 230, the operation of the SRAM operation circuit 200, or the operation of the shift register operation circuit 261. For example, at a specific timing, when only the SRAM operation circuit 200 is allowed to operate, the switch array of the column selection circuit 210 is turned on. For example, at a specific timing, when only the non-volatile memory operation circuit 230 is allowed to operate, the switch array of the column selection circuit 210 is turned off.
  • the array width of the NVSRAM array 220 can be configured as N, i.e., having N columns of memory cells (or 2N bit lines).
  • each row in the NVSRAM array 220 can include N NVSRAM cells.
  • the NVSRAM array 220 can also be configured to have M rows of memory cells.
  • each column in the NVSRAM array 220 can include M NVSRAM cells.
  • Each memory cell has a corresponding address for locating and accessing the memory cell.
  • the NVSRAM array 220 can also be configured to have M rows of memory cells.
  • each row in the NVSRAM array 220 includes N memory cells, and each memory cell is configured with X bit lines (X is greater than or equal to 1).
  • the number of bit lines in the NVSRAM memory array is X*N. If the transmission lines are bit line pairs, X can be configured as 2, and the number of bit lines in the NVSRAM memory array can be configured as 2N. In some embodiments, for example, the NVSRAM array 220 can be configured in units of words.
  • the nonvolatile storage operation circuit 230 can be configured to be coupled to the NVSRAM array 220 through N groups of transmission lines. For example, in at least one example, when the transmission lines are bit lines or bit line pairs (e.g., bit lines BL and BLN as shown in FIG. 1 ), the nonvolatile storage operation circuit 230 can also be configured to be coupled to the NVSRAM array 220 through N or 2N bit lines.
  • the N columns of storage cells of the NVSRAM array 220 may include K columns of data columns and R columns of redundant columns, the data columns store information codes, and the redundant columns store additional check codes required by the encoding.
  • the NVSRAM array 220 is configured in units of words, and each row of the NVSRAM array 220 stores P words of data, and the operation bit width of each word can be configured as W.
  • the NVSRAM array 220 includes K columns of data columns to store information codes, and R columns of redundant columns to store check codes.
  • the information code can be configured in units of "words”
  • the check code can be configured in units of "pages" and the embodiments of the present disclosure are not limited to this.
  • W can be W1 or W2 .
  • data columns and redundant columns can be arranged in various ways. For example, as shown in Figures 15, 16A, and 16B, all data columns can be arranged adjacent to each other, and all redundant columns can be arranged adjacent to each other; or data columns can be grouped, redundant columns can be grouped, and then the data column groups and redundant column groups can be arranged alternately.
  • K-bit data columns and R-bit redundant columns can be arranged as a combination, and the NVSRAM array can include N columns of this combination; or, the NVSRAM array can include multiple groups of K data columns and R data columns; or, the NVSRAM array can include multiple groups of K data bits and R redundant bits.
  • the K data bits can include multiple rows of information code data
  • the R redundant bits can include multiple check code data.
  • the embodiments of the present disclosure do not limit the arrangement of data columns and redundant columns.
  • the error detection and correction circuit 260 can be configured to couple to the SRAM operation circuit 200 via K+R groups of transmission lines.
  • the SRAM operation circuit can be configured to couple to the first input/output interface circuit 250 via W1 groups of transmission lines.
  • the SRAM operation circuit 200 can also be configured to couple to the column selection circuit 210 via W1 groups of transmission lines.
  • the nonvolatile storage operation circuit 230 is coupled to the NVSRAM array 220 via N groups of transmission lines.
  • the column selection circuit 210 is coupled to the NVSRAM array 220 via N groups of transmission lines.
  • the column selection circuit 210 can also be configured to couple to the NVSRAM array 220 via N or 2N bit lines.
  • the column selection circuit 210 can also be configured to set the voltages of the 2N bit lines to the same voltage value.
  • the memory device 2000 may be configured such that W 1 ⁇ K+R ⁇ N*M.
  • the error correction and detection circuit 260 is coupled to the SRAM operation circuit 200 via the K+R group of transmission lines, and writes the encoded data including the R-bit parity code into the SRAM operation circuit 200.
  • the data including the K-bit information code and the R-bit parity code read from the NVSRAM array 220 by the SRAM circuit is written into the error correction and detection circuit 260 via the K+R group of transmission lines.
  • the SRAM operation circuit 200 is connected to the column selection circuit 210 via the W1 group of transmission lines, and is configured to locate and access a specific memory cell in the NVSRAM array 220 based on an address provided by the column selection circuit 210, write data including the R-bit parity code into the NVSRAM array 220, and read data including the K-bit information code and the R-bit parity code from the NVSRAM array 220.
  • the shift register operation circuit 271 can be coupled to the NVSRAM array 220 through N groups of transmission lines
  • the input interface circuit 272 can be coupled to the shift register operation circuit 271 through W 2 groups of transmission lines
  • the output interface circuit 273 can be coupled to the shift register operation circuit 271 through W 2 groups of transmission lines, where W 2 and N are integers and N ⁇ W 2 >1.
  • the shift register operation circuit 271 is connected to the NVSRAM array 220 through N groups of transmission lines.
  • the transmission lines are bit line pairs (for example, the bit lines BL and BLN shown in Figure 1)
  • the shift register operation circuit 271 can also be connected to the NVSRAM array 220 through 2N bit lines.
  • W1 and W2 can be used to represent the operating bit width of each word in the transmitted data.
  • the storage device 2000 can select any first input-output interface circuit 250 or input interface circuit 272 to receive data input to the storage device 2000, or select any first input-output interface circuit 250 or output interface circuit 273 to output data.
  • W1 is greater than W2 and the same
  • the input interface of the data can be determined based on the data bit width of the input storage device 2000; for example, W1 can be 512 bits and W2 can be 32 bits.
  • the first input-output interface circuit 250 is selected to receive or output the data.
  • the word line driving circuit 240 can also be configured to select the SRAM storage sub-unit 222 data in the I-row NVSRAM unit 221 of the NVSRAM array 220 to perform a data backup operation, where I is an integer and M ⁇ I ⁇ 1.
  • the word line driver circuit 240 may select the SRAM storage sub-units 222 in the NVSRAM cells 221 in row 1 of the NVSRAM array 220 according to the received data backup operation instruction.
  • the word line driver circuit 240 may select the SRAM storage sub-units 222 in the NVSRAM cells 221 in rows 1 to 1
  • the non-volatile storage operation circuit 230 may be configured to perform a parallel data backup operation on the data of the SRAM storage sub-units 222 in the NVSRAM cells 221 in rows 1 to 1 selected by the word line driver circuit 240, and back up all the data of the selected SRAM storage sub-units 222 in row 1 to 1 to the non-volatile storage sub-unit 231.
  • the word line driving circuit 240 can also be configured to select the non-volatile storage sub-unit 231 data in the J-row NVSRAM unit 221 of the NVSRM array 220 to perform a data recovery operation, where J is an integer and M ⁇ J ⁇ 1.
  • the word line driver circuit 240 may select the non-volatile storage sub-cells 231 in the Jth row of NVSRAM cells 221 in the NVSRAM array 220 according to the received data recovery operation instruction.
  • the word line driver circuit 240 may select the non-volatile storage sub-cells 231 in the 1st to the Jth rows of NVSRAM cells 221, and the column selection circuit 210 may be configured to perform a parallel data recovery operation on the data of the non-volatile storage sub-cells 231 in the 1st to the Jth rows of NVSRAM cells 221 selected by the word line driver circuit 240, thereby restoring all the data of the non-volatile storage sub-cells 231 in the selected Jth row to the SRAM storage sub-cells 222.
  • the SRAM operation circuit 200 is further configured to, when performing the first data read/write operation, perform the first data read/write operation on the data of the SRAM storage sub-units 222 in the W 1 NVSRAM cells 221 in the i-th row of the selected NVSRAM array 220, where N ⁇ W 1 ⁇ 1 and M ⁇ i ⁇ 1.
  • the operation bit width of the first data read/write operation of the SRAM operation circuit 200 is W 1.
  • the SRAM operation circuit 200 may perform the first data read/write operation on the data of the SRAM storage sub-units 222 in W 1 NVSRAM cells 221 in a row (i-th row) of the selected NVSRAM array 220 according to the received first data read/write operation instruction.
  • the second input/output interface circuit 270 is further configured to, when performing the second data read/write operation, perform the second data read/write operation on the data of the SRAM storage sub-units 222 in the W 2 NVSRAM cells 221 in the i-th row of the selected NVSRAM array 220, where N ⁇ W 2 ⁇ 1 and M ⁇ i ⁇ 1.
  • the operation bit width of the second data read/write operation of the second input/output interface circuit 270 is W 2 .
  • the SRAM operation circuit 200 may perform the second data read/write operation on the data of the SRAM storage sub-units 222 in W 2 NVSRAM cells 221 in a selected row (i-th row) of the NVSRAM array 220 according to the received second data read/write operation instruction.
  • the nonvolatile storage operation circuit 230 is further configured to perform a data backup operation on the data of the SRAM storage sub-units 222 in the NVSRAM cells 221 in the selected E row and/or F column of the NVSRAM array 220 when performing a data backup operation.
  • E and F are integers and M ⁇ E ⁇ 1, and N ⁇ F ⁇ 1.
  • the operation bit width of the data backup operation of the non-volatile storage operation circuit 230 is N*M.
  • the nonvolatile storage operation circuit 230 may perform a data backup operation on the data of the SRAM storage sub-units 222 in the selected NVSRAM cells 221 in row E or column F among the NVSRAM cells 221 with M rows and N columns in the NVSRAM array 220 according to the received data backup operation instruction.
  • the nonvolatile storage operation circuit 230 may perform a data backup operation on all the data of the SRAM storage sub-units 222 in the selected NVSRAM cells 221 in row E and column F among the NVSRAM cells 221 with M rows and N columns in the NVSRAM array 220.
  • the column selection circuit 210 is further configured to, when performing a data recovery operation, perform a data recovery operation on the data of the nonvolatile storage sub-cell 231 in the NVSRAM cell 221 in the G row and/or H column of the selected NVSRAM array 220.
  • G and H are integers and M ⁇ G ⁇ 1, N ⁇ H ⁇ 1.
  • the operation bit width of the data recovery operation of the column selection circuit 210 is N*M.
  • the column selection circuit 210 may perform a data recovery operation on the data of the nonvolatile storage sub-cells 231 in the selected G-row or H-column NVSRAM cells 221 among the M-row and N-column NVSRAM cells 221 in the NVSRAM array 220 according to the received data recovery operation instruction.
  • the nonvolatile storage operation circuit 230 may perform a data recovery operation on all the data of the nonvolatile storage sub-cells 231 in the selected G-row or H-column NVSRAM cells 221 among the M-row and N-column NVSRAM cells 221 in the NVSRAM array 220.
  • parameters such as the number and type of these transmission lines can be flexibly adjusted according to requirements and hardware conditions to optimize the performance and efficiency of the storage device 2000.
  • the error detection circuit 260 when the SRAM operating circuit 200 performs a first data read/write operation, the error detection circuit 260 does not perform error detection on the data. Specifically, when the SRAM operating circuit 200 reads data input from the first input/output interface circuit 250 and writes the data to the NVSRAM array 220 via the column selection circuit 210, the error detection circuit 260 does not perform error detection on the data. When the non-volatile storage operating circuit 230 performs a data backup operation and the column selection circuit 210 completes a data recovery operation, the error detection circuit 260 performs error detection, thereby improving the speed of data reading, writing, storage, backup, and recovery.
  • the storage device 2000 may further include a control circuit 280 (not shown in the figure), and the control circuit 280 may be coupled to the SRAM operation circuit 200, the non-volatile storage operation circuit 230, the first input-output interface circuit 250, the column selection circuit 210, the error correction circuit 260 and the second input-output interface circuit 270.
  • the control circuit 280 may be coupled to the SRAM operation circuit 200, the non-volatile storage operation circuit 230, the first input-output interface circuit 250, the column selection circuit 210, the error correction circuit 260 and the second input-output interface circuit 270.
  • the control circuit 280 can be configured to provide corresponding control signals to the SRAM operation circuit 200, the non-volatile storage operation circuit 230, the first input/output interface circuit 250, the column selection circuit 210, the error correction circuit 260 and the second input/output interface circuit 270 according to the selected operating mode.
  • control circuit 280 may generate a corresponding control signal according to the working mode or specific requirements of the storage device 2000 , and provide the generated control signal to the corresponding operating circuit.
  • control circuit 280 can provide a control signal for performing a first data read and write operation to the SRAM operation circuit 200 according to preset conditions, or provide a control signal for performing a second data read and write operation to the second input and output interface circuit 270.
  • control circuit 280 can provide a control signal for performing the data backup operation to the non-volatile storage operation circuit 230, and the non-volatile storage operation circuit 230 performs a data backup operation on the data in the selected SRAM storage subunit 222 according to the received data backup operation control signal.
  • control circuit 270 can provide a control signal for performing the data recovery operation to the column selection circuit 210, and the column selection circuit 210 can perform a data recovery operation on the data in the selected non-volatile storage sub-unit 231 based on the received data recovery operation control signal.
  • control circuit 280 may further provide a control signal for the error correction and detection circuit 260 to perform the error correction and detection operation.
  • control circuit 280 can also monitor the working status or health status of the storage device 2000. For example, if the first input/output interface circuit 250 fails and the storage device 2000 needs to perform a data read/write operation, the control circuit 280 can provide a second data read/write operation control signal to the second input/output interface circuit 270. The control circuit 280 can also take appropriate measures to repair the failed circuit or report error information to improve the reliability and stability of the storage device 2000.
  • control circuit 280 can improve the operating efficiency of the storage device 2000 in different operating modes by connecting or interacting with other circuits and components of the storage device 2000.
  • the control circuit 280 can also adjust the operating status and parameters of each circuit and component as needed to achieve flexible control and management of the storage device 2000.
  • At least one embodiment of the present disclosure provides a method for controlling a storage device.
  • the method includes controlling an error detection circuit to encode and decode target data, determine whether errors occur in the target data, and then correct the errors.
  • the method can be used, for example, in the storage device shown in FIG12 .
  • the error detection and correction circuit receives target data read from the SRAM storage subunits of the NVSRAM array and inputs the target data from the SRAM operation circuit according to the received control instruction, and encodes or decodes the target data.
  • the error detection and correction circuit can also re-input the encoded target data into the SRAM operation circuit to write it into the SRAM storage subunits of the NVSRAM array, or determine whether the decoded target data has an error and correct the error.
  • FIG17 is a schematic flow chart of a method for controlling a storage device provided by at least one embodiment of the present disclosure.
  • a method for controlling a storage device includes steps S810 - S811 .
  • This control method can be used, for example, for the storage device shown in FIG12 .
  • Step S810 determining whether the non-volatile storage operation circuit performs a data backup operation.
  • Step S811 Encode the target data input from the SRAM operation circuit to the error correction circuit.
  • the error correction and detection circuit encodes target data read from an SRAM storage subunit of the NVSRAM array and input from the SRAM operation circuit.
  • the non-volatile storage operation circuit performing the data backup operation and the error correction and detection circuit encoding the target data can be performed simultaneously, or the data backup can be performed first and then the target data is encoded, or the target data can be encoded first and then the encoded target data is backed up, and the embodiments of the present disclosure are not limited to this.
  • FIG18 is a flow chart showing another method for controlling a storage device provided by at least one embodiment of the present disclosure.
  • a method for controlling a storage device includes steps S820 and S821 .
  • This control method can be used, for example, for the storage device shown in FIG12 .
  • Step S820 Determine whether the column selection circuit completes the data recovery operation.
  • Step S821 Determine whether an error occurs in the target data read from the NVSRAM array by the SRAM operation circuit and input to the error correction circuit, and correct the error.
  • the error correction circuit decodes the target data read by the SRAM operation circuit from the SRAM storage subunit of the NVSRAM array and input into the error correction circuit, and determines whether the decoding result is erroneous. If an error occurs, error correction is performed.
  • FIG19 is a flow chart showing another method for controlling a storage device provided by at least one embodiment of the present disclosure.
  • step S811 in the storage device control method shown in FIG. 17 may further include steps S910 - S911 as shown in FIG. 19 .
  • Step S910 When encoding, the K-bit information code of the read target data is encoded to obtain an R-bit check code.
  • step S910 the error correction and detection circuit encodes the K-bit information code data of the received target data to generate R-bit check code data.
  • the error correction and detection circuit encoding method can be referred to the relevant description above and will not be repeated here.
  • the R-bit check code data can be appended to the K-bit information code data to form data including the K-bit information code and the R-bit check code data.
  • Step S911 writing the R-bit check code into the NVSRAM array through the SRAM operation circuit.
  • step S911 for example, the error detection circuit sends a corresponding control signal to the SRAM operation circuit, which then writes data including the R-bit parity check code into the SRAM storage sub-cells of the NVSRAM array via the column selection circuit.
  • the column selection circuit can be used to select a specific column in the NVSRAM array so that data can be written to the designated storage cell. This step reliably stores the data in the SRAM storage sub-cells of the NVSRAM array for subsequent data recovery or data backup operations.
  • FIG20 is a flow chart showing another method for controlling a storage device provided by at least one embodiment of the present disclosure.
  • step S821 in the storage device control method shown in FIG. 18 may further include steps S920 - S922 as shown in FIG. 20 .
  • Step S920 During decoding, the K-bit information code and R-bit check code of the read target data are decoded and error-checked.
  • Step S921 Determine whether an error occurs in the decoding result.
  • Step S922 In response to an error, error correction is performed, and K bits of error-corrected information code are written into the NVSRAM array via the SRAM operation circuit, where K and R are positive integers.
  • step S920 for example, in response to an instruction from the column selection circuit to complete a data recovery operation, the SRAM operation circuit selects data (i.e., target data) stored in a specific column of the SRAM storage subunit of the NVSRAM array through the column selection circuit, and the SRAM operation circuit reads the target data from the NVSRAM array.
  • the read target data is input by the SRAM operation circuit into the error correction circuit for subsequent decoding and error detection operations.
  • the error correction circuit decodes the target data input by the SRAM operation circuit, which includes the K-bit information code and the R-bit check code, read from the SRAM storage subunit of the NVSRAM array.
  • the decoding process can be the inverse of the encoding process, separating the R-bit check code data from the data according to a specific decoding algorithm, and checking the K-bit information code data based on the check code.
  • the error correction circuit then performs step S921 to determine whether an error occurs in the decoding result. If an error occurs, step S922 is initiated to perform error correction, and the K-bit error-corrected information code is written into the SRAM storage subunit of the NVSRAM array through the SRAM operation circuit to replace the erroneous data. If no errors occur, the target data is input to the input/output interface circuit via the SRAM operation circuit for data output.
  • the input/output interface circuit can transmit the target data to a corresponding external device or other circuit within the electronic device for subsequent operation.
  • the methods for encoding, decoding, and correcting errors in the error detection circuit can be found in the relevant description above and will not be repeated here.
  • Figure 21 shows a flow chart of a method for controlling a storage device according to at least one embodiment of the present disclosure. As shown in Figure 21 , the method may include steps S1000 to S1030.
  • Step S1000 determining that the SRAM operation circuit performs a first data read and write operation.
  • Step S1010 disconnecting the nonvolatile storage operation circuit from the NVSRAM array.
  • Step S1020 controlling the column selection circuit to connect the SRAM operation circuit to the NVSRAM array.
  • Step S1030 Control the second input/output interface circuit to disconnect from the NVSRAM array.
  • the SRAM operation circuit When the SRAM operation circuit is determined to perform the first data read/write operation, it is necessary to isolate the operation of the non-volatile storage operation circuit from the operation of the SRAM operation circuit to prevent the two from interfering with each other and thus affecting the reliability of the first data read/write operation. Therefore, it is necessary to disconnect the non-volatile storage operation circuit from the NVSRAM array and control the column selection circuit to connect the SRAM operation circuit to the NVSRAM array to isolate the operations of the non-volatile storage operation circuit from the SRAM operation circuit.
  • the non-volatile storage operation circuit stops the operation of the non-volatile storage operation circuit according to the received instruction from the SRAM operation circuit to perform the first data read and write operation.
  • step S1020 in one example, for example, when the column selection circuit includes a switch array, step S1020 further includes step S1021 (not shown in the figure).
  • Step S1021 Control the column selection circuit to turn on the switch array coupled to the NVSRAM array.
  • the method of isolating the operation of the non-volatile storage operation circuit and the operation of the SRAM operation circuit can be referred to the relevant description above and will not be repeated here.
  • the second input-output interface circuit stops performing the second data read-write operation according to the instruction received from the SRAM operation circuit to perform the first data read-write operation, and controls the second input-output interface circuit to disconnect from the NVSRAM array to avoid affecting the operation of the SRAM operation circuit.
  • the method shown in FIG21 may further include step S1040 (not shown in the figure).
  • Step S1040 controlling the column selection circuit to stop the data recovery operation.
  • the SRAM operation circuit When the SRAM operation circuit is determined to perform the first data read/write operation, it is necessary to isolate the data recovery operation of the column selection circuit from the operation of the SRAM operation circuit to prevent the two from interfering with each other and thus affecting the reliability of data reading and writing. Therefore, it is necessary to control the column selection circuit to stop the data recovery operation to isolate the data recovery operation of the column selection circuit from the first data read/write operation of the SRAM operation circuit.
  • Figure 22 shows a flow chart of a method for controlling a storage device according to at least one embodiment of the present disclosure. As shown in Figure 22 , the method may include steps S1050 - S1080.
  • Step S1050 determining that the second input/output interface circuit performs a second data read/write operation.
  • Step S1060 disconnecting the nonvolatile storage operation circuit from the NVSRAM array.
  • Step S1070 Connecting the second input/output interface circuit to the NVSRAM array.
  • Step S1080 Control the column selection circuit to disconnect the SRAM operation circuit from the NVSRAM array.
  • the second input/output interface circuit When the second input/output interface circuit is determined to perform the second data read/write operation, it is necessary to isolate the operation of the non-volatile storage operation circuit from the operation of the second input/output interface circuit to prevent the two from interfering with each other and thereby affecting the reliability of the second data read/write operation. Therefore, it is necessary to disconnect the non-volatile storage operation circuit from the NVSRAM array and connect the second input/output interface circuit to the NVSRAM array to isolate the operations of the non-volatile storage operation circuit and the second input/output interface circuit.
  • the non-volatile storage operation circuit may stop the operation of the non-volatile storage operation circuit according to the received instruction from the second input/output interface circuit to perform the second data read/write operation.
  • step S1070 in one example, for example, when the second input-output interface circuit includes an isolation sub-circuit, step S1070 further includes step S1071 (not shown in the figure).
  • Step S1071 Control the isolation sub-circuit to connect the second input/output interface circuit to the NVSRAM array.
  • the method for isolating the operation of the nonvolatile storage operation circuit and the operation of the second input/output interface circuit can be referred to the above description and will not be repeated here.
  • the column selection circuit disconnects the coupling between the SRAM operation circuit and the NVSRAM array according to the instruction received from the second input/output interface circuit to perform the second data read/write operation, so as to avoid affecting the second input/output interface circuit performing the second data read/write operation.
  • the method shown in FIG22 may further include step S1090 (not shown in the figure).
  • Step S1090 controlling the column selection circuit to stop the data recovery operation.
  • the second input/output interface circuit When the second input/output interface circuit is determined to perform the second data read/write operation, it is necessary to isolate the data recovery operation of the column selection circuit from the operation of the second input/output interface circuit to prevent the two from interfering with each other and thus affecting the reliability of data reading and writing. Therefore, it is necessary to control the column selection circuit to stop the data recovery operation to isolate the data recovery operation of the column selection circuit from the second data read/write operation of the second input/output interface circuit.
  • Figure 23 shows a flow chart of another method for controlling a storage device according to at least one embodiment of the present disclosure. As shown in Figure 23 , the control method may include steps S1100 - S1130 .
  • Step S1100 determining whether the non-volatile storage operation circuit performs a data backup operation.
  • Step S1110 Connecting the non-volatile storage operation circuit to the NVSRAM array.
  • Step S1120 Control the column selection circuit to disconnect the SRAM operation circuit from the NVSRAM array.
  • Step S1130 controlling the second input/output interface circuit to disconnect from the NVSRAM array.
  • the non-volatile storage operation circuit When the non-volatile storage operation circuit is determined to perform a data backup operation, it is necessary to isolate the operation of the non-volatile storage operation circuit from the operation of the SRAM operation circuit and the operation of the second input/output interface circuit to prevent mutual interference and thus affect the reliability of the data backup operation. Therefore, it is necessary to connect the non-volatile storage operation circuit to the NVSRAM array, control the column selection circuit to disconnect the SRAM operation circuit from the NVSRAM array, and control the second input/output interface circuit to disconnect the NVSRAM array, thereby isolating the non-volatile storage operation circuit from the SRAM operation circuit and the second input/output interface circuit.
  • step S1120 in one example, the column selection circuit stops the operation of the column selection circuit according to the instruction received from the non-volatile storage operation circuit to perform a data backup operation.
  • step S1120 further includes step S1121 (not shown in the figure).
  • Step S1121 Control the column selection circuit to disconnect the switch array coupled to the NVSRAM array.
  • the method of isolating the operation of the nonvolatile storage operation circuit and the operation of the SRAM operation circuit can be referred to the relevant description above and will not be repeated here.
  • step S1130 in one example, the second input/output interface circuit stops operation of the second input/output interface circuit based on the received instruction from the non-volatile storage operation circuit to perform a data backup operation. For another example, if the second input/output interface circuit further includes an isolation subcircuit, step S1130 further includes step S1131 (not shown).
  • Step S1131 Control the isolation sub-circuit to disconnect the second I/O interface circuit from the NVSRAM array.
  • the method for isolating the operation of the nonvolatile storage operation circuit and the operation of the second I/O interface circuit can be referred to the above description and will not be repeated here.
  • the method shown in FIG23 may further include step S1140 (not shown in the figure).
  • Step S1140 controlling the column selection circuit to stop the data recovery operation.
  • step S1140 may also include controlling the data recovery operation sub-circuit to stop performing the data recovery operation.
  • Figure 24 shows a flow chart of another method for controlling a storage device according to at least one embodiment of the present disclosure. As shown in Figure 24 , the control method may include steps S1150 - S1180 .
  • Step S1150 determining that the column selection circuit performs a data recovery operation.
  • Step S1160 disconnecting the nonvolatile storage operation circuit from the NVSRAM array.
  • Step S1170 Control the column selection circuit to disconnect the SRAM operation circuit from the NVSRAM array.
  • Step S1180 controlling the second input/output interface circuit to disconnect from the NVSRAM array.
  • the column select circuit When the column select circuit is determined to perform a data recovery operation, it is necessary to isolate the operations of the nonvolatile storage operation circuit, the SRAM operation circuit, the second input/output interface circuit, and the data recovery operation of the column select circuit to prevent mutual interference and thus affect the reliability of the data recovery operation. Therefore, it is necessary to disconnect the nonvolatile storage operation circuit from the NVSRAM array, control the column select circuit to disconnect the SRAM operation circuit from the NVSRAM array, and control the second input/output interface circuit to disconnect the NVSRAM array, thereby isolating the operations of the nonvolatile storage operation circuit, the SRAM operation circuit, and the second input/output interface circuit from the data recovery operation of the column select circuit.
  • step S1170 further includes step S1171 (not shown).
  • Step S1171 Controlling the column select circuit to disconnect the switch array coupled to the NVSRAM array. The method for isolating the operation of the nonvolatile storage operation circuit and the data recovery operation of the column select circuit can be referred to the relevant description above and will not be repeated here.
  • step S1180 in one example, for example, the second input/output interface circuit stops the operation of the second input/output interface circuit based on the received instruction from the non-volatile storage operation circuit to perform a data backup operation.
  • step S1180 also includes step S1181 (not shown).
  • Step S1181 Control the isolation subcircuit to disconnect the switch coupling the second input/output interface circuit to the NVSRAM array. The method for the data recovery operation of the isolation column selection circuit and the operation of the second input/output interface circuit can be referred to the relevant description above and will not be repeated here.
  • the method for controlling a storage device may further include steps S1190 - S1192 (not shown in the figure).
  • Step S1190 Receive a working mode signal.
  • Step S1191 Generate a control signal for a first data read/write operation, a data backup operation, a data recovery operation, a second data read/write operation, or data error detection according to the working mode signal.
  • Step S1192 providing control signals to the SRAM operation circuit, the nonvolatile memory operation circuit, the first input/output interface circuit, the column selection circuit, the second input/output interface circuit or the error correction circuit accordingly.
  • the control circuit receives an operating mode signal, which can be used to instruct the storage device which operating mode to perform.
  • the operating mode signal can be used to instruct the storage device to perform data read and write operations, data backup operations, or data recovery operations.
  • step S1191 after the control circuit receives the operating mode signal, the control circuit may generate a corresponding control signal based on the received operating mode signal, such as a control signal for a first data read/write operation, a data backup operation, a data recovery operation, a second data read/write operation, or data error detection.
  • the control signal for the first data read/write operation may include controlling an SRAM operating circuit to perform the first data read/write operation;
  • the control signal for the first data read/write operation may also include controlling a non-volatile storage operating circuit to disconnect from an NVSRAM array.
  • control signal for the data backup operation may include controlling the non-volatile storage operation circuit to perform a data backup operation; exemplary, the control signal for the data backup operation may also include controlling the SRAM operation circuit and the second input-output interface circuit to disconnect from the NVSRAM array; exemplary, the control signal for the data recovery operation may also include controlling the error correction circuit to perform a data error correction operation; exemplary, the control signal for the data recovery operation may be used to include controlling the column selection circuit to perform a data recovery operation, controlling the non-volatile storage operation circuit to disconnect from the NVSRAM array, controlling the second input-output interface circuit to disconnect from the NVSRAM array, and controlling the column selection circuit to disconnect the SRAM operation circuit from the NVSRAM array.
  • the control circuit provides the generated control signals to the corresponding operation circuits.
  • the control circuit may provide the control signals for the first data read/write operation or data recovery operation to the SRAM operation circuit;
  • the control circuit may also provide the control signals for the first data read/write operation or data recovery operation to the non-volatile storage operation circuit.
  • the control circuit may provide the control signals for the data backup operation to the non-volatile storage operation circuit;
  • the control circuit may also provide the control signals for the data backup operation to the SRAM operation circuit and the second input/output interface circuit.
  • control circuit may provide the control signals for the second data read/write operation to the second input/output interface circuit; Exemplarily, the control circuit may also provide the control signals for the second data read/write operation to the non-volatile storage operation circuit.
  • control circuit may provide the control signals for the data backup operation to the error correction and detection circuit.
  • control circuit may also provide the control signals for the data recovery operation to the error correction and detection circuit.
  • control circuit may also provide the control signals for the data recovery operation to the column selection circuit.
  • control circuit generates corresponding control signals based on the received working mode signal, and provides each control signal to the corresponding operation circuit, thereby improving the reliability and efficiency of data reading, writing, backup, recovery and other operations.
  • FIG25 shows a flow chart of a storage device data backup method provided by at least one embodiment of the present disclosure.
  • the data backup method includes steps S1200 to S1291 .
  • the data backup method can be used in the storage device shown in Figure 12 or Figure 13 , for example.
  • Step S1200 Read and write data.
  • the SRAM operation circuit may perform the first data read/write operation or the second input/output interface circuit may perform the second data read/write operation.
  • the SRAM operation circuit may write the first input data received from the first input/output interface circuit into the NVSRAM array, or the SRAM operation circuit may provide the first output data read from the NVSRAM array to the first input/output interface circuit, and the first output data may be output from the first input/output interface circuit to a storage device.
  • the second input/output interface circuit may write the second input data received into the NVSRAM array, or the second input/output interface circuit may output the second output data read from the NVSRAM array to a storage device.
  • Step S1210 Determine whether a data backup operation is required.
  • step S1210 in some embodiments of the present disclosure, the storage device determines whether a data backup operation is required based on the received instruction. If a data backup operation is required, the storage device proceeds to step S1220; otherwise, the storage device proceeds to step S1200 to continue writing data to the SRAM storage subunit in the NVSRAM unit.
  • Step S1220 Read the K-bit information code of the i-th row data.
  • step S1220 the SRAM operation circuit reads the i-th row of data of the SRAM storage subunit in the NVSRAM array through the column selection circuit, the data including the K-bit information code, and inputs the data into the error correction circuit.
  • i and K are integers and 0 ⁇ i, N ⁇ K ⁇ 1.
  • Step S1230 Encode the K-bit information code data of the i-th row to obtain an R-bit check code.
  • step S1230 the error correction and detection circuit encodes the K-bit information code of the received i-th row data to obtain an R-bit check code.
  • Step S1240 Write the R-bit check code in the i-th row.
  • step S1240 for example, the error correction circuit writes the R-bit parity code into the i-th row of data in the SRAM storage subunit of the NVSRAM array via the SRAM operation circuit for subsequent data backup operations.
  • steps S1230-S1240 may correspond to steps S910-S911 shown in FIG19 .
  • the method for encoding data by the error correction circuit can be referred to the relevant description above and will not be repeated here. Then, step S1250 is performed.
  • Step S1250 Determine whether encoding is completed.
  • step S1250 it is determined whether all the data to be backed up in the NVSRAM array has been encoded. If not, the process proceeds to step S1291. If so, the process proceeds to step S1260.
  • Step S1291 The row address is increased by 1.
  • step S1291 when the data encoding operation is not completed, the row address of the data to be encoded in the SRAM storage subunit is updated, and the row address is increased by 1 row. Then the data encoding operation of steps S1220-S1250 will continue until all the data to be encoded are encoded and written into the SRAM storage subunit.
  • Step S1260 Select J rows of NVSRAM cells.
  • step S1260 after the error detection circuit completes data encoding, a data backup operation is performed.
  • the word line driver circuit determines the Jth row of data in the NVSRAM cell based on the address information.
  • J is an integer and 0 ⁇ J.
  • NVSRAM cells in rows 1 to J are selected.
  • Step S1270 Back up all data (including data bits and check bits) in the SRAM storage sub-units in the J-row storage unit at the same time.
  • the non-volatile storage operation circuit performs parallel operation to simultaneously perform data backup operation on the data including K-bit information code and R-bit check code in all storage subunits of J rows in the SRAM storage subunit, and backs up the data to the RRAM storage subunit.
  • Step S1280 Determine whether the data backup is completed.
  • step S1280 the nonvolatile storage operation circuit determines whether the data backup is completed. If the backup is not completed, step S1290 is performed; if it is determined that the data backup is completed, the data backup operation is terminated.
  • Step S1290 The row address is increased by J.
  • step S1290 the word line driver circuit updates the row address of the SRAM storage subunit, increasing the row address by J, so as to proceed to the next step of the data backup operation.
  • the non-volatile storage operation circuit backs up the data in rows (J+1) through 2J of the determined SRAM storage subunit to the RRAM storage subunit.
  • the data backup operation of steps S1260-S1280 is then continued until all data to be backed up has been backed up to the RRAM storage subunit.
  • FIG26 shows a flow chart of a storage device data recovery method provided by at least one embodiment of the present disclosure.
  • the data recovery method includes steps S1300 to S1393.
  • the data recovery method can be used in the storage device shown in Figure 12 or Figure 13, for example.
  • Step S1300 Whether data is restored.
  • step S1300 it is determined whether the storage device is to perform a data recovery operation. This can be determined based on actual needs, or upon receipt of a data recovery instruction. If a data recovery operation is determined to be necessary, step S1310 is performed; if a data recovery operation is not determined to be necessary, step S1391 is performed directly.
  • Step S1310 Select I row of NVSRAM cells.
  • step S1310 the word line driving circuit determines I rows of data in the NVSRAM cells according to the address information.
  • I is an integer and 0 ⁇ I.
  • the NVSRAM cells in rows 1 to 1 are selected.
  • Step S1320 Data is restored for all storage cells in row I simultaneously.
  • this step can be performed by, for example, a column selection circuit.
  • the column selection circuit performs a parallel operation to simultaneously restore the data of one row in the determined RRAM storage sub-unit to the SRAM storage sub-unit. Then, step S1330 is performed.
  • Step S1330 Check whether data recovery is completed.
  • step S1330 determine whether the data recovery operation is completed. If it is completed, proceed to step S1340; if it is not completed, proceed to step S1393.
  • Step S1393 The row address is increased by 1.
  • step S1393 if the data recovery operation is not complete, the row address of the data to be recovered in the RRAM storage subunit is increased by 1.
  • the word line driver circuit can determine the data in the (I+1)th row to the 2Ith row in the RRAM storage subunit based on the address information. Then, steps S1310-S1330 are continued until all the data to be recovered is recovered.
  • Step S1340 Read the data of the j-th row including the K-bit information code and the R-bit check code.
  • step S1340 after the data recovery operation is completed, the SRAM operation circuit reads the data in the j-th row of the SRAM storage subunit, including the K-bit information code and the R-bit check code, and inputs the read data into the error correction circuit for subsequent processing and use.
  • j is an integer and 0 ⁇ j.
  • Step S1350 Decode and perform error detection on the read data of the j-th row including the K-bit information code and the R-bit check code.
  • the error correction and detection circuit decodes and performs error detection on the data of the jth row, including the K-bit information code and the R-bit check code, input from the SRAM operation circuit.
  • the decoding process can be the inverse of the encoding process, separating the R-bit check code data from the data according to a specific decoding algorithm, and verifying the K-bit information code data based on the check code.
  • the method for decoding the data by the error correction and detection circuit can be referred to the relevant description above and will not be repeated here.
  • Step S1360 Determine whether there is an error.
  • step S1360 the error detection circuit will judge the decoding result to determine whether there is an error in the data. If the decoding result is erroneous, an error correction operation is required, and step S1370 is performed; if the decoding result is not erroneous, step S1390 is performed.
  • Step S1370 Correct the j-th row of data to obtain a K-bit error-corrected information code.
  • step S1370 if the error detection circuit determines that the decoding result contains an error, error correction encoding is performed on the data.
  • the error detection circuit performs error correction on the data in row j, obtaining a K-bit error-corrected information code.
  • the error correction encoding method performed by the error detection circuit on the data can be found in the relevant description above and will not be repeated here.
  • Step S1380 Write K bits of error-corrected information code into the j-th row.
  • step S1380 the error correction and detection circuit writes the corrected K-bit information code data into the SRAM storage sub-unit of the NVSRAM array through the SRAM operation circuit to replace the original erroneous data.
  • Step S1390 Determine whether error correction is completed.
  • step S1390 determine whether the error correction and detection circuit has completed the error correction and detection operation. If it has been completed, proceed to step S1391; if not, proceed to step S1392.
  • Step S1391 data reading and writing.
  • step S1391 after the error correction circuit completes the error correction operation, for example, the SRAM operation circuit can perform a first data read/write operation through the column selection circuit to read the data in the NVSRAM array after error correction and input the data to the first input/output interface circuit for subsequent processing.
  • the second input/output interface circuit can also perform a second data read/write operation to read the data in the NVSRAM array after error correction and input.
  • Step S1392 The row address is increased by 1.
  • step S1392 if the error correction operation is not complete, the row address of the data to be corrected and detected in the SRAM storage subunit is updated, and the row address is increased by 1.
  • the SRAM operation circuit can then read the data in the j+1th row of the SRAM storage subunit, including the K-bit information code and the R-bit check code, and input the read data into the error correction and detection circuit. Steps S1340-S1390 are then continued until all data to be corrected and detected are corrected.
  • At least one embodiment of the present disclosure further provides an electronic device including the aforementioned storage device, which can improve the reliability of data reading, writing, backup, and storage.
  • Figure 27 shows a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure.
  • the electronic device 3000 includes a storage device, which includes the storage device 1000 or the storage device 2000 provided by any of the aforementioned embodiments.
  • the electronic device 3000 in the embodiment of the present disclosure may include but is not limited to mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., as well as fixed terminals such as digital TVs, desktop computers, etc.
  • mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., as well as fixed terminals such as digital TVs, desktop computers, etc.

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Abstract

一种存储装置、电子设备和存储装置的控制方法。该存储装置中列选电路与NVSRAM阵列耦接，第一输入输出接口电路与SRAM操作电路耦接，SRAM操作电路与列选电路耦接，非易失存储操作电路与NVSRAM阵列耦接；非易失存储操作电路被配置为对SRAM存储子单元数据进行数据备份操作；SRAM操作电路被配置为对SRAM存储子单元数据进行第一数据读写操作；列选电路被配置为对非易失存储子单元数据进行数据恢复操作，隔离SRAM操作电路的操作和非易失存储操作电路的操作，以及隔离第一数据读写操作、第二数据读写操作和数据恢复操作；第二输入输出接口电路与NVSRAM阵列耦接，且被配置为对NVSRAM阵列进行第二数据读写操作。该存储装置可以提高数据读写、备份、恢复的可靠性和灵活性。

Description

存储装置、电子设备和存储装置的控制方法
本申请要求于2024年4月19日递交的中国专利申请第202410476134.4号、第202410479895.5号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种存储装置、电子设备和存储装置的控制方法。
背景技术
随着科学技术和经济的快速发展，存储器的应用范围越来越广。基本的存储器可以按照存储介质的特性分为易失性存储器和非易失性存储器。易失性存储器指断电之后存储的数据将丢失的存储器，相应地非易失性存储器则是指断电之后存储的数据不会丢失的存储器。通常，易失性存储器操作速度快，而非易失性存储器保存时间长。
SRAM(Static Random Access Memory，静态随机存储器)是易失性存储器，当电源断开的时候其内存储的数据会丢失，因此需要一直提供电源以维持SRAM存储器的编程状态，这种方法消耗较多能量，不利于存储装置的低功耗设计。
发明内容
本公开至少一个实施例提供一种存储装置，包括：NVSRAM阵列、SRAM操作电路、非易失存储操作电路、第一输入输出接口电路、列选电路、第二输入输出接口电路，其中，所述列选电路与所述NVSRAM阵列耦接，所述SRAM操作电路与所述列选电路耦接，所述非易失存储操作电路与所述NVSRAM阵列耦接；所述NVSRAM阵列包括阵列排列的多个NVSRAM单元，且每个NVSRAM单元包括SRAM存储子单元和非易失存储子单元，所述非易失存储子单元被配置为对所述SRAM存储子单元存储的数据进行数据备份；所述非易失存储操作电路被配置为对所述NVSRAM阵列中被选择的NVSRAM单元中的SRAM存储子单元数据进行数据备份操作；所述SRAM操作电路被配置为对所述SRAM存储子单元数据进行第一数据读写操作；所述列选电路被配置为，对所述非易失存储子单元数据进行数据恢复操作；所述列选电路还被配置为，在进行所述数据恢复操作或在所述SRAM操作电路进行所述第一数据读写操作的情况下，选择所述NVSRAM阵列中需要被操作的对象单元列；所述第一输入输出接口电路与所述SRAM操作电路耦接，且被配置为将接收的第一输入数据提供给所述SRAM操作电路以及从所述SRAM操作电路接收要输出的第一输出数据；所述列选电路还被配置为隔离所述SRAM操作电路的操作和所述非易失存储操作电路的操作，以及隔离所述第一数据读写操作、所述第二数据读写操作和所述数据恢复操作；所述第二输入输出接口电路与所述NVSRAM阵列耦接，且被配置为对所述NVSRAM阵列进行第二数据读写操作。
本公开至少一个实施例提供一种存储装置的控制方法，用于本公开任一实施例提供的存储装置。该控制方法包括：在确定所述SRAM操作电路进行所述第一数据读写操作的情况下，断开所述非易失存储操作电路与所述NVSRAM阵列的耦接，控制所述列选电路连通所述SRAM操作电路与所述NVSRAM阵列的耦接，控制所述第二输入输出电路断开与所述NVSRAM阵列的耦接；或，在确定所述第二输入输出接口电路进行所述第二数据读写操作的情况下，断开所述非易失存储操作电路与所述NVSRAM阵列的耦接，连通所述第二输入输出接口电路与所述NVSRAM阵列的耦接，控制所述列选电路断开所述SRAM操作电路与所述NVSRAM阵列的耦接；或，在确定所述非易失存储操作电路进行所述数据备份操作的情况下，连通所述非易失存储操作电路与所述NVSRAM阵列的耦接，控制所述列选电路断开所述SRAM操作电路与所述NVSRAM阵列的耦接，控制所述第二输入输出电路断开与所述NVSRAM阵列的耦接；或，在确定所述列选电路进行所述数据恢复操作的情况下，断开所述非易失存储操作电路与所述NVSRAM阵列的耦接，控制所述列选电路断开所述SRAM操作电路与所述NVSRAM阵列的耦接，控制所述第二输入输出接口电路断开与NVSRAM阵列的耦接。
本公开至少一个实施例提供一种存储装置，包括：NVSRAM阵列、SRAM操作电路、非易失存储操作电路、纠检错电路、第一输入输出接口电路、列选电路、第二输入输出接口电路，其中，所述纠检错电路与所述SRAM操作电路耦接，所述SRAM操作电路与所述列选电路耦接，所述列选电路与所述NVSRAM阵列耦接，所述非易失存储操作电路与所述NVSRAM阵列耦接；所述NVSRAM阵列包括阵列排列的多个NVSRAM单元，且每个NVSRAM单元包括SRAM存储子单元和非易失存储子单元，所述非易失存储子单元被配置为对所述SRAM存储子单元存储的数据进行数据备份；所述非易失存储操作电路被配置为对所述NVSRAM阵列中被选择的NVSRAM单元中的SRAM存储子单元数据进行数据备份操作；所述SRAM操作电路被配置为对所述SRAM存储子单元数据进行第一数据读写操作；所述列选电路被配置为，对所述非易失存储子单元数据进行数据恢复操作；所述列选电路还被配置为，在进行所述数据恢复操作或在所述SRAM操作电路进行所述第一数据读写操作的情况下，选择所述NVSRAM阵列中需要被操作的对象单元列；所述第一输入输出接口电路与所述SRAM操作电路耦接，且被配置为将接收的第一输入数据提供给所述SRAM操作电路以及从所述SRAM操作电路接收要输出的第一输出数据；所述纠检错电路被配置为对目标数据进行编码和解码并判断所述目标数据是否发生错误并纠错；所述列选电路还被配置为隔离所述SRAM操作电路的操作和所述非易失存储操作电路的操作，以及隔离所述第一数据读写操作、所述第二数据读写操作和所述数据恢复操作；所述第二输入输出接口电路与所述NVSRAM阵列耦接，且被配置为对所述NVSRAM阵列进行第二数据读写操作。
本公开至少一个实施例提供一种存储装置的控制方法，用于本公开任一实施例提供的存储装置。该控制方法包括：控制所述纠检错电路对所述目标数据进行编码和解码并判断所述目标数据是否发生错误并纠错。
本公开至少一个实施例提供一种电子设备，包括本公开任一实施例提供的存储装置。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1示出了一种易失性存储子单元与非易失性存储子单元的组合示意图；
图2示出了本公开至少一个实施例提供的一种存储装置的示意框图；
图3示出了本公开至少一个实施例提供的另一种存储装置的示意框图；
图4示出了本公开至少一个实施例提供的另一种存储装置的示意框图；
图5示出了本公开至少一个实施例提供的一种存储装置的控制方法的流程示意图；
图6示出了本公开至少一个实施例提供的另一种存储装置的控制方法的流程示意图；
图7示出了本公开至少一个实施例提供的另一种存储装置的控制方法的流程示意图；
图8示出了本公开至少一个实施例提供的另一种存储装置的控制方法的流程示意图；
图9示出了本公开至少一个实施例提供的一种存储装置工作方法的流程示意图；
图10示出了本公开至少一个实施例提供的一种存储装置数据备份方法的流程示意图；
图11示出了本公开至少一个实施例提供的一种存储装置数据恢复方法的流程示意图；
图12示出了本公开至少一个实施例提供的一种存储装置的示意框图；
图13示出了本公开至少一个实施例提供的另一种存储装置的示意框图；
图14示出了本公开至少一个实施例提供的另一种存储装置的示意框图；
图15示出了本公开至少一个实施例提供的另一种存储装置的示意框图；
图16A示出了本公开至少一个实施例提供的另一种存储装置的示意框图；
图16B示出了本公开至少一个实施例提供的另一种存储装置的示意框图；
图17示出了本公开至少一个实施例提供的一种存储装置的控制方法的流程示意图；
图18示出了本公开至少一个实施例提供的另一种存储装置的控制方法的流程示意图；
图19示出了本公开至少一个实施例提供的另一种存储装置的控制方法的流程示意图；
图20示出了本公开至少一个实施例提供的另一种存储装置的控制方法的流程示意图；
图21示出了本公开至少一个实施例提供的另一种存储装置的控制方法的流程示意图；
图22示出了本公开至少一个实施例提供的另一种存储装置的控制方法的流程示意图；
图23示出了本公开至少一个实施例提供的另一种存储装置的控制方法的流程示意图；
图24示出了本公开至少一个实施例提供的另一种存储装置的控制方法的流程示意图；
图25示出了本公开至少一个实施例提供的一种存储装置数据备份的流程示意图；
图26示出了本公开至少一个实施例提供的一种存储装置数据恢复的流程示意图；以及
图27示出了本公开至少一个实施例提供的一种电子设备的示意框图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
静态随机存储装置(SRAM，Static Random Access Memory)包括存储单元阵列、行/列地址译码器、灵敏放大器、控制电路和缓冲/驱动电路等构成；存储单元阵列包括多个SRAM存储子单元、字线和位线等，这些存储子单元排列为多行和多列，通过字线来进行行方向寻址，通过位线来进行列方向寻址。SRAM可以在需要快速数据访问的场合发挥出色，比如高速缓存或CPU缓存等。由于其快速的数据访问速度，SRAM可以被用作一些需要快速访问的数据的存储。
例如，SRAM可以有多种类型，例如6T-SRAM(即六晶体管类型的SRAM)、7T-SRAM(即七晶体管类型的SRAM)、8T-SRAM(即八晶体管类型的SRAM)等多晶体管类型的SRAM，在此不具体赘述。
然而，SRAM在掉电后，其内存储的数据会丢失。SRAM没有自己独立的电源供应，需要从外部获取电力以维持数据的存储。一旦电力中断，存储子单元将无法继续维持电荷状态，从而导致数据丢失。因此，SRAM的运行需要持续供电以维持其数据存储状态。
NVM(Non-Volatile Memory)非易失性存储器是一种能够在断电后仍能保持数据存储的半导体存储器。例如，非易失性存储器可以是RRAM(Resistive Random Access Memory，阻变随机存储器)、PRAM(Phase-Change Random Access Memory，相变随机存储器)、闪存(Flash)等，例如，RRAM以及PRAM可以通过改变阻值的方式来存储数据。例如，阻变随机存储器可以利用薄膜材料在外加电压条件下的电阻处于不同电阻状态——高阻态(HRS)和低阻态(LRS)——来实现数据存储的。由不同的高低阻态的外在表现来表示逻辑“1”和逻辑“0”，从而实现数据存储，且能够在切断电源后长时间保持。阻变随机存储器由高阻态(HRS)转变到低阻态(LRS)的过程可以被称为SET过程，也可以称为置位过程。由低阻态转变到高阻态的过程可以被称为RESET过程，也可以称为复位过程。非易失性存储器操作速度比较慢且需要较大的操作电流或电压。
因此，将NVM与SRAM结合形成NVSRAM(Nonvolatile Static random Access Memory)非易失静态随机存储器，结合了上述两种类型的存储器的优点，可以解决SRAM掉电后数据丢失的问题以及操作速度等问题。
在NVSRAM中，主存储区包括由多行多列构成的NVSRAM单元阵列，每个NVSRAM单元包括SRAM存储子单元以及与SRAM存储子单元对应的NVM存储子单元，可以实现高速的随机访问。在电源断电后，这个区域的数据仍然可以保持长久存储。比如，可以将SRAM存储子单元中的数据在断电前备份到NVM存储子单元中，并在重新上电时将数据从NVM存储子单元恢复到SRAM存储子单元。当写入数据时，数据首先存储在SRAM存储子单元中，并且数据也被备份到NVM存储子单元中，以实现非易失性的保存。在读取操作中，数据直接从SRAM存储子单元中读取。SRAM存储子单元提供了快速的读取速度和低延迟。当断电发生时，SRAM存储子单元中的数据虽然失去电源供应，但是NVM存储子单元中的数据仍然可以保持，这使得在断电期间，NVSRAM能够保持数据的完整性，而不需要外部电源的持续供电。在重新上电后，NVM存储子单元中的数据被恢复到SRAM存储子单元中，以恢复数据状态，这样NVSRAM可以在重新上电后可以提供数据访问，实现了高速访问和非易失性存储的结合。
但是，NVM存储子单元在数据备份和数据恢复的过程中容易受一些因素的影响而导致错误率较高。比如，在SRAM存储子单元进行数据恢复的时候可能会产生较大的峰值电流，可能会导致NVSRAM的稳定性降低，影响数据恢复的成功率，最终可能导致恢复的数据错误率较大；在将数据备份到NVM存储子单元时也可能会出现错误，例如，在数据备份过程中可能发生电荷注入或释放不完全，或者在数据备份过程中NVM存储子单元可能会受到电压波动、电磁干扰等影响，以及在数据备份到NVM存储子单元时可能发生的数据位错误等，都可能导致NVM存储子单元的错误率高。
此外，例如在NVM存储子单元为RRAM存储子单元的情况下，在通过RRAM存储子单元进行数据备份或SRAM存储子单元进行数据恢复过程中，RRAM存储子单元和SRAM存储子单元可能会出现互相影响的情况。比如，由于RRAM存储子单元和SRAM存储子单元的读写机制不同，如果未能正确地协调它们的操作，同时对RRAM存储子单元和SRAM存储子单元进行读写操作，可能会导致读写冲突致互相干扰；或者，如果没有正确地处理RRAM存储子单元和SRAM存储子单元之间的数据同步，则可能会导致数据丢失，影响存储装置的系统稳定性等等。
本公开的发明人注意到，为了解决这些问题，需要在设计存储装置时充分考虑RRAM存储子单元和SRAM存储子单元的特性和操作要求，并采取相应的措施来协调它们的操作。例如，可以通过制定合理的读写策略来避免二者读写冲突；或者，可以通过优化存储装置的设计来降低两种操作之间的互相影响，比如可以通过改进电路设计、优化读写时序、使用不同的电源等来减少资源冲突和干扰。
本公开的发明人还注意到，需要在设计存储装置时充分考虑RRAM存储子单元和SRAM存储子单元的特性和操作要求，并采取相应的措施来协调它们的操作。例如，可以通过制定合理的读写策略来避免二者读写冲突；或者，可以通过优化存储装置的设计来降低两种操作之间的互相影响，比如可以通过改进电路设计、优化读写时序、使用不同的电源等来减少资源冲突和干扰，并且，还可以采用纠检错技术来检测和校正错误的存储数据。
图1示出了一种易失性存储子单元与非易失性存储子单元的组合示意图。
如图1所示，所示出的NVSRAM组合了易失性存储子单元与非易失性存储子单元。图1所示的示例中，易失性存储子单元是6T-SRAM(即六晶体管类型的SRAM)，晶体管P0、晶体管P1、晶体管N0、晶体管N1、晶体管N2、晶体管N3以及用于操作该存储子单元的位线BL、位线BLN、字线WL、电源线CVDD、地线VSS，该SRAM存储子单元内还包括存储节点Q以及存储节点QN。位线BL以及位线BLN用于读写数据，字线WL用于控制读写操作，晶体管P0、晶体管N0构成一个反相器，而晶体管P1、晶体管N1构成另一个反相器，两个反相器交叉连接由此提供存储节点Q以及存储节点QN。该SRAM存储子单元具有双稳态结构。存储节点Q为高电平时，则存储节点QN为低电平，此时可以被选择认为存储的数据为“1”，对应地，存储节点Q为低电平时，则存储节点QN为高电平，此时可以被选择认为存储的数据为“0”；晶体管N2以及晶体管N3受字线WL控制来导通或关闭存储子单元。
图1所示的示例中，非易失性存储子单元可以包括阻变随机存储子单元(RRAM)R、阻变随机存储子单元RN、晶体管N4以及晶体管N5。非易失性存储子单元通过差分的方式连接在易失性存储子单元上，阻变随机存储子单元R通过晶体管N4连接在存储节点Q上，阻变随机存储子单元RN通过晶体管N5连接在存储节点QN上，晶体管N4和晶体管N5的栅极与控制线CWLN连接，通过控制线CWLN控制晶体管N4和N5的开关状态。例如，将阻变随机存储子单元R的电阻小大于阻变随机存储子单元RN的电阻的状态设定为数据“1”，反之则设定为数据“0”。
在其他形式中，易失性存储子单元还可以是其他形式的SRAM子单元；非易失性存储子单元除采用上述差分的连接方式连接在易失性存储子单元上之外，还可以采用单端的连接方式，例如将仅包括阻变随机存储子单元R与晶体管N4。并且，非易失性存储子单元除使用RRAM子单元之外，还可以使用PRAM子单元等。
本公开的一些实施例提供了一种存储装置、包括该存储装置的电子设备和该存储装置控制方法。
该存储装置包括NVSRAM阵列、SRAM操作电路、非易失存储操作电路、列选电路、第一输入输出接口电路、第二输入输出接口电路。列选电路与NVSRAM阵列耦接，SRAM操作电路与列选电路耦接，非易失存储操作电路与NVSRAM阵列耦接。
NVSRAM阵列包括阵列排列的多个NVSRAM单元，且每个NVSRAM单元包括SRAM存储子单元和非易失存储子单元，非易失存储子单元被配置为对SRAM存储子单元存储的数据进行数据备份。
非易失存储操作电路被配置为对NVSRAM阵列中被选择的NVSRAM单元中的SRAM存储子单元数据进行数据备份操作；SRAM操作电路被配置为对SRAM存储子单元数据进行第一数据读写操作；列选电路被配置为对非易失存储子单元数据进行数据恢复操作；列选电路还被配置为在进行数据恢复操作或者在SRAM操作电路进行第一数据读写操作的情况下，选择NVSRAM阵列中需要被操作的对象单元列；列选电路还被配置为隔离SRAM操作电路的操作和非易失存储操作电路的操作，以及隔离第一数据读写操作、第二数据读写操作和数据恢复操作；第一输入输出接口电路与SRAM操作电路耦接，且被配置为将接收的第一输入数据提供给SRAM操作电路以及从SRAM操作电路接收要输出的第一输出数据；第二输入输出接口电路与NVSRAM阵列耦接，且被配置为对NVSRAM阵列进行第二数据读写操作。
该存储装置通过使用非易失存储子单元来备份SRAM存储子单元的数据，使用列选电路隔离SRAM操作电路的操作和非易失存储操作电路的操作，以及隔离第一数据读写操作、第二数据读写操作和数据恢复操作，还通过第一输入输出接口电路或第二输入输出接口电路来传输输入或者输出存储装置的数据，由此可以提高数据读写、备份、恢复的可靠性、灵活性。
图2示出了本公开至少一个实施例提供的一种存储装置的示意框图。
在本公开的一些实施例中，如图2所示，存储装置1000包括NVSRAM阵列120、SRAM操作电路100、非易失存储操作电路130、列选电路110、第一输入输出接口电路150、第二输入输出接口电路160。
SRAM操作电路100与列选电路110耦接，列选电路110与NVSRAM阵列120耦接，非易失存储操作电路130与NVSRAM阵列120耦接，第一输入输出接口电路150与SRAM操作电路100耦接，第二输入输出接口电路160与NVSRAM阵列120耦接。
在本公开中“耦接”用于指代描述对象之间的信号连接，当描述对象之间建立耦接之后可以进行信号传递，而当描述对象之间断开耦接之后则不能进行信号连接，可以通过例如电连接等方式实现耦接。例如，在本公开的实施例中，“耦接”可以包括两个或多个电子元件或电路之间通过某种方式连接在一起，使得在它们之间的信号互相传递。例如，两个存储子单元可以直接相连，通过信号或能量的传递来实现信息的传递，或者两个存储子单元之间通过其他电路元件相连，如通过电阻、电容、开关、光电元件等元件或传输线网络等，以实现信号的传递。
NVSRAM阵列120包括阵列排列的多个NVSRAM单元121，且每个NVSRAM单元121包括SRAM存储子单元122和非易失存储子单元131，非易失存储子单元131被配置为对SRAM存储子单元122存储的数据进行数据备份。多个NVSRAM单元121构成的阵列包括多行和多列。例如，多个NVSRAM单元121可以构成包括M行、N列的存储阵列，其中，M、N为整数且1≤M，1≤N。该NVSRAM单元121例如可以采用如图1所示的形式，但是本公开的实施例不限于该具体形式。
NVSRAM阵列120的NVSRAM单元121结合了SRAM存储子单元和非易失存储子单元的特性，SRAM存储子单元122可以被配置为存储数据，可以快速读取和写入数据。非易失存储子单元131被配置为对SRAM存储子单元122存储的数据进行数据备份，以防止电源关闭或者系统崩溃等情况发生时SRAM存储子单元122中存储的数据丢失。
例如，非易失存储子单元131可以包括RRAM、FeRAM(Ferroelectric Random Access Memory，铁电随机存储)、MRAM(Magnetic Random Access Memory，磁性随机存储)、PCM(Phase Change Memory，相变存储)、EEPROM(Electrically Erasable Programmable Read-Only Memory，带电可擦可编程只读存储)、PRAM、闪存等存储子单元。对应于不同类型的非易失存储子单元131，本公开实施例中的非易失存储操作电路130则进行相应地调整，本公开对此并不限定。例如，当非易失存储子单元131包括RRAM存储子单元的情形，非易失存储操作电路130则可以包括RRAM操作电路。
非易失存储操作电路130被配置为对NVSRAM阵列120中被选择的NVSRAM单元121中的SRAM存储子单元122数据执行数据备份操作。
在一些实施例中，非易失存储操作电路130可以与多个SRAM存储子单元122进行通信，非易失存储操作电路130可以根据实际需要对SRAM存储子单元122数据进行数据备份操作，比如当电子设备检测到某个应用程序出现故障或异常时，非易失存储操作电路130执行备份操作。又例如，非易失存储操作电路130还可以响应于备份指令对SRAM存储子单元122内的数据执行数据备份操作，或者基于预设的时间对SRAM存储子单元122进行定期数据备份操作，也可以对SRAM存储子单元122实时进行数据备份操作。
为提高数据备份的效率，非易失存储操作电路130可以采用并行处理方法同时对多个被选择的SRAM存储子单元122数据进行数据备份操作。比如，非易失存储操作电路130可以对某一行SRAM存储子单元122中的数据同时进行数据备份操作，或者非易失存储操作电路130可以对多行SRAM存储子单元122数据同时进行数据备份操作。
在本公开的一些实施例中，第一输入输出接口电路150被配置为将接收的第一输入数据提供给SRAM操作电路100以及从SRAM操作电路100接收要输出的第一输出数据。SRAM操作电路100被配置为对SRAM存储子单元122进行第一数据读写操作。列选电路110被配置为对非易失存储子单元数据进行数据恢复操作。第二输入输出接口电路160被配置为对NVSRAM阵列120进行第二数据读写操作。
这里，“第一数据读写操作”是指SRAM操作电路100对SRAM存储子单元122进行数据读写操作。“第二数据读写操作”是指第二输入输出接口电路160对SRAM存储子单元122进行数据读写操作。例如，第一输入输出接口电路150可以被配置为接收输入存储装置1000的第一输入数据，并将该第一输入数据提供给SRAM操作电路100。并在SRAM操作电路100需要进行数据输出的时候，第一输入输出接口电路150可以被配置为从SRAM操作电路100接收要输出的第一输出数据。
例如，存储装置1000可以通过接收的控制指令、输入存储装置1000的数据位宽或数据类型、存储装置1000中各电路的工作情况等，来确定输入存储装置1000的数据从第一输入输出接口电路150输入存储装置1000，或者从第二输入输出接口电路160输入存储装置1000。示例性的，在列选电路110进行数据恢复操作的情况下，可以将输入存储装置1000的数据从第二数据输入输出接口电路160输入。示例性的，在第二输入输出接口电路160进行第二数据读写操作的情况下，可以将输入存储装置1000的数据从第二输入输出接口电路160输入。示例性的，可以预设第一输入输出接口电路150和第二输入输出接口电路160对于输入或输出数据的位宽，例如可以预设输入或输出第一输入输出接口电路150的数据位宽大于第二输入输出接口电路160的；例如，预设输入或输出第一输入输出接口电路150的数据位宽为32bit，输入或输出第二输入输出接口电路160的数据位宽为512bit，则当输入存储装置1000的数据位宽为32bit的情况下，则该数据可以从第一输入输出接口电路150输入，本公开的实施例对此并不限定。
例如，可以通过接收的读写指令、数据位宽或数据类型、存储装置1000中各电路的工作情况等，来确定由SRAM操作电路100对选定的SRAM存储子单元122进行第一数据读写操作，或者由第二输入输出接口电路150对选定的SRAM存储子单元122进行第二数据读写操作。
在一些实施例中，列选电路110被配置为在进行数据恢复操作，或者在SRAM操作电路100进行第一数据读写操作的情况下，选择NVSRAM阵列120中需要被操作的对象单元列。例如，在SRAM操作电路100进行第一数据读写操作或在列选电路110进行数据恢复操作的情况下，列选电路110响应于接收的地址信号，并将其转化为电信号，从而选择NVSRAM阵列120中相应的对象单元列；例如，列选电路110可以根据SRAM操作电路100需要执行第一数据读写操作或者列选电路110需要执行数据恢复操作的指令，选择NVSRAM阵列120中相应的对象单元列。
这里，“对象单元列”用于指代作为被操作对象的存储单元列，其可以是多个存储阵列中的任一列。“地址信号”包括行选择信号和列选择信号，字线驱动电路(下面将描述)使用行选择信号进行行寻址，列选电路使用列选择信号进行列寻址。
如前述内容，在非易失存储操作电路130进行数据备份操作的过程中，或者在SRAM操作电路100进行第一数据读写操作，或者在列选电路110进行数据恢复操作，或者在第二输入输出接口电路160进行第二数据读写操作的过程中，非易失存储操作电路130的操作、SRAM操作电路100、第二输入输出接口电路160的操作以及列选电路110的数据恢复操作之间可能会互相影响，进而影响数据备份和数据恢复的稳定性。
在本公开的至少一些实施例中，列选电路110还可以被配置为隔离SRAM操作电路100的操作和非易失存储操作电路130的操作。例如，第二输入输出接口电路160还可以被配置为隔离第二输入输出接口电路160的操作和非易失存储操作电路130的操作。
例如，可以对非易失存储操作电路130和SRAM操作电路100分别设置独立的列选电路110，以减小二者之间的影响干扰，独立的列选电路110可以具有不同的电路结构和元件，以适应非易失存储操作电路130和SRAM操作电路100的特性以及操作需求。
例如，列选电路110还可以在SRAM操作电路100进行第一数据读写操作、第二输入输出接口电路170进行第二数据读写操作或非易失存储操作电路130进行数据备份操作的情况下，不执行数据恢复操作，以对第一数据读写操作、第二数据读写操作、数据备份操作和数据恢复操作进行操作隔离。
在一些实施例中，还可以对非易失存储操作电路130、SRAM操作电路100或第二输入输出接口电路160进行电源隔离，比如可以为非易失存储操作电路130、SRAM操作电路100或第二输入输出接口电路160分别提供独立的电源或供电线路。例如，还可以通过在非易失存储操作电路130、SRAM操作电路100或第二输入输出接口电路160中增加稳压器，来提高电路的供电稳定。例如，还可以利用光耦合器通过光信号来传输非易失存储操作电路130、SRAM操作电路100或第二输入输出接口电路160的数据。例如，还可以通过逻辑设计来控制非易失存储操作电路130的操作、SRAM操作电路100的操作或第二输入输出接口电路160的操作，如在特定的情形下，可以只允许对非易失存储操作电路130的操作，或只允许对SRAM操作电路100的操作，或只允许第二输入输出接口电路160的操作，禁止非易失存储操作电路130与SRAM操作电路100或第二输入输出接口电路160同时进行操作。
图3示出了本公开至少一个实施例提供的另一种存储装置的示意框图。
如图3所示，在本公开的一些实施例中，第二输入输出接口电路160包括移位寄存操作电路161、输入接口电路162和输出接口电路163。移位寄存操作电路161与NVSRAM阵列120耦接，且被配置为对NVSRAM阵列120进行第二数据读写操作；输入接口电路162与移位寄存操作电路161耦接，且被配置为接收第二输入数据且将接收的第二输入数据提供给移位寄存操作电路161；输出接口电路163与移位寄存操作电路161耦接，且被配置为从移位寄存操作电路161接收要输出的第二输出数据。
这里，“第二输入数据”是指通过第二输入输出接口电路160中的输入接口电路162输入存储装置1000的数据。“第二输出数据”是指通过第二输入输出接口电路160中的输出接口电路163输出存储装置1000的数据，本公开的实施例对数据的内容及形式等并不限制。
例如，移位寄存操作电路161可以将接收的第二输入数据输入NVSRAM阵列120的SRAM存储子单元122中，或者，移位寄存操作电路161可以从NVSRAM阵列120的SRAM存储子单元122中读取第二输出数据，并将该数据通过输出接口电路163输出存储装置1000。
例如，移位寄存操作电路161可以对接收的第二输入数据进行暂存，之后再将该第二输入数据输入NVSRAM阵列120中的SRAM存储子单元122。
例如，移位寄存操作电路161还可以对接收的第二输入数据进行转换。示例性的，移位寄存操作电路161可以将串行接收的第二输入数据转换为并行地输入NVSRAM阵列120中的SRAM存储子单元122。
在本公开的一些实施例中，如图2或图3所示，NVSRAM阵列120还可以被配置为与字线驱动电路140耦接。字线驱动电路140被配置为在SRAM操作电路100进行第一数据读写操作的情况下，或者在第二输入输出接口电路160进行第二数据读写操作的情况下，或者在列选电路进行数据恢复操作的情况下，或者在非易失存储操作电路进行数据备份操作的情况下，选择NVSRAM阵列120中需要被操作的对象单元行。
这里，“对象单元行”用于指代作为被操作对象的存储单元行，其可以是多个存储阵列中的任一行。
用于NVSRAM阵列120的字线驱动电路140(Word Line Driver)被配置为控制NVSRAM阵列120中存储单元所在行(字线)的电路。在NVSRAM阵列120中，例如，每个存储单元都位于信号线的交叉点处，即横向的信号线为字线(Word Line)，纵向的信号线为位线(Bit Line)。例如，字线驱动电路140负责控制与字线相连的开关，以决定哪一行中的存储单元被选中用于进行所需的操作(对应地，列选电路110则负责通过位线决定哪一列的存储单元被选中用于进行所需的操作)。
例如，在一些实施例中，字线驱动电路140可以包括解码器和选择器。解码器用于接收地址信号，并将其解码为对应字线的行地址。选择器则负责根据行地址选择相应的字线以施加驱动信号。在数据读取或写入被选择的存储单元时，字线驱动电路140可以确保对被选择的存储单元的正确访问，同时避免对其他未被选中的存储单元产生干扰或误操作。
例如，在一些实施例中，在第二输入输出接口电路160进行第二数据读写操作的情况下，字线驱动电路140可以被配置为选择NVSRAM阵列120中哪一行的存储单元被选中用于进行第二数据读写操作。在进行数据读取操作的时候，第二输入输出接口电路160可以读取该被选中的行数据；在进行数据写入操作的时候，第二输入输出接口电路160可以将数据写入该被选中的存储单元行。
例如，在一些实施例中，在第二输入输出接口电路160进行第二数据读写操作的情况下，可以根据列选电路确定哪一列的存储单元被选中用于进行第二数据读写操作，也可以对NVSRAM阵列120中存储单元的全部列进行第二数据读写操作，本公开的实施例对此并不限定。
例如，在一些实施例中，在SRAM操作电路100进行第一数据读写操作的情况下，字线驱动电路140可以被配置为选择NVSRAM阵列120中哪一行的存储单元被选中用于进行第一数据读写操作。示例性的，在SRAM操作电路100进行第一数据读写操作的情况下，在进行数据读取操作的时候，SRAM操作电路100可以读取该被选中的行数据；在进行数据写入操作的时候，SRAM操作电路100可以将数据写入该被选中的存储单元行。
例如，在一些实施例中，在非易失存储操作电路130进行数据备份操作的情况下，字线驱动电路140可以被配置为选择NVSRAM阵列120中哪一行的存储单元被选中用于进行数据备份操作。示例性的，在进行数据备份操作的时候，非易失存储操作电路130可以读取SRAM存储子单元122中该被选中的行数据，并将SRAM存储子单元122中的该被选择的行的数据备份至非易失存储子单元131中。
例如，在一些实施例中，在列选电路110进行数据恢复操作的情况下，字线驱动电路140可以被配置为选择NVSRAM阵列120中哪一行的存储单元被选中用于进行数据恢复操作。示例性的，在进行数据恢复操作的时候，列选电路110可以将非易失存储子单元131中的该被选择的行的数据恢复至SRAM存储子单元122中。
图4示出了本公开至少一个实施例提供的另一种存储装置的示意框图。
如图4所示，在本公开的一些实施例中，第二输入输出接口电路160还可以包括隔离子电路164。隔离子电路164耦接在NVSRAM阵列120和移位寄存操作电路161之间。隔离子电路164可以被配置为在移位寄存操作电路161进行第二数据读写操作的情况下，导通移位寄存操作电路161与NVSRAM阵列120耦接的开关。或者，隔离子电路164还可以被配置为在非易失存储操作电路130进行数据备份操作的情况下，断开移位寄存操作电路161与NVSRAM阵列120耦接的开关。
例如，在本公开的至少一些实施例中，在移位寄存操作电路161进行第二数据读写操作的情况下，隔离子电路164可以将移位寄存操作电路161和NVSRAM阵列120耦接起来，则移位寄存操作电路161可以对NVSRAM阵列120中的SRAM存储子单元122进行第二数据读写操作，以实现快速的数据读写传输。同时，由于非易失存储操作电路130与NVSRAM阵列120的连接断开，因此不会对移位寄存操作电路161的读写操作产生影响。
在非易失存储操作电路130需要进行数据备份操作的情况下，隔离子电路164可以将移位寄存操作电路161和NVSRAM阵列120的耦接断开，而非易失存储操作电路130与NVSRAM阵列120耦接，非易失存储操作电路130可以进行数据备份操作，移位寄存操作电路161不会对非易失存储操作电路130的数据备份操作产生影响。
在本公开的一些实施例中，在SRAM操作电路100进行第一数据读写操作的情况下，列选电路110还可以被配置为连通SRAM操作电路100和NVSRAM阵列120的耦接，非易失存储操作电路130可以被配置为断开与NVSRAM阵列120的耦接，第二输入输出接口电路160可以被配置为断开与NVSRAM阵列120的耦接。
在本公开的一些实施例中，在非易失存储操作电路130进行数据备份的情况下，列选电路110还可以被配置为断开SRAM操作电路100和NVSRAM阵列120的耦接，非易失存储操作电路130还可以被配置为连通与NVSRAM阵列120的耦接，第二输入输出接口电路160可以被配置为断开与NVSRAM阵列120的耦接。
在本公开的一些实施例中，在列选电路110进行数据恢复操作的情况下，列选电路还可以被配置为断开SRAM操作电路100和NVSRAM阵列120的耦接，非易失存储操作电路130可以被配置为断开与NVSRAM阵列120的耦接，第二输入输出接口电路160可以被配置为断开与NVSRAM阵列120的耦接。
在本公开的一些实施例中，在第二输入输出接口电路160进行第二数据读写操作的情况下，列选电路110还可以被配置为断开SRAM操作电路100和NVSRAM阵列120的耦接，非易失存储操作电路130还可以被配置为断开与NVSRAM阵列120的耦接。
例如，在本公开的至少一些实施例中，在SRAM操作电路100需要进行第一数据读写操作的情况下，列选电路110将SRAM操作电路100和NVSRAM阵列120耦接起来，则SRAM操作电路100可以对NVSRAM阵列120中的SRAM存储子单元122进行读写操作，以实现快速的数据读写传输。同时，由于非易失存储操作电路130与NVSRAM阵列120的耦接断开，第二输入输出接口电路160与NVSRAM阵列120的耦接断开，因此不会对SRAM操作电路100的读写操作产生影响。
例如，在非易失存储操作电路130需要进行数据备份的情况下，第二输入输出接口电路160与NVSRAM阵列120的耦接断开，列选电路110将SRAM操作电路100和NVSRAM阵列120的耦接断开，而非易失存储操作电路130与NVSRAM阵列120耦接，非易失存储操作电路130可以进行备份操作，SRAM操作电路100不会对数据备份过程产生影响。
例如，在列选电路110需要进行数据恢复操作的情况下，第二输入输出接口电路160与NVSRAM阵列120的耦接断开，列选电路110将SRAM操作电路100和NVSRAM阵列120的耦接断开，并且非易失存储操作电路130也与NVSRAM阵列120的耦接断开，因此，SRAM操作电路100、非易失存储操作电路130以及第二输入输出接口电路160不会对列选电路110的数据恢复操作过程产生影响。
例如，在第二输入输出接口电路160需要进行第二数据读写操作的情况下，非易失存储操作电路130与NVSRAM阵列120的耦接断开，列选电路110将SRAM操作电路100和NVSRAM阵列120的耦接断开，因此SRAM操作电路100、非易失存储操作电路130的操作不会对第二输入输出接口电路160的第二数据读写操作过程产生影响。
在本公开的一些实施例中，如图4所示，列选电路110还包括数据恢复操作子电路111。
例如，在一些实施例中，数据恢复操作子电路111可以被配置为对对象单元列中的非易失存储子单元131数据进行数据恢复操作。例如，数据恢复操作子电路111可以在接收到进行数据恢复操作指令的情况下，将被选择的非易失存储子单元131中存储的数据恢复至SRAM存储子单元122中。例如，在进行数据恢复操作时，数据恢复操作子电路要确保与SRAM操作电路100、第二输入输出接口电路160和非易失存储操作电路130的操作相隔离，以防止第一数据读写操作、第二数据读写操作、数据备份操作和数据恢复操作之间的冲突，提高了数据的完整性和系统的稳定性。
例如，在一些实施例中，列选电路110或隔离子电路164还可以包括开关阵列(图中未示出)。例如，列选电路110可以通过开关阵列来控制SRAM操作电路100与NVSRAM阵列120的耦接。例如，移位寄存操作电路161可以通过隔离子电路164的开关阵列与NVSRAM阵列120耦接。
例如，在SRAM操作电路100进行第一数据读写操作的情况下，列选电路110可以被配置为导通列选电路110与NVSRAM阵列120之间的耦接的开关阵列。例如，在非易失存储操作电路130进行数据备份操作的情况下，列选电路110还可以被配置为断开列选电路110与NVSRAM阵列120之间的耦接的开关阵列。
例如，列选电路110或隔离子电路164的开关阵列还可以根据控制非易失存储操作电路130的操作、SRAM操作电路100的操作或移位寄存操作电路161的操作的时序逻辑来进行导通或关断。例如在特定的时序下，在只允许SRAM操作电路100进行操作时，列选电路110的开关阵列导通。例如，在特定的时序下，在只允许非易失存储操作电路130进行操作时，列选电路110的开关阵列断开。
如上所述，如图3所示，在本公开的一些实施例中NVSRAM阵列120的阵列宽度可以被配置为N，即具有N列存储单元(或位线的数量为2N)，例如，在NVSRAM阵列120中每行可以包括N个NVSRAM单元。NVSRAM阵列120的阵列还可以被配置为具有M行存储单元，例如，在NVSRAM阵列120中每列可以包括M个NVSRAM单元。每个存储单元有一个对应的地址，用于定位和访问该存储单元。NVSRAM阵列120的阵列还可以被配置为具有M行存储单元。示例性的，NVSRAM阵列120中每行包括N个存储单元，每个存储单元配置有X条位线(X大于等于1)，则NVSRAM存储阵列位线数为X*N，在传输线为位线对的情况下，X可以被配置为2，则NVSRAM存储阵列的位线数可以被配置为2N。在一些实施例中，例如，NVSRAM阵列120可以以字(Word)为单位进行配置。非易失存储操作电路130可以被配置为通过N组传输线与NVSRAM阵列120耦接。例如，在至少一个示例中，在传输线为位线或位线对(例如如图1所示的位线BL和BLN)的情况下，非易失存储操作电路130还可以被配置为通过N条或2N条位线与NVSRAM阵列120耦接。
在本公开的一些实施例中，如图3所示，SRAM操作电路100可以被配置为通过W1组传输线与列选电路110耦接。SRAM操作电路100还可以被配置为通过W1组传输线与第一输入输出接口电路150耦接。非易失存储操作电路130通过N组传输线与NVSRAM阵列120耦接。列选电路110通过N组传输线与NVSRAM阵列120耦接。例如，在传输线为位线或位线对(例如如图1所示的位线BL和BLN)的情况下，列选电路110还可以被配置为通过N条或2N条位线与NVSRAM阵列120耦接。W1和N为整数且N≥W1>1。在一些实施例中，例如在列选电路110进行数据恢复操作的情况下，列选电路110还可以被配置为将2N条位线的电压设置为相同电压值。
SRAM操作电路100通过W1组传输线与列选电路110连接，用于根据列选电路110提供的地址定位和访问NVSRAM阵列120中的特定存储单元，将数据写入NVSRAM阵列120中，以及从NVSRAM阵列120中读取数据。
在本公开的一些实施例中，移位寄存操作电路161可以通过N组传输线与NVSRAM阵列120耦接，输入接口电路162可以通过W2组传输线与移位寄存操作电路161耦接，输出接口电路163可以通过W2组传输线与移位寄存操作电路161耦接，其中，W2和N为整数且N≥W2>1。
在传输线为位线的情况下，移位寄存操作电路161通过N组传输线与NVSRAM阵列120连接，在传输线为位线对(例如如图1所示的位线BL和BLN)的情况下，移位寄存操作电路161还可以通过2N条位线与NVSRAM阵列120连接。
在本公开的一些实施例中，W1和W2可以用于表示传输数据中每个字的操作位宽。例如，在W1和W2相同的情况下，则存储装置1000可以选择任意的第一输入输出接口电路150或者输入接口电路162来接收输入存储装置1000的数据，或者选择任意的第一输入输出接口电路150或者输出接口电路163来输出数据。例如，在W1大于W2相同的情况下，则可以根据输入存储装置1000的数据位宽来确定数据的输入接口；示例性的，W1可以为512bit，W2可以为32bit，则当存储装置1000输入或输出的数据为512bit的情况下，则选择第一输入输出接口电路150来接收或者输出数据。
在本公开的一些实施例中，在非易失存储操作电路130进行数据备份操作的情况下，字线驱动电路140还可以被配置为选择NVSRAM阵列120的I行NVSRAM单元121中的SRAM存储子单元122数据以进行数据备份操作，其中，I为整数且M≥I≥1。
例如，字线驱动电路140可以根据接收的数据备份操作指令，选择NVSRAM阵列120中的I行NVSRAM单元121中的SRAM存储子单元122。示例性的，字线驱动电路140可以选择第1行至第I行的NVSRAM单元121中的SRAM存储子单元122，非易失存储操作电路130可以被配置为对被字线驱动电路140选择的第1行至第I行的NVSRAM单元121中的SRAM存储子单元122数据进行并行数据备份操作，将被选择的I行SRAM存储子单元122数据全部备份至非易失存储子单元131中。
在本公开的一些实施例中，在列选电路110进行数据恢复操作的情况下，字线驱动电路140还可以被配置为选择NVSRM阵列120的J行NVSRAM单元121中的非易失存储子单元131数据以进行数据恢复操作，其中，J为整数且M≥J≥1。
例如，字线驱动电路140可以根据接收的数据恢复操作指令，选择NVSRAM阵列120中的J行NVSRAM单元121中的非易失存储子单元131。示例性的，字线驱动电路140可以选择第1行至第J行的NVSRAM单元121中的非易失存储子单元131，列选电路110可以被配置为对被字线驱动电路140选择的第1行至第J行的NVSRAM单元121中的非易失存储子单元131数据进行并行数据恢复操作，将被选择的J行非易失存储子单元131数据全部恢复至SRAM存储子单元122中。
在本公开的一些实施例中，SRAM操作电路100还被配置为在进行第一数据读写操作的情况下，对被选择的NVSRAM阵列120的第i行的W1个NVSRAM单元121中的SRAM存储子单元122的数据进行第一数据读写操作。其中，N≥W1≥1，M≥i≥1。
例如，SRAM操作电路100的第一数据读写操作的操作位宽为W1。示例性的，SRAM操作电路100可以根据接收的第一数据读写操作指令，对被选择的NVSRAM阵列120的某一行(第i行)中的W1个NVSRAM单元121中的SRAM存储子单元122的数据进行第一数据读写操作。
在本公开的一些实施例中，第二输入输出接口电路170还被配置为在进行第二数据读写操作的情况下，对被选择的NVSRAM阵列120的第i行的W2个NVSRAM单元121中的SRAM存储子单元122的数据进行第二数据读写操作。其中，N≥W2≥1，M≥i≥1。
例如，第二输入输出接口电路170的第二数据读写操作的操作位宽为W2。示例性的，SRAM操作电路100可以根据接收的第二数据读写操作指令，对被选择的NVSRAM阵列120的某一行(第i行)中的W2个NVSRAM单元121中的SRAM存储子单元122的数据进行第二数据读写操作。
在本公开的一些实施例中，非易失存储操作电路130还被配置为在进行数据备份操作的情况下，对被选择的NVSRAM阵列120的E行和/或F列的NVSRAM单元121中的SRAM存储子单元122的数据进行数据备份操作。其中，E、F为整数且M≥E≥1，N≥F≥1。
例如，非易失存储操作电路130的数据备份操作的操作位宽为N*M。
例如，非易失存储操作电路130可以根据接收的数据备份操作指令，对NVSRAM阵列120中包括M行N列的NVSRAM单元121中的被选择的E行或者F列的NVSRAM单元121中的SRAM存储子单元122的数据进行数据备份操作。或者，非易失存储操作电路130可以对NVSRAM阵列120中包括M行N列的NVSRAM单元121中的被选择的E行NVSRAM单元121中的F列的SRAM存储子单元122的全部数据进行数据备份操作。
在本公开的一些实施例中，列选电路110还被配置为在进行数据恢复操作的情况下，对被选择的NVSRAM阵列120的G行和/或H列的NVSRAM单元121中的非易失存储子单元131的数据进行数据恢复操作。其中，G、H为整数且M≥G≥1，N≥H≥1。
例如，列选电路110的数据恢复操作的操作位宽为N*M。
例如，列选电路110可以根据接收的数据恢复操作指令，对NVSRAM阵列120中包括M行N列的NVSRAM单元121中的被选择的G行或者H列的NVSRAM单元121中的非易失存储子单元131的数据进行数据恢复操作。或者，非易失存储操作电路130可以对NVSRAM阵列120中包括M行N列的NVSRAM单元121中的被选择的G行NVSRAM单元121中的H列的非易失存储子单元131的全部数据进行数据恢复操作。
本公开至少一实施例的存储装置1000中，可以根据需求和硬件条件，灵活地调整这些传输线的数量及类型等参数，以优化存储装置1000的性能和效率。
在本公开的一些实施例中，存储装置1000还可以包括控制电路170(图中未示出)，控制电路170可以与SRAM操作电路100、非易失存储操作电路130、第一输入输出接口电路150、列选电路110和第二输入输出接口电路160耦接。
控制电路170可以被配置为根据选择的工作模式向SRAM操作电路100、非易失存储操作电路130、第一输入输出接口电路150、列选电路110和第二输入输出接口电路160提供对应的控制信号。
例如，在存储装置1000中控制电路170可以根据存储装置1000的工作模式或者具体需求，生成相应的控制信号，并将生成的控制信号提供给对应的操作电路。
例如，在存储装置1000需要进行数据读取或数据写入的情况下，控制电路170可以根据预设的条件向SRAM操作电路100提供进行第一数据读写操作的控制信号，或者向第二输入输出接口电路160提供进行第二数据读写操作的控制信号。
例如，在存储装置1000需要进行数据备份操作的情况下，控制电路170可以向非易失存储操作电路130提供进行数据备份操作的控制信号，非易失存储操作电路130根据接收的数据备份操作控制信号，对被选择的SRAM存储子单元122中的数据执行数据备份操作。
例如，在存储装置1000需要进行数据恢复操作的情况下，控制电路170可以向列选电路110提供进行数据恢复操作的控制信号，列选电路110可以根据接收的数据恢复操作控制信号，对被选择的非易失存储子单元131中的数据执行数据恢复操作。
例如，控制电路170还可以监控存储装置1000的工作状态或健康状态，如在第一输入输出接口电路150发生故障的情况下，在存储装置1000需要进行数据读写操作时，控制电路170可以向第二输入输出接口电路160提供第二数据读写操作控制信号。控制电路170还可以采取适当的措施对发生故障的电路进行修复或报告错误信息，以提高存储装置1000的可靠性和稳定性。
在本公开的至少一实施例中，控制电路170通过与存储装置1000的其他电路、组件的连接或交互，可以提高存储装置1000在不同工作模式下的运行效率。控制电路170还可以根据需要调整各个电路、组件的工作状态和参数，以实现对存储装置1000的灵活控制和管理。
图5示出了本公开至少一个实施例提供的一种存储装置的控制方法的流程示意图。如图5所示，该方法可以包括步骤S310-S313。
步骤S310：确定SRAM操作电路进行第一数据读写操作。
步骤S311：断开非易失存储操作电路与NVSRAM阵列的耦接。
步骤S312：控制列选电路连通SRAM操作电路与NVSRAM阵列的耦接。
步骤S313：控制第二输入输出接口电路断开与NVSRAM阵列的耦接。
在确定SRAM操作电路进行第一数据读写操作的情况下，需要隔离非易失存储操作电路的操作和SRAM操作电路的操作，以免二者互相影响进而影响第一数据读写操作的可靠性。因此需要断开非易失存储操作电路与NVSRAM阵列的耦接，并控制列选电路连通SRAM操作电路与NVSRAM阵列的耦接，以对非易失存储操作电路和SRAM操作电路进行操作隔离。
对于步骤S311，在一个示例中，例如，非易失存储操作电路根据接收的SRAM操作电路进行第一数据读写操作的指令，停止非易失存储操作电路的操作。
对于步骤S312，在一个示例中，例如，在列选电路包括开关阵列的情况下，步骤S312还包括步骤S3121(图中未示出)。
步骤S3121：控制列选电路导通与NVSRAM阵列耦接的开关阵列。隔离非易失存储操作电路的操作和SRAM操作电路的操作的方法可以参考上文的相关描述，此处不再赘述。
对于步骤S313，在一个示例中，例如，第二输入输出接口电路根据接收的SRAM操作电路进行第一数据读写操作的指令，停止进行第二数据读写操作，并控制第二输入输出接口电路断开与NVSRAM阵列的耦接，以避免影响SRAM操作电路的操作。
在一些实施例中，图5所示的方法还可以包括步骤S314(图中未示出)。步骤S314：控制列选电路停止数据恢复操作。
在确定SRAM操作电路进行第一数据读写操作的情况下，需要隔离列选电路的数据恢复操作和SRAM操作电路的操作，以免二者互相影响进而影响数据读写的可靠性。因此需要控制列选电路停止数据恢复操作，以对列选电路的数据恢复操作和SRAM操作电路的第一数据读写操作进行操作隔离。
图6示出了本公开至少一个实施例提供的一种存储装置的控制方法的流程示意图。如图6所示，该方法可以包括步骤S320-S323。
步骤S320：确定第二输入输出接口电路进行第二数据读写操作。
步骤S321：断开非易失存储操作电路与NVSRAM阵列的耦接。
步骤S322：连通第二输入输出接口电路与NVSRAM阵列的耦接。
步骤S323：控制列选电路断开SRAM操作电路与NVSRAM阵列的耦接。
在确定第二输入输出接口电路进行第二数据读写操作的情况下，需要隔离非易失存储操作电路的操作和第二输入输出接口电路的操作，以免二者互相影响进而影响第二数据读写操作的可靠性。因此需要断开非易失存储操作电路与NVSRAM阵列的耦接，并连通第二输入输出接口电路与NVSRAM阵列的耦接，以对非易失存储操作电路和第二输入输出接口电路进行操作隔离。
对于步骤S321，在一个示例中，例如，非易失存储操作电路可以根据接收的第二输入输出接口电路进行第二数据读写操作的指令，停止非易失存储操作电路的操作。
对于步骤S322，在一个示例中，例如，在第二输入输出接口电路包括隔离子电路的情况下，步骤S322还包括步骤S3221(图中未示出)。
步骤S3221：控制隔离子电路导通第二输入输出接口电路与NVSRAM阵列的耦接。隔离非易失存储操作电路的操作和第二输入输出接口电路的操作的方法可以参考上文的相关描述，此处不再赘述。
对于步骤S323，在一个示例中，例如，列选电路根据接收的第二输入输出接口电路进行第二数据读写操作的指令，断开SRAM操作电路与NVSRAM阵列的耦接，以避免影响第二输入输出接口电路进行第二数据读写操作。
在一些实施例中，图6所示的方法还可以包括步骤S234(图中未示出)。步骤S234：控制列选电路停止数据恢复操作。
在确定第二输入输出接口电路进行第二数据读写操作的情况下，需要隔离列选电路的数据恢复操作和第二输入输出接口电路的操作，以免二者互相影响进而影响数据读写的可靠性。因此需要控制列选电路停止数据恢复操作，以对列选电路的数据恢复操作和第二输入输出接口电路的第二数据读写操作进行操作隔离。
图7示出了本公开至少一个实施例提供的另一种存储装置的控制方法的流程示意图。如图7所示，该控制方法可以包括步骤S330-S333。
步骤S330：确定非易失存储操作电路进行数据备份。
步骤S331：连通非易失存储操作电路与NVSRAM阵列的耦接。
步骤S332：控制列选电路断开SRAM操作电路与NVSRAM阵列的耦接。
步骤S333：控制第二输入输出接口电路断开与NVSRAM阵列的耦接。
在确定非易失存储操作电路进行数据备份操作的情况下，需要隔离非易失存储操作电路的操作和SRAM操作电路的操作以及第二输入输出接口电路的操作，以免互相影响进而影响数据备份操作的可靠性。因此需要连通非易失存储操作电路与NVSRAM阵列的耦接，控制列选电路断开SRAM操作电路与NVSRAM阵列的耦接，控制第二输入输出接口电路断开与NVSRAM阵列的耦接，以对非易失存储操作电路和SRAM操作电路、第二输入输出接口电路进行操作隔离。
对于步骤S332，在一个示例中，例如，列选电路根据接收的非易失存储操作电路进行数据备份操作的指令，停止列选电路的操作。又例如，在列选电路还包括开关阵列的情况下，步骤S332还包括步骤S3321(图中未示出)。步骤S3321：控制列选电路断开与NVSRAM阵列耦接的开关阵列。隔离非易失存储操作电路的操作和SRAM操作电路的操作的方法可以参考上文的相关描述，此处不再赘述。
对于步骤S333，在一个示例中，例如，第二输入输出接口电路根据接收的非易失存储操作电路进行数据备份操作的指令，停止第二输入输出接口电路的操作。又例如，在第二输入输出接口电路还包括隔离子电路的情况下，步骤S333还包括步骤S3331(图中未示出)。步骤S3331：控制隔离子电路断开第二输入输出接口电路与NVSRAM阵列的耦接。隔离非易失存储操作电路的操作和第二输入输出接口电路的操作的方法可以参考上文的相关描述，此处不再赘述。
在一些实施例中，图7所示的方法还可以包括步骤S334(图中未示出)。步骤S334：控制列选电路停止数据恢复操作。
在确定非易失存储操作电路进行数据备份操作的情况下，需要隔离列选电路的数据恢复操作和非易失存储操作电路的操作，以免二者互相影响进而影响数据备份的可靠性。因此需要控制列选电路停止数据恢复操作，以对数据恢复操作和非易失存储操作电路的操作进行操作隔离。例如，在列选电路包括数据恢复操作子电路的情况下，步骤S334还可以包括控制数据恢复操作子电路停止执行数据恢复操作。
图8示出了本公开至少一个实施例提供的另一种存储装置的控制方法的流程示意图。如图8所示，该控制方法可以包括步骤S340-S343。
步骤S340：确定列选电路进行数据恢复操作。
步骤S341：断开非易失存储操作电路与NVSRAM阵列的耦接。
步骤S342：控制列选电路断开SRAM操作电路与NVSRAM阵列的耦接。
步骤S343：控制第二输入输出接口电路断开与NVSRAM阵列的耦接。
在确定列选电路进行数据恢复操作的情况下，需要隔离非易失存储操作电路的操作、SRAM操作电路的操作、第二输入输出接口电路的操作和列选电路的数据恢复操作，以免互相影响进而影响数据恢复操作的可靠性。因此需要断开非易失存储操作电路与NVSRAM阵列的耦接，控制列选电路断开SRAM操作电路与NVSRAM阵列的耦接，控制第二输入输出接口电路断开与NVSRAM阵列的耦接，以对非易失存储操作电路、SRAM操作电路、第二输入输出接口电路的操作与列选电路的数据恢复操作进行操作隔离。
对于步骤S342，在一个示例中，例如，在列选电路还包括开关阵列的情况下，步骤S342还包括步骤S344(图中未示出)。步骤S344：控制列选电路断开与NVSRAM阵列耦接的开关阵列。隔离非易失存储操作电路的操作和列选电路的数据恢复操作的方法例如可以参考上文的相关描述，此处不再赘述。
对于步骤S343，在一个示例中，例如，第二输入输出接口电路根据接收的非易失存储操作电路进行数据备份操作的指令，停止第二输入输出接口电路的操作。又例如，在第二输入输出接口电路还包括隔离子电路的情况下，步骤S343还包括步骤S345(图中未示出)。步骤S345：控制隔离子电路断开第二输入输出接口电路与NVSRAM阵列耦接的开关。隔离列选电路的数据恢复操作和第二输入输出接口电路的操作的方法例如可以参考上文的相关描述，此处不再赘述。
在本公开的一些实施例中，存储装置的控制方法还可以包括步骤S400-S420(图中未示出)。
步骤S400：接收工作模式信号。
步骤S410：根据工作模式信号产生用于第一数据读写操作、数据备份操作、数据恢复操作或第二数据读写操作的控制信号。
步骤S420：将控制信号对应地提供给SRAM操作电路、非易失存储操作电路、第一输入输出接口电路、列选电路或第二输入输出接口电路。
对于步骤S400，控制电路接收工作模式信号，该工作模式信号可以用于指示存储装置进行哪些工作模式，例如，工作模式信号可以用于指示存储装置进行数据读写操作、数据备份操作或者数据恢复操作等。
对于步骤S410，在控制电路接收工作模式信号之后，控制电路可以根据接收的工作模式信号产生对应的控制信号，例如产生用于第一数据读写操作、数据备份操作、数据恢复操作或第二数据读写操作的控制信号。示例性的，用于第一数据读写操作的控制信号可以包括控制SRAM操作电路进行第一数据读写操作；示例性的，用于第一数据读写操作的控制信号还可以包括控制非易失存储操作电路断开与NVSRAM阵列的耦接。示例性的，数据备份操作的控制信号可以包括控制非易失存储操作电路进行数据备份操作；示例性的，数据备份操作的控制信号还可以包括控制SRAM操作电路和第二输入输出接口电路断开与NVSRAM阵列的耦接；示例性的，用于数据恢复操作的控制信号，可以用于包括控制列选电路执行数据恢复操作，控制非易失存储操作电路断开与NVSRAM阵列的耦接，控制第二输入输出接口电路断开与NVSRAM阵列的耦接，控制列选电路断开SRAM操作电路与NVSRAM阵列的耦接。
对于步骤S420，控制电路将生成的控制信号对应提供给相应的操作电路。示例性的，控制电路可以将用于第一数据读写操作的控制信号对应提供给SRAM操作电路；示例性的，控制电路还可以将用于第一数据读写操作或者数据恢复操作的控制信号提供给非易失存储操作电路。示例性的，控制电路可以将用于数据备份操作的控制信号对应提供给非易失存储操作电路；示例性的，控制电路还可以将用于数据备份操作的控制信号提供给SRAM操作电路和第二输入输出接口电路。示例性的，控制电路可以将用于第二数据读写操作的控制信号对应提供给第二输入输出接口电路；示例性的，控制电路还可以将用于第二数据读写操作的控制信号提供给非易失存储操作电路。示例性的，控制电路还可以将用于数据恢复操作的控制信号提供给列选电路。
在本公开的至少一个实施例中，控制电路根据接收的工作模式信号产生相应的控制信号，并将各控制信号对应提供给相应的操作电路，从而可以提高数据读写、备份、恢复等操作的可靠性和效率。
图9示出了本公开至少一个实施例提供的一种存储装置工作方法的流程示意图。如图9所示，在本公开的一些实施例中，该存储装置的工作方法流程包括步骤S500-S560。该工作方法例如可以用于图2或图3所示的存储装置。
步骤S500：存储装置上电。
对于步骤S500，存储装置开始上电，即存储装置连通电源并启动。该过程可以由电源电路控制，电源电路可以向存储装置提供所需的电压和电流，以确保其正常运行。
步骤S510：判断是否要进行数据恢复。
对于步骤S510，存储装置可以根据接收的指令或电子设备的状态来确定是否需要进行数据恢复操作。如果需要进行数据恢复，则进行步骤S520；否则，进行步骤S530。
步骤S520：进行数据恢复。
对于步骤S520，例如，将之前备份到RRAM存储子单元中的数据恢复到SRAM存储子单元中。该步骤例如可以由列选电路控制。例如，在一些实施例中，步骤S520还包括图11所示的步骤S700-S750(下文将描述)。
步骤S530：进行数据读写。
对于步骤S530，该步骤例如可以通过SRAM操作电路或移位寄存操作电路控制。例如，SRAM操作电路(结合字线驱动电路、列选电路的选择操作)读取NVSRAM阵列的SRAM存储子单元中的数据。例如，移位寄存操作电路(可以结合字线驱动电路的选择操作)读取NVSRAM阵列的SRAM存储子单元中的数据。
步骤S540：判断是否进行数据备份。
对于步骤S540，存储装置确定是否需要进行数据备份操作。如果需要进行数据备份，则进行步骤S550；否则，进行步骤S560。
步骤S550：进行数据备份。
对于步骤S550，存储装置进行数据备份操作，将存储装置中SRAM存储子单元中的数据备份到RRAM存储子单元中。该步骤可以由非易失存储操作电路来控制。例如，在一些实施例中，步骤S550还包括图10所示的步骤S600-S650(下文将描述)。
步骤S560：判断是否发生掉电。
对于步骤S560，电子设备判断存储装置是否发生掉电。如果发生掉电，则会结束存储装置的工作；否则，会返回步骤S510，继续判断是否需要进行数据恢复操作。这个过程确保了存储装置在正常工作状态下能够持续运行，同时在掉电情况下能够保护数据的完整性。
图10示出了本公开至少一个实施例提供的一种存储装置数据备份方法的流程示意图。
如图10所示，该数据备份方法包括步骤S600-S650。该数据备份方法例如可以用于如图2或图3所示的存储装置。
步骤S600：进行数据读写。
对于步骤S600，在进行数据写入的情况下，例如可以通过SRAM操作电路将数据写入NVSRAM单元中的SRAM存储子单元，或者可以通过移位寄存操作电路将数据写入NVSRAM单元中的SRAM存储子单元。在进行数据读取的情况下，可以通过SRAM操作电路(可以结合字线驱动电路、列选电路的选择操作)读取SRAM存储子单元中存储的数据，并经过第一输入输出接口电路输出。或者，可以通过移位寄存操作电路(可以结合字线驱动电路的选择操作)读取SRAM存储子单元中存储的数据，并经过输出接口电路输出。
步骤S610：判断是否需要进行数据备份操作。
对于步骤S610，例如，存储装置会根据接收的指令确定是否需要进行数据备份操作。如果需要进行数据备份，则进行步骤S620；否则，继续进行步骤S600，继续数据读写操作。
步骤S620：选中I行NVSRAM单元。
对于步骤S620，在本公开的一些实施例中，在存储装置确定进行数据备份操作的情况下，字线驱动电路根据地址信息确定NVSRAM单元中的I行数据。I为整数且0＜I。示例性的，字线驱动电路根据地址信息确定第1行至第I行NVSRAM单元中的数据。
步骤S630：将选中的I行存储单元中SRAM存储子单元中的数据同时备份至RRAM存储子单元。
对于步骤S630，非易失存储操作电路进行并行操作，同时将确定的SRAM存储子单元中的I行数据备份到RRAM存储子单元中。示例性的，非易失存储操作电路将选中的第1行至第I行SRAM存储子单元中的数据备份到RRAM存储子单元中。
步骤S640：判断数据备份是否完成。
对于步骤S640，非易失存储操作电路确定数据备份是否完成。如果备份未完成，则进行步骤S650；若确定数据备份已完成，则将结束数据备份操作。
步骤S650：将SRAM存储子单元的行地址再增加I。之后继续进行步骤S620-S640的数据备份操作。
对于步骤S650，字线驱动电路更新SRAM存储子单元的行地址，将行地址再增加I，以便继续进行下一步的数据备份操作。示例性的，非易失存储操作电路将确定的第(I+1)行至第2I行SRAM存储子单元中的数据备份到RRAM存储子单元中。之后继续进行步骤S620-S640的数据备份操作，直到所有需要备份的数据都被备份到RRAM存储子单元中。
图11示出了本公开至少一个实施例提供的一种存储装置数据恢复方法的流程示意图。如图11所示，该数据恢复方法包括步骤S700-S750。该数据恢复方法例如可以用于如图2或图3所示的存储装置。
步骤S700：判断是否进行数据恢复操作。
对于步骤S700，在本公开的一些实施例中，存储装置根据接收到的指令或者预设的指令确定是否进行数据恢复操作。如果确定需要进行数据恢复操作，则会进行步骤S710；如果确定不进行数据恢复操作，则直接进行步骤S740。
步骤S710：选中I行NVSRAM单元。
对于步骤S710，字线驱动电路根据地址信息确定NVSRAM单元中的I行数据。I为整数且0＜I。示例性的，字线驱动电路根据地址信息确定第1行至第I行NVSRAM单元中的数据。
步骤S720：将选中的I行RRAM存储子单元的数据同时恢复至SRAM存储子单元中。
对于步骤S720，列选电路进行并行操作，将确定的I行RRAM存储子单元中的数据恢复到SRAM存储子单元中。之后进行步骤S730。
步骤S730：判断数据恢复操作是否完成。
对于步骤S730，若数据恢复操作未完成，则进行步骤S750；若数据恢复操作已完成，则进行步骤S740。
步骤S740：SRAM操作电路或移位寄存操作电路对SRAM存储子单元中的数据进行读写操作。
对于步骤S740，例如，当数据恢复操作完成后，可以通过SRAM操作电路读取SRAM存储子单元中的数据，并将读取出来的数据输入到第一输入输出接口电路中，以供后续处理和使用。或者，可以通过移位寄存操作电路读取SRAM存储子单元中的数据，并将读取出来的数据输入到输出接口电路中，以供后续处理和使用。示例性的，可以通过数据的位宽来确定通过SRAM操作电路或移位寄存操作电路来读取SRAM存储子单元中的数据，例如，可以预设第一输入输出接口电路传输高位宽的数据，输入接口电路、输出接口电路传输低位宽的数据，则当传输的数据为高位宽的数据时，可以通过SRAM操作电路来读取SRAM存储子单元中的数据，当传输的数据为低位宽的数据时，可以通过移位寄存操作电路来读取SRAM存储子单元中的数据。
步骤S750：行地址再增加I行。
对于步骤S750，在数据恢复操作未完成的情况下，更新RRAM存储子单元中需要进行恢复的数据的行地址，将行地址再增加I行，以便继续进行下一步的数据恢复操作。示例性的，列选电路将确定的第(I+1)行至第2I行RRAM存储子单元中的数据恢复到SRAM存储子单元中。然后，将继续进行步骤S710-S730的数据恢复操作，直到所有需要恢复的数据都被恢复到SRAM存储子单元中。
本公开的一些实施例提供了一种存储装置、包括该存储装置的电子设备和该存储装置控制方法。
该存储装置包括NVSRAM阵列、SRAM操作电路、非易失存储操作电路、纠检错电路、第一输入输出接口电路、列选电路、第二输入输出接口电路，其中，纠检错电路与SRAM操作电路耦接，SRAM操作电路与列选电路耦接，列选电路与NVSRAM阵列耦接，非易失存储操作电路与NVSRAM阵列耦接。
NVSRAM阵列包括阵列排列的多个NVSRAM单元，且每个NVSRAM单元包括SRAM存储子单元和非易失存储子单元，非易失存储子单元被配置为对SRAM存储子单元存储的数据进行数据备份。
非易失存储操作电路被配置为对NVSRAM阵列中被选择的NVSRAM单元中的SRAM存储子单元数据进行数据备份操作；SRAM操作电路被配置为对SRAM存储子单元数据进行第一数据读写操作；列选电路被配置为对非易失存储子单元数据进行数据恢复操作；列选电路还被配置为，在进行数据恢复操作或者在SRAM操作电路进行第一数据读写操作的情况下，选择NVSRAM阵列中需要被操作的对象单元列；第一输入输出接口电路与SRAM操作电路耦接，且被配置为将接收的第一输入数据提供给SRAM操作电路以及从SRAM操作电路接收要输出的第一输出数据；纠检错电路被配置为对目标数据进行编码和解码并判断目标数据是否发生错误并纠错；列选电路还被配置为隔离SRAM操作电路的操作和非易失存储操作电路的操作，以及隔离第一数据读写操作、第二数据读写操作和数据恢复操作；第二输入输出接口电路与NVSRAM阵列耦接，且被配置为对NVSRAM阵列进行第二数据读写操作。
该存储装置通过使用非易失存储子单元来备份SRAM存储子单元的数据，使用纠检错电路来检测和校正错误的存储数据，使用列选电路隔离SRAM操作电路的操作和非易失存储操作电路的操作，以及隔离第一数据读写操作、第二数据读写操作和数据恢复操作，还通过第一输入输出接口电路或第二输入输出接口电路来传输输入或者输出存储装置的数据，由此可以提高数据读写、备份、恢复的可靠性、灵活性。
图12示出了本公开至少一个实施例提供的一种存储装置的示意框图。
在本公开的一些实施例中，如图12所示，存储装置2000包括NVSRAM阵列220、SRAM操作电路200、非易失存储操作电路230、列选电路210、第一输入输出接口电路250、第二输入输出接口电路270、纠检错电路260。
纠检错电路260与SRAM操作电路200耦接，SRAM操作电路200与列选电路210耦接，列选电路210与NVSRAM阵列220耦接，非易失存储操作电路230与NVSRAM阵列220耦接，第一输入输出接口电路250与SRAM操作电路200耦接，第二输入输出接口电路270与NVSRAM阵列220耦接。
在本公开中“耦接”用于指代描述对象之间的信号连接，当描述对象之间建立耦接之后可以进行信号传递，而当描述对象之间断开耦接之后则不能进行信号连接，可以通过例如电连接等方式实现耦接。例如，在本公开的实施例中，“耦接”可以包括两个或多个电子元件或电路之间通过某种方式连接在一起，使得在它们之间的信号互相传递。例如，两个存储子单元可以直接相连，通过信号或能量的传递来实现信息的传递，或者两个存储子单元之间通过其他电路元件相连，如通过电阻、电容、开关、光电元件等元件或传输线网络等，以实现信号的传递。
NVSRAM阵列220包括阵列排列的多个NVSRAM单元221，且每个NVSRAM单元221包括SRAM存储子单元222和非易失存储子单元231，非易失存储子单元231被配置为对SRAM存储子单元222存储的数据进行数据备份。多个NVSRAM单元221构成的阵列包括多行和多列。例如，多个NVSRAM单元221可以构成包括M行、N列的存储阵列，其中，M、N为整数且1≤M，1≤N。该NVSRAM单元221例如可以采用如图1所示的形式，但是本公开的实施例不限于该具体形式。
NVSRAM阵列220的NVSRAM单元221结合了SRAM存储子单元和非易失存储子单元的特性，SRAM存储子单元222可以被配置为存储数据，可以快速读取和写入数据。非易失存储子单元231被配置为对SRAM存储子单元222存储的数据进行数据备份，以防止电源关闭或者系统崩溃等情况发生时SRAM存储子单元222中存储的数据丢失。
例如，非易失存储子单元231可以包括RRAM、FeRAM(Ferroelectric Random Access Memory，铁电随机存储)、MRAM(Magnetic Random Access Memory，磁性随机存储)、PCM(Phase Change Memory，相变存储)、EEPROM(Electrically Erasable Programmable Read-Only Memory，带电可擦可编程只读存储)、PRAM、闪存等存储子单元。对应于不同类型的非易失存储子单元231，本公开实施例中的非易失存储操作电路230则进行相应地调整，本公开对此并不限定。例如，当非易失存储子单元231包括RRAM存储子单元的情形，非易失存储操作电路230则可以包括RRAM操作电路。
非易失存储操作电路230被配置为对NVSRAM阵列220中被选择的NVSRAM单元221中的SRAM存储子单元222数据执行数据备份操作。
在一些实施例中，非易失存储操作电路230可以与多个SRAM存储子单元222进行通信，非易失存储操作电路230可以根据实际需要对SRAM存储子单元222数据进行数据备份操作，比如当电子设备检测到某个应用程序出现故障或异常时，非易失存储操作电路230执行备份操作。又例如，非易失存储操作电路230还可以响应于备份指令对SRAM存储子单元222内的数据执行数据备份操作，或者基于预设的时间对SRAM存储子单元222进行定期数据备份操作，也可以对SRAM存储子单元222实时进行数据备份操作。
为提高数据备份的效率，非易失存储操作电路230可以采用并行处理方法同时对多个被选择的SRAM存储子单元222数据进行数据备份操作。比如，非易失存储操作电路230可以对某一行SRAM存储子单元222中的数据同时进行数据备份操作，或者非易失存储操作电路230可以对多行SRAM存储子单元222数据同时进行数据备份操作。
为了提高数据备份的可靠性以及稳定性，本公开的至少一实施例还采取一些安全设计以提高非易失存储操作电路230的冗余性，比如，非易失存储操作电路230可以采取双重备份机制，每个SRAM存储子单元222的数据可以被备份两次或更多次，以降低数据丢失的风险。
例如，在至少一个示例中，非易失存储操作电路230可以采用ECC(Error Checking and Correcting，错误检测和校正)机制，当数据被备份至非易失存储子单元231时，ECC机制可以添加额外的校验位，以便在数据读取时检测和校正错误。ECC机制可以提高数据的可靠性，并降低因硬件故障或数据损坏导致的数据丢失风险。
例如，在至少一个示例中，非易失存储操作电路230还可以采用CRC(Cyclic Redundancy Check，循环冗余校验)机制，在数据备份操作前和操作后计算数据的CRC值，以确保数据的完整性。如果CRC值不匹配，非易失存储操作电路230可以采取相应的措施来恢复数据或进行错误处理。本公开的其他实施例也可以采用其他数据校验和纠错机制，包括但不限于，奇偶校验、SED(Single-bit Error Detection，单比特错误被探测)、SEC(Single-bit Error Correction，单比特错误被校正)，DED(Double-bit Error Detection，双比特错误被探测)或FED(Fatal Error Detection，致命错误被探测)等，本公开的实施例对此不作限制。
在本公开的一些实施例中，第一输入输出接口电路250被配置为将接收的第一输入数据提供给SRAM操作电路200以及从SRAM操作电路200接收要输出的第一输出数据。SRAM操作电路200被配置为对SRAM存储子单元222进行第一数据读写操作。第二输入输出接口电路270被配置为对NVSRAM阵列220进行第二数据读写操作。
这里，“第一数据读写操作”是指SRAM操作电路200对SRAM存储子单元222进行数据读写操作。“第二数据读写操作”是指第二输入输出接口电路270对SRAM存储子单元222进行数据读写操作。例如，第一输入输出接口电路250可以被配置为接收输入存储装置2000的第一输入数据，并将该第一输入数据提供给SRAM操作电路200。并在SRAM操作电路200需要进行数据输出的时候，第一输入输出接口电路250可以被配置为从SRAM操作电路200接收要输出的第一输出数据。
例如，存储装置2000可以通过接收的控制指令、输入存储装置2000的数据位宽或数据类型、存储装置2000中各电路的工作情况等，来确定输入存储装置2000的数据从第一输入输出接口电路250输入存储装置2000，或者从第二输入输出接口电路270输入存储装置2000。示例性的，在列选电路210进行数据恢复操作的情况下，可以将输入存储装置2000的数据从第二数据输入输出接口电路260输入。示例性的，在第二输入输出接口电路270进行第二数据读写操作的情况下，可以将输入存储装置2000的数据从第二输入输出接口电路270输入。示例性的，可以预设第一输入输出接口电路250和第二输入输出接口电路270对于输入或输出数据的位宽，例如可以预设输入或输出第一输入输出接口电路250的数据位宽大于第二输入输出接口电路270的；例如，预设输入或输出第一输入输出接口电路250的数据位宽为32bit，输入或输出第二输入输出接口电路270的数据位宽为512bit，则当输入存储装置2000的数据位宽为32bit的情况下，则该数据可以从第一输入输出接口电路250输入，本公开的实施例对此并不限定。
例如，可以通过接收的读写指令、数据位宽或数据类型、存储装置2000中各电路的工作情况等，来确定由SRAM操作电路200对选定的SRAM存储子单元222进行第一数据读写操作，或者由第二输入输出接口电路250对选定的SRAM存储子单元222进行第二数据读写操作。
例如，SRAM操作电路200通过接收相应的数据读写指令，对选定的SRAM存储子单元222进行第一数据读写操作。当非易失存储子单元231中的数据需要恢复到SRAM存储子单元222时，列选电路210执行数据恢复操作，SRAM操作电路200读取SRAM存储子单元222中的数据，并将该数据输入纠检错电路260中。
在一些实施例中，列选电路210被配置为在进行数据恢复操作，或者在SRAM操作电路200进行第一数据读写操作的情况下，选择NVSRAM阵列220中需要被操作的对象单元列。例如，在SRAM操作电路200进行第一数据读写操作或在列选电路210进行数据恢复操作的情况下，列选电路210响应于接收的地址信号，并将其转化为电信号，从而选择NVSRAM阵列220中相应的对象单元列；例如，列选电路210可以根据SRAM操作电路200需要执行第一数据读写操作或者列选电路210需要执行数据恢复操作的指令，选择NVSRAM阵列220中相应的对象单元列。
这里，“对象单元列”用于指代作为被操作对象的存储单元列，其可以是多个存储阵列中的任一列。“地址信号”包括行选择信号和列选择信号，字线驱动电路(下面将描述)使用行选择信号进行行寻址，列选电路使用列选择信号进行列寻址。
如前述内容，在非易失存储操作电路230进行数据备份操作的过程中，或者在SRAM操作电路200进行第一数据读写操作或者在列选电路210进行数据恢复操作的过程中，或者在第二输入输出接口电路270进行第二数据读写操作的过程中，非易失存储操作电路230的操作、SRAM操作电路200、第二输入输出接口电路270的操作以及列选电路210的数据恢复操作之间可能会互相影响，进而影响数据备份和数据恢复的稳定性。
在本公开的至少一些实施例中，列选电路210还可以被配置为隔离SRAM操作电路200的操作和非易失存储操作电路230的操作。例如，第二输入输出接口电路270还可以被配置为隔离第二输入输出接口电路270的操作和非易失存储操作电路230的操作。
例如，可以对非易失存储操作电路230和SRAM操作电路200分别设置独立的列选电路210，以减小二者之间的影响干扰，独立的列选电路210可以具有不同的电路结构和元件，以适应非易失存储操作电路230和SRAM操作电路200的特性以及操作需求。
例如，列选电路210还可以在SRAM操作电路200进行第一数据读写操作、第二输入输出接口电路270进行第二数据读写操作或非易失存储操作电路230进行数据备份操作的情况下，不执行数据恢复操作，以对第一数据读写操作、第二数据读写操作、数据备份操作和数据恢复操作进行操作隔离。
在一些实施例中，还可以对非易失存储操作电路230、SRAM操作电路200或第二输入输出接口电路270进行电源隔离，比如可以为非易失存储操作电路230、SRAM操作电路200或第二输入输出接口电路270分别提供独立的电源或供电线路。例如，还可以通过在非易失存储操作电路230、SRAM操作电路200或第二输入输出接口电路270中增加稳压器，来提高电路的供电稳定。例如，还可以利用光耦合器通过光信号来传输非易失存储操作电路230、SRAM操作电路200或第二输入输出接口电路270的数据。例如，还可以通过逻辑设计来控制非易失存储操作电路230的操作、SRAM操作电路200的操作或第二输入输出接口电路270的操作，如在特定的情形下，可以只允许对非易失存储操作电路230的操作，或只允许对SRAM操作电路200的操作，或只允许第二输入输出接口电路270的操作，禁止非易失存储操作电路230与SRAM操作电路200或第二输入输出接口电路270同时进行操作。
在一些实施例中，如图12所示，第一输入输出接口电路250被配置为将接收的第一输入数据提供给SRAM操作电路200以及从SRAM操作电路200接收要输出的第一输出数据；纠检错电路260被配置为对目标数据进行编码和解码并判断目标数据是否发生错误并纠错。
在本公开的至少一些实施例中，例如，纠检错电路260可以通过奇偶校验码对数据进行编码，可以通过在数据中添加一个额外的数据校验位，使得整个字节中的1的个数为偶数(偶校验)或奇数(奇校验)，在纠检错电路260接收到待校验数据的时候，可以通过对校验位进行检查。例如，纠检错电路260还可以通过汉明码对数据进行编码，可以将数据分为多个组，并在每个组中增加校验位，使得每个组中错误的数据可以被检测和纠正。又例如，纠检错电路260还可以通过循环冗余校验(CRC)方法对数据进行编码，可以在数据中添加冗余的校验码，将数据看作二进制多项式，使用生成多项式对其进行模2除法运算，得到的余数即为CRC校验码。
在本公开的至少一些实施例中，例如，纠检错电路260还可以包括数据编码器和数据解码器，数据编码器可以被配置为将输入数据转换为特定的编码格式，增加数据的冗余信息，例如奇偶校验码、汉明码、循环冗余校验码等。数据解码器可以被配置为将接收到的编码数据解码为原始数据，同时，它还会对数据进行错误检测，例如通过奇偶校验、CRC校验等。
在本公开的至少一些实施例中，例如，纠检错电路260还可以包括错误检测和纠错逻辑以及包括控制逻辑。错误检测和纠错逻辑可以对解码后的数据进行错误检测，并根据编码方式判断是否能够纠正错误。例如，如果使用奇偶校验码，那么该逻辑会检查校验位并确定错误位，然后对错误位进行修正。对于一些复杂的错误情况，可能需要进行多次纠错或降级处理。控制逻辑用于控制数据编码、传输、解码和纠错的整个过程，还可以用于与其他电路交互，例如向列选电路210发送控制信号以控制数据传输。
在本公开的至少一些实施例中，纠检错电路260还可以被配置为：在非易失存储操作电路230进行数据备份操作的情况下，对从SRAM操作电路200输入纠检错电路260的目标数据进行编码；以及在列选电路210完成数据恢复操作的情况下，确定SRAM操作电路200从NVSRAM阵列220读取并输入纠检错电路260的目标数据是否发生错误并纠错。
在本公开的一个示例中，例如，在根据系统指令需要进行数据备份操作的情形中，SRAM操作电路200从NVSRAM阵列的SRAM存储子单元222中读取数据，并将该数据输入到纠检错电路260中。当从SRAM操作电路200接收到数据后，纠检错电路260对该数据进行编码。该编码可以通过添加额外的校验位，以增加数据的冗余性，以便在数据被再次写入NVSRAM阵列220后，即使部分数据发生损坏或丢失，也能够通过校验位来检测和纠正错误。编码后的数据将被纠检错电路260写入SRAM操作电路200。SRAM操作电路200从纠检错电路260接收编码后的数据，再将其通过列选电路写入NVSRAM阵列220中。
进一步的，在进行编码时，纠检错电路260对读取的目标数据的K位信息码进行编码得到R位校验码，通过SRAM操作电路200将R位校验码写入NVSRAM阵列220的SRAM存储子单元222中。其中，K和R为正整数。
例如，在进行编码时，纠检错电路260获取目标数据的K位信息码，然后可以通过特定的编码算法对其进行处理。该算法可以根据K位信息码的内容，生成与之对应的R位校验码。生成的R位校验码能够用于检测和纠正数据传输或存储过程中可能出现的错误。生成R位校验码后，纠检错电路260会通过SRAM操作电路200将包括R位校验码的数据写入NVSRAM阵列220的SRAM存储子单元222中。通过将校验码存储在NVSRAM阵列220中，可以使得数据在后续的传输或存储过程中得到保护。即使出现数据传输错误或存储介质损坏等情况，也可以通过校验码对数据进行恢复和纠错，从而提高了数据的可靠性和系统的稳定性。
在本公开的一个示例中，例如，根据系统指令在存储装置完成数据恢复操作的情况下，列选电路可以导通SRAM操作电路200与NVSRAM阵列220的耦接，在SRAM操作电路200从NVSRAM阵列220读取已经编码过的数据并输入到纠检错电路260后，纠检错电路260电路可以确定读取的数据是否发生错误并纠错。例如，可以通过比较读取的数据和预期的数据。如果发现错误，纠检错电路260将使用编码过程中添加的校验位来纠正错误。例如，如果读取的数据中有一位是错误的，纠检错电路260可以使用校验位来检测到这一错误，并使用编码过程中预期的正确值来更正这一错误。
进一步的，纠检错电路260对SRAM操作电路200从NVSRAM阵列220读取已经编码过的目标数据进行解码。在进行解码时，纠检错电路260对读取的目标数据的K位信息码和R位校验码进行解码检错，响应于发生错误则进行纠错，将K位纠错后的信息码通过SRAM操作电路200写入NVSRAM阵列220中。例如，在进行解码时，SRAM操作电路200从NVSRAM阵列220中读取包含K位信息码和R位校验码的目标数据，并将其传递给纠检错电路260。然后，纠检错电路260利用特定的解码算法对读取的数据进行解码检错。这个过程中，纠检错电路260可以检查数据的完整性，通过校验码来检测是否存在错误。如果在解码过程中发现错误，纠检错电路260可以启动纠错机制。纠检错电路260可以然后根据错误类型和程度，采取相应的纠错措施。例如，纠检错电路260可以将K位纠错后的信息码通过SRAM操作电路200写入NVSRAM阵列220的SRAM存储子单元222中，以替换原来的错误数据。不仅可以提高数据的准确性，也提高了存储数据的安全性和可靠性。
在本公开的一个示例中，例如，在非易失存储操作电路230进行数据备份操作的情况下，纠检错电路260对从SRAM操作电路200输入纠检错电路260的包括K位信息码的数据进行编码，获得R位校验码数据。之后，纠检错电路260将编码后的包括R位校验码的数据写入SRAM操作电路200中。SRAM操作电路200通过列选电路将包括R位校验码的数据写入到NVSRAM阵列220中。在列选电路210完成数据恢复操作的情况下，纠检错电路260对于SRAM操作电路200从NVSRAM阵列220读取并输入纠检错电路260的包括K位信息码和R位校验码的数据进行解码，并确定解码结果是否发生错误，若发生错误则进行纠错。
例如，在本公开的一些实施例中，存储装置2000可以在进行数据备份操作或在进行数据恢复操作的时候进行纠检错操作，而在进行第一数据读写操作或第二数据读写操作的情况下，不进行纠检错操作，可以提高数据读写的速度。
以上描述的是本公开实施例一个基本的纠检错和存储操作过程。在不同的实施例中，纠检错电路260可能会使用不同的编码和解码算法，例如使用奇偶校验、CRC校验等不同的校验方法，本公开实施例对此并不限定。此外，数据写入和读取的过程也可以因具体的硬件和接口设计而有所不同。
图13示出了本公开至少一个实施例提供的另一种存储装置的示意框图。
如图13所示，在本公开的一些实施例中，第二输入输出接口电路270包括移位寄存操作电路271、输入接口电路272和输出接口电路273。移位寄存操作电路271与NVSRAM阵列220耦接，且被配置为对NVSRAM阵列220进行第二数据读写操作；输入接口电路272与移位寄存操作电路271耦接，且被配置为接收第二输入数据且将接收的第二输入数据提供给移位寄存操作电路271；输出接口电路273与移位寄存操作电路271耦接，且被配置为从移位寄存操作电路271接收要输出的第二输出数据。
这里，“第二输入数据”是指通过第二输入输出接口电路270中的输入接口电路272输入存储装置2000的数据。“第二输出数据”是指通过第二输入输出接口电路270中的输出接口电路273输出存储装置2000的数据，本公开的实施例对数据的内容及形式等并不限制。
例如，移位寄存操作电路271可以将接收的第二输入数据输入NVSRAM阵列220的SRAM存储子单元222中，或者，移位寄存操作电路271可以从NVSRAM阵列220的SRAM存储子单元222中读取第二输出数据，并将该数据通过输出接口电路273输出存储装置2000。
例如，移位寄存操作电路271可以对接收的第二输入数据进行暂存，之后再将该第二输入数据输入NVSRAM阵列220中的SRAM存储子单元222。
例如，移位寄存操作电路271还可以对接收的第二输入数据进行转换。示例性的，移位寄存操作电路271可以将串行接收的第二输入数据转换为并行地输入NVSRAM阵列220中的SRAM存储子单元222。
在本公开的一些实施例中，如图12或图13所示，NVSRAM阵列220还可以被配置为与字线驱动电路240耦接。字线驱动电路240被配置为在SRAM操作电路200进行第一数据读写操作的情况下，或者在第二输入输出接口电路270进行第二数据读写操作的情况下，或者在所述非易失存储操作电路进行所述数据备份操作的情况下，或者在列选电路进行数据恢复操作的情况下，或者在非易失存储操作电路进行数据备份操作的情况下，选择NVSRAM阵列220中需要被操作的对象单元行。
这里，“对象单元行”用于指代作为被操作对象的存储单元行，其可以是多个存储阵列中的任一行。
用于NVSRAM阵列220的字线驱动电路240(Word Line Driver)被配置为控制NVSRAM阵列220中存储单元所在行(字线)的电路。在NVSRAM阵列220中，例如，每个存储单元都位于信号线的交叉点处，即横向的信号线为字线(Word Line)，纵向的信号线为位线(Bit Line)。例如，字线驱动电路240负责控制与字线相连的开关，以决定哪一行中的存储单元被选中用于进行所需的操作(对应地，列选电路210则负责通过位线决定哪一列的存储单元被选中用于进行所需的操作)。
例如，在一些实施例中，字线驱动电路240可以包括解码器和选择器。解码器用于接收地址信号，并将其解码为对应字线的行地址。选择器则负责根据行地址选择相应的字线以施加驱动信号。在数据读取或写入被选择的存储单元时，字线驱动电路240可以确保对被选择的存储单元的正确访问，同时避免对其他未被选中的存储单元产生干扰或误操作。
例如，在一些实施例中，在第二输入输出接口电路270进行第二数据读写操作的情况下，字线驱动电路240可以被配置为选择NVSRAM阵列220中哪一行的存储单元被选中用于进行第二数据读写操作。在进行数据读取操作的时候，第二输入输出接口电路270可以读取该被选中的行数据；在进行数据写入操作的时候，第二输入输出接口电路270可以将数据写入该被选中的存储单元行。
例如，在一些实施例中，在第二输入输出接口电路270进行第二数据读写操作的情况下，可以根据列选电路确定哪一列的存储单元被选中用于进行第二数据读写操作，也可以对NVSRAM阵列220中存储单元的全部列进行第二数据读写操作，本公开的实施例对此并不限定。
例如，在一些实施例中，在SRAM操作电路200进行第一数据读写操作或列选电路210进行数据恢复操作的情况下，字线驱动电路240可以被配置为选择NVSRAM阵列220中哪一行的存储单元被选中用于进行第一数据读写操作或数据恢复操作。示例性的，在SRAM操作电路200进行第一数据读写操作的情况下，在进行数据读取操作的时候，SRAM操作电路200可以读取该被选中的行数据；在进行数据写入操作的时候，SRAM操作电路200可以将数据写入该被选中的存储单元行。
例如，在一些实施例中，在非易失存储操作电路230进行数据备份操作的情况下，字线驱动电路240可以被配置为选择NVSRAM阵列220中哪一行的存储单元被选中用于进行数据备份操作。示例性的，在进行数据备份操作的时候，非易失存储操作电路230可以读取SRAM存储子单元222中该被选中的行数据，并将SRAM存储子单元222中的该行的数据备份至非易失存储子单元231中。
例如，在一些实施例中，在列选电路210进行数据恢复操作的情况下，字线驱动电路240可以被配置为选择NVSRAM阵列220中哪一行的存储单元被选中用于进行数据恢复操作。示例性的，在进行数据恢复操作的时候，列选电路210可以将非易失存储子单元231中的该被选择的行的数据恢复至SRAM存储子单元222中。
图14示出了本公开至少一个实施例提供的另一种存储装置的示意框图。
如图14所示，在本公开的一些实施例中，第二输入输出接口电路270还可以包括隔离子电路274。隔离子电路274耦接在NVSRAM阵列220和移位寄存操作电路271之间。隔离子电路274可以被配置为在移位寄存操作电路271进行第二数据读写操作的情况下，导通移位寄存操作电路271与NVSRAM阵列220耦接的开关。或者，隔离子电路274还可以被配置为在非易失存储操作电路230进行数据备份操作的情况下，断开移位寄存操作电路271与NVSRAM阵列220耦接的开关。
例如，在本公开的至少一些实施例中，在移位寄存操作电路271进行第二数据读写操作的情况下，隔离子电路274可以将移位寄存操作电路271和NVSRAM阵列220耦接起来，则移位寄存操作电路271可以对NVSRAM阵列220中的SRAM存储子单元222进行第二数据读写操作，以实现快速的数据读写传输。同时，由于非易失存储操作电路230与NVSRAM阵列220的连接断开，因此不会对移位寄存操作电路271的读写操作产生影响。
在非易失存储操作电路230需要进行数据备份操作的情况下，隔离子电路274可以将移位寄存操作电路271和NVSRAM阵列220的耦接断开，而非易失存储操作电路230与NVSRAM阵列220耦接，非易失存储操作电路230可以进行数据备份操作，移位寄存操作电路271不会对非易失存储操作电路230的数据备份操作产生影响。
在本公开的一些实施例中，在SRAM操作电路200进行第一数据读写操作的情况下，列选电路210还可以被配置为连通SRAM操作电路200和NVSRAM阵列220的耦接，非易失存储操作电路230可以被配置为断开与NVSRAM阵列220的耦接，第二输入输出接口电路260可以被配置为断开与NVSRAM阵列220的耦接。
在本公开的一些实施例中，在非易失存储操作电路230进行数据备份的情况下，列选电路210还可以被配置为断开SRAM操作电路200和NVSRAM阵列220的耦接，非易失存储操作电路230还可以被配置为连通与NVSRAM阵列220的耦接，第二输入输出接口电路260可以被配置为断开与NVSRAM阵列220的耦接。
在本公开的一些实施例中，在列选电路210进行数据恢复操作的情况下，列选电路还可以被配置为断开SRAM操作电路200和NVSRAM阵列220的耦接，非易失存储操作电路230可以被配置为断开与NVSRAM阵列220的耦接，第二输入输出接口电路260可以被配置为断开与NVSRAM阵列220的耦接。
在本公开的一些实施例中，在第二输入输出接口电路260进行第二数据读写操作的情况下，列选电路210还可以被配置为断开SRAM操作电路200和NVSRAM阵列220的耦接，非易失存储操作电路230还可以被配置为断开与NVSRAM阵列220的耦接。
例如，在本公开的至少一些实施例中，在SRAM操作电路200需要进行第一数据读写操作的情况下，列选电路210将SRAM操作电路200和NVSRAM阵列220耦接起来，则SRAM操作电路200可以对NVSRAM阵列220中的SRAM存储子单元222进行读写操作，以实现快速的数据读写传输。同时，由于非易失存储操作电路230与NVSRAM阵列220的耦接断开，第二输入输出接口电路260与NVSRAM阵列220的耦接断开，因此不会对SRAM操作电路200的读写操作产生影响。
例如，在非易失存储操作电路230需要进行数据备份的情况下，第二输入输出接口电路260与NVSRAM阵列220的耦接断开，列选电路210将SRAM操作电路200和NVSRAM阵列220的耦接断开，而非易失存储操作电路230与NVSRAM阵列220耦接，非易失存储操作电路230可以进行备份操作，SRAM操作电路200不会对数据备份过程产生影响。
例如，在列选电路210需要进行数据恢复操作的情况下，第二输入输出接口电路260与NVSRAM阵列220的耦接断开，列选电路210将SRAM操作电路200和NVSRAM阵列220的耦接断开，并且非易失存储操作电路230也与NVSRAM阵列220的耦接断开，因此，SRAM操作电路200、非易失存储操作电路230以及第二输入输出接口电路260不会对列选电路210的数据恢复操作过程产生影响。
例如，在第二输入输出接口电路260需要进行第二数据读写操作的情况下，非易失存储操作电路230与NVSRAM阵列220的耦接断开，列选电路210将SRAM操作电路200和NVSRAM阵列220的耦接断开，因此SRAM操作电路200、非易失存储操作电路230的操作不会对第二输入输出接口电路260的第二数据读写操作过程产生影响。
在本公开的一些实施例中，如图14所示，列选电路210还包括数据恢复操作子电路211。
例如，在一些实施例中，数据恢复操作子电路211可以被配置为对对象单元列中的非易失存储子单元231数据进行数据恢复操作。例如，数据恢复操作子电路211可以在接收到进行数据恢复操作指令的情况下，将被选择的非易失存储子单元231中存储的数据恢复至SRAM存储子单元222中。例如，在进行数据恢复操作时，数据恢复操作子电路要确保与SRAM操作电路200、第二输入输出接口电路260和非易失存储操作电路230的操作相隔离，以防止第一数据读写操作、第二数据读写操作、数据备份操作和数据恢复操作之间的冲突，提高了数据的完整性和系统的稳定性。
例如，在一些实施例中，列选电路210或隔离子电路264还可以包括开关阵列(图中未示出)。例如，列选电路210可以通过开关阵列来控制SRAM操作电路200与NVSRAM阵列220的耦接。例如，移位寄存操作电路261可以通过隔离子电路264的开关阵列与NVSRAM阵列220耦接。
例如，在SRAM操作电路200进行第一数据读写操作的情况下，列选电路210可以被配置为导通列选电路210与NVSRAM阵列220之间的耦接的开关阵列。例如，在非易失存储操作电路230进行数据备份操作的情况下，列选电路210还可以被配置为断开列选电路210与NVSRAM阵列220之间的耦接的开关阵列。
例如，列选电路210或隔离子电路264的开关阵列还可以根据控制非易失存储操作电路230的操作、SRAM操作电路200的操作或移位寄存操作电路261的操作的时序逻辑来进行导通或关断。例如，在特定的时序下，在只允许SRAM操作电路200进行操作时，列选电路210的开关阵列导通。例如，在特定的时序下，在只允许非易失存储操作电路230进行操作时，列选电路210的开关阵列断开。
如上所述，如图13所示，在本公开的一些实施例中NVSRAM阵列220的阵列宽度可以被配置为N，即具有N列存储单元(或位线的数量为2N)例如，在NVSRAM阵列220中每行可以包括N个NVSRAM单元。NVSRAM阵列220的阵列还可以被配置为具有M行存储单元，例如，在NVSRAM阵列220中每列可以包括M个NVSRAM单元。每个存储单元有一个对应的地址，用于定位和访问该存储单元。NVSRAM阵列220的阵列还可以被配置为具有M行存储单元。示例性的，NVSRAM阵列220中每行包括N个存储单元，每个存储单元配置有X条位线(X大于等于1)，则NVSRAM存储阵列位线数为X*N，在传输线为位线对的情况下，X可以被配置为2，则NVSRAM存储阵列的位线数可以被配置为2N。在一些实施例中，例如，NVSRAM阵列220可以以字(Word)为单位进行配置。非易失存储操作电路230可以被配置为通过N组传输线与NVSRAM阵列220耦接。例如，在至少一个示例中，在传输线为位线或位线对(例如如图1所示的位线BL和BLN)的情况下，非易失存储操作电路230还可以被配置为通过N条或2N条位线与NVSRAM阵列220耦接。
在本公开的一些实施例中，NVSRAM阵列220的N列存储单元可以包括K列数据列和R列冗余列，数据列存储信息码，冗余列存储根据编码需要的额外校验码。NVSRAM阵列220以字(Word)为单位进行配置，NVSRAM阵列220的每行存储P个字的数据，每个字的操作位宽可以被配置为W。NVSRAM阵列220包括K列数据列以存储信息码，以及R列冗余列以存储校验码。例如，信息码可以以“字”为单位进行配置，校验码可以以“页”为单位进行配置，本公开的实施例对此并不限制。例如，K＝W*P，N、W、P、K和R均为正整数，1≤K＜N，1≤R＜N，1≤W≤N。例如，W可以为W1或W2。
在本公开的实施例中，数据列和冗余列可以有多种布置形式。例如，如图15、图16A、图16B所示，可以将全部数据列彼此相邻的布置在一起，将全部冗余列彼此相邻的布置在一起；或者可以将数据列分组，将冗余列分组，然后将数据列分组和冗余列分组彼此交替布置，例如，可以将K位数据列和R位冗余列布置为一个组合，NVSRAM阵列可以包括N列该组合；或者，NVSRAM阵列中可以包括多组K列数据列以及R列数据列；或者，NVSRAM阵列可以包括多组K个数据位和R个冗余位，例如，K个数据位可以包括多行的信息码数据，R个冗余位可以包括多个校验码数据。本公开的实施例对于数据列和冗余列的布置形式并不限定。
在本公开的一些实施例中，如图13所示，纠检错电路260可以被配置为通过K+R组传输线与SRAM操作电路200耦接。SRAM操作电路可以被配置为通过W1组传输线与第一输入输出接口电路250耦接。SRAM操作电路200还可以被配置为通过W1组传输线与列选电路210耦接。非易失存储操作电路230通过N组传输线与NVSRAM阵列220耦接。列选电路210通过N组传输线与NVSRAM阵列220耦接。例如，在传输线为位线或位线对(例如如图1所示的位线BL和BLN)的情况下，列选电路210还可以被配置为通过N条或2N条位线与NVSRAM阵列220耦接。在一些实施例中，例如在列选电路210进行数据恢复操作的情况下，列选电路210还可以被配置为将2N条位线的电压设置为相同电压值。在一些实施例中，例如，存储装置2000可以被配置为W1≤K+R≤N*M。
例如，纠检错电路260通过K+R组传输线与SRAM操作电路200耦接，将编码后的包括R位校验码的数据写入SRAM操作电路200，或者SRAM电路从NVSRAM阵列220读取的包括K位信息码和R位校验码的数据通过K+R组传输线写入纠检错电路260中。SRAM操作电路200通过W1组传输线与列选电路210连接，用于根据列选电路210提供的地址定位和访问NVSRAM阵列220中的特定存储单元，将包括R位校验码的数据写入NVSRAM阵列220中，以及从NVSRAM阵列220中读取包括K位信息码和R位校验码的数据。
在本公开的一些实施例中，移位寄存操作电路271可以通过N组传输线与NVSRAM阵列220耦接，输入接口电路272可以通过W2组传输线与移位寄存操作电路271耦接，输出接口电路273可以通过W2组传输线与移位寄存操作电路271耦接，其中，W2和N为整数且N≥W2>1。
在传输线为位线的情况下，移位寄存操作电路271通过N组传输线与NVSRAM阵列220连接，在传输线为位线对(例如如图1所示的位线BL和BLN)的情况下，移位寄存操作电路271还可以通过2N条位线与NVSRAM阵列220连接。
在本公开的一些实施例中，W1和W2可以用于表示传输数据中每个字的操作位宽。例如，在W1和W2相同的情况下，则存储装置2000可以选择任意的第一输入输出接口电路250或者输入接口电路272来接收输入存储装置2000的数据，或者选择任意的第一输入输出接口电路250或者输出接口电路273来输出数据。例如，在W1大于W2相同的情况下，则可以根据输入存储装置2000的数据位宽来确定数据的输入接口；示例性的，W1可以为512bit，W2可以为32bit，则当存储装置2000输入或输出的数据为512bit的情况下，则选择第一输入输出接口电路250来接收或者输出数据。
在本公开的一些实施例中，在非易失存储操作电路230进行数据备份操作的情况下，字线驱动电路240还可以被配置为选择NVSRAM阵列220的I行NVSRAM单元221中的SRAM存储子单元222数据以进行数据备份操作，其中，I为整数且M≥I≥1。
例如，字线驱动电路240可以根据接收的数据备份操作指令，选择NVSRAM阵列220中的I行NVSRAM单元221中的SRAM存储子单元222。示例性的，字线驱动电路240可以选择第1行至第I行的NVSRAM单元221中的SRAM存储子单元222，非易失存储操作电路230可以被配置为对被字线驱动电路240选择的第1行至第I行的NVSRAM单元221中的SRAM存储子单元222数据进行并行数据备份操作，将被选择的I行SRAM存储子单元222数据全部备份至非易失存储子单元231中。
在本公开的一些实施例中，在列选电路210进行数据恢复操作的情况下，字线驱动电路240还可以被配置为选择NVSRM阵列220的J行NVSRAM单元221中的非易失存储子单元231数据以进行数据恢复操作，其中，J为整数且M≥J≥1。
例如，字线驱动电路240可以根据接收的数据恢复操作指令，选择NVSRAM阵列220中的J行NVSRAM单元221中的非易失存储子单元231。示例性的，字线驱动电路240可以选择第1行至第J行的NVSRAM单元221中的非易失存储子单元231，列选电路210可以被配置为对被字线驱动电路240选择的第1行至第J行的NVSRAM单元221中的非易失存储子单元231数据进行并行数据恢复操作，将被选择的J行非易失存储子单元231数据全部恢复至SRAM存储子单元222中。
在本公开的一些实施例中，SRAM操作电路200还被配置为在进行第一数据读写操作的情况下，对被选择的NVSRAM阵列220的第i行的W1个NVSRAM单元221中的SRAM存储子单元222的数据进行第一数据读写操作。其中，N≥W1≥1，M≥i≥1。
例如，SRAM操作电路200的第一数据读写操作的操作位宽为W1。示例性的，SRAM操作电路200可以根据接收的第一数据读写操作指令，对被选择的NVSRAM阵列220的某一行(第i行)中的W1个NVSRAM单元221中的SRAM存储子单元222的数据进行第一数据读写操作。
在本公开的一些实施例中，第二输入输出接口电路270还被配置为在进行第二数据读写操作的情况下，对被选择的NVSRAM阵列220的第i行的W2个NVSRAM单元221中的SRAM存储子单元222的数据进行第二数据读写操作。其中，N≥W2≥1，M≥i≥1。
例如，第二输入输出接口电路270的第二数据读写操作的操作位宽为W2。示例性的，SRAM操作电路200可以根据接收的第二数据读写操作指令，对被选择的NVSRAM阵列220的某一行(第i行)中的W2个NVSRAM单元221中的SRAM存储子单元222的数据进行第二数据读写操作。
在本公开的一些实施例中，非易失存储操作电路230还被配置为在进行数据备份操作的情况下，对被选择的NVSRAM阵列220的E行和/或F列的NVSRAM单元221中的SRAM存储子单元222的数据进行数据备份操作。其中，E、F为整数且M≥E≥1，N≥F≥1。
例如，非易失存储操作电路230的数据备份操作的操作位宽为N*M。
例如，非易失存储操作电路230可以根据接收的数据备份操作指令，对NVSRAM阵列220中包括M行N列的NVSRAM单元221中的被选择的E行或者F列的NVSRAM单元221中的SRAM存储子单元222的数据进行数据备份操作。或者，非易失存储操作电路230可以对NVSRAM阵列220中包括M行N列的NVSRAM单元221中的被选择的E行NVSRAM单元221中的F列的SRAM存储子单元222的全部数据进行数据备份操作。
在本公开的一些实施例中，列选电路210还被配置为在进行数据恢复操作的情况下，对被选择的NVSRAM阵列220的G行和/或H列的NVSRAM单元221中的非易失存储子单元231的数据进行数据恢复操作。其中，G、H为整数且M≥G≥1，N≥H≥1。
例如，列选电路210的数据恢复操作的操作位宽为N*M。
例如，列选电路210可以根据接收的数据恢复操作指令，对NVSRAM阵列220中包括M行N列的NVSRAM单元221中的被选择的G行或者H列的NVSRAM单元221中的非易失存储子单元231的数据进行数据恢复操作。或者，非易失存储操作电路230可以对NVSRAM阵列220中包括M行N列的NVSRAM单元221中的被选择的G行NVSRAM单元221中的H列的非易失存储子单元231的全部数据进行数据恢复操作。
本公开至少一实施例的存储装置2000中，可以根据需求和硬件条件，灵活地调整这些传输线的数量及类型等参数，以优化存储装置2000的性能和效率。
本公开至少一实施例的存储装置2000中，在SRAM操作电路200进行第一数据读写操作的情况下，纠检错电路260不对数据进行纠检错，即在SRAM操作电路200读取第一输入输出接口电路250输入的数据，并将该数据通过列选电路210写入NVSRAM阵列220的过程中，纠检错电路260不对该数据进行纠检错。在非易失存储操作电路230进行数据备份操作、列选电路210完成数据恢复操作的情况下，纠检错电路260执行纠检错功能，可以提高数据读写、存储、备份、恢复的速度。
在本公开的一些实施例中，存储装置2000还可以包括控制电路280(图中未示出)，控制电路280可以与SRAM操作电路200、非易失存储操作电路230、第一输入输出接口电路250、列选电路210、纠检错电路260和第二输入输出接口电路270耦接。
控制电路280可以被配置为根据选择的工作模式向SRAM操作电路200、非易失存储操作电路230、第一输入输出接口电路250、列选电路210、纠检错电路260和第二输入输出接口电路270提供对应的控制信号。
例如，在存储装置2000中控制电路280可以根据存储装置2000的工作模式或者具体需求，生成相应的控制信号，并将生成的控制信号提供给对应的操作电路。
例如，在存储装置2000需要进行数据读取或数据写入的情况下，控制电路280可以根据预设的条件向SRAM操作电路200提供进行第一数据读写操作的控制信号，或者向第二输入输出接口电路270提供进行第二数据读写操作的控制信号。
例如，在存储装置2000需要进行数据备份操作的情况下，控制电路280可以向非易失存储操作电路230提供进行数据备份操作的控制信号，非易失存储操作电路230根据接收的数据备份操作控制信号，对被选择的SRAM存储子单元222中的数据执行数据备份操作。
例如，在存储装置2000需要进行数据恢复操作的情况下，控制电路270可以向列选电路210提供进行数据恢复操作的控制信号，列选电路210可以根据接收的数据恢复操作控制信号，对被选择的非易失存储子单元231中的数据执行数据恢复操作。
例如，在存储装置2000需要进行数据备份操作或者数据恢复操作的情况下，控制电路280还可以向纠检错电路260提供进行纠检错操作的控制信号。
例如，控制电路280还可以监控存储装置2000的工作状态或健康状态，如在第一输入输出接口电路250发生故障的情况下，在存储装置2000需要进行数据读写操作时，控制电路280可以向第二输入输出接口电路270提供第二数据读写操作控制信号。控制电路280还可以采取适当的措施对发生故障的电路进行修复或报告错误信息，以提高存储装置2000的可靠性和稳定性。
在本公开的至少一实施例中，控制电路280通过与存储装置2000的其他电路、组件的连接或交互，可以提高存储装置2000在不同工作模式下的运行效率。控制电路280还可以根据需要调整各个电路、组件的工作状态和参数，以实现对存储装置2000的灵活控制和管理。
本公开至少一个实施例提供的一种存储装置的控制方法。该控制方法包括控制纠检错电路对目标数据进行编码和解码并判断目标数据是否发生错误并纠错。该控制方法例如可以用于图12所示的存储装置。
例如，纠检错电路根据接收到的控制指令，接收SRAM操作电路输入的从NVSRAM阵列的SRAM存储子单元中读取的目标数据，并对该目标数据进行编码或解码。纠检错电路还可以将编码后的目标数据再输入SRAM操作电路以写入NVSRAM阵列的SRAM存储子单元中，或者对解码后的目标数据进行判断，确认是否发生错误并纠错。
图17示出了本公开至少一个实施例提供的一种存储装置的控制方法的流程示意图。
如图17所示，在本公开的一些实施例中，存储装置的控制方法包括步骤S810-S811。该控制方法例如可以用于图12所示的存储装置。
步骤S810：确定非易失存储操作电路进行数据备份操作。
步骤S811：对从SRAM操作电路输入纠检错电路的目标数据进行编码。
例如，纠检错电路响应于非易失存储操作电路进行数据备份操作的指令，纠检错电路对从SRAM操作电路输入的从NVSRAM阵列的SRAM存储子单元读取的目标数据进行编码。可选的，非易失存储操作电路进行数据备份操作以及纠检错电路对目标数据进行编码，可以同时进行，也可以先进行数据备份再对目标数据编码，还可以先进行目标数据进行编码，再将编码后的目标数据进行备份，本公开实施例对此并不限定。
图18示出了本公开至少一个实施例提供的另一种存储装置的控制方法的流程示意图。
如图18所示，在本公开的一些实施例中，存储装置的控制方法包括步骤S820-S821。该控制方法例如可以用于图12所示的存储装置。
步骤S820：确定列选电路完成数据恢复操作。
步骤S821：确定SRAM操作电路从NVSRAM阵列读取并输入纠检错电路的目标数据是否发生错误并纠错。
例如，纠检错电路响应于列选电路完成数据恢复操作的指令，纠检错电路对SRAM操作电路从NVSRAM阵列的SRAM存储子单元中读取的并输入纠检错电路的目标数据进行解码，并判断解码的结果是否错误，若发生错误则进行纠错。
纠检错电路对数据编码、解码以及纠错的方法可以参考上文的相关描述，此处不再赘述。
图19示出了本公开至少一个实施例提供的另一种存储装置的控制方法的流程示意图。
在本公开的一些实施例中，图17所示的存储装置的控制方法中步骤S811还可以包括如图19所示的步骤S910-S911。
步骤S910：在进行编码时，对读取的目标数据的K位信息码进行编码得到R位校验码。
对于步骤S910，纠检错电路将对接收到的目标数据的K位信息码数据进行编码，以生成R位校验码数据。纠检错电路编码方法可以参考上文的相关描述，此处不再赘述。例如，编码完成后，R位校验码数据可以附加到K位信息码数据后面，以形成包括K位信息码和R位校验码的数据。
步骤S911：通过SRAM操作电路将R位校验码写入NVSRAM阵列中。
对于步骤S911，例如，纠检错电路将向SRAM操作电路发送相应的控制信号，SRAM操作电路可以通过列选电路将包括R位校验码的数据写入NVSRAM阵列的SRAM存储子单元中。列选电路可以用于选择NVSRAM阵列中的特定列，以便将数据写入指定的存储单元。该步骤可以将数据可靠地存储在NVSRAM阵列的SRAM存储子单元中，以供后续的数据恢复操作或数据备份操作。
图20示出了本公开至少一个实施例提供的另一种存储装置的控制方法的流程示意图。
在本公开的一些实施例中，图18所示的存储装置的控制方法中步骤S821还可以包括如图20所示的步骤S920-S922。
步骤S920：在进行解码时，对读取的目标数据的K位信息码和R位校验码进行解码检错。
步骤S921：判断解码结果是否发生错误。
步骤S922：响应于发生错误则进行纠错，将K位纠错后的信息码通过SRAM操作电路写入NVSRAM阵列中。其中，K和R为正整数。
对于步骤S920，例如，响应于列选电路完成数据恢复操作的指令，SRAM操作电路通过列选电路选择NVSRAM阵列的SRAM存储子单元中特定列存储的数据(即目标数据)，SRAM操作电路将目标数据从NVSRAM阵列中读取出来。读取出来的目标数据被SRAM操作电路输入到纠检错电路中，以便进行后续的解码和错误检测操作。纠检错电路对于SRAM操作电路输入的从NVSRAM阵列的SRAM存储子单元中读取的包括K位信息码和R位校验码的目标数据进行解码。在一些实施例中，解码的过程可以是编码过程的逆操作，根据特定的解码算法将R位校验码数据从数据中分离出来，并根据校验码对K位信息码数据进行校验。随后纠检错电路进行步骤S921，判断解码的结果是否发生错误，若发生错误则开始步骤S922进行纠错，将K位纠错后的信息码通过SRAM操作电路写入NVSRAM阵列的SRAM存储子单元中，以替换错误的数据。若没有发生错误，则将该目标数据通过SRAM操作电路输入到输入输出接口电路进行数据输出。输入输出接口电路可以将目标数据发送到相应的外部设备或电子设备中的其他电路，以供后续的操作。纠检错电路对数据编码、解码以及纠错的方法可以参考上文的相关描述，此处不再赘述。
图21示出了本公开至少一个实施例提供的一种存储装置的控制方法的流程示意图。如图21所示，该方法可以包括步骤S1000-S1030。
步骤S1000：确定SRAM操作电路进行第一数据读写操作。
步骤S1010：断开非易失存储操作电路与NVSRAM阵列的耦接。
步骤S1020：控制列选电路连通SRAM操作电路与NVSRAM阵列的耦接。
步骤S1030:控制第二输入输出接口电路断开与NVSRAM阵列的耦接。
在确定SRAM操作电路进行第一数据读写操作的情况下，需要隔离非易失存储操作电路的操作和SRAM操作电路的操作，以免二者互相影响进而影响第一数据读写操作的可靠性。因此需要断开非易失存储操作电路与NVSRAM阵列的耦接，并控制列选电路连通SRAM操作电路与NVSRAM阵列的耦接，以对非易失存储操作电路和SRAM操作电路进行操作隔离。
对于步骤S1010，在一个示例中，例如，非易失存储操作电路根据接收的SRAM操作电路进行第一数据读写操作的指令，停止非易失存储操作电路的操作。
对于步骤S1020，在一个示例中，例如，在列选电路包括开关阵列的情况下，步骤S1020还包括步骤S1021(图中未示出)。
步骤S1021：控制列选电路导通与NVSRAM阵列耦接的开关阵列。隔离非易失存储操作电路的操作和SRAM操作电路的操作的方法可以参考上文的相关描述，此处不再赘述。
对于步骤S1030，在一个示例中，例如，第二输入输出接口电路根据接收的SRAM操作电路进行第一数据读写操作的指令，停止进行第二数据读写操作，并控制第二输入输出接口电路断开与NVSRAM阵列的耦接，以避免影响SRAM操作电路的操作。
在一些实施例中，图21所示的方法还可以包括步骤S1040(图中未示出)。步骤S1040：控制列选电路停止数据恢复操作。
在确定SRAM操作电路进行第一数据读写操作的情况下，需要隔离列选电路的数据恢复操作和SRAM操作电路的操作，以免二者互相影响进而影响数据读写的可靠性。因此需要控制列选电路停止数据恢复操作，以对列选电路的数据恢复操作和SRAM操作电路的第一数据读写操作进行操作隔离。
图22示出了本公开至少一个实施例提供的一种存储装置的控制方法的流程示意图。如图22所示，该方法可以包括步骤S1050-S1080。
步骤S1050：确定第二输入输出接口电路进行第二数据读写操作。
步骤S1060：断开非易失存储操作电路与NVSRAM阵列的耦接。
步骤S1070：连通第二输入输出接口电路与NVSRAM阵列的耦接。
步骤S1080：控制列选电路断开SRAM操作电路与NVSRAM阵列的耦接。
在确定第二输入输出接口电路进行第二数据读写操作的情况下，需要隔离非易失存储操作电路的操作和第二输入输出接口电路的操作，以免二者互相影响进而影响第二数据读写操作的可靠性。因此需要断开非易失存储操作电路与NVSRAM阵列的耦接，并连通第二输入输出接口电路与NVSRAM阵列的耦接，以对非易失存储操作电路和第二输入输出接口电路进行操作隔离。
对于步骤S1060，在一个示例中，例如，非易失存储操作电路可以根据接收的第二输入输出接口电路进行第二数据读写操作的指令，停止非易失存储操作电路的操作。
对于步骤S1070，在一个示例中，例如，在第二输入输出接口电路包括隔离子电路的情况下，步骤S1070还包括步骤S1071(图中未示出)。
步骤S1071：控制隔离子电路导通第二输入输出接口电路与NVSRAM阵列的耦接。隔离非易失存储操作电路的操作和第二输入输出接口电路的操作的方法可以参考上文的相关描述，此处不再赘述。
对于步骤S1080，在一个示例中，例如，列选电路根据接收的第二输入输出接口电路进行第二数据读写操作的指令，断开SRAM操作电路与NVSRAM阵列的耦接，以避免影响第二输入输出接口电路进行第二数据读写操作。
在一些实施例中，图22所示的方法还可以包括步骤S1090(图中未示出)。步骤S1090：控制列选电路停止数据恢复操作。
在确定第二输入输出接口电路进行第二数据读写操作的情况下，需要隔离列选电路的数据恢复操作和第二输入输出接口电路的操作，以免二者互相影响进而影响数据读写的可靠性。因此需要控制列选电路停止数据恢复操作，以对列选电路的数据恢复操作和第二输入输出接口电路的第二数据读写操作进行操作隔离。
图23示出了本公开至少一个实施例提供的另一种存储装置的控制方法的流程示意图。如图23所示，该控制方法可以包括步骤S1100-S1130。
步骤S1100：确定非易失存储操作电路进行数据备份操作。
步骤S1110：连通非易失存储操作电路与NVSRAM阵列的耦接。
步骤S1120：控制列选电路断开SRAM操作电路与NVSRAM阵列的耦接。
步骤S1130：控制第二输入输出接口电路断开与NVSRAM阵列的耦接。
在确定非易失存储操作电路进行数据备份操作的情况下，需要隔离非易失存储操作电路的操作和SRAM操作电路的操作以及第二输入输出接口电路的操作，以免互相影响进而影响数据备份操作的可靠性。因此需要连通非易失存储操作电路与NVSRAM阵列的耦接，控制列选电路断开SRAM操作电路与NVSRAM阵列的耦接，控制第二输入输出接口电路断开与NVSRAM阵列的耦接，以对非易失存储操作电路和SRAM操作电路、第二输入输出接口电路进行操作隔离。
对于步骤S1120，在一个示例中，例如，列选电路根据接收的非易失存储操作电路进行数据备份操作的指令，停止列选电路的操作。又例如，在列选电路还包括开关阵列的情况下，步骤S1120还包括步骤S1121(图中未示出)。
步骤S1121：控制列选电路断开与NVSRAM阵列耦接的开关阵列。隔离非易失存储操作电路的操作和SRAM操作电路的操作的方法可以参考上文的相关描述，此处不再赘述。
对于步骤S1130，在一个示例中，例如，第二输入输出接口电路根据接收的非易失存储操作电路进行数据备份操作的指令，停止第二输入输出接口电路的操作。又例如，在第二输入输出接口电路还包括隔离子电路的情况下，步骤S1130还包括步骤S1131(图中未示出)。
步骤S1131：控制隔离子电路断开第二输入输出接口电路与NVSRAM阵列的耦接。隔离非易失存储操作电路的操作和第二输入输出接口电路的操作的方法可以参考上文的相关描述，此处不再赘述。
在一些实施例中，图23所示的方法还可以包括步骤S1140(图中未示出)。步骤S1140：控制列选电路停止数据恢复操作。
在确定非易失存储操作电路进行数据备份操作的情况下，需要隔离列选电路的数据恢复操作和非易失存储操作电路的操作，以免二者互相影响进而影响数据备份的可靠性。因此需要控制列选电路停止数据恢复操作，以对数据恢复操作和非易失存储操作电路的操作进行操作隔离。例如，在列选电路包括数据恢复操作子电路的情况下，步骤S1140还可以包括控制数据恢复操作子电路停止执行数据恢复操作。
图24示出了本公开至少一个实施例提供的另一种存储装置的控制方法的流程示意图。如图24所示，该控制方法可以包括步骤S1150-S1180。
步骤S1150：确定列选电路进行数据恢复操作。
步骤S1160：断开非易失存储操作电路与NVSRAM阵列的耦接。
步骤S1170：控制列选电路断开SRAM操作电路与NVSRAM阵列的耦接。
步骤S1180：控制第二输入输出接口电路断开与NVSRAM阵列的耦接。
在确定列选电路进行数据恢复操作的情况下，需要隔离非易失存储操作电路的操作、SRAM操作电路的操作、第二输入输出接口电路的操作和列选电路的数据恢复操作，以免互相影响进而影响数据恢复操作的可靠性。因此需要断开非易失存储操作电路与NVSRAM阵列的耦接，控制列选电路断开SRAM操作电路与NVSRAM阵列的耦接，控制第二输入输出接口电路断开与NVSRAM阵列的耦接，以对非易失存储操作电路、SRAM操作电路、第二输入输出接口电路的操作与列选电路的数据恢复操作进行操作隔离。
对于步骤S1170，在一个示例中，例如，在列选电路还包括开关阵列的情况下，步骤S1170还包括步骤S1171(图中未示出)。步骤S1171：控制列选电路断开与NVSRAM阵列耦接的开关阵列。隔离非易失存储操作电路的操作和列选电路的数据恢复操作的方法例如可以参考上文的相关描述，此处不再赘述。
对于步骤S1180，在一个示例中，例如，第二输入输出接口电路根据接收的非易失存储操作电路进行数据备份操作的指令，停止第二输入输出接口电路的操作。又例如，在第二输入输出接口电路还包括隔离子电路的情况下，步骤S1180还包括步骤S1181(图中未示出)。步骤S1181：控制隔离子电路断开第二输入输出接口电路与NVSRAM阵列耦接的开关。隔离列选电路的数据恢复操作和第二输入输出接口电路的操作的方法例如可以参考上文的相关描述，此处不再赘述。
在本公开的一些实施例中，存储装置的控制方法还可以包括步骤S1190-S1192(图中未示出)。
步骤S1190：接收工作模式信号。
步骤S1191：根据工作模式信号产生用于第一数据读写操作、数据备份操作、数据恢复操作、第二数据读写操作或数据纠检错的控制信号。
步骤S1192：将控制信号对应地提供给SRAM操作电路、非易失存储操作电路、第一输入输出接口电路、列选电路、第二输入输出接口电路或纠检错电路。
对于步骤S1190，控制电路接收工作模式信号，该工作模式信号可以用于指示存储装置进行哪些工作模式，例如，工作模式信号可以用于指示存储装置进行数据读写操作、数据备份操作或者数据恢复操作等。
对于步骤S1191，在控制电路接收工作模式信号之后，控制电路可以根据接收的工作模式信号产生对应的控制信号，例如产生用于第一数据读写操作、数据备份操作、数据恢复操作、第二数据读写操作或数据纠检错的控制信号。示例性的，用于第一数据读写操作的控制信号可以包括控制SRAM操作电路进行第一数据读写操作；示例性的，用于第一数据读写操作的控制信号还可以包括控制非易失存储操作电路断开与NVSRAM阵列的耦接。示例性的，数据备份操作的控制信号可以包括控制非易失存储操作电路进行数据备份操作；示例性的，数据备份操作的控制信号还可以包括控制SRAM操作电路和第二输入输出接口电路断开与NVSRAM阵列的耦接；示例性的，用于数据恢复操作的控制信号还可以包括控制纠检错电路进行数据纠检错操作；示例性的，用于数据恢复操作的控制信号，可以用于包括控制列选电路执行数据恢复操作，控制非易失存储操作电路断开与NVSRAM阵列的耦接，控制第二输入输出接口电路断开与NVSRAM阵列的耦接，控制列选电路断开SRAM操作电路与NVSRAM阵列的耦接。
对于步骤S1192，控制电路将生成的控制信号对应提供给相应的操作电路。示例性的，控制电路可以将用于第一数据读写操作或数据恢复操作的控制信号对应提供给SRAM操作电路；示例性的，控制电路还可以将用于第一数据读写操作或者数据恢复操作的控制信号提供给非易失存储操作电路。示例性的，控制电路可以将用于数据备份操作的控制信号对应提供给非易失存储操作电路；示例性的，控制电路还可以将用于数据备份操作的控制信号提供给SRAM操作电路和第二输入输出接口电路。示例性的，控制电路可以将用于第二数据读写操作的控制信号对应提供给第二输入输出接口电路；示例性的，控制电路还可以将用于第二数据读写操作的控制信号提供给非易失存储操作电路。示例性的，控制电路可以将用于数据备份操作的控制信号提供给纠检错电路。示例性的，控制电路还可以将用于数据恢复操作的控制信号提供给纠检错电路。示例性的，控制电路还可以将用于数据恢复操作的控制信号提供给列选电路。
在本公开的至少一个实施例中，控制电路根据接收的工作模式信号产生相应的控制信号，并将各控制信号对应提供给相应的操作电路，从而可以提高数据读写、备份、恢复等操作的可靠性和效率。
图25示出了本公开至少一个实施例提供的一种存储装置数据备份方法的流程示意图。
如图25所示，该数据备份方法包括步骤S1200-S1291。该数据备份方法例如可以用于如图12或图13所示的存储装置。
步骤S1200：进行数据读写。
对于步骤S1200，可以是SRAM操作电路执行第一数据读写操作或者第二输入输出接口电路执行第二数据读写操作。例如，SRAM操作电路将从第一输入输出接口电路接收的第一输入数据写入NVSRAM阵列中，或者，SRAM操作电路将从NVSRAM阵列中读取的第一输出数据提供给第一输入输出接口电路，将第一输出数据从第一输入输出接口电路输出存储装置。例如，还可以是第二输入输出接口电路将接收的第二输入数据写入到NVSRAM阵列中，或者，第二输入输出接口电路将从NVSRAM阵列中读取的第二输出数据输出存储装置。
步骤S1210：判断是否需要进行数据备份操作。
对于步骤S1210，在本公开的一些实施例中，存储装置会根据接收的指令确定是否需要进行数据备份操作。如果需要进行数据备份操作，则会进行步骤S1220；否则，继续进行步骤S1200，继续将数据写入NVSRAM单元中的SRAM存储子单元。
步骤S1220：读取第i行数据K位信息码。
对于步骤S1220，SRAM操作电路通过列选电路，读取NVSRAM阵列中的SRAM存储子单元的第i行数据，该数据包括K位信息码，并将该数据输入纠检错电路中。i、K为整数且0＜i，N≥K≥1。
步骤S1230：对第i行的K位信息码数据编码得到R位校验码。
对于步骤S1230，纠检错电路对接收的第i行数据的K位信息码进行编码，得到R位校验码。
步骤S1240：写入第i行R位校验码。
对于步骤S1240，例如，纠检错电路将R位校验码通过SRAM操作电路写入NVSRAM阵列的SRAM存储子单元的第i行数据中，以用于进行后续的数据备份操作。例如，在一些实施例中，步骤S1230-S1240可以对应于图19所示的步骤S910-S911。纠检错电路对数据编码的方法可以参考上文的相关描述，此处不再赘述。之后则进行步骤S1250。
步骤S1250：判断是否编码完成。
对于步骤S1250，判断NVSRAM阵列中的待备份数据是否都完成编码，若未完成，则进行步骤S1291。若完成，则进行步骤S1260。
步骤S1291：行地址增加1。
对于步骤S1291，在数据编码操作未完成的情况下，更新SRAM存储子单元中需要进行编码的数据的行地址，将行地址再增加1行，之后将继续进行步骤S1220-S1250的数据编码操作，直到所有需要编码的数据都编码完成并写入到SRAM存储子单元中。
步骤S1260：选中J行NVSRAM单元。
对于步骤S1260，在纠检错电路对数据编码完成后，则进行数据备份操作。例如，字线驱动电路根据地址信息确定NVSRAM单元中的J行数据。J为整数且0＜J。示例性的，选中第1行至第J行NVSRAM单元。
步骤S1270：对J行存储单元中的SRAM存储子单元中所有数据(包括数据位和校验位)同时进行数据备份。
对于步骤S1270，非易失存储操作电路进行并行操作，对SRAM存储子单元中的J行的所有存储子单元中的包括K位信息码和R位校验码的数据同时进行数据备份操作，将该数据备份至RRAM存储子单元中。
步骤S1280：判断是否数据备份完毕。
对于步骤S1280，非易失存储操作电路确定数据备份是否完成。如果备份未完成，则进行步骤S1290；若确定数据备份已完成，则将结束数据备份操作。
步骤S1290：行地址增加J。
对于步骤S1290，字线驱动电路更新SRAM存储子单元的行地址，将行地址再增加J，以便继续进行下一步的数据备份操作。示例性的，非易失存储操作电路将确定的SRAM存储子单元中的第(J+1)行至第2J行数据备份到RRAM存储子单元中。之后继续进行步骤S1260-S1280的数据备份操作，直到所有需要备份的数据都被备份到RRAM存储子单元中。
图26示出了本公开至少一个实施例提供的一种存储装置数据恢复方法的流程示意图。
如图26所示，该数据恢复方法包括步骤S1300-S1393。该数据恢复方法例如可以用于如图12或图13所示的存储装置。
步骤S1300：是否数据恢复。
对于步骤S1300，确定存储装置是否进行数据恢复操作。可以根据实际需要确定存储装置是否进行数据恢复，或者接收到进行数据恢复的指令，以确定进行数据恢复操作。如果确定需要进行数据恢复操作，则会进行步骤S1310；如果确定不进行数据恢复操作，则直接进行步骤S1391。
步骤S1310：选中I行NVSRAM单元。
对于步骤S1310，字线驱动电路根据地址信息确定NVSRAM单元中的I行数据。I为整数且0＜I。示例性的，选中第1行至第I行NVSRAM单元。
步骤S1320：对I行所有存储单元同时进行数据恢复。
对于步骤S1320，该步骤例如可以由列选电路执行。例如，列选电路进行并行操作，将确定的RRAM存储子单元中的I行数据同时恢复到SRAM存储子单元中。之后进行步骤S1330。
步骤S1330：是否数据恢复完毕。
对于步骤S1330，判断数据恢复操作是否完成，若完成则进行步骤S1340，若未完成，则进行步骤S1393。
步骤S1393：行地址增加I。
对于步骤S1393，在数据恢复操作未完成的情况下，将RRAM存储子单元中需要恢复的数据的行地址再增加I，示例性的，字线驱动电路可以根据地址信息确定RRAM存储子单元中的第(I+1)行至第2I行的数据。之后继续进行步骤S1310-S1330，直至所有待恢复的数据都恢复完成。
步骤S1340：读取第j行的包括K位信息码和R位校验码的数据。
对于步骤S1340，当数据恢复操作完成后，SRAM操作电路会读取SRAM存储子单元中的第j行中包括K位信息码和R位校验码的数据，并将读取出来的数据输入到纠检错电路中，以供后续处理和使用。j为整数且0＜j。
步骤S1350：对读取的第j行的包括K位信息码和R位校验码的数据进行解码检错。
对于步骤S1350，纠检错电路会对从SRAM操作电路输入的第j行的包括K位信息码和R位校验码的数据进行解码并检错。在一些实施例中，解码的过程可以是编码过程的逆操作，根据特定的解码算法将R位校验码数据从数据中分离出来，并根据校验码对K位信息码数据进行校验。纠检错电路对数据的解码方法可以参考上文的相关描述，此处不再赘述。
步骤S1360：判断是否有错。
对于步骤S1360，纠检错电路会对解码结果进行判断，确定数据是否存在错误。如果解码结果有错误，则需要进行错误纠正操作，进行步骤S1370；如果解码结果没有错误，则进行步骤S1390。
步骤S1370：对第j行数据进行纠错得到K位纠错后的信息码。
对于步骤S1370，如果纠检错电路判断解码结果存在错误，则对数据进行纠错编码。纠检错电路对第j行的数据进行纠错，得到K位纠错后的信息码。纠检错电路对数据的纠错编码方法可以参考上文的相关描述，此处不再赘述。
步骤S1380：第j行写入K位纠错后的信息码。
对于步骤S1380，纠检错电路将纠错后的K位信息码数据通过SRAM操作电路写入到NVSRAM阵列的SRAM存储子单元中，以替换原错误的数据。
步骤S1390：判断是否纠错完毕。
对于步骤S1390，判断纠检错电路是否完成纠检错操作，若已完成则进行步骤S1391，若未完成，则进行步骤S1392。
步骤S1391：数据读写。
对于步骤S1391，在纠检错电路完成纠检错操作后，例如，可以由SRAM操作电路通过列选电路进行第一数据读写操作，读取NVSRAM阵列中纠检错完成后的数据，并将该数据输入到第一输入输出接口电路以供后续处理使用。例如，还可以由第二输入输出接口电路进行第二数据读写操作，读取NVSRAM阵列中纠检错完成后的数据。
步骤S1392：行地址增加1。
对于步骤S1392，在纠错操作未完成的情况下，更新SRAM存储子单元中需要进行纠检错操作的数据的行地址，将行地址再增加1，则SRAM操作电路可以读取SRAM存储子单元中的第j+1行中包括K位信息码和R位校验码的数据，并将读取出来的数据输入到纠检错电路中。之后继续进行步骤S1340-S1390，直至所有待纠检错的数据都纠错完成。
本公开的至少一个实施例还提供了一种电子设备，该电子设备包括上述的存储装置。该电子设备可以提高数据读写、备份、存储的可靠性。
图27示出了本公开至少一个实施例提供的一种电子设备的示意框图。如图27所示，该电子设备3000存储装置，该存储装置包括前述任一实施例提供的存储装置1000或存储装置2000。
本公开实施例中的电子设备3000可以包括但不限于诸如移动电话、笔记本电脑、数字广播接收器、PDA(个人数字助理)、PAD(平板电脑)、PMP(便携式多媒体播放器)、车载终端(例如车载导航终端)等等的移动终端以及诸如数字TV、台式计算机等等的固定终端。
本公开上述实施例中的电子设备3000的具体功能和技术效果可以参考上文中关于存储装置1000或存储装置2000的描述，此处不再赘述。
有以下几点需要说明：
(1)本公开实施例附图只涉及到本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (37)

  1. 一种存储装置，包括：NVSRAM阵列、SRAM操作电路、非易失存储操作电路、第一输入输出接口电路、列选电路、第二输入输出接口电路，
    其中，所述列选电路与所述NVSRAM阵列耦接，所述SRAM操作电路与所述列选电路耦接，所述非易失存储操作电路与所述NVSRAM阵列耦接；
    所述NVSRAM阵列包括阵列排列的多个NVSRAM单元，且每个NVSRAM单元包括SRAM存储子单元和非易失存储子单元，所述非易失存储子单元被配置为对所述SRAM存储子单元存储的数据进行数据备份；
    所述非易失存储操作电路被配置为对所述NVSRAM阵列中被选择的NVSRAM单元中的SRAM存储子单元数据进行数据备份操作；
    所述SRAM操作电路被配置为对所述SRAM存储子单元数据进行第一数据读写操作；
    所述列选电路被配置为，对所述非易失存储子单元数据进行数据恢复操作；
    所述列选电路还被配置为，在进行所述数据恢复操作或在所述SRAM操作电路进行所述第一数据读写操作的情况下，选择所述NVSRAM阵列中需要被操作的对象单元列；
    所述第一输入输出接口电路与所述SRAM操作电路耦接，且被配置为将接收的第一输入数据提供给所述SRAM操作电路以及从所述SRAM操作电路接收要输出的第一输出数据；
    所述列选电路还被配置为隔离所述SRAM操作电路的操作和所述非易失存储操作电路的操作，以及隔离所述第一数据读写操作、所述第二数据读写操作和所述数据恢复操作；
    所述第二输入输出接口电路与所述NVSRAM阵列耦接，且被配置为对所述NVSRAM阵列进行第二数据读写操作。
  2. 根据权利要求1所述的存储装置，其中，所述第二输入输出接口电路包括移位寄存操作电路、输入接口电路和输出接口电路，
    所述移位寄存操作电路与所述NVSRAM阵列耦接，且被配置为对所述NVSRAM阵列进行所述第二数据读写操作；
    所述输入接口电路与所述移位寄存操作电路耦接，且被配置为接收第二输入数据且将接收的所述第二输入数据提供给所述移位寄存操作电路；
    所述输出接口电路与所述移位寄存操作电路耦接，且被配置为从所述移位寄存操作电路接收要输出的第二输出数据。
  3. 根据权利要求1所述的存储装置，还包括：字线驱动电路，
    所述字线驱动电路被配置为，在所述SRAM操作电路进行所述第一数据读写操作的情况下，或者在所述列选电路进行所述数据恢复操作的情况下，或者在所述第二输入输出接口电路进行所述第二数据读写操作的情况下，或者在所述非易失存储操作电路进行所述数据备份操作的情况下，选择所述NVSRAM阵列中需要被操作的对象单元行。
  4. 根据权利要求2所述的存储装置，其中，所述第二输出接口电路还包括隔离子电路，其中，所述隔离子电路耦接在所述NVSRAM阵列和所述移位寄存操作电路之间；
    所述隔离子电路被配置为，在所述移位寄存操作电路进行所述第二数据读写操作的情况下，导通所述移位寄存操作电路与所述NVSRAM阵列的耦接。
  5. 根据权利要求4所述的存储装置，其中，
    所述隔离子电路还被配置为，在所述非易失存储操作电路进行所述数据备份操作的情况下，或者在所述列选电路进行所述数据恢复操作的情况下，或者在所述SRAM操作电路进行所述第一数据读写操作的情况下，断开所述移位寄存操作电路与所述NVSRAM阵列的耦接。
  6. 根据权利要求2所述的存储装置，其中，所述移位寄存操作电路通过N组传输线与所述NVSRAM阵列耦接；
    所述输入接口电路通过W2条传输线与所述移位寄存操作电路耦接；
    所述输出接口电路通过W2条传输线与所述移位寄存操作电路耦接，其中，W2和N为整数且N≥W2>1。
  7. 根据权利要求1所述的存储装置，其中，所述非易失存储操作电路还被配置为，在所述SRAM操作电路进行所述第一数据读写操作的情况下，或者在所述列选电路进行所述数据恢复操作的情况下，或者在所述第二输入输出接口电路进行所述第二数据读写操作的情况下，断开与所述NVSRAM阵列的耦接；
    所述列选电路还被配置为，在所述SRAM操作电路进行所述第一数据读写操作的情况下，连通所述SRAM操作电路和所述NVSRAM阵列的耦接；
    所述列选电路还被配置为，在进行所述数据恢复操作的情况下，断开所述SRAM操作电路和所述NVSRAM阵列的耦接；
    所述列选电路还被配置为，在所述第二输入输出接口电路进行所述第二数据读写操作的情况下，断开所述SRAM操作电路和所述NVSRAM阵列的耦接。
  8. 根据权利要求7所述的存储装置，其中，所述非易失存储操作电路还被配置为，在所述非易失存储操作电路进行所述数据备份操作的情况下，连通与所述NVSRAM阵列的耦接；
    所述列选电路还被配置为，在所述非易失存储操作电路进行所述数据备份操作的情况下，断开所述SRAM操作电路和所述NVSRAM阵列的耦接；
    所述第二输入输出接口电路还被配置为，断开与所述NVSRAM阵列的耦接。
  9. 根据权利要求1所述的存储装置，其中，所述列选电路还包括数据恢复操作子电路；
    所述数据恢复操作子电路被配置为，对所述对象单元列中的非易失存储子单元数据进行所述数据恢复操作。
  10. 根据权利要求1-9中任一项所述的存储装置，其中，所述NVSRAM阵列的阵列宽度为N；
    所述NVSRAM阵列包括M行所述NVSRAM单元；
    所述非易失存储操作电路通过N组传输线与所述NVSRAM阵列耦接；
    所述SRAM操作电路通过W1组传输线与所述输入输出接口电路耦接；
    所述SRAM操作电路通过W1组传输线与所述列选电路耦接；
    所述列选电路通过N组传输线与所述NVSRAM阵列耦接，其中，W1、N和M为整数且N≥W1>1，M≥1。
  11. 根据权利要求10所述的存储装置，其中，所述字线驱动电路还被配置为，在所述非易失存储操作电路进行所述数据备份操作的情况下，选择所述NVSRAM阵列的I行NVSRAM单元中的SRAM存储子单元数据以进行所述数据备份操作；或，
    在所述列选电路进行所述数据恢复操作的情况下，选择所述NVSRAM阵列的J行NVSRAM单元中的非易失存储子单元数据以进行所述数据恢复操作，其中，I和J为整数，且M≥I≥1，M≥J≥1。
  12. 根据权利要求10所述的存储装置，其中，所述SRAM操作电路还被配置为，在进行所述第一数据读写操作的情况下，对被选择的所述NVSRAM阵列的第i行的W1个NVSRAM单元中的SRAM存储子单元的数据进行所述第一数据读写操作；
    所述第二输入输出接口电路还被配置为，在进行所述第二数据读写操作的情况下，对被选择的所述NVSRAM阵列的第i行的W2个NVSRAM单元中的SRAM存储子单元的数据进行所述第二数据读写操作；
    所述非易失存储操作电路还被配置为，在进行所述数据备份操作的情况下，对被选择的所述NVSRAM阵列的E行和/或F列的NVSRAM单元中的SRAM存储子单元的数据进行所述数据备份操作；
    所述列选电路还被配置为，在进行数据恢复操作的情况下，对被选择的所述NVSRAM阵列的G行和/或H列的NVSRAM单元中的非易失存储子单元的数据进行所述数据恢复操作，其中，i、E、F、G、H、W为整数，且N≥W1≥1，N≥W2≥1，M≥E≥1，M≥G≥1，N≥F≥1，N≥H≥1，M≥i≥1。
  13. 根据权利要求1所述的存储装置，还包括控制电路，其中，
    所述控制电路与所述SRAM操作电路、所述非易失存储操作电路、所述第一输入输出接口电路、所述列选电路和所述第二输入输出接口电路耦接，且被配置为，根据选择的工作模式向所述SRAM操作电路、所述非易失存储操作电路、所述第一输入输出接口电路、所述列选电路和所述第二输入输出接口电路提供对应的控制信号。
  14. 一种用于权利要求1-13中任一项所述的存储装置的控制方法，包括：
    在确定所述SRAM操作电路进行所述第一数据读写操作的情况下，断开所述非易失存储操作电路与所述NVSRAM阵列的耦接，控制所述列选电路连通所述SRAM操作电路与所述NVSRAM阵列的耦接，控制所述第二输入输出电路断开与所述NVSRAM阵列的耦接；或，
    在确定所述第二输入输出接口电路进行所述第二数据读写操作的情况下，断开所述非易失存储操作电路与所述NVSRAM阵列的耦接，连通所述第二输入输出接口电路与所述NVSRAM阵列的耦接，控制所述列选电路断开所述SRAM操作电路与所述NVSRAM阵列的耦接；
    或，在确定所述非易失存储操作电路进行所述数据备份操作的情况下，连通所述非易失存储操作电路与所述NVSRAM阵列的耦接，控制所述列选电路断开所述SRAM操作电路与所述NVSRAM阵列的耦接，控制所述第二输入输出电路断开与所述NVSRAM阵列的耦接；或，
    在确定所述列选电路进行所述数据恢复操作的情况下，断开所述非易失存储操作电路与所述NVSRAM阵列的耦接，控制所述列选电路断开所述SRAM操作电路与所述NVSRAM阵列的耦接，控制所述第二输入输出接口电路断开与NVSRAM阵列的耦接。
  15. 根据权利要求14所述的控制方法，还包括：
    接收工作模式信号；
    根据所述工作模式信号产生用于所述第一数据读写操作、所述数据备份操作、所述数据恢复操作或所述第二数据读写操作的控制信号；
    将所述控制信号对应地提供给所述SRAM操作电路、所述非易失存储操作电路、所述第一输入输出接口电路、所述列选电路或所述第二输入输出接口电路。
  16. 一种存储装置，包括：NVSRAM阵列、SRAM操作电路、非易失存储操作电路、纠检错电路、第一输入输出接口电路、列选电路、第二输入输出接口电路，
    其中，所述纠检错电路与所述SRAM操作电路耦接，所述SRAM操作电路与所述列选电路耦接，所述列选电路与所述NVSRAM阵列耦接，所述非易失存储操作电路与所述NVSRAM阵列耦接；
    所述NVSRAM阵列包括阵列排列的多个NVSRAM单元，且每个NVSRAM单元包括SRAM存储子单元和非易失存储子单元，所述非易失存储子单元被配置为对所述SRAM存储子单元存储的数据进行数据备份；
    所述非易失存储操作电路被配置为对所述NVSRAM阵列中被选择的NVSRAM单元中的SRAM存储子单元数据进行数据备份操作；
    所述SRAM操作电路被配置为对所述SRAM存储子单元数据进行第一数据读写操作；
    所述列选电路被配置为，对所述非易失存储子单元数据进行数据恢复操作；
    所述列选电路还被配置为，在进行所述数据恢复操作或在所述SRAM操作电路进行所述第一数据读写操作的情况下，选择所述NVSRAM阵列中需要被操作的对象单元列；
    所述第一输入输出接口电路与所述SRAM操作电路耦接，且被配置为将接收的第一输入数据提供给所述SRAM操作电路以及从所述SRAM操作电路接收要输出的第一输出数据；
    所述纠检错电路被配置为对目标数据进行编码和解码并判断所述目标数据是否发生错误并纠错；
    所述列选电路还被配置为隔离所述SRAM操作电路的操作和所述非易失存储操作电路的操作，以及隔离所述第一数据读写操作、所述第二数据读写操作和所述数据恢复操作；
    所述第二输入输出接口电路与所述NVSRAM阵列耦接，且被配置为对所述NVSRAM阵列进行第二数据读写操作。
  17. 根据权利要求16所述的存储装置，其中，所述纠检错电路还被配置为：在所述非易失存储操作电路进行所述数据备份操作的情况下，对从所述SRAM操作电路输入所述纠检错电路的目标数据进行编码；以及
    所述纠检错电路还被配置为，在所述列选电路完成所述数据恢复操作的情况下，确定所述SRAM操作电路从所述NVSRAM阵列读取并输入所述纠检错电路的目标数据是否发生错误并纠错。
  18. 根据权利要求17所述的存储装置，其中，所述纠检错电路还被配置为，在进行编码时，对读取的所述目标数据的K位信息码进行编码得到R位校验码，通过所述SRAM操作电路将所述R位校验码写入所述NVSRAM阵列中；以及，
    所述纠检错电路还被配置为，在进行解码时，对读取的所述目标数据的K位信息码和R位校验码进行解码检错，响应于发生错误则进行纠错，将K位纠错后的信息码通过所述SRAM操作电路写入所述NVSRAM阵列中，其中，K和R为正整数。
  19. 根据权利要求16所述的存储装置，其中，所述第二输入输出接口电路包括移位寄存操作电路、输入接口电路和输出接口电路，
    所述移位寄存操作电路与所述NVSRAM阵列耦接，且被配置为对所述NVSRAM阵列进行所述第二数据读写操作；
    所述输入接口电路与所述移位寄存操作电路耦接，且被配置为接收第二输入数据且将接收的所述第二输入数据提供给所述移位寄存操作电路；
    所述输出接口电路与所述移位寄存操作电路耦接，且被配置为从所述移位寄存操作电路接收要输出的第二输出数据。
  20. 根据权利要求16所述的存储装置，还包括：字线驱动电路，
    所述字线驱动电路被配置为，在所述SRAM操作电路进行所述第一数据读写操作的情况下，或者在所述列选电路进行所述数据恢复操作的情况下，或者在所述第二输入输出接口电路进行所述第二数据读写操作的情况下，或者在所述非易失存储操作电路进行所述数据备份操作的情况下，选择所述NVSRAM阵列中需要被操作的对象单元行。
  21. 根据权利要求19所述的存储装置，其中，所述第二输出接口电路还包括隔离子电路，其中，所述隔离子电路耦接在所述NVSRAM阵列和所述移位寄存操作电路之间；
    所述隔离子电路被配置为，在所述移位寄存操作电路进行所述第二数据读写操作的情况下，导通所述移位寄存操作电路与所述NVSRAM阵列的耦接。
  22. 根据权利要求21所述的存储装置，其中，
    所述隔离子电路还被配置为，在所述非易失存储操作电路进行所述数据备份操作的情况下，或者在所述列选电路进行所述数据恢复操作的情况下，或者在所述SRAM操作电路进行所述第一数据读写操作的情况下，断开所述移位寄存操作电路与所述NVSRAM阵列的耦接。
  23. 根据权利要求19所述的存储装置，其中，所述移位寄存操作电路通过N组传输线与所述NVSRAM阵列耦接；
    所述输入接口电路通过W2组传输线与所述移位寄存操作电路耦接；
    所述输出接口电路通过W2组传输线与所述移位寄存操作电路耦接，其中，W2和N为整数且N≥W2>1。
  24. 根据权利要求16所述的存储装置，其中，所述非易失存储操作电路还被配置为，在所述SRAM操作电路进行所述第一数据读写操作的情况下，或者在所述列选电路进行所述数据恢复操作的情况下，或者在所述第二输入输出接口电路进行所述第二数据读写操作的情况下，断开与所述NVSRAM阵列的耦接；
    所述列选电路还被配置为，在所述SRAM操作电路进行所述第一数据读写操作的情况下，连通所述SRAM操作电路和所述NVSRAM阵列的耦接；
    所述列选电路还被配置为，在进行所述数据恢复操作的情况下，断开所述SRAM操作电路和所述NVSRAM阵列的耦接；
    所述列选电路还被配置为，在所述第二输入输出接口电路进行所述第二数据读写操作的情况下，断开所述SRAM操作电路和所述NVSRAM阵列的耦接。
  25. 根据权利要求24所述的存储装置，其中，所述非易失存储操作电路还被配置为，在所述非易失存储操作电路进行所述数据备份操作的情况下，连通与所述NVSRAM阵列的耦接；
    所述列选电路还被配置为，在所述非易失存储操作电路进行所述数据备份操作的情况下，断开所述SRAM操作电路和所述NVSRAM阵列的耦接；
    所述第二输入输出接口电路还被配置为，断开与所述NVSRAM阵列的耦接。
  26. 根据权利要求24所述的存储装置，其中，所述列选电路还包括数据恢复操作子电路；
    所述数据恢复操作子电路被配置为，对所述对象单元列中的非易失存储子单元数据进行所述数据恢复操作。
  27. 根据权利要求16-26中任一所述的存储装置，其中，所述NVSRAM阵列的阵列宽度为N；
    所述NVSRAM阵列包括M行所述NVSRAM单元；
    所述纠检错电路通过传输线与所述SRAM操作电路耦接；
    所述SRAM操作电路通过W1组传输线与所述输入输出接口电路耦接；
    所述SRAM操作电路通过W1组传输线与所述列选电路耦接；
    所述列选电路通过N组传输线与所述NVSRAM阵列耦接；
    所述非易失存储操作电路通过N组传输线与所述NVSRAM阵列耦接，
    其中，W1、N和M为整数且1＜N，1＜M，1＜W1≤N。
  28. 根据权利要求27所述的存储装置，其中，所述字线驱动电路还被配置为，在所述非易失存储操作电路进行所述数据备份操作的情况下，选择所述NVSRAM阵列的I行NVSRAM单元中的SRAM存储子单元数据以进行所述数据备份操作；或，
    在所述列选电路进行所述数据恢复操作的情况下，选择所述NVSRAM阵列的J行NVSRAM单元中的非易失存储子单元数据以进行所述数据恢复操作，其中，I和J为整数，且M≥I≥1，M≥J≥1。
  29. 根据权利要求27所述的存储装置，其中，所述SRAM操作电路还被配置为，在进行所述第一数据读写操作的情况下，对被选择的所述NVSRAM阵列的第i行的W1个NVSRAM单元中的SRAM存储子单元的数据进行所述第一数据读写操作；
    所述第二输入输出接口电路还被配置为，在进行所述第二数据读写操作的情况下，对被选择的所述NVSRAM阵列的第i行的W2个NVSRAM单元中的SRAM存储子单元的数据进行所述第二数据读写操作；
    所述非易失存储操作电路还被配置为，在进行所述数据备份操作的情况下，对被选择的所述NVSRAM阵列的E行和/或F列的NVSRAM单元中的SRAM存储子单元的数据进行所述数据备份操作；
    所述列选电路还被配置为，在进行数据恢复操作的情况下，对被选择的所述NVSRAM阵列的G行和/或H列的NVSRAM单元中的非易失存储子单元的数据进行所述数据恢复操作，其中，i、E、F、G、H、W为整数，且N≥W1≥1，N≥W2≥1，M≥E≥1，M≥G≥1，N≥F≥1，N≥H≥1，M≥i≥1。
  30. 根据权利要求16-29中任一所述的存储装置，还包括控制电路，其中，
    所述控制电路与所述SRAM操作电路、所述非易失存储操作电路、所述纠检错电路、所述第一输入输出接口电路、所述列选电路和所述第二输入输出接口电路耦接且被配置为，根据选择的工作模式向所述SRAM操作电路、所述非易失存储操作电路、所述纠检错电路、所述第一输入输出接口电路、所述列选电路和所述第二输入输出接口电路提供对应的控制信号。
  31. 一种用于权利要求16-30中任一所述的存储装置的控制方法，包括：
    控制所述纠检错电路对所述目标数据进行编码和解码并判断所述目标数据是否发生错误并纠错。
  32. 根据权利要求31所述的控制方法，其中，控制所述纠检错电路对所述目标数据进行编码和解码并判断所述目标数据是否发生错误并纠错，包括：
    在所述非易失存储操作电路进行所述数据备份操作的情况下，对从所述SRAM操作电路输入所述纠检错电路的目标数据进行编码；以及
    在所述列选电路完成所述数据恢复操作的情况下，确定所述SRAM操作电路从所述NVSRAM阵列读取并输入所述纠检错电路的目标数据是否发生错误并纠错。
  33. 根据权利要求32所述的控制方法，其中，在进行编码时，对读取的所述目标数据的K位信息码进行编码得到R位校验码，通过所述SRAM操作电路将所述R位校验码写入所述NVSRAM阵列中；
    在进行解码时，对读取的所述目标数据的K位信息码和R位校验码进行解码检错，响应于发生错误则进行纠错，将K位纠错后的信息码通过所述SRAM操作电路写入所述NVSRAM阵列中，其中，K和R为正整数。
  34. 根据权利要求31或32所述的控制方法，还包括：
    在确定所述SRAM操作电路进行所述第一数据读写操作的情况下，断开所述非易失存储操作电路与所述NVSRAM阵列的耦接，控制所述列选电路连通所述SRAM操作电路与所述NVSRAM阵列的耦接，控制所述第二输入输出电路断开与所述NVSRAM阵列的耦接；或，
    在确定所述第二输入输出接口电路进行所述第二数据读写操作的情况下，断开所述非易失存储操作电路与所述NVSRAM阵列的耦接，连通所述第二输入输出接口电路与所述NVSRAM阵列的耦接，控制所述列选电路断开所述SRAM操作电路与所述NVSRAM阵列的耦接；或，
    在确定所述非易失存储操作电路进行所述数据备份操作的情况下，连通所述非易失存储操作电路与所述NVSRAM阵列的耦接，控制所述列选电路断开所述SRAM与所述NVSRAM阵列的耦接，控制所述移位寄存操作电路断开与所述NVSRAM阵列的耦接；或，
    在确定所述列选电路进行所述数据恢复操作的情况下，断开所述非易失存储操作电路与所述NVSRAM阵列的耦接，控制所述列选电路断开所述SRAM操作电路与所述NVSRAM阵列的耦接，控制所述第二输入输出接口电路断开与NVSRAM阵列的耦接。
  35. 根据权利要求31所述的控制方法，还包括：
    接收工作模式信号；
    根据所述工作模式信号产生用于所述第一数据读写操作、所述数据备份操作、所述数据恢复操作、所述第二数据读写操作或数据纠检错操作的控制信号；
    将所述控制信号对应地提供给所述SRAM操作电路、所述非易失存储操作电路、所述列选电路、所述第二输入输出接口电路、所述纠检错电路或所述第一输入输出接口电路。
  36. 根据权利要求1-13、16-30中任一项所述的存储装置，其中，所述非易失存储子单元包括RRAM、MRAM存储子单元或PRAM存储子单元。
  37. 一种电子设备，包括：权利要求1-13、16-30中任一项所述的存储装置。
PCT/CN2025/090092 2024-04-19 2025-04-21 存储装置、电子设备和存储装置的控制方法 Pending WO2025218809A1 (zh)

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