WO2025212975A1 - Software defined radio architecture - Google Patents

Abstract

A radio architecture may include antenna elements each configured to receive horizontally polarized component signal and a vertically polarized component signal, and receive a radio frequency beam. The radio architecture may include polarizer circuits that receive one of the horizontally polarized component signals and one of the vertically polarized component signals and output a right handed circular polarization (RHCP) component signal and a left handed circular polarization (LHCP) component signal. The radio architecture may include amplifiers that amplify the RHCP component signals or the LHCP component signals. The radio architecture may include analog-to- digital converters (ADCs) that convert the RHCP component signals or the LHCP component signals into digital signals. The radio architecture may include digital signal processors that process the first digital signals, the second digital signals, or both to obtain a beam signal associated with the radio frequency beam.

Description

SOFTWARE DEFINED RADIO ARCHITECTURE

BACKGROUND

[0001] The following relates generally to communications, including software defined radio architectures.

[0002] Communications devices may communicate with one another using wired connections, wireless (e.g., radio frequency (RF)) connections, or both. Wireless communications between devices, including satellite communications, may employ software defined radio techniques. However, such techniques may be improved.

SUMMARY

[0003] The described techniques relate to improved methods, systems, devices, and apparatuses that support software defined radio architectures.

[0004] An apparatus is described. The apparatus may include a plurality of antenna elements, each of the plurality of antenna elements configured to receive a respective horizontally polarized component signal and a respective vertically polarized component signal, the plurality of antenna elements configured to receive a radio frequency beam. The apparatus may include a plurality of polarizer circuits coupled with the plurality of antenna elements, each of the plurality of polarizer circuits configured to receive one of the respective horizontally polarized component signals and one of the respective vertically polarized component signals and output a right handed circular polarization (RHCP) component signal and a left handed circular polarization (LHCP) component signal. The apparatus may include a plurality of amplifiers coupled with the plurality of polarizer circuits, each of the plurality of amplifiers configured to amplify one of the respective RHCP component signals or one of the respective LHCP component signals. The apparatus may include a plurality of analog-to- digital converters (ADCs) coupled with the plurality of amplifiers, each of the plurality of ADCs configured to convert one of the respective RHCP component signals or one of the respective LHCP component signals into a respective first digital signal or a respective second digital signal. The apparatus may include one or more digital signal processors that process the first digital signals, the second digital signals, or both according to a set of beam weights to obtain a beam signal associated with the radio frequency beam. [0005] In some examples of the apparatus, a first digital signal processor of the one or more digital signal processors processes multiple beams associated with the respective first digital signal or the respective second digital signal.

[0006] In some examples of the apparatus, each of the plurality of ADCs may have a first bit resolution and the one or more digital signal processors combine the first digital signals, the second digital signals, or both, to obtain the beam signal having a second bit resolution that may be greater than the first bit resolution.

[0007] In some examples of the apparatus, the one or more digital signal processors comprise a plurality of digital signal processing (DSP) layers, wherein a first layer of the plurality of digital signal processor (DSP) layers processes the first digital signals having the first bit resolution and output intermediate digital signals having a third bit resolution, and wherein a second layer of the plurality of DSP layers processes the intermediate digital signals and outputs the beam signal having the second bit resolution, and wherein the third bit resolution may be greater than the first bit resolution and less than the second bit resolution.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG. 1 shows an example of a satellite communication system that supports software defined radio architectures in accordance with aspects described herein.

[0009] FIGs. 2A and 2B show examples of resources for a satellite communication system that supports software defined radio architectures in accordance with aspects described herein.

[0010] FIG. 3 shows an example of a radio architecture that supports software defined radio architectures in accordance with aspects described herein.

[0011] FIG. 4 shows an example of a radio architecture that supports software defined radio architectures in accordance with aspects described herein.

[0012] FIG. 5 shows an example of a radio architecture that supports software defined radio architectures in accordance with aspects described herein.

[0013] FIG. 6 shows an example of a system that supports software defined radio architectures in accordance with aspects described herein. DETAILED DESCRIPTION

[0014] Wireless communications may be performed using software defined radio. Software define radio may offer additional flexibility for communications, as many operations or processing may be performed in the digital domain. In some approaches to software defined radio for phased array antennas, it may be desirable to support various polarizations, including vertical and horizontal polarizations, as well as circular polarizations, including right handed circular polarization (RHCP) signals and left handed circular polarization (LHCP) signals. However, in some approaches that attempt to support such polarizations, separate analog to digital converters (ADCs) for both vertical and horizontal polarization signals, and to create the RHCP and LHCP signals, manipulation of the digital signals in the digital domain after the ADCs (e.g., phase shifting, time delay, and other operations) may be expensive in terms of power consumption or processing resources.

[0015] To reduce or eliminate such issues, a radio architecture may include antenna elements that output vertical and horizontal polarization signals to analog polarizer circuits. The polarizer circuits may transform the vertical and horizontal polarization signals to circular polarization signals (e.g., RHCP and LHCP signals) that are then converted to the digital domain by ADCs (e.g., using direct sampling techniques). In some examples, the RHCP and LHCP circuits may be amplified by amplifiers before being digitized by the ADCs. With such a radio architecture, expensive (e.g., in terms of power consumption or processing resources) operations that may be used to generate the circularly polarized signals may be reduced or eliminated, as the circularly polarized signals may be generated in the analog domain before digital conversion. Further, in a multi-beam scenario, if both beams are of the same circular polarization, then some of the ADCs that would otherwise be employed to digitize the circular polarization signals may be deactivated, resulting in additional power and processing savings.

[0016] Aspects of the disclosure are initially described in the context of satellite communication systems. Aspects of the disclosure are then described with reference to a wireless communications system and radio architectures. Aspects of the disclosure are further illustrated by and described with reference to apparatus diagrams, system diagrams, block diagrams, and flowcharts that relate to software defined radio architecture.

[0017] FIG. 1 shows an example of a satellite communication system 100 that supports software defined radio architectures in accordance with aspects described herein. Satellite communication system 100 may include a ground system 135, terminals 120, and satellite system 101. The ground system 135 may include a network of access nodes 140 that are configured to communicate with the satellite system 101 via a feeder link 132. The access nodes 140 may be coupled with access node transceivers 145 that are configured to process signals received from and to be transmitted through corresponding access node(s) 140. The access node transceivers 145 may also be configured to interface with a network 125 (e.g., the Internet) — e.g., via a network device 130 (e.g., a network operations center, satellite and gateway terminal command centers, or other central processing centers or devices) that may provide an interface for communicating with the network 125.

[0018] Terminals 120 may include various devices configured to communicate signals with the satellite system 101. Although terminals 120 are illustrated as being on aircraft, terminals 120 may include fixed terminals (e.g., ground-based stationary terminals), or mobile terminals mounted on mobile platforms (e.g., boats, aircraft, ground-based vehicles, and the like), or a combination of fixed and mobile terminals. A terminal 120 may communicate data and information with an access node 140 via the satellite system 101. The data and information may be communicated with a destination device such as a network device 130, or some other device or distributed server associated with a network 125.

[0019] Terminals 120 may include an antenna assembly which may also include various hardware for mounting an antenna. An antenna assembly may also include circuits and/or processors for converting (e.g., performing frequency conversion, modulating/demodulating, multiplexing/demultiplexing, filtering, forwarding, etc.) between radio frequency (RF) satellite communication signals, and satellite terminal communications signals transmitted between the antenna and a satellite terminal receiver. For mobile terminals, the antenna assembly may be mounted on the outside of the mobile platform (e.g., outside of the fuselage of an aircraft). Additionally, or alternatively, the terminal 120 may include a transceiver, which may be mounted on the inside or outside of the mobile platform and may include circuits and/or processors for performing various RF signal operations (e.g., receiving, performing frequency conversion, modulating/demodulating, multiplexing/demultiplexing, etc.).

[0020] The satellite system 101 may include a single satellite 105, or a network of satellites 105 that are deployed in space orbits (e.g., low earth orbits, medium earth orbits, geosynchronous orbits, geostationary orbits, etc.). One or more satellites 105 included in satellite system 101 may be equipped with multiple antennas (e.g., one or more antenna arrays). In some examples, the one or more satellites 105 equipped with multiple antennas may each include one or more antenna panels that include an array of evenly distributed antennas (which may also be referred to as antenna elements). In some examples, a satellite may be equipped with an antenna array including antennas that are unevenly distributed across a large region. The ground system 135 may also contain access nodes 140 with multiple antenna array elements.

[0021] The satellite system 101 may have a large aperture size, which may be spanned by the antenna arrays or multiple satellites of the satellite system 101. The satellite system 101 may use the one or more satellites to support beamforming techniques within the coverage area 155 of the satellite system to increase a utilization of resources used for communications. Beamforming, including using multiple-input multiple-output (MIMO) techniques, may be used to exploit multipath signal propagation and increase spectral efficiency by transmitting or receiving multiple signals via different spatial layers over the same frequency resources. The multiple signals may, for example, be transmitted by a transmitting device (e.g., a satellite system) via a set of antennas in accordance with a set of weighting coefficients. Likewise, the multiple signals may be received by a receiving device (e.g., a satellite system) via a set of antennas in accordance with a set of weighting coefficients. Each of the multiple signals may be associated with a separate spatial stream and may carry bits associated with the same data stream (e.g., the same codeword) or different data streams (e.g., different codewords).

[0022] In some examples, some or all of the antenna elements on the satellite and/or the ground system may be arranged as an array of constituent receive and/or transmit feed elements that cooperate to enable various examples of on-board beamforming (OBBF), ground-based beamforming (GBBF), end-to-end beamforming, or other types of beamforming. In the GBBF implementation, there may be multiple transmit or receive antennas on the ground system access node(s).

[0023] To determine weighting coefficients to apply to the set of antennas such that N spatial layers are formed, an (M x N) MIMO matrix may be formed, where M may represent the quantity of antennas of the set of antennas. In some examples, M may be equal to N. The MIMO matrix may be determined based on a channel matrix and used to isolate the different spatial layers of the channel. In some examples, the weighting coefficients are selected to emphasize signals transmitted using the different spatial layers while reducing interference of signals transmitted in the other spatial layers. Accordingly, processing signals received at each antenna of the set of antennas (e.g., a signal received at the set of antennas) using the MIMO matrix may result in multiple signals being output, where each of the multiple signals may correspond to one of the spatial layers. In some examples, the weighting coefficients used for MIMO communications may be referred to as beam coefficients or beamforming coefficients, and the multiple spatial layers may be referred to as beams or spot beams.

[0024] The elements of the MIMO matrix used to form the spatial layers of the channel may be determined based on channel sounding probes communicated between a satellite system 101 and one or more devices. Channel sounding probes include reference signals transmitted periodically between a satellite system and a device (e.g., a terminal) coupled with the satellite system. For example, a channel sounding probe may be periodically transmitted from a terminal to the satellite system, or from the satellite system to a terminal, or both, and may include a sequence that is known to the transmitter and receiver (e.g., based on a terminal identifier or other parameters known to the transmitter and receiver). The receiving device (e.g., the terminal or the satellite system) may use the received channel sounding probe to evaluate the connection by correlating a received channel sounding probe to the expected signal for the channel sounding probe (e.g., to determine a signal strength, an interference, etc.) and make decisions based thereon. Due to the periodicity of the signal, the receiving device may know when the signal should be received.

[0025] Beamforming techniques may be used to shape or steer a communication beam 150 along a spatial path between a satellite system 101 and a geographic area. A communication beam 150 may be formed by determining weighting coefficients for antenna elements of an antenna array that result in the signals transmitted from or received at the antenna elements being combined such that signals propagating in a particular orientation with respect to an antenna array experience constructive interference while others experience destructive interference. Thus, beamforming may be used to transmit signals having energy that is focused in a direction of a communication beam 150 and to receive signals that arrive in a direction of the communication beam 150 with increased signal power (relative to the absence of beamforming). The weighting coefficients may be used to apply amplitude offsets, phase offsets, TTD, or combinations thereof to signals carried via the antennas.

[0026] In some examples, the weighting coefficients applied to the antennas may be used to form multiple communication beams 150, each associated with a different direction, where the multiple communication beams 150 may be used to communicate multiple signals having the same frequency at the same time to different user terminals. This may be referred to as multi-beam processing, and may support multiuser MIMO. The weighting coefficients used for beamforming may be referred to as beam coefficients, and the multiple signals may be referred to as beam signals. The resulting communication beams 15- may be referred to herein as beamformed spot beams, spot beams, or beams.

[0027] The amplitude and phase of each weighting coefficient may be calculated given the antenna array and reflector geometry and location and the desired beam locations. However, due to inaccuracies (e.g., in the satellite location, array orientation, geometry, atmospheric scintillation effects, etc.), such an approach may not be practical. Instead, the weighting coefficients may be calculated by continuously measuring the MIMO propagation channel characteristics (e.g., pairwise channels from each system antenna element to each terminal antenna element) and adjusting the weighting coefficients based on the changing channel characteristics. The measured MIMO channel characteristics may include pairwise gain and phase response and noise level and may be referred to as MIMO channel state information (CSI). Once the MIMO CSI is available, the weighting coefficients may be derived by solving a set of equations or applying a set of adaptation formulas. Various beamformer calculation and adaptation techniques may be used, including minimum mean square (MMSE) beamformer, zero forcing beamformer, MIMO sphere decoder, and others.

[0028] The beamformed communication beams 150 may be associated with a set of resources of the satellite system 101. The set of resources may include frequency resources, time resources, and polarization resources. Beamformed communication beams 150 may overlap spatially without interfering if they are associated with different resources. For example, a given frequency range for the satellite system 101 may be divided into frequency resources or channels, and a given amount of time may be divided into different recurring time slots, where a frequency resource may be used to carry a beam signal (e.g., a modulated signal carried in a beamformed spot beam) on one of the recurring time slots. By doing this, beamformed communication beams 150 may overlap spatially without interfering if they are associated with different frequency and/or time resources. In addition, multiple polarizations may be used such that two beamformed communication beams 150 may overlap spatially without interfering if they are associated with different polarizations.

[0029] FIG. 2A shows an example of resources 200-a for a satellite communication system that support software defined radio architectures in accordance with aspects described herein. Resources 200-a may correspond to frequency divisions of a satellite communication system. For example, a frequency range 205 (e.g., a frequency band) may be divided up into a set of different frequencies or frequency channels 210 (e.g., frequency channel 210- a, frequency channel 210-b, frequency channel 210-c, frequency channel 210-d) that carry the signals between the satellite communication system and the terminals. The resources 200-a may correspond to the frequency channels 210 of the frequency range 205.

[0030] Each frequency channel 210 may carry signals associated with a single terminal (e.g., at a time). For example, each frequency channel 210 may carry a single modulated signal. Information (e.g., data, control information) may be modulated onto the modulated signal using a variety of single-carrier or multi-carrier modulation techniques (e.g., Orthogonal Frequency Division Multiplexing (OFDM), Direct Sequence Spread Spectrum (DSSS), linearly pre-coded OFDM (LP-OFDM)). A beamformed spot beam may be associated with one or more frequency channels 210.

[0031] In the example of FIG. 2A, the resources 200-a may correspond to the frequency channels 210. That is, each frequency channel 210 may be a separate resource. As such, in this example the number of available resources may correspond to the number of frequency channels, N.

[0032] FIG. 2B shows another example of resources 200-b for a satellite communication system that support software defined radio architectures in accordance with aspects described herein. In this example, frequency channels 210 may again be used to carry the signals associated with the terminals. In addition, the frequency channels 210 may be time multiplexed. That is, each frequency channel 210 may be configured to carry signals to the terminals in time slots that repeat after a period of time. For example, a time period 215 may be divided into a set of sub-periods or time slots t (e.g., time slot ti, time slot t2, time slot ts, time slot t_m) each having a length 225. Each frequency channel 210 may carry a signal to a different terminal during each time slot t, although in some cases multiple time slots within a time period 215 may be allocated to the same terminal. For example, each frequency channel 210 may carry a single modulated signal during each time slot t. Information (e.g., data, control information) may be modulated onto the modulated signal using a variety of singlecarrier or multi-carrier modulation techniques (e.g., OFDM, DSSS, LP-OFDM).

[0033] At the completion of the time period 215, the process may repeat such that each frequency channel 210 may carry further signals associated with the different terminals in a resource period. As a result, the frequency channel 210 may be used for communication with the terminal during one time slot t per time period 215. In some examples, a terminal may be assigned to more than one time slot per time period, and thus communication with a terminal may occur over more than one time slot per time period for the frequency channel 210.

[0034] In the example of FIG. 2B, the resources 200-b may correspond to the combination of frequency channels 210-and time slots t in a time period 215. That is, each unique combination of frequency channel 210-and time slot t may be a separate resource 200-b. As such, in this example the number of available resources may correspond to the number of frequency channels times the number of time slots, or N x m. Thus, this example may provide more resources that the example of FIG. 2A.

[0035] In addition to being multiplexed in time or frequency, different polarizations may be used to define the resources for assignment to beamformed spot beams. For example, a set of resources may include a first sub-set of resources associated with a first polarization and a second sub-set of resources associated with a second, orthogonal, polarization. The first and second polarizations may be any orthogonal polarizations, and may be linearly polarized or circularly polarized (e.g., RHCP, LHCP). Thus, a set of resources available for assignment to beamformed spot beams may be defined according to frequency resources (e.g., frequency channels), time resources (e.g., sub-periods of resource periods), or polarization resources.

[0036] In some examples, the types of resources may be combined. For example, in the same system, one or more frequency channels may be divided into time slots and one or more other frequency channels may be used, undivided, as separate resources. Other combinations are also possible.

[0037] FIG. 3 shows an example of a radio architecture 300 that supports software defined radio architectures in accordance with examples as disclosed herein. In some examples, the radio architecture may be employed for receive operations.

[0038] In some examples, architectures for improved software defined radio may involve the use of ADCs at an element level (e.g., one or more ADCs per antenna element, tile 310, or subtile). This may be done to increase the quantity of beams that can be formed and the scan range for each of them. In contrast, a hybrid solution would suffer from reduced scan range due to the higher directivity of the analog tile (e.g., the tile 310) and the presence of grating lobes. The subject matter described herein involves the use of direct sampling to reduce the quantity of components used, which may be particularly helpful in the Ka-band and above, where a geometrical lattice may affect the physical space available for components.

Moreover, each digital signal combination adds 3 dB in SNR, which may be desirable. In contrast, the corresponding analog alternative suffers from gain and phase imbalances at each analog recombination (e.g., in addition to the distributed losses next to the elements which may directly affect the antenna gain and throughput).

[0039] The radio architecture 300 includes multiple tiles 310 of an antenna array (e.g., a phased antenna array). In some examples, each tile 310 may output a horizontally polarized signal and a vertically polarized signal, which may be achieved, at least in part, by coupling to different points on an antenna element to capture the different polarizations. In some examples, each of the horizontally polarized signals and vertically polarized signals may, optionally, be amplified by an amplifier 312 before being passed to the polarizer 314. In some examples, the amplifier 312 may be a low noise amplifier (LNA).

[0040] The polarizer 314 may be an analog polarizer circuit that may transform a horizontally polarized signal and a vertically polarized signal into an RHCP signal and a LHCP signal. Such transformation may be performed in the analog domain, which may reduce the amount of processing performed in the DSP 320 in the processing entity 330, resulting in power and processing consumption. For example, the polarizer 314 may perform one or more transformations, such as Hilbert transformations, in the analog domain to achieve the transformation from a horizontally polarized signal and a vertically polarized signal into an RHCP signal and a LHCP signal.

[0041] The RHCP and LHCP signals may further be amplified by the amplifiers 316, after which the RHCP and LHCP signals may be converted to the digital domain by the ADCs 318. Once digitized, additional digital processing may be performed on the digitized signals. However, since the transformation to RCHP and LCHP was performed by the polarizer 314 in the analog domain, the DSP 320 need not perform such conversion, which may reduce the overall power and resource consumption or free up power and resources to be used for other processing operations.

[0042] In some examples, once processed, the digital signals may be passed to a serializer/deserializer (SERDES), such as the SERDES 328, which may convert signaling between serial and parallel arrangements (e.g., to facilitate further processing or communication of the digital signals).

[0043] In some examples, it may be desirable to provide the ADCs 318 with circularly polarized signals. In a single beam scenario, the signal provided to the ADC 318 will either be RHCP or LHCP, and as such, half of the ADCs 318 (e.g., the half that is configured to digitize the other, “unused” polarization) of a signal path associated with a tile 310 may be deactivated, resulting in power and processing savings. Similarly, in a multi beam scenario, similar power and processing savings may be achieved if the multiple beams are of the same circular polarization, thereby allowing some of the ADCs 318 to be deactivated.

[0044] Some approaches may employ ADCs that are of relatively high bit depths. Such approaches may desire the benefits of higher and higher bit depths to extend the capability to capture the dynamic range of signals. However, the radio architecture 300 may not employ such ADCs and may, in fact, employ ADCs with much lower bit depths than other ADCs. In some examples, such ADCs may only include 1, 2, 3, or 4 bits of range. Such relatively low bit depths may be employed as the radio architecture is, in some respects, designed to capture noise, as the signal to be captured may be lower (e.g., in terms of SNR) than noise present in the signal (e.g., quantization noise). However, in light of further “downstream” processing, (e.g., summing), the noise may be reduced or canceled, and the desired signal may become more apparent. As such, higher bit depths may not be advantageous, and the use of the low bit depth ADCs 318 may result in significant savings in terms of power and resource consumption.

[0045] For example, in some cases, the ADCs 318 may be 1 -bit ADCs, which may be considered to be comparators. In some respects, an ADC may be considered to be a set of comparators that compare the input signal to various levels at the various comparators. In response to the input signal hitting a signal level, a comparator may trigger and register the level of the input signal, which may produce the digitized signal level for that sample.

[0046] The radio architecture 300 may maintain the bias and other parameters of the system to maintain a DC point in the middle of a possible range of a 1 bit ADC or other low bit rate ADCs (of which the ADCs 318 may be examples), the digitized noise signal may be flipping between zeros and ones that represent the noise. Such a signal, if averaged out, may be representative of the signal, even though the received noise may be quite strong, and subsequent stages of processing may be used to reveal the signal that is “buried” within the noise, while still allowing the ADCs 318 to have reduced bit depths, resulting in power and resource savings. Additionally, or alternatively, and in some examples, by reducing the dynamic range of the ADCs 318, the amount of amplification applied to the digital signal may be reduced, which may result in significant power and resource savings, particularly when such savings are achieved relatively early in the signal chain (e.g., closer to the tiles 310).

Such savings may be particularly significant in systems that employ large quantities of ADCs 318. Further, power consumption of the ADCs 318, the DSP 320, or both, may be significantly reduced due to the reduced bit depths of the ADCs 318. For example, the ADCs 318 themselves may consume less power in the analog to digital conversion operations, and the DSP 320 may consume less power as the processing applied by the DSP 320 may be of a reduced bit depth.

[0047] In some examples, the ADCs 318 may be of a given bit rate or resolution, and the DSP 320 may perform one or more operations on the signals digitized by the ADCs 318 that may result in a digital signal that is of a higher bit rate or resolution. Such operations may include a combination operation or other DSP operations involving one or more digital signals. In some examples, the bit rate or resolution of the ADCs 318 may be based on an SNR associated with the signals received at the ADCs 318 (e.g., after being transformed by the polarizer 314 and amplified by the amplifiers 316). For example, the ADCs 318 may be adapted or configured to be of a greater bit depth or resolution based on the SNR being higher, or a lesser bit depth or resolution based on the SNR being lower. In some examples, associations between SNR values and bit depths or resolutions may be established and the bit depth or resolution may be configured or selected based on such associations.

[0048] In some examples, the ADCs 318 may be of various architectures, including a successive approximation register ADC architecture, a delta-sigma ADC architecture, a flash ADC architecture, an integrating ADC architecture, a pipeline ADC architecture, or any combination thereof. In some examples, all of the ADCs 318 may be of the same architecture, and in other examples, different groups or individual ADCs 318 may be of different architectures.

[0049] In some examples, the DSP 320 may include multiple processing layers. A first processing layer may process the signals output from the ADCs 318, and such signals may be of a first bit rate (e.g., sample rate) or resolution. After being processed by the DSP 320, the signals (e.g., which may be referred to as intermediate signals) may be of a higher resolution than the first bit rate or resolution (and optionally, of a different sample rate). A second processing layer may further process the intermediate signals and may output signals that are of a yet higher bit rate or resolution than the intermediate signals (and, optionally, of another different sample rate). Such processing may be carried on for any quantity of DSP layers to increase the bit rate or resolution through multiple layers of processing. In some examples, the DSP 320 may perform one or more operations on input signals, including fractional filtering, complex multi-beam processing, coordinate rotation digital computer (CORDIC) processing, complex multiplication, phase shifting, buffering, true time delay processing, or any combination thereof.

[0050] In some examples, the processing entity 330 may include one or more control elements, such as the control element 322, which may provide an interface for controlling one or more aspects of the processing entity 330.

[0051] For example, the control element 322 may dynamically configure one or more elements of the processing entity 330 to adapt the radio architecture 300 for different scenarios. For example, the use of the radio architecture 300 may involve intentional jamming, in which case additional dynamic range (or adjustment of any other parameters or characteristics described herein) may be desirable and increased power consumption may be acceptable. Once the situation subsides, the control element 322 may reconfigure the processing entity 330 (or one or more elements thereof) to reduce the dynamic range (or adjust any other parameters or characteristics described herein. For example, in the absence of jamming (e.g., where a received signal power is below a threshold), the control element 322 may configure ADCs 318 for a first bit resolution (e.g., 1 -bit, 2-bit, 3-bit, 4-bit), while in the presence of jamming (e.g., where the received signal power satisfies the threshold), the control element 322 may configure ADCs 318 for a second bit resolution (e.g., 2-bit, 3-bit, 4- bit, 8-bit).

[0052] Additionally, or alternatively, the radio architecture 300 may be used in satellite scenarios in which orbits may be crowded. As such, during a pointing phase of communications operations, it may be desirable to have increased dynamic range (or adjustment of any other parameters or characteristics described herein) to combat against the competing signaling from other satellites. After the pointing phase is over (e.g., a link is closed and a modem is connected), the control element 322 may configure the processing entity 330 (or one or more elements thereof) to reduce the dynamic range (or adjust any other parameters or characteristics described herein). In some examples, the control element 322 may be included in or may itself be a radio architecture manager that configures one or more parameters associated with the polarizers 314, the amplifiers 312, the amplifiers 316, the ADCs 318, the DSP 320, or any combination thereof, based on one or more communication characteristics associated with the radio architecture (e.g., SNR, bandwidth, a bit depth of one or more of the ADCs 318, a dynamic range one or more of the ADCs 318, a gain associated the amplifiers 312 and/or the amplifiers 316, a transformation function associated with the polarizers 314, any other communication characteristics described herein, or any combination thereof).

[0053] In some examples, to allow for control of the various elements of the radio architecture 300, such elements may be implemented in one or more programmable logic elements (e.g., field programmable gate arrays (FPGAs) or other programmable logic elements). For example, the ADCs 318 and the DSP 320 (e.g., all or a subset of multiple processing cells, processing layers, or any other processing elements), may be implemented through such programmable logic. Further, the control element 322 may configure the one or more programmable logic elements to configure the ADCs 318 and the DSP 320 in accordance with the techniques described herein.

[0054] In some examples, the processing entity 330 may include the DC supply 324, which may provide DC current to one or more elements of the processing entity 330. In some examples, the DC supply 324 may be scaled down (e.g., configured to provide less energy or power) as the elements of the processing entity 330 may consume less power as a result of the techniques described herein.

[0055] In some examples, the processing entity 330 may include a phase locked loop (PLL) entity, such as the PLL 326, which may support the operations of the DSP 320 or other elements of the processing entity 330.

[0056] FIG. 4 shows an example of a radio architecture 400 that supports software defined radio architectures in accordance with examples as disclosed herein. In some examples, the radio architecture 400 may be employed for transmit operations.

[0057] In some examples, architectures for improved software defined radio may involve the use of DACs at an element level (e.g., one or more DACs per antenna element, tile 410, or subtile). This may be done to increase the quantity of beams that can be formed and the scan range for each of them. In contrast, a hybrid solution would suffer from reduced scan range due to the higher directivity of the analog tile (e.g., the tile 410) and the presence of grating lobes. The subject matter described herein involves the use of direct conversion to reduce the quantity of components used, which may be particularly helpful in the Ka-band and above, where a geometrical lattice may affect the physical space available for components.

Moreover, each digital signal combination adds 3 dB in SNR, which may be desirable. In contrast, the corresponding analog alternative suffers from gain and phase imbalances at each analog recombination (e.g., in addition to the distributed losses next to the elements which may directly affect the antenna gain and throughput).

[0058] The radio architecture 400 includes multiple tiles 410 of an antenna array (e.g., a phased antenna array).

[0059] In some examples, digital signals may be received by a serializer/deserializer (SERDES), such as the SERDES 428, which may convert signaling between serial and parallel arrangements (e.g., to facilitate further processing or communication of the digital signals).

[0060] In some examples, the RHCP and LHCP signals may be converted to analog signals by the DACs 418, after which the RHCP and LHCP signals may be amplified by the amplifiers 416 and passed to the polarizer 414. The polarizer 414 may be an analog polarizer circuit that may transform an RHCP signal and an LHCP signal into a horizontally polarized signal and a vertically polarized signal for transmission by the tile 410. Such transformation may be performed in the analog domain, which may reduce the amount of processing performed in the DSP 420 in the processing entity 430, resulting in power and processing consumption. For example, the polarizer 414 may perform one or more transformations, such as Hilbert transformations, in the analog domain to achieve the transformation from an RHCP signal and an LHCP signal into a horizontally polarized signal and a vertically polarized signal. Since the transformation to vertical and horizontal polarizations was performed by the polarizer 414 in the analog domain (and not performed by the DSP 420), the DSP 420 need not perform such conversion, which may reduce the overall power and resource consumption or free up power and resources to be used for other processing operations.

[0061] In some examples, each tile 410 may receive a horizontally polarized signal and a vertically polarized signal, which may be achieved, at least in part, by coupling to different points on an antenna element to transmit the different polarizations. In some examples, each of the horizontally polarized signals and vertically polarized signals may be amplified by an amplifier 412 before being passed to the tile 410. In some examples, the amplifier 412 may be a power amplifier.

[0062] In some examples, it may be desirable for the DSP 420 to process circularly polarized signals. In a single beam scenario, the signal at the DSP 420 will either be RHCP or LHCP, and as such, half of the DACs 418 (e.g., the half that is configured to digitize the other, “unused” polarization) of a signal path associated with a tile 410 may be deactivated, resulting in power and processing savings. Similarly, in a multi beam scenario, similar power and processing savings may be achieved if the multiple beams are of the same circular polarization, thereby allowing some of the DACs 418 to be deactivated.

[0063] In some examples, the DACs 418 may be of a given bit rate (e.g., sample rate) or resolution, and the DSP 420 may perform one or more operations on the signals before passing the signals to the DACs 418 that may result in an output signal that is of lower bit rate (e.g., sample rate) or resolution. In some examples, to support transmission at a lower bit rate (e.g., sample rate) or resolution, the DACs 418 may be linearized (e.g., using digital pre distortion (DPD) or other techniques). Additionally, or alternatively, in some examples, such linearization may be applied to the amplifiers 412. Such operations may include a division operation or other DSP operations involving one or more digital signals. In some examples, the bit rate or resolution of the DACs 418 may be based on a dynamic range associated with the signals processed at the DACs 418 (e.g., before being transformed by the polarizer 414). For example, the DACs 418 may be adapted or configured to be of a greater bit depth or resolution based on the dynamic range being higher, or a lesser bit depth or resolution based on the dynamic range being lower. In some examples, associations between dynamic range and bit depths or resolutions may be established and the bit depth or resolution may be configured or selected based on such associations.

[0064] In some examples, the DACs 418 may be of various architectures, including a string DAC architecture, a delta-sigma DAC architecture, a binary weighted DAC architecture, a ladder DAC architecture, one or more other DAC architecture, or any combination thereof. In some examples, all of the DACs 418 may be of the same architecture, and in other examples, different groups or individual DACs 418 may be of different architectures.

[0065] In some examples, the DSP 420 may include multiple processing layers. A first processing layer may process and provide the signals to the DACs 418, and such signals may be of a first bit rate (e.g., sample rate) or resolution. Signals received at the first layer (e.g., from other layers) (e.g., which may be referred to as intermediate signals) may be of a higher bit rate (e.g., sample rate) or resolution than the first bit rate (e.g., sample rate) or resolution. For example, a second processing layer may produce the intermediate signals based on received signals that are of a yet higher bit rate (e.g., sample rate) or resolution than the intermediate signals, which received signals may he received from yet another layer of the DSP 420. Such processing may be carried on for any quantity of DSP layers to reduce the bit rate or resolution through multiple layers of processing before passing the signals to the DACs 418. In some examples, the DSP 420 may perform one or more operations on input signals, including fractional filtering, complex multi-beam processing, coordinate rotation digital computer (CORDIC) processing, complex multiplication, phase shifting, buffering, true time delay processing, or any combination thereof.

[0066] In some examples, the processing entity 430 may include one or more control elements, such as the control element 422, which may provide an interface for controlling one or more aspects of the processing entity 430.

[0067] For example, the control element 422 may dynamically configure control one or more elements of the processing entity 430 to adapt the radio architecture 400 for different scenarios. For example, the use of the radio architecture 400 may involve intentional jamming, in which case additional dynamic range (or adjustment of any other parameters or characteristics described herein) may be desirable and increased power consumption may be acceptable. Once the situation subsides, the control element 422 may reconfigure the processing entity 430 (or one or more elements thereof) to reduce the dynamic range (or adjust any other parameters or characteristics described herein. Additionally, or alternatively, the radio architecture 400 may be used in satellite scenarios in which orbits may be crowded. As such, during a pointing phase of communications operations, it may be desirable to have increased dynamic range (or adjustment of any other parameters or characteristics described herein) to combat against the competing signaling from other satellites. After the pointing phase is over (e.g., a link is closed and a modem is connected), the control element 422 may configure the processing entity 430 (or one or more elements thereof) to reduce the dynamic range (or adjust any other parameters or characteristics described herein). In some examples, the control element 422 may be included in or may itself be a radio architecture manager that configures one or more parameters associated with the polarizers 414, the amplifiers 412, the amplifiers 416, the DACs 418, the DSP 420, or any combination thereof, based on one or more communication characteristics associated with the radio architecture (e.g., SNR, bandwidth, a bit depth of one or more of the DACs 418, a dynamic range one or more of the DACs 418, a gain associated the amplifiers 412 and/or the amplifiers 416, a transformation function associated with the polarizers 414, any other communication characteristics described herein, or any combination thereof).

[0068] In some examples, to allow for control of the various elements of the radio architecture 400, such elements may be implemented in one or more programmable logic elements (e.g., field programmable gate arrays (FPGAs) or other programmable logic elements). For example, the DACs 418 and the DSP 420 (e.g., all or a subset of multiple processing cells, processing layers, or any other processing elements), may be implemented through such programmable logic. Further, the control element 422 may configure the one or more programmable logic elements to configure the DACs 418 and the DSP 420 in accordance with the techniques described herein.

[0069] In some examples, the processing entity 430 may include the DC supply 424, which may provide DC current to one or more elements of the processing entity 430. In some examples, the DC supply 424 may be scaled down (e.g., configured to provide less energy or power) as the elements of the processing entity 430 may consume less power as a result of the techniques described herein.

[0070] In some examples, the processing entity 430 may include a phase locked loop (PLL) entity, such as the PEL 426, which may support the operations of the DSP 420 or other elements of the processing entity 430.

[0071] FIG. 5 shows an example of a radio architecture 500 that supports software defined radio architectures in accordance with aspects described herein. The radio architecture 500 may include multiple tiles 510, amplifiers 512, polarizers 514, amplifiers 516, ADCs 518, DSP 522, and SERDES 524 that may operate as do similarly named elements discussed herein. One or more such elements may be included in or grouped as a processing element 526. The radio architecture 500 may further include resamplers 520, which may resample the signals output from the ADCs 518 to achieve different characteristics of the signals, including different bit rates or resolutions, to improve subsequent processing by the DSPs 522 and to support multi-beam processing.

[0072] The radio architecture 500 may support the use of multi-beam processing. For example, the RHCP signal may be amplified by the amplifier 516, digitized by the ADC 518, resampled by the resampler 520 to produce multiple beams that may be processed by the DSP 522. In some examples, if multiple beams are of the same polarization (e.g., RHCP), then one or more elements of the signal chains of other polarizations (e.g., LHCP) may be deactivated. For example, since beam 1 and beam 2 are associated with the RHCP signal then (assuming that beam 3 does not exist for this example), the amplifier 516, the ADC 518, the resampler 520, and the DSP 522 may be deactivated, placed in a low power state, or reconfigured for other operations, which may result in significant power savings. [0073] In some examples, the radio architecture 500 may perform phase shifting on input signals and may replicate this phase shifting for each beam (e.g., N iterations, which may be the quantity of beams), and then perform DSP processing (e.g., true time delay processing or other processing, such as to support beamforming operations). Such an arrangement may provide significant power savings, as a reduced amount of hardware (e.g., a single FPGA) may implement a reconfigurable multi beamformer.

[0074] Such reconfigurable hardware may be tuned significantly. For example, in a case in which the radio architecture 500 is implemented in a satellite in space in a multi beam scenario. The satellite may be employed in a low earth orbit constellation. At times the satellite may not be located over an area with large amounts of land, so the radio architecture 500 may be configured to save power and not perform many operations. However, some land areas may be within the coverage area of the satellite, and the radio architecture 500 may adapt some elements (e.g., the ADCs 518 or the DSP 522) to provide high quality service (including multi beam operation) for those areas, while reducing or deactivating service for other areas. In this way, the configurability of the techniques and architectures described herein allow for significant power savings, as the elements may be configured for some situations to support complex operations and may further be configured for power savings in other situations.

[0075] FIG. 6 shows an example of system 600 including a device 605 that supports software defined radio architectures in accordance with examples as disclosed herein. The device 605 may include multiple tiles 610, which may be examples of tiles 310 described herein. The device may include programmable logic 615 (e.g., one or more FPGAs or other programmable logic hardware), which may implement one or more processing cells 620. The programmable logic 615 may be addressable by the processor 640, the radio architecture manager 625, or both, to perform one or more operations described herein. Additionally, or alternatively, the ADCs 618, the processing cells 620, or both, may be implemented using modular hardware, which may allow for individual, subgroup, or group addressing of the processing cells (e.g., by the processor 640, the radio architecture manager 625, or both, to perform one or more operations described herein). In both cases (e.g., processing cells 620 implemented in programmable logic 615 or in modular hardware) or any combination thereof, the processing cells 620 may be organized into one or more DSP layers as described herein to perform operations described herein. It should be noted that additional elements depicted and discussed elsewhere is not included here for clarity, but that implementations of the techniques described herein may include any combination of any elements described herein.

[0076] In some examples, the radio architecture manager 625 may configure the ADCs 618, the processing cells 620, or both, (e.g., as implemented in the programmable logic 615, in modular hardware, other hardware, or any combination thereof) to configure processing operations at the ADCs 618, the processing cells 620, or both. For example, as described herein, one or more processing cells 620 may be organized into a layer 0, one or more processing cells 620 may be organized into a layer 1, one or more processing cells 620 may be organized into a layer 2, and so on, for as many DSP layers as desired, which may be implemented in the DSP 320 or DSP 420. The radio architecture manager 625 may transmit signaling to configure the processing cells 620 to implement processing blocks to perform any of the operations described herein. Similarly, the ADCs 618 may be configured for various tiles 610 to digitize the signals received from the polarizers that transform the vertical and horizontal polarization signals to RHCP and LHCP signals.

[0077] As described herein, various configurations of processing blocks, processing cells 620, DSP layers, ADCs 318, any other elements or entities described herein (including similarly named elements described herein), or any combination thereof, may be configured by the radio architecture manager 625 in accordance with one or more desired arrangements of the device 605 to support the software defined radio architectures described herein.

[0078] Although the radio architecture manager 625 is illustrated as a separate component, in some examples, one or more functions described with reference to the radio architecture manager 625 may be supported by or performed by the at least one processor 640, the at least one memory 630, the code 635, or any combination thereof. For example, the code 635 may include instructions executable by the at least one processor 640 to cause the device 605 to perform various aspects of data burst handling as described herein, or the at least one processor 640 and the at least one memory 630 may be otherwise configured to, individually or collectively, perform or support such operations.

[0079] The at least one memory 630 may include random access memory (RAM) and read-only memory (ROM). The at least one memory 630 may store computer-readable, computer-executable, or processor-executable code, such as the code 635. The code 635 may include instructions that, when executed by the at least one processor 640, cause the device 605 to perform various functions described herein. The code 635 may be stored in a non- transitory computer-readable medium such as system memory or another type of memory. In some cases, the code 635 may not be directly executable by the at least one processor 640 but may cause a computer (e.g., when compiled and executed) to perform functions described herein. In some cases, the at least one memory 630 may include, among other things, a basic I/O system (BIOS) which may control basic hardware or software operation such as the interaction with peripheral components or devices.

[0080] The at least one processor 640 may include one or more intelligent hardware devices (e.g., one or more general-purpose processors, one or more DSPs, one or more CPUs, one or more graphics processing units (GPUs), one or more neural processing units (NPUs) (also referred to as neural network processors or deep learning processors (DLPs)), one or more microcontrollers, one or more ASICs, one or more FPGAs, one or more programmable logic devices, discrete gate or transistor logic, one or more discrete hardware components, or any combination thereof). In some cases, the at least one processor 640 may be configured to operate a memory array using a memory controller. In some other cases, a memory controller may be integrated into the at least one processor 640. The at least one processor 640 may be configured to execute computer-readable instructions stored in a memory (e.g., the at least one memory 630) to cause the device 605 to perform various functions (e.g., functions or tasks supporting data burst handling). For example, the device 605 or a component of the device 605 may include at least one processor 640 and at least one memory 630 coupled with or to the at least one processor 640, the at least one processor 640 and the at least one memory 630 configured to perform various functions described herein.

[0081] In some examples, the at least one processor 640 may include multiple processors and the at least one memory 630 may include multiple memories. One or more of the multiple processors may be coupled with one or more of the multiple memories, which may, individually or collectively, be configured to perform various functions described herein. In some examples, the at least one processor 640 may be a component of a processing system, which may refer to a system (such as a series) of machines, circuitry (including, for example, one or both of processor circuitry (which may include the at least one processor 640) and memory circuitry (which may include the at least one memory 630)), or components, that receives or obtains inputs and processes the inputs to produce, generate, or obtain a set of outputs. The processing system may be configured to perform one or more of the functions described herein. For example, the at least one processor 640 or a processing system including the at least one processor 640 may be configured to, configurable to, or operable to cause the device 605 to perform one or more of the functions described herein. Further, as described herein, being “configured to,” being “configurable to,” and being “operable to” may be used interchangeably and may be associated with a capability, when executing code 635 (e.g., processor-executable code) stored in the at least one memory 630 or otherwise, to perform one or more of the functions described herein.

[0082] It should be noted that these methods describe examples of implementations, and that the operations and the steps may be rearranged or otherwise modified such that other implementations are possible. In some examples, aspects from two or more of the methods may be combined. For example, aspects of each of the methods may include steps or aspects of the other methods, or other steps or techniques described herein.

[0083] Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0084] The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed with a general purpose processor, a DSP, an ASIC, an FPGA, or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0085] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted over as one or more instructions or code on a computer readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions may also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.

[0086] Computer readable media includes both non transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non transitory storage medium may be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non transitory computer readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), flash memory, compact disk read-only memory (CDROM) or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non transitory medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general purpose or special purpose computer, or a genera] purpose or special purpose processor. Also, any connection is properly termed a computer readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer readable media.

[0087] As used herein, including in the claims, “or” as used in a list of items (e.g., a list of items prefaced by a phrase such as “at least one of’ or “one or more of’) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an exemplary step that is described as “based on condition A” may be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be construed in the same manner as the phrase “based at least in part on.”

[0088] In the appended figures, similar components or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If just the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label, or other subsequent reference label.

[0089] The description set forth herein, in connection with the appended drawings, describes example configurations and does not represent all the examples that may be implemented or that are within the scope of the claims. The term “exemplary” used herein means “serving as an example, instance, or illustration,” and not “preferred” or “advantageous over other examples.” The detailed description includes specific details for the purpose of providing an understanding of the described techniques. These techniques, however, may be practiced without these specific details. In some instances, well known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

[0090] The description herein is provided to enable a person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not limited to the examples and designs described herein but is to be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

CLAIMS What is claimed is:

1. A radio architecture, comprising: a plurality of antenna elements, each of the plurality of antenna elements configured to receive a respective horizontally polarized component signal and a respective vertically polarized component signal, the plurality of antenna elements configured to receive a radio frequency beam; a plurality of polarizer circuits (314) coupled with the plurality of antenna elements, each of the plurality of polarizer circuits (314) configured to receive one of the respective horizontally polarized component signals and one of the respective vertically polarized component signals and output a right handed circular polarization (RHCP) component signal and a left handed circular polarization (LHCP) component signal; a plurality of amplifiers (316) coupled with the plurality of polarizer circuits (314), each of the plurality of amplifiers (316) configured to amplify one of the respective RHCP component signals or one of the respective LHCP component signals; a plurality of analog-to-digital converters (ADCs) (318) coupled with the plurality of amplifiers (316), each of the plurality of ADCs (318) configured to convert one of the respective RHCP component signals or one of the respective LHCP component signals, into a respective first digital signal or a respective second digital signal; and one or more digital signal processors (320) that process the first digital signals, the second digital signals, or both according to a set of beam weights to obtain a beam signal associated with the radio frequency beam.

2. The radio architecture of claim 1, wherein: a first digital signal processor (320) of the one or more digital signal processors processes multiple beams associated with the respective first digital signal or the respective second digital signal.

3. The radio architecture of any one of claim 1 or claim 2, wherein: each of the plurality of ADCs (318) have a first bit resolution; and the one or more digital signal processors (320) combine the first digital signals, the second digital signals, or both, to obtain the beam signal having a second bit resolution that is greater than the first bit resolution.

4. The radio architecture of claim 3, wherein: the one or more digital signal processors (32) comprise a plurality of digital signal processing (DSP) layers, wherein a first layer of the plurality of DSP layers processes the first digital signals having the first bit resolution and output intermediate digital signals having a third bit resolution, and wherein a second layer of the plurality of DSP layers processes the intermediate digital signals and outputs the beam signal having the second bit resolution, and wherein the third bit resolution is greater than the first bit resolution and less than the second bit resolution.

5. The radio architecture of any one of claims 1 through 4, wherein: a bit depth of one or more ADCs (318) of the plurality of ADCs (318) is based at least in part on a signal to noise ratio associated with respective component signals output by the plurality of antenna elements.

6. The radio architecture of any one of claims 1 through 5, wherein: the one or more digital signal processors (318) are configured for fractional filtering, complex multi-beam processing, coordinate rotation digital computer (CORDIC) processing, complex multiplication, phase shifting, amplification, buffering, true time delay processing, or any combination thereof.

7. The radio architecture of any one of claims 1 through 6, wherein: the plurality of ADCs (318) comprise a successive approximation register ADC architecture, a delta-sigma ADC architecture, a flash ADC architecture, an integrating ADC architecture, a pipeline ADC architecture, a time-interleaved ADC architecture, or any combination thereof.

8. The radio architecture of any one of claims 1 through 7, wherein: the plurality of polarizer circuits (314) perform Hilbert transformations in an analog domain.

9. The radio architecture of any one of claims 1 through 8, further comprising: a radio architecture manager (625) that configures one or more parameters associated with the plurality of polarizer circuits (314), the plurality of amplifiers (316), the plurality of ADCs (318), the one or more digital signal processors (320), or any combination thereof, based at least in part on one or more communication characteristics associated with the radio architecture.

10. The radio architecture of claim 9, wherein: the one or more parameters comprise a bit depth associated with the plurality of ADCs (318), a dynamic range associated with the plurality of ADCs (318), a gain associated with the plurality of amplifiers (316), a transformation function associated with the plurality of polarizer circuits (314), or any combination thereof.

11. The radio architecture of any one of claims 1 through 10, further comprising: one or more programmable logic elements that implement the plurality of ADCs (318), the one or more digital signal processors (320), or both; wherein configuration of the plurality of ADCs (318), the one or more digital signal processors (320), or both, is performed through configuration of the one or more programmable logic elements.