WO2025201057A1 - 一种脉冲电压产生电路及半导体工艺设备 - Google Patents

一种脉冲电压产生电路及半导体工艺设备

Info

Publication number
WO2025201057A1
WO2025201057A1 PCT/CN2025/082073 CN2025082073W WO2025201057A1 WO 2025201057 A1 WO2025201057 A1 WO 2025201057A1 CN 2025082073 W CN2025082073 W CN 2025082073W WO 2025201057 A1 WO2025201057 A1 WO 2025201057A1
Authority
WO
WIPO (PCT)
Prior art keywords
pulse voltage
circuit
energy storage
voltage
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2025/082073
Other languages
English (en)
French (fr)
Inventor
李东彧
韦刚
王景远
王蕾越
葛军
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Beijing Naura Microelectronics Equipment Co Ltd
Original Assignee
Beijing Naura Microelectronics Equipment Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Beijing Naura Microelectronics Equipment Co Ltd filed Critical Beijing Naura Microelectronics Equipment Co Ltd
Publication of WO2025201057A1 publication Critical patent/WO2025201057A1/zh
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/53—Generators characterised by the type of circuit or by the means used for producing pulses by the use of an energy-accumulating element discharged through the load by a switching device controlled by an external signal and not incorporating positive feedback
    • H03K3/57—Generators characterised by the type of circuit or by the means used for producing pulses by the use of an energy-accumulating element discharged through the load by a switching device controlled by an external signal and not incorporating positive feedback the switching device being a semiconductor device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/04—Modifications for accelerating switching
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/53—Generators characterised by the type of circuit or by the means used for producing pulses by the use of an energy-accumulating element discharged through the load by a switching device controlled by an external signal and not incorporating positive feedback
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof

Definitions

  • the present application relates to the field of semiconductor manufacturing technology, and in particular to a pulse voltage generating circuit and semiconductor process equipment.
  • Low-pressure, low-temperature, weakly ionized glow discharge plasmas are widely used in integrated circuit manufacturing, particularly in processes such as plasma etching and plasma-enhanced chemical vapor deposition.
  • processes such as plasma etching and plasma-enhanced chemical vapor deposition.
  • IEDF unimodal ion energy distribution
  • FIG1 shows a pulse voltage generating circuit in the prior art.
  • the circuit uses a switch tube T1 and a switch tube T2 to form a half-bridge circuit. By alternately turning on the two switch tubes and processing them through the subsequent circuit, an operating pulse voltage for controlling ion distribution can be output.
  • the present application is committed to providing a pulse voltage generating circuit and semiconductor process equipment, which, on the basis of meeting the switching loss requirements and high voltage output, increases the pulse frequency of the operating pulse voltage, improves the single-peak IEDF control effect, and meets actual process requirements.
  • the present application provides a pulse voltage generating circuit for semiconductor process equipment, the circuit comprising: a tank circuit and a switch unit, the switch unit comprising a plurality of first controllable switches, wherein:
  • the input end of the energy storage circuit is used to be connected to a DC power supply, the output end of the energy storage circuit is respectively connected to the input end of each first controllable switch, and the output end of each first controllable switch is used to be grounded;
  • connection point between the energy storage circuit and each of the first controllable switches is used to output an operating pulse voltage
  • each of the first controllable switches is used to be connected to a controller
  • Each of the first controllable switches is used to be turned on in sequence under the control of the controller to output the operating pulse voltage
  • the conduction periods of the first controllable switches do not overlap with each other and the conduction periods of two first controllable switches that are adjacent in conduction sequence are separated by a preset time interval;
  • the energy storage circuit is used to store electrical energy when any of the first controllable switches is turned on, and release the electrical energy within the preset time period.
  • the controller is configured as follows:
  • the pulse voltage generating circuit provided in the first aspect of the present application further includes: an oscillation suppression circuit, wherein:
  • the input end of the oscillation suppression circuit is connected to the energy storage circuit and the connection point of each of the first controllable switches, and the output end of the oscillation suppression circuit is used to output the operating pulse voltage;
  • the oscillation suppression circuit is used to suppress voltage fluctuations of the operating pulse voltage.
  • the parameter acquisition circuit is used to collect the actual operating pulse voltage at a preset sampling point, wherein the preset sampling point includes at least one of the input end of the oscillation suppression circuit, the output end of the oscillation suppression circuit, and a bias electrode, and the bias electrode is located in the wafer carrier of the semiconductor process equipment;
  • the controller is configured to adjust the DC voltage output by the DC power supply and/or the conduction process of each of the first controllable switches according to the actual operating pulse voltage.
  • the pulse voltage generating circuit provided in the first aspect of the present application further includes: a protection circuit, wherein:
  • the first connection end of the protection circuit is used to be connected to the output end of the DC power supply, and the second connection end of the protection circuit is connected to the input end of the energy storage circuit;
  • the controller is connected to the control end of the protection circuit
  • the controller is configured to control the protection circuit to disconnect the DC power supply from the energy storage circuit and release the electric energy stored in the energy storage circuit when the voltage amplitude of the actual operating pulse voltage is greater than a first preset voltage threshold.
  • the protection circuit includes: a second controllable switch, a third controllable switch, and a first resistor, wherein:
  • the input terminal of the second controllable switch serves as the first connection terminal of the protection circuit
  • a connection point between the output terminal of the second controllable switch and the input terminal of the third controllable switch serves as a second connection terminal of the protection circuit
  • the output end of the third controllable switch is connected to one end of the first resistor, and the other end of the first resistor is grounded;
  • control ends of the second controllable switch and the third controllable switch are respectively connected to the controller.
  • the energy storage circuit includes: an energy storage inductor and a voltage stabilizing capacitor, wherein:
  • the first end of the energy storage inductor is connected to the first end of the voltage stabilizing capacitor, and the second end of the energy storage inductor serves as the output end of the energy storage circuit;
  • the second end of the voltage stabilizing capacitor is used for grounding
  • connection point between the energy storage inductor and the voltage stabilizing capacitor serves as the input end of the energy storage circuit.
  • the present application provides a semiconductor process device, comprising: a process chamber, a controller, and a pulse voltage generating circuit as described in any one of the first aspects of the present application, wherein:
  • a wafer carrying device is provided in the process chamber, and a bias electrode is provided in the wafer carrying device;
  • the controller is electrically connected to the control end of each first controllable switch of the pulse voltage generating circuit
  • the output end of the pulse voltage generating circuit is connected to the bias electrode
  • the controller is used to control the pulse voltage generating circuit to output an operating pulse voltage to the bias electrode to control ion energy distribution.
  • the semiconductor process equipment provided in the second aspect of the present application further includes: a radio frequency coil, a matcher, and a radio frequency power supply, wherein:
  • the RF power supply is used to apply RF power to the RF coil through the matching device to excite plasma in the process chamber;
  • the controller is also electrically connected to the RF power supply to control the output power of the RF power supply.
  • the semiconductor process equipment provided in the second aspect of the present application further includes: an ion current detector, wherein:
  • the ion current detector is used to collect the actual ion current bombarding the wafer placed on the wafer carrier, and the actual ion current is used to characterize the actual ion flux;
  • the controller is further configured to adjust the radio frequency power of the radio frequency power supply until a deviation between the actual ion flux and the target ion flux is within a preset flux deviation range.
  • controller is further configured to perform the following steps:
  • the DC voltage output by the DC power supply connected to the pulse voltage generating circuit and/or the conduction process of each first controllable switch in the pulse voltage generating circuit are adjusted so that the energy distribution of the actual ion energy is a single-peak distribution.
  • the pulse voltage generating circuit includes a protection circuit and an energy storage circuit, and the controller is further configured to perform the following steps:
  • the protection circuit is controlled to connect the DC power supply and the energy storage circuit.
  • the pulse voltage generating circuit includes a tank circuit and a switch unit.
  • the connection point between the tank circuit and each first controllable switch in the switch unit is used to output an operating pulse voltage.
  • the conduction state of each first controllable switch in the switch unit is controlled by a controller. Since the first controllable switches are connected in parallel, the conduction of any first controllable switch causes the output end of the tank circuit to be grounded, thereby storing electrical energy.
  • each first controllable switch is turned off during the preset time, and the tank circuit releases electrical energy.
  • the pulse voltage generating circuit outputs a low level
  • the time corresponding to the aforementioned conduction period is the duration of the low level.
  • the pulse voltage generating circuit outputs a high level
  • the aforementioned preset time is the duration of the high level.
  • Each first controllable switch is turned on in sequence in the above manner to output the operating pulse voltage.
  • the pulse frequency of the operating pulse voltage is the sum of the on-state switching frequencies of each first controllable switch.
  • the pulse frequency of the operating pulse voltage can be effectively increased.
  • the pulse frequency of the operating pulse voltage is constant, the pulse frequency is shared by each first controllable switch, and the on-state switching frequency of each first controllable switch is effectively reduced, thereby effectively reducing switching losses.
  • the energy storage circuit can store electrical energy, when it releases electrical energy within a preset time period, it will be superimposed with the electrical energy output by the DC power supply, thereby effectively increasing the voltage amplitude of the operating pulse voltage. Therefore, this application can increase the pulse frequency of the operating pulse voltage while meeting the switching loss requirements and high voltage output, thereby improving the single-peak IEDF control effect and meeting actual process requirements.
  • FIG1 is a circuit topology diagram of a pulse voltage generating circuit in the prior art.
  • FIG2 is a circuit topology diagram of a pulse voltage generating circuit provided in an embodiment of the present application.
  • FIG3 is a schematic diagram of a control timing sequence corresponding to the pulse voltage generating circuit provided by the embodiment shown in FIG2 .
  • 4a-4c are schematic diagrams showing the simulation control effects of pulse voltage generation by using the pulse voltage generating circuit provided in an embodiment of the present application.
  • 5a-5b are schematic diagrams showing actual control effects of pulse voltage generation by using the pulse voltage generating circuit provided in an embodiment of the present application.
  • FIG6 is a circuit topology diagram of another pulse voltage generating circuit provided in an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a control timing sequence corresponding to the pulse voltage generating circuit provided in the embodiment shown in FIG. 6 .
  • FIG8 is a circuit topology diagram of another pulse voltage generating circuit provided in an embodiment of the present application.
  • FIG9 is a structural block diagram of a pulse voltage generating circuit provided in an embodiment of the present application.
  • FIG10 is a schematic structural diagram of an ion current detector provided in an embodiment of the present application.
  • FIG11 is a flow chart of a pulse voltage generating method provided in an embodiment of the present application.
  • FIG13 is a flow chart of another pulse voltage generating method provided in an embodiment of the present application.
  • FIG14 is a flow chart of another pulse voltage generating method provided in an embodiment of the present application.
  • FIG. 1 shows a pulse voltage generating circuit in the prior art.
  • the circuit uses a switch tube T1 and a switch tube T2 to form a half-bridge circuit.
  • the drain of the switch tube T1 is connected to the DC high voltage Vbus, the source of the switch tube T1 is connected to the drain of the switch tube T2, and the source of the switch tube T2 is grounded.
  • the driving voltage between the gate and source of the two switch tubes is controlled to achieve the switching of the conduction state of the switch tubes. Then, the two switch tubes are alternately turned on and, after being processed by the subsequent circuit, an operating pulse voltage for controlling ion distribution is output.
  • the pulse frequency of the operating pulse voltage output by this circuit is consistent with the pulse frequency of the driving pulse voltage of the switching tube.
  • the voltage amplitude of the operating pulse voltage is the DC voltage amplitude that directly acts on the switching tube. Therefore, the pulse frequency and voltage amplitude of the operating pulse voltage output by this circuit directly affect the loss of the switching tube. That is, the higher the pulse frequency, the greater the loss of the switching tube. At the same time, the higher the voltage amplitude, the greater the loss of the switching tube.
  • the existing technology can only output low-frequency operating pulse voltage.
  • the plasma bombarding the wafer surface i.e., ion current
  • the plasma bombarding the wafer surface will cause a significant increase in the wafer surface potential. This will cause the generated ion energy distribution to be widely broadened, making it difficult to meet the requirements of advanced processes such as high aspect ratio and high selectivity.
  • the present application provides a pulse voltage generating circuit, which increases the pulse frequency of the operating pulse voltage on the basis of meeting the switching loss requirements and high voltage output, thereby improving the single-peak IEDF control effect and meeting actual process requirements.
  • the pulse voltage generating circuit provided in this application is applied to semiconductor process equipment.
  • the semiconductor process equipment may be an ICP (Inductively Coupled Plasma) etcher, a CCP (Capacitively Coupled Plasma) etcher, or a PECVD (Plasma Enhanced Chemical Vapor Deposition) etcher.
  • FIG2 illustrates an application scenario of the pulse voltage generating circuit provided in this application using an ICP etcher as an example.
  • the semiconductor process equipment includes a process chamber 140, a controller 70, an RF power supply 90, an impedance matching circuit 100, and an upper electrode.
  • the upper electrode includes a coupling coil 110.
  • the output end of the RF power supply 90 is connected to the impedance matching circuit 100, which is in turn connected to the coupling coil 110. After the RF power supply 90 is started, it applies RF power to the coupling coil 110 through the impedance matching circuit 100, thereby generating plasma within the process chamber 140.
  • a wafer carrier 130 is disposed within the process chamber 140, positioned opposite the upper electrode.
  • the wafer carrier 130 may include, for example, an electrostatic chuck or a mechanical chuck.
  • a bias electrode 40 is disposed within the wafer carrier 130.
  • the pulse voltage generating circuit provided herein is used to provide a bias voltage to the bias electrode 40 of the wafer carrier 130 within the process chamber 140. As shown in FIG2 , the pulse voltage generating circuit includes a tank circuit 20 and a switch unit 30.
  • the voltage-stabilizing capacitor C1 is generally selected as a ⁇ F capacitor to maintain the stability of the output voltage to the subsequent circuit.
  • the energy storage inductor L1 is generally selected as a ⁇ H inductor to store or release energy.
  • the specific selection of the voltage-stabilizing capacitor C1 and the energy storage inductor L1 needs to be determined in combination with factors such as the specific application scenario of the control circuit and the circuit design parameters. This application does not limit the specific selection of the energy storage inductor L1 and the voltage-stabilizing capacitor C1.
  • the switch unit 30 when all first controllable switches are turned off, the switch unit 30 is turned off.
  • the connection point between the input end of the switch unit 30 and the output end of the energy storage circuit 20 serves as the output end of the pulse voltage generating circuit and is connected to the bias electrode 40 disposed in the process chamber 140.
  • the control end of each first controllable switch in the switch unit 30 is respectively connected to the controller 70, which can control the conduction state of each first controllable switch.
  • the control end of the DC power supply 10 is connected to the controller 70, and the controller 70 is also used to control the DC power supply to output a DC voltage.
  • the controller 70 can control the working state of the DC power supply 10, that is, control the DC power supply 10 to output a DC voltage or stop outputting the DC voltage.
  • the output voltage of the DC power supply 10 is adjustable, and the controller 70 can adjust the amplitude of the DC voltage actually output by the DC power supply 10 according to the actual operating conditions of the circuit and the pulse voltage generation requirements.
  • the output end of the DC power supply 10 is connected to the input end of the energy storage circuit 20, and outputs a DC voltage to the energy storage circuit 20. As for the specific process of the controller 70 controlling the DC power supply 10 to output the DC voltage, it will be expanded in the subsequent content and will not be described in detail here.
  • the pulse voltage generating circuit provided by this embodiment, the sum of the duration corresponding to the conduction period of the first controllable switch and the preset duration is the pulse period of the operating pulse voltage.
  • the pulse frequency of the operating pulse voltage is the sum of the conduction state switching frequencies of each first controllable switch. Therefore, by providing multiple first controllable switches, the pulse frequency of the operating pulse voltage can be effectively increased.
  • the pulse frequency of the operating pulse voltage is constant, the pulse frequency is shared by each first controllable switch, and the conduction state switching frequency of each first controllable switch is effectively reduced, thereby effectively reducing switching losses.
  • an implementation method of a control signal that can meet the above-mentioned control rules for the conduction state of the first controllable switch is provided.
  • the switching of the conduction state of each first controllable switch in the switch unit is driven by a pulse voltage, that is, the first controllable switch is controlled to be turned on by the high level of the pulse voltage, and the first controllable switch is controlled to be turned off by the low level of the pulse voltage.
  • this application defines the pulse voltage used to drive the conduction state of the first controllable switch as a driving pulse voltage.
  • the controller can be configured with drive pulse voltage parameters, such as the pulse period, duty cycle, and voltage amplitude of the drive pulse voltage.
  • the controller can determine the drive pulse voltage to be output based on the preset drive pulse voltage parameters. After receiving the control instruction, the controller can output the drive pulse voltage to each first controllable switch respectively.
  • the voltage amplitude, pulse frequency, duty cycle and other parameters of the operating pulse voltage ultimately output by the pulse voltage generating circuit are all affected by the switching unit. Therefore, when the parameters of the operating pulse voltage are determined, the driving pulse voltage can also be determined in reverse. This is of great significance in practical applications. This content will be expanded in subsequent content and will not be described in detail here.
  • the first controllable switch S1 is turned on and the first controllable switch S2 is turned off.
  • the output end of the DC power supply 10 forms a closed loop through the energy storage inductor L1 and the first controllable switch S1.
  • the DC power supply 10 charges the energy storage inductor L1, and the output voltage (i.e., Vout) of the pulse voltage generating circuit is 0V.
  • both the first controllable switch S1 and the first controllable switch S2 are turned off.
  • the energy storage inductor L1 in the energy storage circuit 20 releases electrical energy, which is superimposed on the electrical energy output by the DC power supply 10, thereby increasing the output voltage amplitude.
  • the output voltage amplitude remains substantially constant during the period when both first controllable switches are turned off.
  • both first controllable switches S1 and S2 are off, and the DC power supply and energy storage inductor L1 continue to provide a high-amplitude DC voltage.
  • first controllable switch S1 turns on, while first controllable switch S2 turns off.
  • both first controllable switches S1 and S2 have completed a drive cycle. By periodically repeating this process, the operating pulse voltage can be output.
  • both the drive pulse voltage of the first controllable switch S1 and the drive pulse voltage of the first controllable switch S2 have a single high-level output, while the operating pulse voltage generates two high-level outputs. Therefore, the pulse frequency of the operating pulse voltage is twice the pulse frequency of the drive pulse voltage of the first controllable switches. That is, the pulse frequency of the operating pulse voltage is the sum of the pulse frequencies of the drive pulse voltages of all first controllable switches.
  • the voltage amplitude of the operating pulse voltage can be controlled by the switching unit.
  • the voltage amplitude of the operating pulse voltage finally output by the pulse voltage generating circuit can be calculated by the following formula compared with the amplification factor of the DC voltage output by the DC power supply:
  • N the voltage amplification factor
  • t c -t d represents a preset duration of an interval between the conduction periods of two first controllable switches that are adjacent in the conduction sequence.
  • Figures 4a-4c are schematic diagrams of the simulation control effect of pulse voltage generation using the pulse voltage generating circuit provided in the embodiment of the present application.
  • Figure 4a is a waveform diagram of the operating pulse voltage finally output by the pulse voltage generating circuit.
  • the pulse frequency of the operating pulse voltage is 10MHz and the duty cycle is 20%
  • the pulse width is 20ns
  • the voltage amplitude of the operating pulse voltage is 5000V. Due to the flat capacitor effect between the bias electrode and the wafer, when the pulse voltage generating circuit outputs a high level, the wafer surface will also couple out the same high level.
  • n 0 represents the plasma density
  • V0 represents the amplitude of the pulse voltage on the wafer surface, which is directly related to the voltage amplitude of the operating pulse voltage output by the pulse voltage generating circuit;
  • T on represents the pulse width of the operating pulse voltage
  • T represents the pulse period of the operating pulse voltage
  • f represents the pulse frequency of the operating pulse voltage.
  • Figures 5a and 5b are schematic diagrams of the actual control effect of pulse voltage generation by applying the pulse voltage generating circuit provided in the embodiment of the present application, wherein Figure 5a shows the voltage waveform induced on the wafer surface when the operating pulse voltage with a pulse frequency of 10MHz is connected to the bias electrode, and the dotted line in the figure shows the average sheath field voltage waveform actually felt by the ions.
  • the switch unit includes four first controllable switches (ie, S1 - S4 ), and the control timing of the circuit can be seen in FIG7 .
  • the first controllable switch S1 is turned on and the other three first controllable switches are turned off.
  • the DC power supply 10 forms a closed loop through the energy storage inductor L1 and the first controllable switch S1.
  • the DC power supply 10 charges the energy storage inductor L1, and the output voltage (i.e., Vout) of the pulse voltage generating circuit is 0V.
  • the four first controllable switches are all turned off, and the DC power supply 10 and the energy storage inductor L1 simultaneously provide power to the bias electrode 40 .
  • the first controllable switch S2 is turned on, and the other three first controllable switches are turned off.
  • the DC power supply 10 forms a closed loop through the energy storage inductor L1 and the first controllable switch S2 .
  • the DC power supply 10 charges the energy storage inductor L1 , and the output voltage of the pulse voltage generating circuit drops to 0 V again.
  • the four first controllable switches are all turned off, and the DC power supply 10 and the energy storage inductor L1 simultaneously provide power to the bias electrode 40 .
  • the first controllable switch S3 is turned on, and the other three first controllable switches are turned off.
  • the DC power supply 10 forms a closed loop through the energy storage inductor L1 and the first controllable switch S3 .
  • the DC power supply 10 charges the energy storage inductor L1 , and the output voltage of the pulse voltage generating circuit drops to 0 V again.
  • the four first controllable switches are all turned off, and the DC power supply 10 and the energy storage inductor L1 simultaneously provide power to the bias electrode 40 .
  • the first controllable switch S4 is turned on, and the other three first controllable switches are turned off.
  • the DC power supply 10 forms a closed loop through the energy storage inductor L1 and the first controllable switch S4.
  • the DC power supply 10 charges the energy storage inductor L1, and the output voltage of the pulse voltage generating circuit drops to 0V again.
  • the conduction state switching frequency of each first controllable switch can be the same (as shown in the contents shown in Figures 6 and 7) or different (when two first controllable switches are included, the two are alternately turned on, and the conduction state switching frequency must be the same).
  • the conduction state switching frequency of each first controllable switch is the same.
  • the pulse frequency of the driving pulse voltage of the first controllable switch S1 and the first controllable switch S2 can be increased, or the pulse frequency of the driving pulse voltage of the first controllable switch S1 and the first controllable switch S2 can be reduced.
  • the pulse frequency of the operating pulse voltage is still the sum of the pulse frequencies of the driving pulse voltages of each first controllable switch, and the aforementioned voltage amplification factor needs to be calculated in combination with the driving pulse voltages of each first controllable switch, and the sum of the amplification factors corresponding to each first controllable switch is used as the final voltage amplification factor of the switching unit.
  • the pulse voltage generating circuit provided in the embodiment shown in FIG6 further includes an oscillation suppression circuit 50.
  • the oscillation suppression circuit 50 is connected between the switch unit 30 and the bias electrode 40 and is configured to output an operating pulse voltage.
  • the input end of the oscillation suppression circuit 50 is connected to the connection point between the tank circuit 20 and each first controllable switch, and the output end of the oscillation suppression circuit 50 is connected to the bias electrode 40.
  • the oscillation suppression circuit 50 can suppress voltage fluctuations in the operating pulse voltage output to the bias electrode 40.
  • the oscillation suppression circuit 50 includes a diode D2, a second resistor R2 and a third resistor R3, wherein the anode of the diode D2 is connected to the first end of the third resistor R3, and the connection point between the two serves as the input end of the oscillation suppression circuit 50, the cathode of the diode D2 is connected to the first end of the second resistor R2, the second end of the second resistor R2 is connected to the second end of the third resistor R3, and the connection point between the two serves as the output end of the oscillation suppression circuit 50, and is connected to the bias electrode 40.
  • the pulse voltage generating circuit provided in this embodiment is provided with an oscillation suppression circuit, which can relatively separate the current of the plasma load flowing into the process chamber from the current of the plasma load flowing out of the process chamber through the oscillation suppression circuit, thereby suppressing the pulse voltage waveform oscillation caused by the line inductance between the pulse voltage generating circuit and the bias electrode, making the operating pulse voltage output to the bias electrode more stable, and thus making the wafer induced voltage more stable, thereby effectively improving the pulse voltage generation effect.
  • the parameter acquisition circuit is primarily used to collect actual operating pulse voltages at preset sampling points.
  • These preset sampling points include the input and output terminals of the oscillation suppression circuit 50, and at least one of the bias electrodes 40. The functions of each preset sampling point and their connection to the parameter acquisition circuit will be discussed in detail in the subsequent embodiment illustrated in FIG. 9 and will not be described in detail here.
  • the controller is further configured to adjust the output voltage of the DC power supply 10 and/or the conduction state of each first controllable switch based on the actual operating pulse voltage, thereby adjusting the operating pulse voltage ultimately output to the bias electrode 40.
  • the specific adjustment process will be discussed in detail later and will not be described in detail here.
  • the protection circuit 60 is connected between the DC power supply 10 and the energy storage circuit 20.
  • the protection circuit includes a second controllable switch Sp, a third controllable switch Sq, and a first resistor R1.
  • the input end of the second controllable switch Sp serves as the first connection end of the protection circuit 60 and is connected to the output end of the DC power supply 10.
  • the output end of the second controllable switch Sp is connected to the input end of the third controllable switch Sq.
  • the connection point between the two serves as the second connection end of the protection circuit 60 and is connected to the input end of the energy storage circuit 20.
  • the output end of the third controllable switch Sq is connected to one end of the first resistor R1, and the other end of the first resistor R1 is grounded.
  • the control ends of the second controllable switch Sp and the third controllable switch Sq are respectively connected to the controller.
  • the controller is further configured to control the protection circuit 60 to disconnect the DC power supply 10 from the energy storage circuit 20 and release the stored energy in the energy storage circuit 20 when the voltage amplitude of the actual operating pulse voltage acquired by the parameter acquisition circuit exceeds a first preset voltage threshold.
  • the specific implementation of the protection process will be discussed in detail later and will not be discussed in detail here.
  • the present application also provides a semiconductor process equipment.
  • the semiconductor process equipment provided by the present application includes a process chamber 140 , a controller 70 , and a pulse voltage generating circuit provided by any of the aforementioned embodiments.
  • the semiconductor process equipment provided in this embodiment also includes: a radio frequency power supply 90, an impedance matching circuit 100, an ion current detector 120, and an upper electrode arranged opposite to the wafer carrier 130.
  • the semiconductor process equipment provided in this application can be an ICP etcher or a CCP etcher.
  • the upper electrode is a coupling coil 110.
  • the semiconductor process equipment is a CCP etcher
  • the upper electrode is an air intake uniform flow plate. Based on this, in the embodiment shown in Figure 9, the upper electrode is shown as a coupling coil 110.
  • the RF power supply 90 is mainly used to apply RF power to the upper electrode, thereby generating plasma that bombards the wafer.
  • Impedance matching circuit 100 is used for impedance matching of the plasma generation circuit, maximizing the power of RF power source 90 to be applied to coupling coil 110 and process chamber 140.
  • the configuration and matching impedance value of impedance matching circuit 100 need to be determined in conjunction with the actual wiring of process chamber 140, coupling coil 110, and the overall circuit. This application does not limit the specific implementation of impedance matching circuit 100.
  • the coupling coil 110 is used to couple the electrical energy output by the RF power supply 90 to the process chamber 140 via electromagnetic field coupling, thereby generating a stable plasma within the process chamber.
  • the coupling coil 110 is typically positioned opposite the bias electrode 40 in the process chamber 140.
  • the output end of the RF power supply 90 is connected to the impedance matching circuit 100, and the impedance matching circuit 100 is connected to the coupling coil 110. After the RF power supply 90 is started, plasma can be generated inside the process chamber 140 through the impedance matching circuit 100 and the coupling coil 110.
  • a wafer carrier 130 is also provided in the process chamber 140, and the wafer 150 to be processed is carried by the wafer carrier 130.
  • the wafer carrier 130 can choose an electrostatic adsorption chuck with an insulating ceramic layer inside.
  • other implementation methods that can carry the wafer 150 and enable the wafer 150 to generate an induced voltage and thus affect the movement of ions can also be selected, which will not be described in detail here.
  • the bias electrode 40 described in the aforementioned embodiments is arranged inside the wafer carrier 130. After the operating pulse voltage output by the pulse voltage generating circuit is output to the bias electrode 40, the bias electrode 40 and the wafer 150 are between the insulating ceramic layer inside the wafer carrier 130. The bias electrode 40 and the wafer 150 generate a flat capacitor effect. The operating pulse voltage output by the pulse voltage generating circuit will act on the plasma inside the process chamber 140 in a capacitive coupling manner, thereby achieving control of the plasma.
  • the circuit portion of the pulse voltage generating circuit for outputting the operating pulse voltage is arranged directly below the process chamber 140. This effectively shortens the connection line between the pulse voltage generating circuit and the bias electrode 40, thereby greatly reducing the inductance of the connection line, reducing the pulse waveform oscillation caused by the inductance, and helping to improve the control effect of the single-peak IEDF.
  • the parameter acquisition circuit 80 is primarily used to acquire the actual operating pulse voltage at preset sampling points.
  • the preset sampling points are the input of the oscillation suppression circuit 50 (which can also be considered the output of the switch unit 30), the output of the oscillation suppression circuit 50, and the bias electrode 40. It should be noted that in actual applications, one or more of the three preset sampling points may be used. The selection of the preset sampling point depends primarily on factors such as the ease of connecting the parameter acquisition circuit 80 to the preset sampling point, the accuracy of the sampling parameters, and the matching degree between the sampling parameters and the control function. When multiple preset sampling points are used, a controller must be configured to implement a sampling parameter screening mechanism, i.e., how to determine the sampling parameter to be ultimately used from among the multiple sampling parameters.
  • the parameter acquisition circuit 80 includes three acquisition modules, namely, an ion energy acquisition module, a first voltage acquisition module, and a second voltage acquisition module.
  • the ion energy collection module is connected to the back of the wafer 150 through a conductive pin, and collects the operating pulse voltage induced on the surface of the wafer 150 in real time.
  • the operating pulse voltage can usually be characterized by three parameters, namely voltage amplitude, pulse frequency and pulse width.
  • the ion energy collection module includes three main components: voltage amplitude collection module, pulse frequency collection module and pulse width collection module.
  • the voltage amplitude collection module collects the voltage peak value of the operating pulse voltage on the surface of the wafer 150
  • the pulse frequency collection module collects the pulse frequency of the operating pulse voltage on the surface of the wafer 150
  • the pulse width collection module collects the pulse width of the operating pulse voltage on the surface of the wafer 150.
  • the first voltage sampling module is used to collect the operating pulse voltage at the input end of the oscillation suppression circuit 50
  • the second voltage sampling module is used to collect the operating pulse voltage at the output end of the oscillation suppression circuit 50 .
  • Each component module in the parameter acquisition circuit 80 sends the obtained parameter information to the controller 70, and the controller 70 controls the operation process of the pulse voltage generating circuit.
  • the specific control process it will be expanded in the subsequent content and will not be described in detail here.
  • the pulse voltage generating circuit provided in this embodiment further includes an ion current detector 120 , which can collect ion currents that are accelerated by the sheath field inside the process chamber 140 and bombard the surface of the wafer 150 .
  • the ion current detector 120 includes a filter grid 1201, a first grid electrode 1202, a second grid electrode 1203, and a collector 1204.
  • the filter grid 1201 is designed to allow ions and electrons from the plasma within the process chamber 140 to enter the ion current detector 120. In practical applications, the filter grid 1201 needs to be grounded.
  • the first grid electrode 1202 has the same mesh aperture as the filter grid 1201.
  • the ion current detector 120 needs to apply a negative voltage of a certain magnitude to the first grid electrode 1202 to prevent electrons from entering the ion collection space within the ion current detector 120.
  • the collector 1204 is used to attract ions into the collection space and thereby detect the ion current.
  • the second grid electrode 1203 has the same mesh aperture as the filter grid 1201, but the negative voltage applied to it is lower than that of the collector 1204, thereby preventing ions from bombarding the collector 1204 and causing secondary electrons to escape, potentially affecting the measurement results.
  • the collecting portion 1204 is made of graphite material and collects the actual ion current bombarding the wafer.
  • the parameter acquisition circuit 80 also includes an ion flux acquisition module.
  • This module is connected to the bottom of the collecting portion 1204 of the ion current detector 120 via a wire.
  • This module uses a resistor to convert the actual ion current into a voltage signal and collects the signal. This voltage signal is then used to determine the actual ion flux impacting the wafer 150 and is fed back to the controller 70.
  • the controller 70 then adjusts the output power of the RF power supply 90 based on the actual ion flux, ultimately achieving precise control of the ion flux.
  • the pulse voltage generating circuit provided in this embodiment on the basis of outputting the operating pulse voltage to realize precise control of the ion energy, also includes a plasma generating circuit and a plasma detector.
  • the output power of the plasma generator is adjusted based on the actual ion flux fed back by the plasma detector and the parameter acquisition circuit, and the ion flux is adjusted, thereby realizing dual control of the ion energy and ion flux, which can effectively improve the pulse voltage generation effect and thus improve the wafer processing technology level.
  • the controller in the semiconductor process equipment mainly realizes the control of the operation process of the semiconductor process equipment.
  • the controller includes at least one memory and at least one processor, and the processor is configured to execute the pulse voltage generation method provided by any embodiment of Figures 11 to 14.
  • an optional embodiment of the pulse voltage generating method provided in the present application includes the following steps:
  • the control instruction can come from any device or apparatus that can control the operation of the pulse voltage generating circuit.
  • it can be the semiconductor process equipment to which the pulse voltage generating circuit belongs, or other host computers that can communicate with the controller in the pulse voltage generating circuit.
  • the controller in the pulse voltage generating circuit communicates with other modules in the semiconductor process equipment.
  • the control instruction is automatically generated by the controller itself. This application does not limit the specific method for the pulse voltage generating circuit to obtain the control instruction.
  • the controller After receiving the control instruction, the controller controls the DC power supply in the pulse voltage generating circuit to output the DC voltage and controls the switch unit to work, so that the pulse voltage generating circuit outputs the operating pulse voltage.
  • control instruction includes a target voltage value.
  • the controller may control the operation of the DC power supply according to the target voltage value.
  • control instruction may only include the enabling information of the DC power supply, and the controller controls the operation of the DC power supply based on the enabling information according to its own preset initial voltage value or the initial voltage value calculated by other parameters.
  • control instruction may also include target parameters for controlling the operation of the switch unit, such as the voltage amplitude, pulse frequency and duty cycle of the driving pulse voltage.
  • target parameters for controlling the operation of the switch unit, such as the voltage amplitude, pulse frequency and duty cycle of the driving pulse voltage.
  • control instruction may also only include the enabling information of the switch unit, and the controller controls the switch unit to operate according to its own preset control information based on the enabling information.
  • each first controllable switch is turned on sequentially, the conduction periods of each first controllable switch do not overlap, and the conduction periods of two first controllable switches that are adjacent in the conduction sequence are separated by a preset duration.
  • the specific circuit topology of the pulse voltage generating circuit and the specific process of outputting the operating pulse voltage based on this control rule can be referred to the relevant content in the aforementioned embodiment and will not be repeated here.
  • the pulse frequency of the output operating pulse voltage is the sum of the on-state switching frequencies of each first controllable switch. Therefore, by providing multiple first controllable switches, the pulse frequency of the operating pulse voltage can be effectively increased.
  • the pulse frequency of the operating pulse voltage is constant, the pulse frequency is shared by each first controllable switch, effectively reducing the on-state switching frequency of each first controllable switch, thereby effectively reducing switching losses.
  • the energy storage circuit can store electrical energy, when it releases electrical energy within a preset time period, it is superimposed with the electrical energy output by the DC power supply, thereby effectively increasing the voltage amplitude of the operating pulse voltage. Therefore, this application can increase the pulse frequency of the operating pulse voltage while meeting switching loss and voltage amplitude requirements, thereby improving the single-peak IEDF control effect and meeting actual process requirements.
  • the control logic of the ion circuit control method provided in this embodiment is simpler, which can reduce the logic overhead of the controller and the requirements for the controller hardware performance.
  • FIG12 is a flow chart of another pulse voltage generating method provided in an embodiment of the present application. Based on the aforementioned embodiment, the pulse voltage generating method provided in this embodiment includes the following steps.
  • control instruction For the optional implementation of the control instruction and the optional implementation of the controller controlling the DC power supply to output the DC voltage in response to the control instruction, reference may be made to the relevant contents in the aforementioned embodiments and will not be repeated here.
  • a driving pulse voltage is used to control the conduction state of each first controllable switch in the switch unit.
  • Each first controllable switch uses a driving pulse voltage with the same pulse waveform.
  • a controller Based on this, a controller outputs a driving pulse voltage to each first controllable switch based on preset driving pulse voltage parameters.
  • driving pulse voltage there are multiple parameters that can characterize the driving pulse voltage, such as voltage amplitude, pulse period, pulse frequency, duty cycle and pulse width.
  • the complete driving pulse voltage waveform can be defined by combining some of these parameters. In practical applications, specific driving pulse voltage parameters can be selected according to actual needs.
  • the waveform of the operating pulse voltage required for processing the wafer can usually be determined in advance. Furthermore, based on the above content, it can be seen that the waveform of the operating pulse voltage is directly affected by the DC voltage output by the DC power supply in the pulse voltage generating circuit, the setting of the first controllable switch in the switching unit, and the driving condition. For a certain pulse voltage generating circuit, the range of the DC voltage output by the DC power supply and the setting of the first controllable switch in the switching unit are both known. Therefore, the initial values of the parameters of the driving pulse voltage and the initial value of the DC voltage of the DC power supply can be reversely determined based on the above information.
  • the above-mentioned conduction control rules also need to be met. Therefore, it is necessary to limit the phase difference between the driving pulse voltages corresponding to each first controllable switch.
  • the specific limitation method can be implemented by referring to the relevant content in the above-mentioned embodiment and will not be repeated here.
  • the parameter acquisition circuit acquires the actual operation pulse voltage at the preset sampling point and feeds the obtained actual operation pulse voltage back to the controller.
  • the operating pulse voltage can also be characterized by parameters such as voltage amplitude, pulse period, pulse frequency, duty cycle and pulse width. Therefore, obtaining the actual operating pulse voltage mentioned in this step is actually obtaining the actual value of the target parameter among the aforementioned parameters.
  • the selection of the target parameter is based on the premise of being able to fully describe the operating pulse voltage waveform.
  • the target parameters may include voltage amplitude, pulse frequency and pulse width.
  • the ion energy is affected by the voltage amplitude, pulse width and pulse frequency of the operating pulse voltage.
  • the pulse voltage generating circuit provided in the above embodiment, it can be seen that these parameters are directly affected by the DC voltage output by the DC power supply and the conduction process of each first controllable switch in the switch unit. Therefore, the output operating pulse voltage can be adjusted by adjusting the DC voltage output by the DC power supply and/or the conduction process of each first controllable switch, thereby adjusting the actual ion energy so that the energy distribution of the actual ion energy is a single-peak distribution.
  • each first controllable switch in the switch unit multiple parameters such as the voltage amplification factor, pulse frequency and pulse width can be changed.
  • adjusting the DC voltage and voltage amplification factor of the DC power supply can change the voltage amplitude of the operating pulse voltage.
  • both the DC power supply and the switching unit can affect the final output of the pulse voltage generating circuit, at least one of the DC power supply and the switching unit can be adjusted. Furthermore, in actual adjustment, multiple adjustments are often required to adjust the energy distribution of the actual ion energy to a single peak distribution.
  • the pulse voltage generating method adjusts the operation process of the pulse voltage generating circuit according to the actual ion energy acting on the wafer during the operation of the pulse voltage generating circuit, adjusts the energy distribution of the actual ion energy to a single-peak distribution, effectively improves the control accuracy of the ion energy, and helps to improve the process level of wafer processing.
  • FIG13 is a flow chart of another pulse voltage generating method provided in an embodiment of the present application.
  • the pulse voltage generating method provided in this embodiment includes the following steps.
  • S300 may be implemented with reference to the relevant content of S210 in the embodiment shown in FIG12 , which will not be repeated here.
  • the pulse voltage generating circuit In combination with the working process of the pulse voltage generating circuit provided in the above-mentioned embodiment, it can be seen that when all the first controllable switches in the switch unit are turned off, the pulse voltage generating circuit outputs a high level.
  • This high level is obtained by superimposing the electric energy released by the energy storage circuit and the electric energy output by the DC power supply, and has a very high voltage amplitude. Moreover, this high level will be directly applied to each first controllable switch, thereby increasing the risk of the first controllable switch being damaged due to overvoltage.
  • the first preset voltage threshold can be set based on the maximum withstand voltage of the first controllable switch. It is understood that the first preset voltage threshold should be less than or equal to the maximum withstand voltage of the first controllable switch.
  • the specific value of the first preset voltage threshold needs to be determined in combination with specific control and protection requirements, and this application does not impose any restrictions on this.
  • the control pulse voltage generating circuit continues to operate and will not trigger the protection circuit action.
  • S320 Control the protection circuit to disconnect the DC power supply from the energy storage circuit and release the electric energy stored in the energy storage circuit.
  • the control protection circuit disconnects the DC power supply from the energy storage circuit, stops the DC power supply from continuing to provide power to the subsequent circuit, and at the same time, releases the power stored in the energy storage circuit.
  • the controller when the voltage amplitude of the actual operating pulse voltage is greater than the first preset voltage threshold, the controller first controls the second controllable switch Sp to turn off, cutting off the output of the DC power supply. At the same time, the controller controls the third controllable switch Sq to turn on, and the electric energy stored in the energy storage inductor L1 will be quickly released through the first resistor R1 to avoid damage to each first controllable switch in the switching unit.
  • the controller controls the second controllable switch Sp to turn on, the third controllable switch Sq to turn off, the DC power supply continues to output, and the operating pulse voltage is output after conversion by the switching unit.
  • the controller may further set a second preset voltage threshold, wherein the second preset voltage threshold is less than the first preset voltage threshold.
  • the controller may reduce the DC voltage output by the DC power supply to ensure the safety of the first controllable switch when the protection circuit does not operate, that is, when the overall operation of the circuit is not affected.
  • a stepped protection of the first controllable switch and the pulse voltage generating circuit as a whole can be achieved, which can avoid frequent operation of the protection circuit while ensuring the safety of the circuit, thereby improving the stability and reliability of the circuit operation.
  • S330 Adjust the DC voltage output by the DC power supply and/or the conduction process of each first controllable switch until the voltage amplitude of the actual operating pulse voltage is less than or equal to the first preset voltage threshold.
  • the voltage amplitude of the operating pulse voltage output by the pulse voltage generating circuit is primarily affected by two parameters: the DC voltage output by the DC power supply, and the voltage amplification factor of the switching unit. Based on this, after the control protection circuit executes the protection action described in S320, the DC voltage output by the DC power supply can be reduced, or the voltage amplification factor can be reduced by adjusting the conduction process of each first controllable switch. Of course, both of these adjustment measures can be implemented simultaneously until the voltage amplitude of the actual operating pulse voltage is less than or equal to the first preset voltage threshold.
  • the voltage amplitude of the operating pulse voltage can be collected again, and the above steps can be repeatedly performed. After multiple adjustments, the voltage amplitude of the actual operating pulse voltage is less than or equal to the first preset voltage threshold.
  • the pulse voltage generating circuit When the amplitude of the actual operating pulse voltage is less than or equal to the first preset voltage threshold, the pulse voltage generating circuit is operating normally.
  • the controller controls the protection circuit to connect the DC power supply and the energy storage circuit. Using the pulse voltage generating circuit shown in FIG8 as an example, the controller controls the third controllable switch Sq to turn off and, accordingly, controls the second controllable switch Sp to turn on, restoring normal circuit operation.
  • the pulse voltage generating method monitors the voltage amplitude of the actual operating pulse voltage, and controls the action and recovery of the protection circuit according to the relationship between the voltage amplitude of the actual operating pulse voltage and the preset voltage threshold, which can effectively improve the safety of each first controllable switch in the switching unit and the overall safety of the pulse voltage generating circuit, thereby improving the stability and reliability of the operation of the pulse voltage generating circuit.
  • the pulse voltage generating circuit is provided with an ion current detector and a parameter acquisition circuit.
  • the ion current detector collects the actual ion current inside the process chamber that is accelerated by the sheath field and bombards the wafer surface, and outputs the obtained actual ion current to the parameter acquisition circuit.
  • the parameter acquisition circuit includes an ion flux acquisition module, which is connected to the bottom of the ion current detector's collection section via wires. Using resistors, it converts the actual ion current into a voltage signal and collects it, thereby determining the actual ion flux impacting the wafer.
  • a controller is connected to the parameter acquisition circuit to obtain the actual ion flux feedback from the circuit.
  • the target ion flux is the ion flux expected to be required for processing the wafer. It can usually be determined before processing the wafer based on the specifications of the wafer to be processed and the specific processing process. Of course, the target ion flux can also be determined based on other information or methods, which are not limited in this application. In actual application, after the target ion flux is determined, the target ion flux can be stored in the controller.
  • the present application provides a preset flux deviation range, which limits the deviation between the actual ion flux and the target ion flux by the preset flux deviation range. It can be understood that when the deviation between the actual ion flux and the target ion flux is within the preset flux deviation range, it is believed that the current actual ion flux meets the process requirements. On the contrary, when the deviation between the actual ion flux and the target ion flux is not within the preset flux deviation range, it is believed that the current actual ion flux cannot meet the process requirements.
  • the preset flux deviation range can be set according to the performance of the pulse voltage generating circuit and the specific process requirements. The present application does not limit the specific setting of the preset flux deviation range.
  • the output power of the plasma generator is adjusted until the deviation between the actual ion flux and the target ion flux is within the preset flux deviation range.
  • the pulse voltage generating method provided in this embodiment on the basis of outputting the operating pulse voltage to achieve precise control of ion energy, adjusts the output power of the plasma generator based on the actual ion flux feedback from the plasma detector and the parameter acquisition circuit, and adjusts the ion flux, thereby realizing dual control of ion energy and ion flux, which can effectively improve the pulse voltage generation effect and thus improve the wafer processing technology level.
  • this embodiment further provides a computer-readable storage medium, such as a floppy disk, an optical disk, a hard disk, a flash memory, a USB flash drive, an SD (Secure Digital Memory Card), an MMC (Multimedia Card), etc., in which one or more instructions for implementing each of the above steps are stored.
  • a computer-readable storage medium such as a floppy disk, an optical disk, a hard disk, a flash memory, a USB flash drive, an SD (Secure Digital Memory Card), an MMC (Multimedia Card), etc.
  • an embodiment of the present application may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the pulse voltage generation method according to various embodiments of the present application described in the above content of this specification.
  • the computer program product may be written in any combination of one or more programming languages to implement the program code for performing the operations of the embodiments of the present application, including object-oriented programming languages such as Java, C++, and conventional procedural programming languages such as "C" or similar programming languages.
  • the program code may be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

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Abstract

本申请提供一种脉冲电压产生电路及半导体工艺设备，应用于半导体制造技术领域，该电路包括储能电路和开关单元，储能电路与开关单元中各第一可控开关的连接点用于输出作业脉冲电压，开关单元中各第一可控开关的导通状态受控制器控制，各第一可控开关呈并联关系，各第一可控开关的导通时段互不重叠且导通顺序相邻的两个第一可控开关的导通时段间隔预设时长，各第一可控开关按照上述方式依次导通，即可输出作业脉冲电压，作业脉冲电压的脉冲频率是各第一可控开关导通状态切换频率之和，通过设置多个第一可控开关即可有效提高作业脉冲电压的脉冲频率，进而改善单峰IEDF控制效果，满足实际工艺需求。

Description

一种脉冲电压产生电路及半导体工艺设备 技术领域
本申请涉及半导体制造技术领域，具体涉及一种脉冲电压产生电路及半导体工艺设备。
背景技术
低压、低温、弱电离的辉光放电等离子体广泛应用于集成电路制造领域，特别是等离子体刻蚀和等离子体增强化学气相沉积等工艺过程。而随着集成电路集成度不断提高以及高深宽比、高选择比等先进工艺需求的提出，精确和独立实现等离子体的单峰离子能量分布(Ion Energy Distribution Function，IEDF)控制变得越来越重要。
图1所示为现有技术中一种脉冲电压产生电路，该电路采用开关管T1和开关管T2构成半桥电路，通过两个开关管交替导通，并经过后级电路处理就可以输出用于控制离子分布的作业脉冲电压。
结合图1所示可知，该电路输出作业脉冲电压的脉冲频率与开关管的驱动脉冲电压的脉冲频率一致，作业脉冲电压的电压幅值即直接作用于开关管的直流电压幅值，因此该电路输出的作业脉冲电压的脉冲频率与电压幅值直接影响开关管的损耗，即脉冲频率越高，开关管损耗越大，同时电压幅值越高，开关管损耗也会越大。现有技术为了实现高电压输出同时满足开关管损耗要求，只能输出低频的作业脉冲电压，导致单峰IEDF控制效果欠佳。现有技术中的单峰IEDF存在较大含量的低能峰，与理想的单峰IEDF相差甚远，严重影响实际的工艺效果。
发明内容
有鉴于此，本申请致力于提供一种脉冲电压产生电路及半导体工艺设备，在满足开关损耗要求以及高电压输出的基础上，提高作业脉冲电压的脉冲频率，改善单峰IEDF控制效果，满足实际工艺需求。
第一方面，本申请提供一种脉冲电压产生电路，用于半导体工艺设备，该电路包括：储能电路和开关单元，所述开关单元包括多个第一可控开关，其中，
所述储能电路的输入端用于与直流电源相连，所述储能电路的输出端分别与各所述第一可控开关的输入端相连，各所述第一可控开关的输出端用于接地；
所述储能电路与各所述第一可控开关的连接点用于输出作业脉冲电压；
各所述第一可控开关的控制端用于与控制器相连；
各所述第一可控开关用于在所述控制器的控制下依次导通，以输出所述作业脉冲电压；
其中，各所述第一可控开关的导通时段互不重叠且导通顺序相邻的两个所述第一可控开关的导通时段间隔预设时长；
所述储能电路用于在任一所述第一可控开关导通时存储电能，在所述预设时长内释放电能。
在一种可选的实施方式中，所述控制器配置为：
根据预设的驱动脉冲电压参数，分别向各所述第一可控开关输出驱动脉冲电压，其中，所述驱动脉冲电压用于控制所述第一可控开关的导通状态。
在一种可选的实施方式中，本申请第一方面提供的脉冲电压产生电路，还包括：振荡抑制电路，其中，
所述振荡抑制电路的输入端与所述储能电路以及各所述第一可控开关的连接点相连，所述振荡抑制电路的输出端用于输出所述作业脉冲电压；
所述振荡抑制电路用于抑制所述作业脉冲电压的电压波动。
在一种可选的实施方式中，本申请第一方面提供的脉冲电压产生电路，还包括：参数采集电路，其中，
所述参数采集电路用于采集预设采样点的实际作业脉冲电压，所述预设采样点包括所述振荡抑制电路的输入端、所述振荡抑制电路的输出端以及偏压电极中的至少一个，所述偏压电极位于所述半导体工艺设备的晶圆承载装置中；
所述控制器配置为：根据所述实际作业脉冲电压调节所述直流电源输出的直流电压和/或各所述第一可控开关的导通过程。
在一种可选的实施方式中，本申请第一方面提供的脉冲电压产生电路，还包括：保护电路，其中，
所述保护电路的第一连接端用于与所述直流电源的输出端相连，所述保护电路的第二连接端与储能电路的输入端相连；
所述控制器与所述保护电路的控制端相连；
所述控制器配置为：在所述实际作业脉冲电压的电压幅值大于第一预设电压阈值情况下，控制所述保护电路断开所述直流电源与所述储能电路的连接并释放所述储能电路存储的电能。
在一种可选的实施方式中，所述保护电路包括：第二可控开关、第三可控开关以及第一电阻，其中，
所述第二可控开关的输入端作为所述保护电路的第一连接端；
所述第二可控开关的输出端与所述第三可控开关的输入端的连接点，作为所述保护电路的第二连接端；
所述第三可控开关的输出端与所述第一电阻的一端相连，所述第一电阻的另一端接地；
所述第二可控开关以及所述第三可控开关的控制端分别与所述控制器相连。
在一种可选的实施方式中，所述储能电路包括：储能电感和稳压电容，其中，
所述储能电感的第一端与所述稳压电容的第一端相连，所述储能电感的第二端作为所述储能电路的输出端；
所述稳压电容的第二端用于接地；
所述储能电感与所述稳压电容的连接点作为所述储能电路的输入端。
第二方面，本申请提供一种半导体工艺设备，包括：工艺腔室、控制器以及如本申请第一方面任一项所述的脉冲电压产生电路，其中，
所述工艺腔室内设置有晶圆承载装置，所述晶圆承载装置内设置有偏压电极；
所述控制器与所述脉冲电压产生电路的各第一可控开关的控制端电连接；
所述脉冲电压产生电路的输出端与所述偏压电极相连；
所述控制器用于控制所述脉冲电压产生电路向所述偏压电极输出作业脉冲电压，以控制离子能量分布。
在一种可选的实施方式中，本申请第二方面提供的半导体工艺设备，还包括：射频线圈、匹配器和射频电源，其中，
所述射频电源用于通过所述匹配器向所述射频线圈施加射频功率，以在所述工艺腔室内激发等离子体；
所述控制器还与所述射频电源电连接，以控制所述射频电源的输出功率。
在一种可选的实施方式中，本申请第二方面提供的半导体工艺设备，还包括：离子电流探测器，其中，
所述离子电流探测器用于采集轰击到所述晶圆承载装置上放置的晶圆的实际离子电流，所述实际离子电流用于表征实际离子通量；
所述控制器还用于调节所述射频电源的射频功率，直至所述实际离子通量与目标离子通量的偏差处于预设通量偏差范围内。
在一种可选的实施方式中，所述控制器还配置为执行以下步骤：
获取所述脉冲电压产生电路中预设采样点的实际作业脉冲电压；
根据所述实际作业脉冲电压确定实际离子能量；
调节与所述脉冲电压产生电路相连的直流电源输出的直流电压和/或所述脉冲电压产生电路中各第一可控开关的导通过程，以使所述实际离子能量的能量分布为单峰分布。
在一种可选的实施方式中，所述脉冲电压产生电路包括保护电路和储能电路，所述控制器还配置为执行以下步骤：
若所述实际作业脉冲电压的电压幅值大于第一预设电压阈值，控制所述保护电路断开直流电源与所述储能电路的连接，并释放所述储能电路存储的电能；
调节所述直流电源输出的直流电压和/或各所述第一可控开关的导通过程，直至所述实际作业脉冲电压的电压幅值小于或等于所述第一预设电压阈值；
控制所述保护电路连通所述直流电源和所述储能电路。
基于上述内容，本申请提供的脉冲电压产生电路，包括储能电路和开关单元，储能电路与开关单元中各第一可控开关的连接点用于输出作业脉冲电压，开关单元中各第一可控开关的导通状态受控制器控制，由于各第一可控开关呈并联关系，任一第一可控开关导通均使得储能电路输出端接地，进而存储电能，相应的，由于各第一可控开关的导通时段互不重叠(即不会同时导通)且导通顺序相邻的两个第一可控开关的导通时段间隔预设时长，在该预设时长内各第一可控开关均关断，储能电路释放电能，基于此设置，在任一第一可控开关导通时，脉冲电压产生电路输出低电平，前述导通时段对应的时长即低电平持续时长，相应的，在各第一可控开关均关断时输出高电平，前述预设时长即高定平的持续时长，各第一可控开关按照上述方式依次导通，即可输出作业脉冲电压。
由此可见，作业脉冲电压的脉冲频率是各第一可控开关导通状态切换频率之和，通过设置多个第一可控开关即可有效提高作业脉冲电压的脉冲频率，对于第一可控开关而言，在作业脉冲电压的脉冲频率一定的情况下，由各第一可控开关共同分担该脉冲频率，各第一可控开关的导通状态切换频率有效降低，从而有效降低开关损耗。同时，由于储能电路可存储电能，其在预设时长内释放电能时将与直流电源输出的电能叠加，从而有效提高作业脉冲电压的电压幅值，因此，本申请可在满足开关损耗要求以及高电压输出的基础上，提高作业脉冲电压的脉冲频率，进而改善单峰IEDF控制效果，满足实际工艺需求。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术中一种脉冲电压产生电路的电路拓扑图。
图2是本申请实施例提供的一种脉冲电压产生电路的电路拓扑图。
图3是图2所示实施例提供的脉冲电压产生电路对应的控制时序示意图。
图4a-图4c是应用本申请实施例提供的脉冲电压产生电路进行脉冲电压产生的仿真控制效果示意图。
图5a-图5b是应用本申请实施例提供的脉冲电压产生电路进行脉冲电压产生的实际控制效果示意图。
图6是本申请实施例提供的另一种脉冲电压产生电路的电路拓扑图。
图7是图6所示实施例提供的脉冲电压产生电路对应的控制时序示意图。
图8是本申请实施例提供的再一种脉冲电压产生电路的电路拓扑图。
图9是本申请实施例提供的一种脉冲电压产生电路的结构框图。
图10是本申请实施例提供的一种离子电流探测器的结构示意图。
图11是本申请实施例提供的一种脉冲电压产生方法的流程图。
图12是本申请实施例提供的另一种脉冲电压产生方法的流程图。
图13是本申请实施例提供的再一种脉冲电压产生方法的流程图。
图14是本申请实施例提供的又一种脉冲电压产生方法的流程图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
如前所述，低压、低温、弱电离的辉光放电等离子体广泛应用于集成电路制造领域，特别是等离子体刻蚀和等离子体增强化学气相沉积等工艺过程。而随着集成电路集成度不断提高以及高深宽比、高选择比等先进工艺需求的提出，刻蚀过程中采用的双峰离子能量分布(Ion Energy Distribution Function，IEDF)控制已经难以满足实际应用需求，精确和独立实现等离子体的单峰IEDF控制变得越来越重要。
图1所示为现有技术中一种脉冲电压产生电路，该电路采用开关管T1和开关管T2构成半桥电路，开关管T1的漏极连接直流高压Vbus，开关管T1的源极连接开关管T2的漏极，开关管T2的源极接地，控制两个开关管栅极与源极之间的驱动电压，实现开关管导通状态的切换，进而通过两个开关管交替导通，并经过后级电路处理后输出用于控制离子分布的作业脉冲电压。
结合图1所示可知，该电路输出作业脉冲电压的脉冲频率与开关管的驱动脉冲电压的脉冲频率一致，作业脉冲电压的电压幅值即直接作用于开关管的直流电压幅值，因此该电路输出的作业脉冲电压的脉冲频率与电压幅值直接影响开关管的损耗，即脉冲频率越高，开关管损耗越大，同时电压幅值越高，开关管损耗也会越大。现有技术为了实现高电压输出同时满足开关管损耗要求，只能输出低频的作业脉冲电压，由于频率不够高，等离子体轰击晶圆表面(即离子电流)会引起晶圆表面电势明显增加，这将导致产生的离子能量分布展宽较大，难以满足高深宽比、高选择比等先进工艺的需求。
实际应用中虽然存在其他的技术方案，在图1所示电路的基础上增加电流补偿电路，从而对输出的作业脉冲电压增加一端负电压斜坡，此举虽然可以在一定程度上改善单峰IEDF控制效果，但由于没有解决作业脉冲电压脉冲频率低的根本问题，实际应用效果依然差强人意，同时，由于增加了新的电路，导致整体电路结构以及控制过程更为复杂，控制器逻辑开销更大，电路的整体成本也明显提高。
为解决上述技术问题，本申请提供一种脉冲电压产生电路，在满足开关损耗要求以及高电压输出的基础上，提高作业脉冲电压的脉冲频率，进而改善单峰IEDF控制效果，满足实际工艺需求。
本申请提供的脉冲电压产生电路应用于半导体工艺设备，在实际应用中，该半导体工艺设备可以是ICP(Inductively Coupled Plasma，电感耦合等离子体)刻蚀机、CCP(Capacitively Coupled Plasma，电容耦合等离子体)刻蚀机或PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气相沉积)等设备。基于此，参见图2，图2以ICP刻蚀机为例阐明本申请所提供的脉冲电压产生电路的应用场景，半导体工艺设备包括工艺腔室140、控制器70、射频电源90、阻抗匹配电路100以及上电极，其中，对于ICP刻蚀机而言，上电极包括耦合线圈110，射频电源90的输出端与阻抗匹配电路100相连，阻抗匹配电路100与耦合线圈110相连，射频电源90在启动后，即可通过阻抗匹配电路100对耦合线圈110施加射频功率，并在工艺腔室140内部生成等离子体。工艺腔室140内设置有与上电极相对设置的晶圆承载装置130，该晶圆承载装置130例如可以包括静电卡盘、或机械卡盘等，晶圆承载装置130内设置有偏压电极40，本申请提供的脉冲电压产生电路即用于向工艺腔室140内的晶圆承载装置130的偏压电极40提供偏压。结合图2所示，该脉冲电压产生电路包括：储能电路20和开关单元30。
结合图2所示，在一种可能的实施方式中，储能电路20包括储能电感L1和稳压电容C1，其中，储能电感L1的第一端与稳压电容C1的第一端相连，且储能电感L1与稳压电容C1的连接点作为储能电路20的输入端，与直流电源10的输出端相连，储能电感L1的第二端作为储能电路20的输出端，与开关单元30的输入端相连，稳压电容C1的第二端接地。在实际应用中，稳压电容C1一般选择μF级电容，用于保持向后级电路所输出电压的稳定。储能电感L1一般选择μH级电感，用于存储能量或释放能量。对于稳压电容C1以及储能电感L1的具体选型，需要结合控制电路的具体应用场景以及电路设计参数等因素确定，本申请对于储能电感L1以及稳压电容C1的具体选型不做限定。
作为一种优选的实施方式，本实施例提供的储能电路20中还设置有二极管D1，通过二极管D1的单向导通功能，可以保证储能电感L1上的电流方向恒定，即只能由直流电源10侧流向开关单元30侧，同时，还可以避免出现LC振荡。
进一步的，开关单元30包括多个第一可控开关，即至少包括两个第一可控开关，在图2所示实施例中，以开关单元30包括两个第一可控开关(即第一可控开关S1和第一可控开关S2)示出。各第一可控开关的输入端相连，作为开关单元30的输入端与储能电路20的输出端相连，同时，各第一可控开关的输出端接地。基于上述连接关系可知，开关单元30中的各第一可控开关呈并联关系，任一第一可控开关导通，均可使开关单元30导通，进而将储能电路20接地，相应的，所有第一可控开关关断时，可使开关单元30关断。开关单元30的输入端与储能电路20输出端的连接点作为脉冲电压产生电路的输出端，与工艺腔室140内设置的偏压电极40相连。开关单元30中各第一可控开关的控制端分别与控制器70相连，控制器70可以控制各第一可控开关的导通状态。
需要说明的是，在图2所示实施例以及后续各实施例中，第一可控开关可以选择Si、SiC或GaN等类型的开关管实现，当然，还可以选择其他能够满足电路运行需求的可控开关管，此处不再一一展开。
基于上述连接关系，控制器70可以是上位机，也可是下位机，在本申请中主要用于控制开关单元30中各第一可控开关的导通状态，其中，具体的导通状态控制规则为：各第一可控开关依次导通，各第一可控开关的导通时段互不重叠且导通顺序相邻的两个第一可控开关的导通时段间隔预设时长。可以理解的是，各第一可控开关依次导通，要求开关单元中各第一可控开关在脉冲电压产生电路工作过程中按照预设顺序循环导通，以图2所示第一可控开关S1和第一可控开关S2为例，二者依次导通的过程为：第一可控开关S1→第一可控开关S2→第一可控开关S1……如此循环，直至脉冲电压产生电路停止运行。而各第一可控开关的导通时段互不重叠，则可以保证开关单元中不会出现同时导通的第一可控开关，导通顺序相邻的两个第一可控开关的导通时段间隔预设时长，则用于保证在该预设时长内各第一可控开关全部关断。
如前所述，开关单元30中各第一可控开关呈并联关系，控制器70在控制各第一可控开关依次导通过程中，任一第一可控开关导通均使得储能电路20输出端接地，此时储能电路20存储电能，相应的，由于各第一可控开关的导通时段互不重叠且导通顺序相邻的两个第一可控开关的导通时段间隔预设时长，在该预设时长内各第一可控开关均关断，储能电路20将释放前期所存储的电能。
基于此设置，在任一第一可控开关导通时，脉冲电压产生电路输出低电平，前述导通时段对应的时长即低电平持续时长，相应的，在各第一可控开关均关断时输出高电平，前述预设时长即高定平的持续时长，从而通过开关单元30实现将直流电源10输出的直流电压转换为脉冲电压，控制器70控制各第一可控开关按照上述方式依次导通，即可通过储能电路20与各第一可控开关的连接点向偏压电极40输出作业脉冲电压。
结合图2所示，在一种可能的实施方式中，直流电源10的控制端与控制器70相连，控制器70还用于控制直流电源输出直流电压。在实际应用中，控制器70可以控制直流电源10的工作状态，即控制直流电源10输出直流电压或停止输出该直流电压。在一种优选的实施方式中，直流电源10的输出电压可调，控制器70可以根据电路实际的运行情况以及脉冲电压产生需求调节直流电源10实际输出的直流电压的幅值。直流电源10的输出端与储能电路20的输入端相连，向储能电路20输出直流电压，至于控制器70控制直流电源10输出直流电压的具体过程，将在后续内容中展开，此处暂不详述。
综上所述，通过本实施例提供的脉冲电压产生电路，第一可控开关导通时段对应的时长与预设时长之和，即作业脉冲电压的脉冲周期，相应的，作业脉冲电压的脉冲频率是各第一可控开关导通状态切换频率之和，因此，通过设置多个第一可控开关可以有效提高作业脉冲电压的脉冲频率，对于第一可控开关而言，在作业脉冲电压的脉冲频率一定的情况下，由各第一可控开关共同分担该脉冲频率，各第一可控开关的导通状态切换频率有效降低，从而有效降低开关损耗。同时，由于储能电路可存储电能，其在预设时长内释放电能时将与直流电源输出的电能叠加，从而有效提高作业脉冲电压的电压幅值，因此，本申请可在满足开关损耗要求以及电压幅值要求的基础上，提高作业脉冲电压的脉冲频率，进而改善单峰IEDF控制效果，满足实际工艺需求。
进一步的，由于本申请提供的脉冲电压产生电路输出的作业脉冲电压的脉冲频率足够高，在不增加其他电流补偿电路的情况下仍然能够达到良好的单峰IEDF控制效果，与现有技术相比，可以简化控制过程，从而降低控制器的逻辑开销，同时有效降低电路整体成本。
下面以图2所示电路拓扑为例，提供一种可以满足上述第一可控开关导通状态控制规则的控制信号的实现方式，在本实施例中，以脉冲电压的方式驱动开关单元中的各第一可控开关导通状态的切换，即通过脉冲电压的高电平控制第一可控开关导通，通过脉冲电压的低电平控制第一可控开关关断，为了与前述作业脉冲电压区分，本申请将用于驱动第一可控开关导通状态的脉冲电压定义为驱动脉冲电压。在实际应用中，根据脉冲电压产生需求，可以向控制器配置驱动脉冲电压参数，比如驱动脉冲电压的脉冲周期、占空比以及电压幅值等，控制器根据预设的驱动脉冲电压参数，即可确定需要输出的驱动脉冲电压，在接收到控制指令之后，即可分别向各第一可控开关输出该驱动脉冲电压。
进一步的，如前所述，脉冲电压产生电路最终输出的作业脉冲电压的电压幅值、脉冲频率，以及占空比等参数均受开关单元影响，因此，在作业脉冲电压的参数确定的情况下，还可以逆向确定驱动脉冲电压，这在实际应用中具有重要意义，对于这一内容将在后续内容中展开，此处暂不详述。
控制器根据预设的驱动脉冲电压控制开关单元的控制时序可参见图3所示。
在t0-t1时段，第一可控开关S1导通，第一可控开关S2关断，此时直流电源10的输出端经过储能电感L1和第一可控开关S1构成闭合回路，直流电源10对储能电感L1充电，脉冲电压产生电路的输出电压(即Vout)为0V。
在t1-t2时段(对应前述预设时长)，第一可控开关S1和第一可控开关S2都已关断，储能电路20中储能电感L1释放电能，并与直流电源10输出的电能相叠加，提高输出电压幅值。同时，由于稳压电容C1的作用，在两个第一可控开关都关断的阶段输出电压的幅值基本保持恒定。
在t2-t3时段，第一可控开关S1关断，第一可控开关S2导通，此时，直流电源10经储能电感L1和第一可控开关S2构成闭合回路，直流电源10继续对储能电感L1充电，相应的，脉冲电压产生电路的输出电压再次降到0V。
在t3-t4时段，第一可控开关S1和第一可控开关S2都已关断，直流电源和储能电感L1继续提供高幅值的直流电压。在t4时刻，第一可控开关S1导通，第一可控开关S2关断，至此，第一可控开关S1和第一可控开关S2都完整的经过一个驱动周期，通过周期性重复上述的过程，即可输出作业脉冲电压。
结合图3所示可以看出：
首先，在t0-t4时间段内，无论是第一可控开关S1的驱动脉冲电压，还是第一可控开关S2的驱动脉冲电压均有一次高电平输出，而作业脉冲电压产生两次高电平输出，因此，作业脉冲电压的脉冲频率是第一可控开关的驱动脉冲电压的脉冲频率的2倍，即作业脉冲电压的脉冲频率是各第一可控开关的驱动脉冲电压的脉冲频率之和。因此，在不提高可控开关驱动脉冲电压的脉冲频率的情况下，通过设置多个第一可控开关可以显著提高作业脉冲电压的脉冲频率，进而有效降低可控开关的损耗，同时实现高脉冲频率的作业脉冲电压输出。
其次，通过开关单元可以控制作业脉冲电压的电压幅值，在稳态下，脉冲电压产生电路最终输出的作业脉冲电压的电压幅值，相较于直流电源输出的直流电压的放大倍率可以按照如下公式计算：
其中，N表示电压放大倍率；
M表示开关单元中第一可控开关的个数；
ta-tb表示任一第一可控开关处于导通状态的时长；
tc-td表示导通顺序相邻的两个第一可控开关的导通时段间隔的预设时长。
比如，第一可控开关S1和第一可控开关S2的驱动脉冲电压的频率为5MHz，任一第一可控开关导通时段的时长为80ns，则输出的作业脉冲电压的脉冲频率为10MHz，脉冲宽度(即高电平持续时长)为20ns。如果直流电源输出的直流电压为100V，那么最终作业脉冲电压的电压幅值将放大到800V。因此，经过储能电感可以将直流电源输出的直流电压放大，并且电压放大倍率可以根据第一可控开关的驱动脉冲电压进行调控。
需要说明的是，在图3所对应的驱动方式中，各第一可控开关使用相同脉冲频率的驱动脉冲电压，为了满足前述各第一可控开关的导通时段互不重叠且导通顺序相邻的两个第一可控开关的导通时段间隔预设时长这一原则，各第一可控开关的驱动脉冲电压之间必然存在相位差。结合图3所示，导通顺序相邻的两个第一可控开关之间的相位差应与预期输出的作业脉冲电压的脉冲周期相等，相应的，导通顺序相邻的两个第一可控开关的导通时段间隔的预设时长，即作业脉冲电压输出高电平的时长。在实际应用中，可以基于导通顺序相邻的两个第一可控开关对应的驱动脉冲电压的上升沿实现这一控制，或者，也可以使用在先导通的第一可控开关的驱动脉冲电压的下降沿以及在后导通的第一可控开关的驱动脉冲电压的上升沿实现这一控制。当然，还可以采用其他典型时刻，只要满足前述导通原则的控制方式都是可选的，在未超出本申请核心思想范围的前提下，同样属于本申请保护的范围内。
基于上述内容，以作业脉冲电压的脉冲频率为10MHz为例，图4a-图4c是应用本申请实施例提供的脉冲电压产生电路进行脉冲电压产生的仿真控制效果示意图。其中，图4a为脉冲电压产生电路最终输出的作业脉冲电压的波形示意图，作业脉冲电压的脉冲频率为10MHz，占空比为20％时，脉冲宽度为20ns，作业脉冲电压的电压幅值为5000V。由于偏压电极与晶圆之间存在平板电容效应，当脉冲电压产生电路输出高电平的时候，晶圆表面也会耦合出同样的高电平，此时晶圆表面高电平与等离子体之前会形成加速电场，吸引电子向晶圆表面移动，导致晶圆表面电压降低。当脉冲电压产生电路输出低电平的时候，晶圆表面电压会变为负电压，吸引离子向晶圆表面移动。由于离子运动速度远小于电子运动速度，电子引起的晶圆表面电压下降将远大于离子引起的晶圆表面电压上升，由于作业脉冲电压的脉冲频率足够高，需要经过多个脉冲周期才会在晶圆表面形成稳定的如图4b实线所示的负偏压脉冲波形。在本例中，离子将在80％的脉冲周期内从鞘场加速到晶圆表面，在剩下20％的脉冲周期内电子加速到晶圆表面，用于中和离子轰击晶圆表面残余的正电荷。
通常来说，离子穿越鞘场到达晶圆表面的时间τi为
其中，表示鞘场平均厚度；
mi表示离子质量；
n0表示等离子体密度；
表示平均鞘场电压。
通常，离子穿越鞘场到达晶圆表面的时间一般为几百ns。由于本申请提供的脉冲电压产生电路可以提供高频率的作业脉冲电压，离子会经过多个作业脉冲电压的脉冲周期后才能穿越鞘场达到晶圆表面，而这个过程中离子不能实时响应鞘场电压V(t)，而是感受到鞘场平均电压Vd(t)的作用，此时，将满足下列关系：
结合图4b所示，图中虚线展示了当偏压电极接入高频率的作业脉冲电压的情况下，离子感受到的鞘场平均电压波形基本保持恒定，这将产生如图4c所示的单峰离子能量分布。
在实际应用中，鞘场平均电压波形的震荡变化范围将决定单峰IEDF的展宽。一般情况下，作业脉冲电压的脉冲频率越高，离子穿越鞘场到达晶圆表面经过的脉冲周期越多，平均鞘场的效果越明显，鞘场平均电压波形的震荡变化引起的离子能量展宽越小。这种情况加速出的离子平均能量E0可以表示为：
其中，V0表示晶圆表面脉冲电压幅值，与脉冲电压产生电路输出的作业脉冲电压的电压幅值直接相关；
Ton表示作业脉冲电压的脉冲宽度；
T表示作业脉冲电压的脉冲周期；
f表示作业脉冲电压的脉冲频率。
基于公式(4)可以看出，作业脉冲电压的脉冲宽度越小，加速出的离子平均能量越大，作业脉冲电压的脉冲频率越高，上述公式的近似效果越好，因为离子穿越鞘场到达晶圆表面经过的脉冲周期越多，平均鞘场的效果越明显，离子能量控制越精准。
进一步的，参见图5a-图5b所示，图5a和图5b为应用本申请实施例提供的脉冲电压产生电路进行脉冲电压产生的实际控制效果示意图，其中，图5a所示为脉冲频率为10MHz的作业脉冲电压接入偏压电极时，在晶圆表面感应出的电压波形，图中虚线则展示离子实际感受到的平均鞘场电压波形。相较于图4a，由于工艺腔室负载的变化以及传输线路的电感，会引起晶圆表面电压波形出现震荡，即出现如图5a所示的作业脉冲电压的下降沿存在一定范围的过冲(-350V至-300V部分)，但是，由于离子需要经过多个作业脉冲电压的脉冲周期后才能穿越鞘场达到晶圆表面，离子实际感受到的平均鞘场电压波形并不会受到影响，从而保证图5b所示的实际的单峰IEDF具有较小展宽，与图4c所示仿真效果基本一致，满足实际使用过程中的工艺要求。
进一步的，参见图6所示实施例，本实施例提供的脉冲电压产生电路中，开关单元包括四个第一可控开关(即S1-S4)，该电路的控制时序可以参见图7所示。
在t0-t1时段，第一可控开关S1导通，其他3个第一可控开关关断，此时，直流电源10经储能电感L1和第一可控开关S1构成闭合回路，直流电源10向储能电感L1充电，脉冲电压产生电路的输出电压(即Vout)为0V。
在t1-t2时段，4个第一可控开关都关断，直流电源10和储能电感L1同时向偏压电极40提供电能。
在t2-t3时段，第一可控开关S2导通，其他3个第一可控开关关断，此时，直流电源10经储能电感L1和第一可控开关S2构成闭合回路，直流电源10向储能电感L1充电，脉冲电压产生电路的输出电压再次降到0V。
在t3-t4时段，4个第一可控开关都关断，直流电源10和储能电感L1同时向偏压电极40提供电能。
在t4-t5时段，第一可控开关S3导通，其他3个第一可控开关关断，此时，直流电源10经储能电感L1和第一可控开关S3构成闭合回路，直流电源10向储能电感L1充电，脉冲电压产生电路的输出电压再次降到0V。
在t5-t6时段，4个第一可控开关都关断，直流电源10和储能电感L1同时向偏压电极40提供电能。
在t6-t7时段，第一可控开关S4导通，其他3个第一可控开关关断，此时，直流电源10经储能电感L1和第一可控开关S4构成闭合回路，直流电源10向储能电感L1充电，脉冲电压产生电路的输出电压再次降到0V。
在t7-t8时段，4个第一可控开关都关断，直流电源10和储能电感L1同时向偏压电极40提供电能。在t8时刻，第一可控开关S1导通，其他3个第一可控开关关断，开始周期性重复上述的过程，最终向偏压电极40输出作业脉冲电压。如果4个第一可控开关的驱动脉冲电压的脉冲频率为5MHz，则所得作业脉冲电压的脉冲频率为20MHz。
图6所示实施例解决技术问题的原理以及其他相关控制过程，均可以参照前述实施例实现，此处不再复述。
需要说明的是，在开关单元包括三个及以上数量的第一可控开关的情况下，各第一可控开关的导通状态切换频率可以相同(如图6和图7所示内容所示)也可以不同(包括两个第一可控开关时，二者交替导通，导通状态切换频率必然相同)。以图6所示为例，在采用图7所示的驱动脉冲电压时，各第一可控开关的导通状态切换频率相同，在另一种实施方式中，可以提高第一可控开关S1以及第一可控开关S2的驱动脉冲电压的脉冲频率，或者，降低第一可控开关S1以及第一可控开关S2的驱动脉冲电压的脉冲频率，当然，还可以有其他调整方式，此处不再一一列举，在实际应用中，可以根据实际需求或电路设计成本，搭配不同规格的可控开关。需要强调的是，不论如何设置各第一可控开关的驱动脉冲电压，前述可控开关的导通原则是必须满足的，相应的，任何能够满足这一原则的控制方式都是可选的，同样都属于本申请保护的范围内。
可以理解的是，在各第一可控开关的导通状态切换频率不同的情况下，作业脉冲电压的脉冲频率依然为各第一可控开关的驱动脉冲电压的脉冲频率之和，而前述电压放大倍率则需要结合各第一可控开关的驱动脉冲电压分别计算相应的放大倍率，将各第一可控开关对应的放大倍率之和作为开关单元最终的电压放大倍率。
进一步的，在图6所示实施例提供的脉冲电压产生电路中，还包括振荡抑制电路50。振荡抑制电路50连接于开关单元30与偏压电极40之间，用于输出作业脉冲电压，即振荡抑制电路50的输入端与储能电路20以及各第一可控开关的连接点相连，振荡抑制电路50的输出端与偏压电极40相连。通过振荡抑制电路50可以抑制输出至偏压电极40的作业脉冲电压的电压波动。
在一种可能的实施方式中，振荡抑制电路50包括二极管D2、第二电阻R2和第三电阻R3，其中，二极管D2的阳极与第三电阻R3的第一端相连，二者的连接点作为振荡抑制电路50的输入端，二极管D2的阴极与第二电阻R2的第一端相连，第二电阻R2的第二端与第三电阻R3的第二端相连，二者的连接点作为振荡抑制电路50的输出端，与偏压电极40相连。
本实施例提供的脉冲电压产生电路设置有振荡抑制电路，通过振荡抑制电路可以使流入工艺腔室的离子体负载的电流与流出工艺腔室的离子体负载的电流相对分离，抑制由于脉冲电压产生电路与偏压电极之间的线路电感所引起的脉冲电压波形振荡，使得输出至偏压电极的作业脉冲电压更稳定，进而使得晶圆感应电压同样更为稳定，有效提高脉冲电压产生效果。
在上述任一实施例的基础上，本申请还提供另一种脉冲电压产生电路，结合图8所示，本实施例提供的脉冲电压产生电路还包括参数采集电路(图8中未示出)和保护电路60。
在本实施例中，参数采集电路主要用于在预设采样点采集实际作业脉冲电压，其中，预设采样点包括振荡抑制电路50的输入端、振荡抑制电路50的输出端以及偏压电极40中的至少一个。对于各预设采样点的作用以及与参数采集电路的连接方式，将在后续图9所示实施例中具体展开，此处暂不详述。
在本实施例中，控制器还用于根据实际作业脉冲电压调节直流电源10的输出电压和/或各第一可控开关的导通状态，从而调节最终输出至偏压电极40的作业脉冲电压。对于具体的调节过程，将在后续内容中展开，此处暂不详述。
进一步的，如图8所示，保护电路60连接于直流电源10与储能电路20之间。在一种可能的实施方式中，保护电路包括第二可控开关Sp、第三可控开关Sq以及第一电阻R1。具体的，第二可控开关Sp的输入端作为保护电路60的第一连接端，与直流电源10的输出端相连，第二可控开关Sp的输出端与第三可控开关Sq的输入端相连，二者的连接点作为保护电路60的第二连接端，与储能电路20的输入端相连，第三可控开关Sq的输出端与第一电阻R1的一端相连，第一电阻R1的另一端接地。第二可控开关Sp以及第三可控开关Sq的控制端分别与控制器相连。
在本实施例中，控制器还用于在参数采集电路采集的实际作业脉冲电压的电压幅值大于第一预设电压阈值情况下，控制保护电路60断开直流电源10与储能电路20的连接并释放储能电路20存储的电能。至于保护过程的具体实现方式，将在后续内容中展开，此处暂不详述。
综上所述，相较于前述实施例，本实施例提供的脉冲电压产生电路新增参数采集电路和保护电路，通过采集输出的实际作业脉冲电压，实现对于开关单元以及脉冲电压产生电路整体的过压保护，有助于提高开关单元中各第一可控开关以及脉冲电压产生电路整体的安全性和使用寿命。
进一步的，本申请还提供一种半导体工艺设备，结合图9所示，本申请提供的半导体工艺设备包括工艺腔室140、控制器70以及前述任一实施例提供的脉冲电压产生电路。
如前所述，工艺腔室140内设置有晶圆承载装置130，且该晶圆承载装置130内设置有偏压电极40，前述任一实施例提供的脉冲电压产生电路的输出端即与偏压电极40相连，向偏压电压40输出作业脉冲电压。结合图9所示，为清楚的展示本实施例提供的半导体工艺设备，脉冲电压产生电路以结构框图的形式示出，对于图9所示实施例中脉冲电压产生电路各构成子电路的具体实现方式，均可参见前述实施例相关内容，此处不再复述。
进一步的，本实施例提供的半导体工艺设备还包括：射频电源90、阻抗匹配电路100、离子电流探测器120以及与晶圆承载装置130相对设置的上电极，如前所述，本申请提供的半导体工艺设备可以是ICP刻蚀机或CCP刻蚀机，在半导体工艺设备为ICP刻蚀机时，上电极为耦合线圈110，在半导体工艺设备为CCP刻蚀机时，上电极为进气匀流板，基于此，在图9所示实施例中，上电极以耦合线圈110示出。
具体的，射频电源90主要用于向上电极施加射频功率，进而生成轰击晶圆的等离子体。
阻抗匹配电路100用于等离子体发生回路的阻抗匹配，使射频电源90的功率最大化的加载到耦合线圈110以及工艺腔室140。在实际应用中，阻抗匹配电路100的构成方式以及匹配阻抗值，需要结合工艺腔室140、耦合线圈110以及线路整体的实际布线等情况设置，本申请对于阻抗匹配电路100的具体实现同样不做限定。
耦合线圈110用于将射频电源90输出的电能以电磁场耦合的方式加载到工艺腔室140，进而在工艺腔室中产生稳定的等离子体。在实际应用中，为了达到更好的脉冲电压产生效果，耦合线圈110通常与工艺腔室140中的偏压电极40相对设置。
基于上述内容，射频电源90的输出端与阻抗匹配电路100相连，阻抗匹配电路100与耦合线圈110相连，射频电源90在启动运行后，即可通过阻抗匹配电路100以及耦合线圈110在工艺腔室140内部生成等离子体。
结合图9所示，工艺腔室140中还设置有晶圆承载装置130，通过晶圆承载装置130承载待处理的晶圆150。在实际应用中，晶圆承载装置130可以选择内部设置有绝缘陶瓷层的静电吸附卡盘，当然，还可以选择其他能够承载晶圆150，同时能够使得晶圆150产生感应电压进而对离子运动产生影响的实现方式，此处不再详述。前述各实施例中述及的偏压电极40，即设置在晶圆承载装置130内部，当脉冲电压产生电路输出的作业脉冲电压输出至偏压电极40之后，偏压电极40与晶圆150之间是晶圆承载装置130内部的绝缘陶瓷层，偏压电极40与晶圆150产生平板电容效应，脉冲电压产生电路输出的作业脉冲电压将以电容耦合的方式作用于工艺腔室140内部的等离子体，进而实现对等离子体的控制。
在一种优选的实施方式中，脉冲电压产生电路中用于输出作业脉冲电压的电路部分，设置于工艺腔室140正下方，这样有效缩短脉冲电压产生电路与偏压电极40之间的连接线，从而大大降低连接线路的电感，减小电感引起的脉冲波形振荡，有助于改善单峰IEDF的控制效果。
前述实施例中述及参数采集电路80主要用于在预设采样点采集实际作业脉冲电压，结合图9所示，预设采样点分别是振荡抑制电路50的输入端(也可以看作是开关单元30的输出端)、振荡抑制电路50的输出端以及偏压电极40。需要说明的是，在实际应用中，上述三个预设采样点可以使用一个或多个，对于预设采样点的选取主要取决于参数采集电路80与预设采样点连接的难易程度、采样参数的准确度以及采样参数与控制功能之间的匹配度等影响条件。当预设采样点使用多个时，还需要配置控制器实现采样参数的筛选机制，即如何在多个采样参数中确定最终使用的采样参数。
为实现参数采集电路80可在多个预设采样点采集参数，在一种可能的实施方式中，参数采集电路80包括3路采集模块，分别为离子能量采集模块、第一电压采集模块和第二电压采集模块。
离子能量采集模块通过导电的顶针连接至晶圆150背面，实时采集晶圆150表面感应的作业脉冲电压，可以理解的是，作业脉冲电压通常可以通过三个参数来表征，即电压幅值、脉冲频率以及脉冲宽度，基于此，离子能量采集模块包括电压幅值采集模块、脉冲频率采集模块和脉冲宽度采集模块3个主要部件，电压幅值采集模块采集晶圆150表面作业脉冲电压的电压峰值，脉冲频率采集模块采集晶圆150表面作业脉冲电压的脉冲频率，脉冲宽度采集模块采集晶圆150表面的作业脉冲电压的脉冲宽度。
第一电压采样模块用于采集振荡抑制电路50输入端的作业脉冲电压，第二电压采样模块则用于采集振荡抑制电路50输出端的作业脉冲电压。
参数采集电路80中的各构成模块将所得参数信息发送至控制器70，由控制器70实现对脉冲电压产生电路运行过程的控制，至于具体的控制过程，将在后续内容中展开，此处暂不详述。
至于图9所示的脉冲电压产生电路中的其他构成部分的具体实现方式，比如直流电源10、保护电路60、储能电路20、开关单元30以及振荡抑制电路50等，均可参照前述各个实施例中的相关内容，此处不再复述。
进一步的，本实施例提供的脉冲电压产生电路还包括离子电流探测器120，通过离子电流探测器120可以收集工艺腔室140内部经过鞘场加速后轰击到晶圆150表面的离子电流。
结合图10所示，离子电流探测器120包括过滤栅网1201、第一栅网电极1202、第二栅网电极1203以及收集部1204。其中，过滤栅网1201的作用是使工艺腔室140内部的等离子体的离子和电子进入离子电流探测器120，在实际应用中需要将过滤栅网1201接地。第一栅网电极1202与过滤栅网1201的栅网孔径保持一致，离子电流探测器120运行时需要对第一栅网电极1202施加一定幅值的负电压，阻止电子进入离子电流探测器120内部的离子收集空间。收集部1204用于吸引离子进入收集空间，从而探测离子电流。第二栅网电极1203与过滤栅网1201的栅网孔径保持一致，区别在于施加的负电压要低于收集部1204，从而阻止离子轰击收集部1204而产生二次电子逃逸，影响测量结果。收集部1204为石墨材料，收集轰击到晶圆的实际离子电流。
为了将离子电流探测器120采集的离子电流反馈至控制器70，参数采集电路80还包括离子通量采集模块，该模块通过导线连接至离子电流探测器120收集部1204的底部，利用电阻将实际离子电流转化为电压信号并进行采集，由此确定轰击到晶圆150的实际离子通量，并将实际离子通量反馈至控制器70。控制器70根据实际离子通量调节射频电源90的输出功率，最终达到精确控制离子通量的目的。
综上所述，相较于前述实施例，本实施例提供的脉冲电压产生电路，在输出作业脉冲电压实现离子能量精准控制的基础上，还包括等离子体发生回路以及等离子体探测器，基于等离子体探测器以及参数采集电路配合反馈的实际离子通量调节等离子体发生器的输出功率，调节离子通量，从而实现离子能量和离子通量的双重控制，能够有效提高脉冲电压产生效果，进而提高晶圆加工工艺水平。
在上述各个实施例中，半导体工艺设备中的控制器主要实现半导体工艺设备运行过程的控制，该控制器包括至少一个存储器和至少一个处理器，该处理器配置为执行图11至图14任一实施例所提供的脉冲电压产生方法。
参见图11，本申请提供的脉冲电压产生方法的一种可选实施方式包括如下步骤：
S100、响应于控制指令，控制直流电源输出直流电压，以及控制开关单元中各第一可控开关依次导通，以使脉冲电压产生电路输出用于控制离子的作业脉冲电压。
在实际应用中，控制指令可以来源于任何能够控制脉冲电压产生电路运行的设备或装置，比如，可以是脉冲电压产生电路所属的半导体工艺设备，还可以其他能够与脉冲电压产生电路中的控制器进行通信的上位机，又或者，脉冲电压产生电路中的控制器与半导体工艺设备中的其他模块进行通信，在确定需要脉冲电压产生电路运行时，由控制器本身自动生成该控制指令，本申请对于脉冲电压产生电路获取控制指令的具体方式不做限定。
控制器在得到控制指令之后，即控制脉冲电压产生电路中的直流电源输出直流电压以及控制开关单元工作，使得脉冲电压产生电路输出作业脉冲电压。
在一种可能的实施方式中，控制指令中包括有目标电压值，控制器在接收到控制指令后，即可按照该目标电压值控制直流电源运行。
在另一种可能的实施方式中，控制指令可以仅包括直流电源的使能信息，控制器基于该使能信息按照自身预设的初始电压值或通过其他参数计算得到的初始电压值控制直流电源运行。
在一种可能的实施方式中，控制指令中还可以包括控制开关单元工作的目标参数，比如驱动脉冲电压的电压幅值、脉冲频率以及占空比等，控制器在得到控制指令之后，即可按照该目标参数控制开关单元工作。
在另一种可能的实施方式中，控制指令中同样可以仅包括开关单元的使能信息，控制器基于该使能信息按照自身预设的控制信息控制开关单元工作。
需要说明的是，在控制开关单元中各第一可控开关的导通状态以输出作业脉冲电压的过程中，应遵守的控制规则同样为：各第一可控开关依次导通，各第一可控开关的导通时段互不重叠且导通顺序相邻的两个第一可控开关的导通时段间隔预设时长。至于基于脉冲电压产生电路的具体电路拓扑以及这一控制规则输出作业脉冲电压的具体过程，可参照前述实施例中的相关内容，此处不再复述。
通过本实施例提供的脉冲电压产生方法，所输出的作业脉冲电压的脉冲频率是各第一可控开关导通状态切换频率之和，因此，通过设置多个第一可控开关可以有效提高作业脉冲电压的脉冲频率，对于第一可控开关而言，在作业脉冲电压的脉冲频率一定的情况下，由各第一可控开关共同分担该脉冲频率，各第一可控开关的导通状态切换频率有效降低，从而有效降低开关损耗。同时，由于储能电路可存储电能，其在预设时长内释放电能时将与直流电源输出的电能叠加，从而有效提高作业脉冲电压的电压幅值，因此，本申请可在满足开关损耗要求以及电压幅值要求的基础上，提高作业脉冲电压的脉冲频率，进而改善单峰IEDF控制效果，满足实际工艺需求。
并且，由于脉冲电压产生电路输出的作业脉冲电压的脉冲频率足够高，在不增加其他电流补偿电路的情况下仍然能够达到良好的单峰IEDF控制效果，与现有技术相比，本实施例提供的离子电路控制方法的控制逻辑更为简单，能够降低控制器的逻辑开销以及对于控制器硬件性能的要求。
进一步的，参见图12，图12为本申请实施例提供的另一种脉冲电压产生方法的流程图，在前述实施例基础上，本实施例提供的脉冲电压产生方法包括以下步骤。
S200、响应于控制指令，控制直流电源输出直流电压，以及根据预设的驱动脉冲电压参数，分别向各第一可控开关输出驱动脉冲电压。
对于控制指令的可选实现方式，以及控制器响应控制指令控制直流电源输出直流电压的可选实现方式，均可以参照前述实施例中的相关内容，此处不再复述。
在本实施例提供的脉冲电压产生方法中，采用驱动脉冲电压控制开关单元中各第一可控开关的导通状态，并且各第一可控开关使用相同脉冲波形的驱动脉冲电压。基于此，控制器基于预设的驱动脉冲电压参数，分别向各第一可控开关输出驱动脉冲电压。
需要说明的是，能够表征驱动脉冲电压的参数包括多个，比如电压幅值、脉冲周期、脉冲频率、占空比以及脉冲宽度等，通过其中部分参数的组合即可限定完整的驱动脉冲电压波形，在实际应用中，可以根据实际需求选择具体的驱动脉冲电压参数。
还需要说明的是，在确定的作业场景中，处理晶圆所需的作业脉冲电压的波形通常是可以预先确定的，进一步的，基于前述内容可知，作业脉冲电压的波形受到脉冲电压产生电路中直流电源输出的直流电压、开关单元中第一可控开关的设置情况以及驱动情况的直接影响，而对于确定的脉冲电压产生电路而言，直流电源输出的直流电压的范围以及开关单元中第一可控开关的设置情况都是已知的，因此，可以基于前述信息逆向确定驱动脉冲电压的参数的初始值，以及直流电源的直流电压的初始值。
如前所述，在采用驱动脉冲电压控制开关单元工作过程中，同样需要满足前述导通控制规则，因此，需要限制各第一可控开关对应的驱动脉冲电压之间的相位差，具体的限制方式可以参照前述实施例中的相关内容实现，此处不再复述。
S210、获取脉冲电压产生电路中预设采样点的实际作业脉冲电压。
预设采样点的具体选取可以参照前述内容，此处不再复述。参数采集电路采集预设采样点的实际作业脉冲电压，并将所得实际作业脉冲电压反馈至控制器。
需要说明的是，与前述驱动脉冲电压类似，作业脉冲电压同样可以通过电压幅值、脉冲周期、脉冲频率、占空比以及脉冲宽度等参数来表征，因此，在本步骤中述及的获取实际作业脉冲电压，实际是获取前述各参数中的目标参数的实际值，当然，目标参数的选取是以能够完整描述作业脉冲电压波形为前提的，比如，目标参数可以包括电压幅值、脉冲频率以及脉冲宽度。
S220、根据实际作业脉冲电压确定实际离子能量。
根据实际作业脉冲电压计算实际离子能量的具体实现可参照相关技术，此处不再详述。
S230、调节直流电源输出的直流电压和/或各第一可控开关的导通过程，以使所述实际离子能量的能量分布为单峰分布。
在实际应用中，由于作业脉冲电压在传输至偏压电极的过程中，不可避免的会产生损耗以及受到电磁干扰，导致实际作业脉冲电压与脉冲电压产生电路输出的作业脉冲电压存在一定偏差，进而导致用于脉冲电压产生的实际离子能量的能量分布不为单峰分布，影响离子控制效果。
基于前述公式(4)，离子能量受作业脉冲电压的电压幅值、脉冲宽度以及脉冲频率影响，而基于前述实施例提供的脉冲电压产生电路可知，这些参数直接由直流电源输出的直流电压以及开关单元中各第一可控开关的导通过程影响，因此，可以通过调节直流电源输出的直流电压和/或各第一可控开关的导通过程，实现对输出的作业脉冲电压的调整，进而调整实际离子能量，使得实际离子能量的能量分布为单峰分布。基于前述内容可知，调节开关单元中各第一可控开关，可以改变电压放大倍率、脉冲频率以及脉冲宽度等多个参数，而且，调节直流电源的直流电压以及电压放大倍率，都可以改变作业脉冲电压的电压幅值。
需要说明的是，由于直流电源和开关单元都能影响脉冲电压产生电路的最终输出，因此，可以调节直流电源和开关单元中的至少一个。并且，在实际调节过程中，往往需要经过多次调节才能将实际离子能量的能量分布调整为单峰分布。
综上所述，本实施例提供的脉冲电压产生方法，根据脉冲电压产生电路运行过程中作用于晶圆的实际离子能量调整脉冲电压产生电路的运行过程，将实际离子能量的能量分布调整为单峰分布，有效提高离子能量的控制精度，有助于提高处理晶圆的工艺水平。
进一步的，参见图13，图13是本申请实施例提供的再一种脉冲电压产生方法的流程图，本实施例提供的脉冲电压产生方法包括如下步骤。
S300、获取脉冲电压产生电路中预设采样点的实际作业脉冲电压。
在一种可选的实施方式中，S300可参照图12所示实施例中S210的相关内容实现，此处不再复述。
S310、判断实际作业脉冲电压的电压幅值是否大于第一预设电压阈值，若是，执行S320。
结合前述实施例提供的脉冲电压产生电路的工作过程可知，当开关单元中全部第一可控开关均关断时，脉冲电压产生电路输出高电平，该高电平是储能电路释放的电能与直流电源输出电能叠加得到，具有很高的电压幅值，而且，该高电平将直接施加于各第一可控开关，使得第一可控开关因过压损坏的风险增大。
为了提高各第一可控开关的运行安全性，需要判断实际作业脉冲电压的电压幅值与第一预设电压阈值的大小关系。在实际应用中，不同规格的第一可控开关对应不同的最高耐受电压，因此，可以基于第一可控开关的最高耐受电压设置第一预设电压阈值，可以理解的是，第一预设电压阈值应小于或等于第一可控开关的最高耐受电压，至于第一预设电压阈值的具体取值，则需要结合具体的控制需求以及保护需求设置，本申请对此不做限定。
如果实际作业脉冲电压的电压幅值大于第一预设电压阈值，继续执行S320，相反的，如果实际作业脉冲电压的电压幅值小于或等于第一预设电压阈值，则控制脉冲电压产生电路继续运行，不会触发保护电路动作。
S320、控制保护电路断开直流电源与储能电路的连接并释放储能电路存储的电能。
在实际作业脉冲电压的电压幅值大于第一预设电压阈值的情况下，控制保护电路断开直流电源与储能电路的连接，终止直流电源继续向后级电路提供电能，同时，释放储能电路存储的电能。
以图8所示实施例提供的脉冲电压产生电路为例，在实际作业脉冲电压的电压幅值大于第一预设电压阈值的情况下，控制器首先控制第二可控开关Sp关断，切断直流电源的输出，同时，控制器控制第三可控开关Sq导通，储能电感L1存储的电能将快速通过第一电阻R1释放，避免开关单元中各第一可控开关损坏。
可以理解的是，在实际作业脉冲电压的电压幅值小于或等于第一预设电压阈值的情况下，控制器控制第二可控开关Sp导通，第三可控开关Sq关断，直流电源持续输出，经开关单元转换后输出作业脉冲电压。
在另一种可能的实施方式中，控制器还可以设置第二预设电压阈值，其中，第二预设电压阈值小于第一预设电压阈值，在实际作业脉冲电压的电压幅值大于第二预设电压阈值且小于第一预设电压阈值的情况下，说明实际作业脉冲电压的电压幅值达到预警阶段，但尚未明显影响第一可控开关的安全，控制器可以降低直流电源输出的直流电压，以在保护电路不动作，即不影响电路整体运行的情况下，确保第一可控开关的安全。通过第一预设电压阈值以及第二预设电压阈值的配合，可以实现第一可控开关以及脉冲电压产生电路整体的阶梯型保护，能够在确保电路安全的情况下，避免保护电路频繁动作，进而提高电路运行的稳定性和可靠性。
S330、调节直流电源输出的直流电压和/或各第一可控开关的导通过程，直至实际作业脉冲电压的电压幅值小于或等于第一预设电压阈值。
如前所述，脉冲电压产生电路输出的作业脉冲电压的电压幅值主要受两个参数影响，其一是直流电源输出的直流电压，其二是开关单元的电压放大倍率。基于此，在控制保护电路执行S320所述的保护动作之后，可以降低直流电源输出的直流电压，或者，通过调节各第一可控开关的导通过程降低电压放大倍率，当然，可以同时采取前述两种调节措施，直至使得实际作业脉冲电压的电压幅值小于或等于第一预设电压阈值。
在实际应用中，可以在进行一次调节后，再次采集作业脉冲电压的电压幅值，重复的执行前述步骤，经过多次调节使得实际作业脉冲电压的电压幅值小于或等于第一预设电压阈值。
S340、控制保护电路连通直流电源和储能电路。
在实际作业脉冲电压的电压幅值小于或等于第一预设电压阈值的情况下，说明脉冲电压产生电路可以正常运行，控制器即控制保护电路连通直流电源和储能电路。以图8所示实施例提供的脉冲电压产生电路为例，控制器控制第三可控开关Sq关断，相应的，控制第二可控开关Sp导通，电路恢复正常运行。
综上所述，本实施例提供的脉冲电压产生方法，对实际作业脉冲电压的电压幅值的监测，根据实际作业脉冲电压的电压幅值与预设电压阈值的大小关系控制保护电路的动作和恢复，能够有效提高开关单元中各第一可控开关以及脉冲电压产生电路整体的安全性，进而提高脉冲电压产生电路运行的稳定性和可靠性。
进一步的，在上述任一实施例提供的脉冲电压产生方法的基础上，还可以包括如图14所示的如下步骤。
S400、获取轰击晶圆的实际离子通量。
如前所述，脉冲电压产生电路设置有离子电流探测器和参数采集电路，离子电流探测器采集工艺腔室内部经过鞘场加速后轰击到晶圆表面的实际离子电流，并将所得实际离子电流输出至参数采集电路。
参数采集电路中设置有离子通量采集模块，该模块通过导线连接至离子电流探测器收集部的底部，利用电阻将实际离子电流转化为电压信号并进行采集，由此确定轰击到晶圆的实际离子通量。控制器与参数采集电路相连，获取参数采集电路反馈的实际离子通量。
S410、调节等离子体发生器的输出功率，直至实际离子通量与目标离子通量的偏差处于预设通量偏差范围内。
目标离子通量是处理晶圆预期所需要的离子通量，通常在处理晶圆之前可根据待处理晶圆的规格以及具体的处理工艺确定，当然，还可以根据其他信息或方式确定目标离子通量，本申请对此不做限定。在实际应用过程中，可以在确定目标离子通量之后，将该目标离子通量存储至控制器。
进一步的，考虑到实际控制难度以及控制精度的需求，本申请提供预设通量偏差范围，通过预设通量偏差范围限制实际离子通量与目标离子通量之间的偏差，可以理解的是，实际离子通量与目标离子通量之间的偏差处于该预设通量偏差范围内时，认为当前的实际离子通量是满足工艺要求的，相反的，实际离子通量与目标离子通量之间的偏差未处于该预设通量偏差范围内时，认为当前的实际离子通量不能满足工艺要求。在实际应用中，预设通量偏差范围可以根据脉冲电压产生电路的性能以及具体的工艺要求设置，本申请对于预设通量偏差范围的具体设置不做限定。
基于上述内容，在实际离子通量与目标离子通量之间的偏差未处于该预设通量偏差范围内的情况下，即调节等离子体发生器的输出功率，直至实际离子通量与目标离子通量的偏差处于预设通量偏差范围内。
综上所述，相较于前述实施例提供的脉冲电压产生方法，本实施例提供的脉冲电压产生方法，在输出作业脉冲电压实现离子能量精准控制的基础上，基于等离子体探测器以及参数采集电路配合反馈的实际离子通量调节等离子体发生器的输出功率，调节离子通量，从而实现离子能量和离子通量的双重控制，能够有效提高脉冲电压产生效果，进而提高晶圆加工工艺水平。
在一些实施例中，本实施例还提供了一种计算机可读存储介质，如软盘、光盘、硬盘、闪存、U盘、SD(Secure Digital Memory Card，安全数码卡)卡、MMC(Multimedia Card，多媒体卡)卡等，在该计算机可读存储介质中存储有实现上述各个步骤的一个或者多个指令，这一个或者多个指令被一个或者多个处理器执行时，使得所述处理器执行前文描述的脉冲电压产生方法。相关具体实现请参考前述描述，此处不过多赘述。
除了上述方法和设备以外，本申请的实施例还可以是计算机程序产品，其包括计算机程序指令，计算机程序指令在被处理器运行时使得处理器执行本说明书上述内容中描述的根据本申请各种实施例的脉冲电压产生方法中的步骤。
计算机程序产品可以以一种或多种程序设计语言的任意组合来编写用于执行本申请实施例操作的程序代码，程序设计语言包括面向对象的程序设计语言，诸如Java、C++等，还包括常规的过程式程序设计语言，诸如“C”语言或类似的程序设计语言。程序代码可以完全地在用户计算设备上执行、部分地在用户设备上执行、作为一个独立的软件包执行、部分在用户计算设备上部分在远程计算设备上执行、或者完全在远程计算设备或服务器上执行。
本领域技术人员能够理解，本申请所披露的内容可以出现多种变型和改进。例如，以上所描述的各种设备或组件可以通过硬件实现，也可以通过软件、固件、或者三者中的一些或全部的组合实现。
此外，虽然本申请对根据本申请的实施例的系统中的某些单元做出了各种引用，然而，任何数量的不同单元可以被使用并运行在客户端和/或服务器上。单元仅是说明性的，并且系统和方法的不同方面可以使用不同单元。
本申请中使用了流程图用来说明根据本申请的实施例的方法的步骤。应当理解的是，前面或后面的步骤不一定按照顺序来精确的进行。相反，可以按照倒序或同时处理各种步骤。同时，也可以将其他操作添加到这些过程中。
本领域普通技术人员可以理解上述方法中的全部或部分的步骤可通过计算机程序来指令相关硬件完成，程序可以存储于计算机可读存储介质中，如只读存储器等。可选地，上述实施例的全部或部分步骤也可以使用一个或多个集成电路来实现。相应地，上述实施例中的各模块/单元可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。本申请并不限制于任何特定形式的硬件和软件的结合。
除非另有定义，这里使用的所有术语具有与本申请所属领域的普通技术人员共同理解的相同含义。还应当理解，诸如在通常字典里定义的那些术语应当被解释为具有与它们在相关技术的上下文中的含义相一致的含义，而不应用理想化或极度形式化的意义来解释，除非这里明确地这样定义。
以上是对本申请的说明，而不应被认为是对其的限制。尽管描述了本申请的若干示例性实施例，但本领域技术人员将容易地理解，在不背离本申请的新颖教学和优点的前提下可以对示例性实施例进行许多修改。因此，所有这些修改都意图包含在权利要求书所限定的本申请范围内。应当理解，上面是对本申请的说明，而不应被认为是限于所公开的特定实施例，并且对所公开的实施例以及其他实施例的修改意图包含在所附权利要求书的范围内。本申请由权利要求书及其等效物限定。

Claims (12)

  1. 一种脉冲电压产生电路，用于半导体工艺设备，其特征在于，包括：储能电路和开关单元，所述开关单元包括多个第一可控开关，其中，
    所述储能电路的输入端用于与直流电源相连，所述储能电路的输出端分别与各所述第一可控开关的输入端相连，各所述第一可控开关的输出端用于接地；
    所述储能电路与各所述第一可控开关的连接点用于输出作业脉冲电压；
    各所述第一可控开关的控制端用于与控制器相连；
    各所述第一可控开关用于在所述控制器的控制下依次导通，以输出所述作业脉冲电压；
    其中，各所述第一可控开关的导通时段互不重叠且导通顺序相邻的两个所述第一可控开关的导通时段间隔预设时长；
    所述储能电路用于在任一所述第一可控开关导通时存储电能，在所述预设时长内释放电能。
  2. 根据权利要求1所述的脉冲电压产生电路，其特征在于，所述控制器配置为：
    根据预设的驱动脉冲电压参数，分别向各所述第一可控开关输出驱动脉冲电压，其中，所述驱动脉冲电压用于控制所述第一可控开关的导通状态。
  3. 根据权利要求1所述的脉冲电压产生电路，其特征在于，还包括：振荡抑制电路，其中，
    所述振荡抑制电路的输入端与所述储能电路以及各所述第一可控开关的连接点相连，所述振荡抑制电路的输出端用于输出所述作业脉冲电压；
    所述振荡抑制电路用于抑制所述作业脉冲电压的电压波动。
  4. 根据权利要求3所述的脉冲电压产生电路，其特征在于，还包括：参数采集电路，其中，
    所述参数采集电路用于采集预设采样点的实际作业脉冲电压，所述预设采样点包括所述振荡抑制电路的输入端、所述振荡抑制电路的输出端以及偏压电极中的至少一个，所述偏压电极位于所述半导体工艺设备的晶圆承载装置中；
    所述控制器配置为：根据所述实际作业脉冲电压调节所述直流电源输出的直流电压和/或各所述第一可控开关的导通过程。
  5. 根据权利要求4所述的脉冲电压产生电路，其特征在于，还包括：保护电路，其中，
    所述保护电路的第一连接端用于与所述直流电源的输出端相连，所述保护电路的第二连接端与储能电路的输入端相连；
    所述控制器与所述保护电路的控制端相连；
    所述控制器配置为：在所述实际作业脉冲电压的电压幅值大于第一预设电压阈值情况下，控制所述保护电路断开所述直流电源与所述储能电路的连接并释放所述储能电路存储的电能。
  6. 根据权利要求5所述的脉冲电压产生电路，其特征在于，所述保护电路包括：第二可控开关、第三可控开关以及第一电阻，其中，
    所述第二可控开关的输入端作为所述保护电路的第一连接端；
    所述第二可控开关的输出端与所述第三可控开关的输入端的连接点，作为所述保护电路的第二连接端；
    所述第三可控开关的输出端与所述第一电阻的一端相连，所述第一电阻的另一端接地；
    所述第二可控开关以及所述第三可控开关的控制端分别与所述控制器相连。
  7. 根据权利要求1至6任一项所述的脉冲电压产生电路，其特征在于，所述储能电路包括：储能电感和稳压电容，其中，
    所述储能电感的第一端与所述稳压电容的第一端相连，所述储能电感的第二端作为所述储能电路的输出端；
    所述稳压电容的第二端用于接地；
    所述储能电感与所述稳压电容的连接点作为所述储能电路的输入端。
  8. 一种半导体工艺设备，其特征在于，包括：工艺腔室、控制器以及如权利要求1至7任一项所述的脉冲电压产生电路，其中，
    所述工艺腔室内设置有晶圆承载装置，所述晶圆承载装置内设置有偏压电极；
    所述控制器与所述脉冲电压产生电路的各第一可控开关的控制端电连接；
    所述脉冲电压产生电路的输出端与所述偏压电极相连；
    所述控制器用于控制所述脉冲电压产生电路向所述偏压电极输出作业脉冲电压，以控制离子能量分布。
  9. 根据权利要求8所述的半导体工艺设备，其特征在于，还包括：射频线圈、匹配器和射频电源，其中，
    所述射频电源用于通过所述匹配器向所述射频线圈施加射频功率，以在所述工艺腔室内激发等离子体；
    所述控制器还与所述射频电源电连接，以控制所述射频电源的输出功率。
  10. 根据权利要求9所述的半导体工艺设备，其特征在于，还包括：离子电流探测器，其中，
    所述离子电流探测器用于采集轰击到所述晶圆承载装置上放置的晶圆的实际离子电流，所述实际离子电流用于表征实际离子通量；
    所述控制器还用于调节所述射频电源的射频功率，直至所述实际离子通量与目标离子通量的偏差处于预设通量偏差范围内。
  11. 根据权利要求8至10任一项所述的半导体工艺设备，其特征在于，所述控制器还配置为执行以下步骤：
    获取所述脉冲电压产生电路中预设采样点的实际作业脉冲电压；
    根据所述实际作业脉冲电压确定实际离子能量；
    调节与所述脉冲电压产生电路相连的直流电源输出的直流电压和/或所述脉冲电压产生电路中各第一可控开关的导通过程，以使所述实际离子能量的能量分布为单峰分布。
  12. 根据权利要求11所述的半导体工艺设备，其特征在于，所述脉冲电压产生电路包括保护电路和储能电路，所述控制器还配置为执行以下步骤：
    若所述实际作业脉冲电压的电压幅值大于第一预设电压阈值，控制所述保护电路断开直流电源与所述储能电路的连接，并释放所述储能电路存储的电能；
    调节所述直流电源输出的直流电压和/或各所述第一可控开关的导通过程，直至所述实际作业脉冲电压的电压幅值小于或等于所述第一预设电压阈值；
    控制所述保护电路连通所述直流电源和所述储能电路。
PCT/CN2025/082073 2024-03-29 2025-03-12 一种脉冲电压产生电路及半导体工艺设备 Pending WO2025201057A1 (zh)

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