WO2025196141A1

WO2025196141A1 - Solid-state imaging element including a compensation circuit

Info

Publication number: WO2025196141A1
Application number: PCT/EP2025/057537
Authority: WO
Inventors: Jae-sung AN
Original assignee: Sony Europe BV; Sony Semiconductor Solutions Corp
Current assignee: Sony Europe BV; Sony Semiconductor Solutions Corp
Priority date: 2024-03-20
Filing date: 2025-03-19
Publication date: 2025-09-25
Anticipated expiration: 2026-09-20

Abstract

A solid-state imaging element (200) includes a pixel array (212). The pixel array (212) includes a plurality of pixels (220). Each of the plurality of pixels (220) is configured to output a pixel signal to a signal line (Vsl). A load transistor circuit block (250) is configured to supply a current to the signal line (Vsl). The load transistor circuit block (250) includes a load MOS transistor (252) including a first load terminal (D) electrically coupled to the signal line (Vsl), a control terminal (G), and a second load terminal (S). The load transistor circuit block (250) further includes a compensation circuit including a first switch (253) electrically coupled to the second load terminal (S) of the load MOS transistor (252), and a sampling element (254) electrically coupled between the control terminal (G) of the load MOS transistor (252) and the second load terminal (S) of the load MOS transistor (252).

Description

SOLID-STATE IMAGING ELEMENT

INCLUDING A COMPENSATION CIRCUIT

The present disclosure relates to a solid-state imaging element. In particular, the present disclosure relates to a solid-state imaging element having a compensation circuit.

BACKGROUND

In solid-state imaging elements photoelectric conversion elements generate a photocurrent proportional to the radiation intensity received during an exposure period. The photocurrent gradually accumulates charge. A pixel circuit transforms the small photocurrent generated by the photoelectric conversion element into a comparatively large output voltage which, for example, a downstream analog-to-digital converter of a column signal processing unit converts into a digital signal. Typically, pixels are two-dimensionally arranged in a row direction and a column direction, that is, in a matrix. Output signals of the pixels arranged along a column may be electrically coupled to a signal line, e.g. vertical signal line, and input to the column signal processing unit. A load current of the signal line is adjusted by a load transistor, e.g. load MOS transistor, of a load transistor circuit block. Due to process variations, the load currents of different signals lines may vary due to threshold voltage variations in the load transistors. As the current level becomes smaller and smaller in low-power imaging elements, the load current variation may increase. This may have a negative impact on the output image, e.g. appearance of stripes.

Development of solid-state imaging elements having low power consumption without loss of functionality and quality is challenging and requires solutions for counteracting drawbacks caused by manufacturing process variations.

SUMMARY

The present disclosure has been made in view of the above circumstances.

To this purpose, a solid-state imaging element includes a pixel array. The pixel array includes a plurality of pixels. Each of the plurality of pixels is configured to output a pixel signal to a signal line. The solid- state imaging element further includes a load transistor circuit block. The load transistor circuit block is configured to supply a current to the signal line. The load transistor circuit block includes a load MOS transistor. The load MOS transistor includes a first load terminal electrically coupled to the signal line, a control terminal, and a second load terminal. The load transistor circuit block further includes a compensation circuit. The compensation circuit includes a first switch electrically coupled to the second load terminal of the load MOS transistor. The compensation circuit further includes a sampling element electrically coupled between the control terminal of the load MOS transistor and the second load terminal of the load MOS transistor.

BRIEF DESCRIPTION OF THE DRAWINGS A more complete appreciation of the disclosure and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:

Fig. 1 is a simplified circuit diagram depicting an exemplary circuit configuration of a solid-state imaging element including a compensation circuit in a load transistor circuit block according to an embodiment of the present technology.

Fig. 2 illustrates a simplified circuit diagram depicting an exemplary circuit configuration of a load transistor circuit block portion.

Figs. 3A to 6B are exemplary timing and circuit diagrams for illustrating control signals and processes for compensating threshold voltage variations in load transistors of the load transistor circuit block.

Fig. 7 is a block diagram illustrating a configuration example of an imaging apparatus according to the present technology.

Fig. 8 is a block diagram illustrating a configuration example of a solid-state imaging element according to the present technology.

Fig. 9 is a circuit diagram illustrating a configuration example of a pixel according to the present technology.

Fig. 10 is a block diagram illustrating a configuration example of a load metal -oxide-semiconductor (MOS) circuit block and a column signal processing circuit according to the present technology.

FIG. 11A is a perspective view schematically depicting a flat chip structure, and Fig. 1 IB is an exploded perspective view schematically depicting a stacked semiconductor chip structure.

FIG. 12 is a diagram depicting an application example of the technology according to the present disclosure.

FIG. 13 is a block diagram depicting an example of a schematic configuration of a vehicle control system.

FIG. 14 is a diagram of assistance in explaining an example of installation positions of an outside-vehicle information detecting section and an imaging section of the vehicle control system of FIG. 13.

DETAILED DESCRIPTION

Embodiments for implementing techniques of the present disclosure (also referred to as “embodiments” in the following) will be described below in detail using the drawings. The techniques of the present disclosure are not limited to the described embodiments, and various features in the embodiments are illustrative only. The same elements or elements with the same functions are denoted by the same reference signs.

The terms "having", "containing", "including", "comprising" and the like are open, and the terms indicate the presence of stated structures, elements or features but do not preclude the presence of additional elements or features. The articles "a", "an" and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

Connected electronic elements may be directly electrically connected through a direct, permanent low- resistive connection, e.g., through a conductive line or an ohmic contact. The terms “electrically connected” and “signal-connected” may also include a connection through other electronic elements provided and suitable for permanent and/or temporary signal transmission and/or transmission of energy. Electronic elements can be electrically connected or signal-connected via resistors, capacitors, electronic switches such as FETs (field effect transistors), or transistor circuits such as transmission gates. The load path of a transistor is the controlled path of a transistor. For example, a voltage applied to a gate of a FET controls by field effect the current flow in the load path between source and drain.

Fig. 1 illustrates a configuration example of a solid-state imaging element 200 according to a configuration example of the present technology. The solid-state imaging element 200 includes a pixel array 212. The pixel array 212 includes a plurality of pixels 220. Although Fig. 1 exemplifies the pixel array 212 by illustrating a single pixel, the pixels of the pixel array 212 may be arranged in a two-dimensional lattice shape. For example, the pixels 220 may be two-dimensionally arranged in a row direction and a column direction, that is, in a matrix.

Each of the plurality of pixels 220 is configured to output a pixel signal, e.g. to a vertical signal line Vsl. For example, pixels arranged along a column may be electrically coupled to a common vertical signal line, e.g. the signal line Vsl illustrated in Fig. 1. Pixels arranged along another column in the pixel array 212 may be electrically coupled to another vertical signal line.

The solid-state imaging element 200 further includes a load transistor circuit block 250. The load transistor circuit block 250 may supply a current to the signal line Vsl.

A load MOS transistor 252 of the load transistor circuit block 250 has a first load terminal D, e.g. drain terminal in case of an NMOS field effect transistor (NMOSFET), electrically coupled to the vertical signal line Vsl. The load MOS transistor 252 further has a control or gate terminal G, and a second load terminal S, e.g. source terminal in case of an NMOS transistor.

The load transistor circuit block 250 further includes a compensation circuit. A first switch 253 of the compensation circuit is electrically coupled to the second load terminal S of the load MOS transistor 252. For example, the first switch 253 may be electrically connected or coupled between the second load terminal S of the load MOS transistor 252 and a reference supply line or node, e.g. GND. The compensation circuit further includes a sampling element 254 electrically coupled between the control terminal G of the load MOS transistor 252 and the second load terminal S of the load MOS transistor 252. For example, the sampling element is configured to sample and store or capture information related to the threshold voltage of the load MOS transistor 252 of the associated vertical signal line Vsl.

As is illustrated in the configuration example of the solid-state imaging element 200 of Fig. 2, the sampling element 254 may be a capacitor 2541. For example, the capacitor 2541 may have a capacitance value in a range from tens of fF to hundreds of fF, e.g. 10 fF to 900 fF, or 20 fF to 500 fF. The first switch 253 in the configuration example of Fig. 2 is exemplified as a MOS transistor 2531. The MOS transistor 2531 may have a same channel conductivity type as the load MOS transistor 252. For example, a chip or layout area or size of the MOS transistor 2531 may be smaller than 10 % of a chip or layout area or size of the load MOS transistor 252.

In some examples, the solid-state imaging element 200 further includes a first chip or substrate including the pixel array. The solid-state imaging element 200 further includes a second chip or substrate including the load transistor circuit block 250. For example, the first chip and the second chip may be electrically connected via junction portions including a metal-metal junction such as a Cu-Cu junction, or a through silicon via (TSV), a micro-bump, and the like. For example, the solid-state imaging element 200 may include further chips or substrates forming a chip stack with the first and second chips, e.g. a third chip, or a third and fourth chip.

In some examples, the solid-state imaging element 200 further includes a reference voltage circuit. The reference voltage circuit is configured to supply a load reference voltage VREF to the first load terminal D of the load MOS transistor 252 via a second switch. For solid-state imaging elements having a first chip including the pixels 220 of the pixel array 212 and a second chip including the load transistor circuit block 250, the reference voltage circuit may be formed in the first chip, or in the second chip. For solid-state imaging elements having more than two chips stacked on one another, the reference voltage circuit may also be arranged in a chip different from the chip where the pixel array 212 or the load transistor circuit block 250 is arranged.

In some examples, the solid-state imaging element 200 further includes a gate driving circuit configured to supply a gate voltage to the control terminal G of the load MOS transistor 252 via a third switch. In some examples, the gate driving circuit and the load transistor circuit block 250 are formed in the same chip.

In some examples, the solid-state imaging element 200 further includes a control circuit configured to supply control signals to the first switch 253, the second switch, and the third switch. The control circuit may be divided into a plurality of control sub-circuits. The control sub-circuits may be formed in the chip where the load transistor circuit block is arranged or may also be arranged in another chip. The sub-circuits of the control circuit may also be arranged in separate chips, for example.

For example, during a first control period, e.g. prior to pixel signal read out, the control circuit may be configured to supply a control signal to the first switch 253 of the load transistor circuit block 250 for turning off the first switch 253. The control circuit may be further configured to supply a control signal to the second switch of the reference voltage circuit for turning on the second switch. The control circuit may be further configured to supply a control signal to the third switch of the gate driving circuit for turning on the third switch. During the first control period the gate driving circuit may be configured to supply a reference gate voltage to the control terminal G of the load MOS transistor 252 via the third switch. The first control period may initiate capturing of the threshold voltage of the load MOS transistor 252 in the sampling element 254.

For example, during a second control period, the control circuit may be configured to supply a control signal to the first switch 253 of the load transistor circuit block 250 for turning off the first switch 253. The control circuit may be further configured to supply a control signal to the second switch of the reference voltage circuit for turning on the second switch. The control circuit may be further configured to supply a control signal to the third switch of the gate driving circuit for turning on the third switch. During the second control period, the gate driving circuit may be configured to supply a voltage to the control terminal G of the load MOS transistor 252 via the third switch 2701 that differs from the reference gate voltage in the first control period. The second control period may initiate programming of compensation data in the sampling element 254. The compensation data is associated with the voltage supplied by the gate driving circuit.

For example, during a third control period, the control circuit may be configured to supply a control signal to the first switch 253 of the load transistor circuit block 250 for turning on the first switch 253. The control circuit may be further configured to supply a control signal to the second switch of the reference voltage circuit for turning off the second switch. The control circuit may be further configured to supply a control signal to the third switch of the gate driving circuit for turning off the third switch. The third control period may initiate generation of the load current supplied by the load MOS transistor 252 with compensated threshold variation.

For example, during a fourth control period, e.g. a pixel signal read-out period or phase, the control circuit may be configured to supply a control signal to the first switch 253 of the load transistor circuit block 250 for turning on the first switch. The control circuit may be further configured to supply a control signal to the second switch of the reference voltage circuit for turning off the second switch. The control circuit may be further configured to supply a control signal to the third switch of the gate driving circuit for turning off the third switch. The control circuit may be further configured to initiate read-out of the pixel signal during the fourth control period. For example, the fourth control period may be divided or include sub-phases, e.g. a P-phase directed to processing a pixel noise signal and a D-phase directed to processing a pixel data signal.

In some examples, the solid-state imaging element 200 further includes a fourth switch. The signal line Vsl may be electrically coupled to the first load terminal D of the load MOS transistor 252 via the fourth switch. The fourth switch may electrically disconnect the signal line Vsl and pixels 200 from the load MOS transistor 252 when compensating for threshold voltage variations in the first and second control periods, for example. For example, during the first and second control periods, the control circuit may be configured to supply a control signal to the fourth switch for turning off the fourth switch. During the third and fourth control periods, the control circuit may be configured to supply a control signal to the fourth switch for turning on the fourth switch. For example, the threshold voltage compensation may be carried out with the fourth switch turned off during the first and second control periods, and the load current generation and pixel read out may be carried out with the fourth switch turned on during the third and fourth control periods.

The control periods are exemplified with reference to the timing and circuit diagrams of Figs 3 A to 6B.

Electric potentials at Nodes A, B, and C refer to the first load terminal D, the control or gate terminal G, and the second load terminal S of the load MOS transistor 252. For illustration purpose, turned off MOS transistors are indicated as crossed transistors in the circuit diagrams of Figs, 3B, 4B, 5B, 6B.

Referring to Figs. 3A and 3B, a first control period exemplified by Phasel is described. In Phasel, a control signal EN_LM is supplied to the first switch 253 exemplified as MOS transistor 2531 for turning off the MOS transistor 2531. A control signal SEL_BOT is supplied to a second switch 2601 of a reference voltage circuit 260 for turning on the second switch 2601. The second switch 2601 is exemplified as a MOS transistor and allows for providing a reference voltage VREF to the first load terminal D of the load MOS transistor 252. A control signal LM_SW is supplied to a third switch 2701 of a gate driving circuit 270 for turning on the third switch 2701. The third switch 2701 is exemplified as a MOS transistor. During Phasel, the gate driving circuit 2701 supplies a reference gate voltage VREF_LM to the control terminal G of the load MOS transistor 252 via the third switch 2701. A control signal VSL_CUT is supplied to a fourth switch 2801 connected between the vertical signal line Vsl and the first load terminal D of the load MOS transistor 252. The fourth switch 2801 is exemplified as a MOS transistor and allows for providing a connection/disconnection between the vertical signal line Vsl and the load MOS transistor 252. The control signal VSL_CUT during Phasel turns off the fourth switch 2801 and thus disconnects the vertical signal line Vsl from the load MOS transistor 252. When arranging the load MOS transistor 252 and the vertical signal line Vsl or parts thereof on different chips, e.g. bottom chip (including the load MOS transistor 252) and top chip (including the pixies 200 and the vertical signal line Vsl), a junction portion CCC, e.g. metalmetal junction including a Cu-Cu junction, a through silicon via (TSV), a micro-bump, and the like, may allow for chip interconnections. During Phasel, the voltage at Node C turns to VREF_LM - VTH LM, VTH LM being the threshold voltage of the load MOS transistor 252 that is subject to process variations.

Referring to Figs. 4A and 4B, a second control period exemplified by Phase2 is described. In Phase2, the control signal EN_LM is supplied to the MOS transistor 2531 for turning off the MOS transistor 2531. The control signal SEL_BOT is supplied to the MOS transistor 2601 of the reference voltage circuit 260 for turning on the MOS transistor 2601, thereby providing the reference voltage VREF to the first load terminal D of the load MOS transistor 252. The control signal LM_SW is supplied to the MOS transistor 2701 of the gate driving circuit 270 for turning on the third switch 2701. The gate driving circuit 270 supplies a data voltage VDATA to the control terminal G of the load MOS transistor 252 via the third switch 2701. The data voltage VDATA differs from the reference gate voltage VREF LM. The voltage at the Node C is also changed by the voltage difference (VREF LM-VDATA), and a capacitive ratio a between a capacitance Csampie of the sampling capacitor 2542 and a capacitance C_para of a parasitic capacitor 2542 (Cs_ampie/( C_sampie + C_para)) and amounts to VREF_LM - VTH LM + a (VREF_LM - VDATA). The control signal VSL_CUT supplied to the fourth switch 2801 disconnects the vertical signal line Vsl and pixels 200 from the load MOS transistor 252.

Referring to Figs. 5A and 5B, a third control period exemplified by Phase3 is described. In Phase3, the control signal EN_LM is supplied to the MOS transistor 2531 for turning on the MOS transistor 2531, and the control signal LM_SW is supplied to the MOS transistor 2701 of the gate driving circuit 270 for turning off the third switch or MOS transistor 2701. In Phase3, the control signal SEL BOT is supplied to MOS transistor 2601 of the reference voltage circuit 260 for turning off the MOS transistor 2601. The voltage at the node B depends on the voltage difference level to Node C, i.e. VREF_LM - VTH LM + a (VREF_LM - VDATA), and a capacitive dividing ratio p between a capacitance Csampie of the sampling capacitor 2542 and a capacitance C_para of a parasitic capacitor 2543 (C_sam_Pie/( C_sam_Pie + C_para)) and amounts to VDATA - (VREF_LM - VTH LM + a (VREF LM - VDATA)). Thus, the voltage at the Node B includes threshold information.

Referring to Figs. 6A and 6B, a fourth control period exemplified by Phase4 is described. In Phase4, similar to Phase3, the control signal EN_LM is supplied to the MOS transistor 2531 for turning on the MOS transistor 2531, and the control signal LM_SW is supplied to the MOS transistor 2701 of the gate driving circuit 270 for turning off the third switch 2701. During Phase4, pixel signals are read out. When the load MOS transistor 252 is operated in the strong-inversion region (e.g. load currents in the range of pA), the load current supplied by the load MOS transistor 252 amounts to I = 0.5 p_n C_ox (((VDATA - P (VREF_LM - VTH LM + a (VREF_LM - VDATA)- VTH L )², p_n being the mobility for electrons under the assumption that the load MOS transistor 252 is an n-channel FET, and C_ox being the gate oxide capacitance. When the capacitance C_sampie of the sampling capacitor 2541 is set much larger (e.g. more than a factor 100 or more than a factor 1000) than a than the capacitance C_para of the parasitic capacitors 2542, 2543, i.e. C_sampie » C_par_a, the capacitance ratios a and p are approximately 1, i.e. a = 1 and p = 1. This results in a load current I that is immune to threshold variations, i.e. I = 0.5 p_n C_ox (2 VDATA - 2 VREF LM)² based on the compensation circuit described in the examples herein. When the load MOS transistor 252 is operated in the sub-threshold- region region (e.g. load currents in the range of nA or pA), the load current supplied by the load MOS transistor 252 amounts to I =

[{VDATA-P{VREF_LM- VTH_LM+ UJVREF_LM-VDATA₎ \-VTH_LM\ -nV_{DS LM}+yV_{BS LM}( ^VDS_LM\ - - = - = — 1-e ^VT l_o e ' ' n being the slope factor,

VT being the thermal voltage, y being the substrate bias coefficient, VDS_LM being the drain-to-source voltage, and VBS LM being the bulk-to-source voltage. When the capacitance C_sampie of the sampling capacitor 2541 is set much larger (e.g. more than a factor 100 or more than a factor 1000) than a than the capacitance C_para of the parasitic capacitors 2542, 2543, i.e. C_sampie » C_para, the capacitance ratios a and p are approximately 1, i.e. a = 1 and p = 1. This results in a load current I that is immune to threshold variations, i.e. I = on the compensation circuit described in the examples herein. For illustration purpose, only those circuit elements of circuits/block are illustrated in Figs. 3A to 6A that are referred to for exemplifying the associated function. The reference voltage VREF may not only be supplied to Node A via the reference voltage circuit 260 in the bottom chip but may likewise be arranged in the top chip or another chip as illustrated by a fifth transistor 2901 that is controlled via a control signal SEL TOP.

A configuration example of an imaging apparatus 100 including the solid-state imaging element 200 described herein is illustrated in the block diagram illustrating a configuration example of an imaging apparatus according to the present technology. The imaging lens 110 collects light and guides the collected light to the solid-state imaging element 200. The imaging control unit 130 causes the solid-state imaging element 200 to capture image data. The imaging control unit 130 supplies, for example, an imaging control signal including a vertical synchronization signal VSYNC to the solid-state imaging element 200 via a signal line 139. The record unit 120 records the image data.

Here, the vertical synchronization signal VSYNC is a signal indicating the timing of imaging, and a cyclic signal having a fixed frequency (e.g., 60 Hertz) is used as the vertical synchronization signal VSYNC.

Note that, although the imaging apparatus 100 records image data, the image data may be transmitted to the outside of the imaging apparatus 100. In this case, an external interface for transmitting the image data is further provided. Alternatively, the imaging apparatus 100 may further display the image data. In this case, a display unit is further provided.

A configuration example of the solid-state imaging 200 element is given in Fig. 8. The solid-state imaging element 200 includes a vertical scanning circuit 211, a pixel array unit 212, a timing control circuit 213, a digital to analog converter (DAC) 214, a load MOS circuit block 250, and a column signal processing circuit 260. In the pixel array unit 212, a plurality of pixels 220 is arranged in a two-dimensional lattice shape. The load MOS circuit block 250 may be formed as described with reference to the examples described herein, see e.g. Figs. 1 and 2.

Hereinafter, a set of pixels 220 arranged in a horizontal direction is referred to as a “row”, and a set of pixels 220 arranged in a direction perpendicular to the row is referred to as a “column”.

The timing control circuit 213 controls the operation timing of each of the vertical scanning circuit 211, the DAC 214, and the column signal processing circuit 260 in synchronization with the vertical synchronization signal VSYNC from the imaging control unit 130.

The DAC 214 uses digital to analog (DA) conversion to generate an analog reference signal that changes with lapse of time. For example, a sawtooth ramp signal is used as a reference signal. The DAC 214 supplies the generated reference signal to the column signal processing circuit 260. The vertical scanning circuit 211 sequentially selects and drives the rows and outputs an analog pixel signal. The pixel 220 generates an analog pixel signal by photoelectrically converting incident light. The pixel 220 supplies a pixel signal to the column signal processing circuit 260 via the load MOS circuit block 250.

In the load MOS circuit block 250, a MOS transistor for supplying a constant current may be provided for each column.

The column signal processing circuit 260 executes signal processing such as AD conversion processing on pixel signals with respect to each column. The column signal processing circuit 260 supplies image data including the processed signal to the record unit 120. Note that the column signal processing circuit 260 is an example of the signal processing circuit described in the claims.

Fig. 9 is a circuit diagram illustrating a configuration example of the pixel 220 according to the first embodiment of the present technology. The pixel 220 includes a photodiode 221 , a transfer transistor 222, a reset transistor 223, a floating diffusion layer 224, an amplification transistor 225, and a selection transistor 226.

The photodiode 221 photoelectrically converts incident light and generates charges. The transfer transistor 222 transfers charges from the photodiode 221 to the floating diffusion layer 224 according to a transfer signal TX from the vertical scanning circuit 211. The reset transistor 223 initializes the charge amount of the floating diffusion layer 224 according to a reset signal RST from the vertical scanning circuit 211. The floating diffusion layer 224 accumulates charges and generates a voltage corresponding to the charge amount.

The amplification transistor 225 amplifies the signal of the voltage of the floating diffusion layer 224. The selection transistor 226 outputs the amplified signal as a pixel signal to the load MOS circuit block 250 via a vertical signal line Vsl according to the selection signal SEL from the vertical scanning circuit 211.

Note that the circuit of the pixel 220 is not limited to the configuration illustrated in the drawing as long as it can generate a pixel signal by photoelectric conversion. Although the pixel 220 adopting a 4-Tr configuration including four transistors, that is, the transfer transistor 222, the reset transistor 223, the amplification transistor 225, and the selection transistor 226 has been exemplified in the above-described circuit example, the present invention is not limited thereto. For example, a 3-Tr configuration in which the selection transistor 226 is omitted and the amplification transistor 225 also functions as the selection transistor 25 can also be adopted, and a 5-Tr, or 6-Tr, or more configurations in which the number of transistors is increased can also be adopted as necessary.

Fig. 10 is a block diagram illustrating a configuration example of the load MOS circuit block 250 and the column signal processing circuit 260 according to the the present technology.

In the load MOS circuit block 250, a vertical signal line is wired with respect to each column. When the number of columns is I (I is an integer), I vertical signal lines Vsl are wired. Furthermore, a load MOS circuit 251 for supplying a constant current is connected to each of the vertical signal lines Vsl. For example, the load MOS circuit 251 may be configured as described with reference to the examples described herein, see e.g. Figs. 1 and 2.

A plurality of ADCs 300 and a digital signal processing unit 261 are arranged in the column signal processing circuit 260. The ADC 300 is arranged for each column. When the number of columns is I, I ADCs 300 are arranged. Note that although the column ADC method in which the ADC 300 is arranged for each column is used, the ADC is not limited to this configuration. For example, the ADC 300 may be arranged for each pixel.

The ADC 300 converts the analog pixel signal from the corresponding column into a digital signal using the reference signal (ramp signal Rmp or the like) from the DAC 214. The ADC 300 supplies the digital signal to the digital signal processing unit 261.

The digital signal processing unit 261 performs predetermined signal processing on each digital signal for each column. The details of the processing content will be described later. The digital signal processing unit 261 supplies image data including the processed digital signal to the record unit 120.

As a semiconductor chip structure of the solid-state imaging element 200, e.g. CMOS image sensor, having the above-described configuration, a flat semiconductor chip structure and a stacked semiconductor chip structure may be used. Furthermore, regarding a pixel structure, assuming that a substrate surface on a side on which a wiring layer is formed is defined as a front surface (front), it is possible to adopt a back surface irradiation pixel structure which captures light irradiated from a back surface side on the opposite side, or a front surface irradiation pixel structure which captures light irradiated from the front surface side.

Hereinafter, an outline of the flat semiconductor chip structure and the stacked semiconductor chip structure will be described.

Fig. 11A is a perspective view schematically depicting the flat chip structure of the solid-state imaging element 200 exemplified as a CMOS image sensor 1. As depicted in Fig. 11A, the flat semiconductor chip structure has a structure in which the respective constituent elements of a peripheral circuit section of the pixel array section 11 are formed on the same semiconductor substrate or chip 41 as a pixel array section 11 in which the pixels (pixel circuits) 220 are arranged in a matrix. Specifically, a row selection section 12, an analog -to-digital conversion section 13, a logic circuit section 14, a timing control section 15, and the like are formed on the same semiconductor substrate or chip 41 as the pixel array section 11. Pads 42 for external connection and power supply are provided, for example, at both left and right ends of the semiconductor substrate or chip 41. The pixel array section 11 may include the pixel array 212 as described in the examples herein.

Hereinafter, an outline of the stacked semiconductor chip structure will be described. FIG. 1 IB is an exploded perspective view schematically depicting the stacked semiconductor chip structure of the solid-state imaging element 200 exemplified as a CMOS image sensor 1. As depicted in FIG. 1 IB, the stacked semiconductor chip structure, that is, the stacked structure has a structure in which at least two semiconductor chips of a first semiconductor chip 43 and a second semiconductor chip 44 are stacked.

In this stacked semiconductor chip structure, the first semiconductor chip 43 is a pixel chip in which the pixel array section 11 in which the pixels 200 including photoelectric conversion elements (for example, photodiodes) are two-dimensionally arranged in a matrix is formed. The pads 42 for external connection and power supply are provided, for example, at both left and right ends of the first semiconductor chip 43.

The second semiconductor chip 44 is a circuit chip in which the peripheral circuit section of the pixel array section 11, that is, the row selection section 12, the analog -to-digital conversion section 13, the logic circuit section 14, the timing control section 15, and the like are formed. Note that the arrangement of the row selection section 12, the analog-to-digital conversion section 13, the logic circuit section 14, and the timing control section 15 is an example, and is not limited to this arrangement example. For example, the load transistor circuit block 250 described in the examples herein may be arranged in the second semiconductor chip 44.

The pixel array section 11 on the first semiconductor chip 43 and the peripheral circuit section on the second semiconductor chip 44 are electrically connected via junction portions 72 and 73 including a metal-metal junction including a Cu-Cu junction, a through silicon via (TSV), a micro-bump, and the like.

According to the stacked semiconductor chip structure described above, a process suitable for manufacturing the pixel array section 11 can be applied to the first semiconductor chip 43, and a process suitable for manufacturing the circuit part can be applied to the second semiconductor chip 44. Therefore, the processes can be optimized in manufacturing the CMOS image sensor 1. In particular, an advanced process can be applied to manufacture the circuit part.

Examples of Application will be described below. The solid-state imaging elements according to the examples described above can be used for various devices that sense light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as depicted in FIG. 12. Specific examples of the various devices are listed hereinafter: i) A device that captures an image for use in viewing, such as a digital camera or a portable device equipped with a camera function. ii) A device used in transportation, such as a vehicle-mounted sensor that captures images of a front, a rear, surroundings, an interior, and the like of a vehicle, a monitoring camera that monitors traveling vehicles and roads, or a range-finding sensor that measures a distance between vehicles and the like, for safety driving such as automatic stop, recognition of a state of a driver state, and the like iii) A device used for home appliances such as a TV, a refrigerator, and an air conditioner, to capture an image of a gesture of a user and operate such an appliance in accordance with the gesture. iv) A device used for medical care and health care, such as an endoscope or a device that performs angiography by receiving infrared light. v) A device used for security, such as a monitoring camera for a crime prevention application or a camera for a person authentication application. vi) A device used for beauty care, such as a skin measuring instrument that captures an image of a skin or a microscope that captures an image of a scalp. vi) A device used for sports, such as an action camera or a wearable camera for sports applications and the like vii) A device used for agriculture, such as a camera for monitoring states of fields and crops.

The technology according to the present disclosure may be realized in a light receiving device mounted in a mobile body of any type such as automobile, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility, airplane, drone, ship, or robot.

The technology according to the present disclosure (present technology) is applicable to a variety of products. For example, the technology according to the present disclosure may be implemented as apparatuses mounted on any type of movable bodies such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobilities, airplanes, drones, ships, or robots.

Fig. 13 is a block diagram illustrating a schematic configuration example of a vehicle control system, which is an example of a movable body control system to which the technology according to the present disclosure can be applied.

The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example illustrated in Fig. 29, the vehicle control system 12000 includes a drive line control unit 12010, a body system control unit 12020, a vehicle outside information detecting unit 12030, a vehicle inside information detecting unit 12040, and an integrated control unit 12050. Furthermore, a microcomputer 12051, an audio and image output unit 12052, and an in-vehicle network interface (I/F) 12053 are illustrated as functional configurations of the integrated control unit 12050.

The drive line control unit 12010 controls the operation of apparatuses related to the drive line of the vehicle in accordance with a variety of programs. For example, the drive line control unit 12010 functions as a control apparatus for a driving force generating apparatus such as an internal combustion engine or a driving motor that generates the driving force of the vehicle, a driving force transferring mechanism that transfers the driving force to wheels, a steering mechanism that adjusts the steering angle of the vehicle, a braking apparatus that generates the braking force of the vehicle, and the like.

The body system control unit 12020 controls the operations of a variety of apparatuses attached to the vehicle body in accordance with a variety of programs. For example, the body system control unit 12020 functions as a control apparatus for a keyless entry system, a smart key system, a power window apparatus, or a variety of lights such as a headlight, a backup light, a brake light, a blinker, or a fog lamp. In this case, the body system control unit 12020 can receive radio waves transmitted from a portable device that serves instead of the key or signals of a variety of switches. The body system control unit 12020 accepts input of these radio waves or signals, and controls the door lock apparatus, the power window apparatus, the lights, or the like of the vehicle.

The vehicle outside information detecting unit 12030 detects information regarding the outside of the vehicle including the vehicle control system 12000. For example, the imaging unit 12031 is connected to the vehicle outside information detecting unit 12030. The vehicle outside information detecting unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle, and receives the captured image. The vehicle outside information detecting unit 12030 may perform processing of detecting an object such as a person, a car, an obstacle, a traffic sign, or a letter on a road, or processing of detecting the distance on the basis of the received image.

The imaging unit 12031 is an optical sensorthat receives light and outputs an electric signal corresponding to the amount of received light. The imaging unit 12031 can output the electric signal as the image or output the electric signal as ranging information. Furthermore, the light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

The vehicle inside information detecting unit 12040 detects information of the inside of the vehicle. The vehicle inside information detecting unit 12040 is connected, for example, to a driver state detecting unit 12041 that detects the state of the driver. The driver state detecting unit 12041 includes, for example, a camera that images a driver, and the vehicle inside information detecting unit 12040 may compute the degree of the driver's tiredness or the degree of the driver's concentration or determine whether or not the driver has a doze, on the basis of detection information input from the driver state detecting unit 12041.

The microcomputer 12051 can calculate a control target value of the driving force generating apparatus, the steering mechanism, or the braking apparatus on the basis of information regarding the inside and outside of the vehicle acquired by the vehicle outside information detecting unit 12030 or the vehicle inside information detecting unit 12040 and output a control instruction to the drive line control unit 12010. For example, the microcomputer 12051 can perform cooperative control for the purpose of executing the functions of the advanced driver assistance system (ADAS) including vehicle collision avoidance or impact reduction, follow-up driving based on the inter-vehicle distance, constant vehicle speed driving, vehicle collision warning, vehicle lane deviation warning, or the like. Furthermore, the microcomputer 12051 can perform cooperative control for the purpose of automatic driving or the like for autonomous running without depending on the driver’s manipulation through control of the driving force generating apparatus, the steering mechanism, the braking apparatus, or the like on the basis of information around the vehicle acquired by the vehicle outside information detecting unit 12030 or the vehicle inside information detecting unit 12040.

Furthermore, the microcomputer 12051 can output a control instruction to the body system control unit 12020 on the basis of the information outside the vehicle obtained by the vehicle outside information detecting unit 12030. For example, the microcomputer 12051 can perform the cooperative control for realizing glare protection such as controlling the head light according to a position of a preceding vehicle or an oncoming vehicle detected by the vehicle outside information detecting unit 12030 to switch a high beam to a low beam.

The audio and image output unit 12052 transmits an output signal of at least one of a sound or an image to an output apparatus capable of visually or aurally notifying a passenger of the vehicle or the outside of the vehicle of information. In the example of Fig. 29, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as the output apparatus. For example, the display unit 12062 may include at least one of an onboard display or a head-up display.

Fig. 14 is a view illustrating an example of an installation position of the imaging unit 12031.

In Fig. 14, imaging units 12101, 12102, 12103, 12104, and 12105 are provided as the imaging unit 12031.

Imaging units 12101, 12102, 12103, 12104 and 12105 are positioned, for example, at the front nose, a side mirror, the rear bumper, the back door, the upper part of the windshield in the vehicle compartment, or the like of the vehicle 12100. The imaging unit 12101 attached to the front nose and the imaging unit 12105 attached to the upper part of the windshield in the vehicle compartment mainly acquire images of the area ahead of the vehicle 12100. The imaging units 12102 and 12103 attached to the side mirrors mainly acquire images of the areas on the sides of the vehicle 12100. The imaging unit 12104 attached to the rear bumper or the back door mainly acquires images of the area behind the vehicle 12100. The imaging unit 12105 attached to the upper part of the windshield in the vehicle compartment is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

Note that Fig. 14 illustrates an example of the respective imaging ranges of the imaging units 12101 to 12104. An imaging range 12111 represents the imaging range of the imaging unit 12101 attached to the front nose. Imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging units 12102 and 12103 attached to the side mirrors. An imaging range 12114 represents the imaging range of the imaging unit 12104 attached to the rear bumper or the back door. For example, overlaying image data captured by the imaging units 12101 to 12104 offers an overhead image that looks down on the vehicle 12100. At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of image sensors, or may be an image sensor having pixels for phase difference detection.

For example, the microcomputer 12051 may extract especially a closest three-dimensional object on a traveling path of the vehicle 12100, the three-dimensional object traveling at a predetermined speed (for example, 0 km/h or higher) in a direction substantially the same as that of the vehicle 12100 as the preceding vehicle by determining a distance to each three-dimensional object in the imaging ranges 12111 to 12114 and change in time of the distance (relative speed relative to the vehicle 12100) on the basis of the distance information obtained from the imaging units 12101 to 12104. Moreover, the microcomputer 12051 can set an inter-vehicle distance to be secured in advance from the preceding vehicle, and can perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. In this manner, it is possible to perform the cooperative control for realizing automatic driving or the like to autonomously travel independent from the manipulation of the driver.

For example, the microcomputer 12051 can extract three-dimensional object data regarding the three- dimensional object while sorting the data into a two-wheeled vehicle, a regular vehicle, a large vehicle, a pedestrian, and other three-dimensional object such as a utility pole on the basis of the distance information obtained from the imaging units 12101 to 12104 and use the data for automatically avoiding obstacles. For example, the microcomputer 12051 discriminates obstacles around the vehicle 12100 into an obstacle visibly recognizable to a driver of the vehicle 12100 and an obstacle difficult to visually recognize. Then, the microcomputer 12051 determines a collision risk indicating a degree of risk of collision with each obstacle, and when the collision risk is equal to or higher than a setting value and there is a possibility of collision, the microcomputer 12051 can perform driving assistance for avoiding the collision by outputting an alarm to the driver via the audio speaker 12061 and the display unit 12062 or performing forced deceleration or avoidance steering via the drive line control unit 12010.

At least one of the imaging units 12101 to 12104 may be an infrared camera for detecting infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not there is a pedestrian in the captured images of the imaging units 12101 to 12104. Such pedestrian recognition is carried out, for example, by a procedure of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras and a procedure of performing pattern matching processing on a series of feature points indicating an outline of an object to discriminate whether or not the object is a pedestrian. When the microcomputer 12051 determines that there is a pedestrian in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio and image output unit 12052 causes the display unit 12062 to superimpose a rectangular contour for emphasis on the recognized pedestrian. Furthermore, the audio and image output unit 12052 may causes the display unit 12062 to display icons or the like indicating pedestrians at desired positions.

An example of the vehicle control system to which the technology according to the present disclosure is applicable is heretofore described. The technology according to the present disclosure can be applied to the imaging unit 12031 among the configurations described above. Specifically, the solid-state imaging elements 200 described herein, e.g. included in the imaging apparatus 100 of Fig. 7, can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, the speed of reading the image data can be increased and a moving image that is more viewable can be obtained, and thus driver fatigue can be reduced.

Note that the effects described in the present description are merely illustrative and are not limitative, and other effects may be provided. The present technology can also be configured as described below:

[1] A solid-state imaging element (200), comprising: a pixel array (212) including a plurality of pixels (220), wherein each of the plurality of pixels (220) is configured to output a pixel signal to a signal line (Vsl); a load transistor circuit block (250) configured to supply a current to the signal line (Vsl), wherein the load transistor circuit block (250) includes: a load MOS transistor (252) including a first load terminal (D) electrically coupled to the signal line (Vsl), a control terminal (G), and a second load terminal (S); and a compensation circuit including a first switch (253) electrically coupled to the second load terminal (S) of the load MOS transistor (252), and a sampling element (254) electrically coupled between the control terminal (G) of the load MOS transistor (252) and the second load terminal (S) of the load MOS transistor (252).

[2] The solid-state imaging element (200) of [1] above, wherein the sampling element (254) is a capacitor (2541).

[3] The solid-state imaging element (200) of [2] above, wherein the capacitor (2541) has a capacitance value in a range from tens of fF to hundreds of fF.

[4] The solid-state imaging element (200) of any of [1] to [3] above, wherein the first switch (253) is a MOS transistor (2531) having a same channel conductivity type as the load MOS transistor (252).

[5] The solid-state imaging element (200) of [4] above, wherein a chip area of the MOS transistor (2531) is smaller than 10% of a chip area of the load MOS transistor (252).

[6] The solid-state imaging element (200) of any of [1] to [5] above, further comprising a first chip (43) including the pixel array (212), and a second chip (44) including the load transistor circuit block (250).

[7] The solid-state imaging element (200) of any of [1] to [6] above, further comprising a reference voltage circuit (260) configured to supply a load reference voltage (VREF) to the first load terminal (D) of the load MOS transistor (252) via a second switch (2601).

[8] The solid-state imaging element (200) of [7] above, further comprising a gate driving circuit (270) configured to supply a gate voltage to the control terminal (G) of the load MOS transistor (252) via a third switch (2701). [9] The solid-state imaging element (200) of [8] above, further comprising a control circuit configured to supply control signals (SEL_BOT, LM_SW, EN_LM) to the first switch (253), the second switch (2601), and the third switch (2701).

[10] The solid-state imaging element (200) of [9] above, wherein, during a first control period (Phasel), the control circuit is configured to supply a control signal (EN_LM) to the first switch (253) of the load transistor circuit block (250) for turning off the first switch (253), and to further supply a control signal (SEL_BOT) to the second switch (2601) of the reference voltage circuit (260) for turning on the second switch (2601), and to further supply a control signal (LM_SW) to the third switch (2701 ) of the gate driving circuit (270) for turning on the third switch (2601), and wherein, during the first phase, the gate driving circuit (270) is configured to supply a reference gate voltage (VREF _LM) to the control terminal (G) of the load MOS transistor (252) via the third switch (2701).

[11] The solid-state imaging element (200) of any of [9] to [10] above, wherein, during a second control period (Phase2), the control circuit is configured to supply a control signal (EN_LM) to the first switch (253) of the load transistor circuit block (250) for turning off the first switch (253), and to further supply a control signal (SEL_BOT) to the second switch (2601) of the reference voltage circuit (260) for turning on the second switch (2601), and to further supply a control signal (LM_SW) to the third switch (2701) of the gate driving circuit (270) for turning on the third switch (2601), and wherein, during the second control period (Phase2), the gate driving circuit (270) is configured to supply a voltage (VDATA) to the control terminal (G) of the load MOS transistor (252) via the third switch (2701) that differs from the reference gate voltage (VREF_LM) .

[12] The solid-state imaging element (200) of any of [9] to [11] above, wherein, during a third control period (Phase3), the control circuit is configured to supply a control signal (EN_LM) to the first switch (253) of the load transistor circuit block (250) for turning on the first switch (253), and to further supply a control signal (SEL_BOT) to the second switch (2601) of the reference voltage circuit (260) for turning off the second switch (2601), and to further supply a control signal (LM_SW) to the third switch (2701) of the gate driving circuit (270) for turning off the third switch (2601).

[13] The solid-state imaging element (200) of any of [9] to [12] above, wherein, during a fourth control period (Phase ), the control circuit (270) is configured to supply a control signal (EN_LM) to the first switch (253) of the load transistor circuit block (250) for turning on the first switch (253), and to further supply a control signal (SEL_BOT) to the second switch (2601) of the reference voltage circuit (260) for turning off the second switch (2601), and to further supply a control signal (LM_SW) to the third switch (2701) of the gate driving circuit (270) for turning off the third switch (2601), and wherein the control circuit is further configured to initiate read-out of the pixel signal during the fourth control period (Phased).

[14] The solid-state imaging element (200) of any of [1] to [13] above, further comprising a fourth switch (282), wherein the signal line (Vsl) is electrically coupled to the first load terminal (D) of the load MOS transistor (252) via the fourth switch (282). [15] The solid-state imaging element (200) of [14] above, wherein, during the first and second control periods (Phase 1, Phase2), the control circuit is configured to supply a control signal (VSL CUT) to the fourth switch (282) for turning off the fourth switch (282), and, during the third and fourth control periods (Phase3, Phase ), the control circuit (270) is configured to supply a control signal (VSL_CUT) to the fourth switch (282) for turning on the fourth switch (282).

Claims

1. A solid-state imaging element, comprising: a pixel array including a plurality of pixels, wherein each of the plurality of pixels is configured to output a pixel signal to a signal line; a load transistor circuit block configured to supply a current to the signal line, wherein the load transistor circuit block includes: a load MOS transistor including a first load terminal electrically coupled to the signal line, a control terminal, and a second load terminal; and a compensation circuit including a first switch electrically coupled to the second load terminal of the load MOS transistor, and a sampling element electrically coupled between the control terminal of the load MOS transistor and the second load terminal of the load MOS transistor.

2. The solid-state imaging element of the preceding claim, wherein the sampling element is a capacitor.

3. The solid-state imaging element of the preceding claim, wherein the capacitor has a capacitance value in a range from tens of fF to hundreds of fF.

4. The solid-state imaging element of claim 1, wherein the first switch is a MOS transistor having a same channel conductivity type as the load MOS transistor.

5. The solid-state imaging element of the preceding claim, wherein a chip area of the MOS transistor is smaller than 10% of a chip area of the load MOS transistor.

6. The solid-state imaging element of claim 1, further comprising a first chip including the pixel array, and a second chip including the load transistor circuit block.

7. The solid-state imaging element of claim 1, further comprising a reference voltage circuit configured to supply a load reference voltage to the first load terminal of the load MOS transistor via a second switch.

8. The solid-state imaging element of the preceding claim, further comprising a gate driving circuit configured to supply a gate voltage to the control terminal of the load MOS transistor via a third switch.

9. The solid-state imaging element of the preceding claim, further comprising a control circuit configured to supply control signals to the first switch, the second switch, and the third switch.

10. The solid-state imaging element of the preceding claim, wherein, during a first control period, the control circuit is configured to supply a control signal to the first switch of the load transistor circuit block for turning off the first switch, and to further supply a control signal to the second switch of the reference voltage circuit for turning on the second switch, and to further supply a control signal to the third switch of the gate driving circuit for turning on the third switch, and wherein, during the first phase, the gate driving circuit is configured to supply a reference gate voltage to the control terminal of the load MOS transistor via the third switch.

11. The solid-state imaging element of the preceding claim, wherein, during a second control period, the control circuit is configured to supply a control signal to the first switch of the load transistor circuit block for turning off the first switch, and to further supply a control signal to the second switch of the reference voltage circuit for turning on the second switch, and to further supply a control signal to the third switch of the gate driving circuit for turning on the third switch, and wherein, during the second control period, the gate driving circuit is configured to supply a voltage to the control terminal of the load MOS transistor via the third switch that differs from the reference gate voltage.

12. The solid-state imaging element of the preceding claim, wherein, during a third control period, the control circuit is configured to supply a control signal to the first switch of the load transistor circuit block for turning on the first switch, and to further supply a control signal to the second switch of the reference voltage circuit for turning off the second switch, and to further supply a control signal to the third switch of the gate driving circuit for turning off the third switch.

13. The solid-state imaging element of the preceding claim, wherein, during a fourth control period, the control circuit is configured to supply a control signal to the first switch of the load transistor circuit block for turning on the first switch, and to further supply a control signal to the second switch of the reference voltage circuit for turning off the second switch, and to further supply a control signal to the third switch of the gate driving circuit for turning off the third switch, and wherein the control circuit is further configured to initiate read-out of the pixel signal during the fourth control period.

14. The solid-state imaging element of claim 1, further comprising a fourth switch, wherein the signal line is electrically coupled to the first load terminal of the load MOS transistor via the fourth switch.

15. The solid-state imaging element of the preceding claim, wherein, during the first and second control periods, the control circuit is configured to supply a control signal to the fourth switch for turning off the fourth switch, and, during the third and fourth control periods, the control circuit is configured to supply a control signal to the fourth switch for turning on the fourth switch.