WO2025190898A1

WO2025190898A1 - Toggle flipflop circuitry, ripple counter circuitry and image sensor

Info

Publication number: WO2025190898A1
Application number: PCT/EP2025/056531
Authority: WO
Inventors: Matteo Perenzoni
Original assignee: Sony Europe Bv; Sony Semiconductor Solutions Corp
Current assignee: Sony Europe Bv; Sony Semiconductor Solutions Corp
Priority date: 2024-03-12
Filing date: 2025-03-11
Publication date: 2025-09-18
Anticipated expiration: 2026-09-12

Abstract

The disclosure pertains to a toggle flipflop circuitry that includes: a first count switch that is configured to couple an input node to a first output node during a first count signal level, wherein the first count switch is configured to retard a path signal propagation from the first output node to the input node by a predetermined delay; a first inverter that is configured to couple a second output node to the first output node; a first switchable active feedback loop that is configured to selectively propagate a path signal from the input node to the first output node during the first count signal level; a second switchable active feedback loop that is configured to propagate a negation of a path signal from the second output node to the first output node during a second count signal level different from the first count signal level; and a second count switch that is configured to selectively couple the input node to the second output node during the second count signal level.

Description

TOGGLE FLIPFLOP CIRCUITRY, RIPPLE COUNTER CIRCUITRY AND

IMAGE SENSOR

TECHNICAL FIELD

The present disclosure generally pertains to a toggle flipflop circuitry, a ripple counter circuitry and an image sensor.

TECHNICAL BACKGROUND

It is generally known to count photons detected by a single-photon avalanche diode (SPAD) with a ripple counter that includes toggle flipflops. It is further known to include the ripple counter in an image sensor for counting photons detected by the image sensor.

Although there exist techniques for a toggle flipflop, it is generally desirable to provide an improved toggle flipflop circuitry, ripple counter circuitry and image sensor.

SUMMARY

According to a first aspect, the disclosure provides a toggle flipflop circuitry that includes: a first count switch that is configured to couple an input node to a first output node during a first count signal level, wherein the first count switch is configured to retard a path signal propagation from the first output node to the input node by a predetermined delay; a first inverter that is configured to couple a second output node to the first output node; a first switchable active feedback loop that is configured to selectively propagate a path signal from the input node to the first output node during the first count signal level; a second switchable active feedback loop that is configured to propagate a negation of a path signal from the second output node to the first output node during a second count signal level different from the first count signal level; and a second count switch that is configured to selectively couple the input node to the second output node during the second count signal level.

According to a second aspect, the disclosure provides a ripple counter circuitry that includes: a first toggle flipflop circuitry according to the first aspect; and a second toggle flipflop circuitry according to the first aspect; wherein the ripple counter circuitry is configured to: provide a ripple signal as a count signal to the first toggle flipflop circuitry; and provide a path signal from one of the first output node of the first toggle flipflop circuitry and the second output node of the first toggle flipflop circuitry as a count signal to the second toggle flipflop circuitry. According to a third aspect, the disclosure provides an image sensor that includes: the ripple counter circuitry according to the second aspect; and a photosensitive element that is configured to detect single photons; wherein the ripple counter circuitry is configured to receive, from the photosensitive element, a photon detection signal as the ripple signal.

Further aspects are set forth in the dependent claims, the drawings and the following description.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments are explained by way of example with respect to the accompanying drawings, in which:

Fig. 1 illustrates an embodiment of an image sensor;

Fig. 2 illustrates an embodiment of a counter array;

Fig. 3 illustrates an embodiment of a ripple counter circuitry;

Fig. 4 illustrates an example of a static toggle flipflop circuitry;

Fig. 5 illustrates an example of a dynamic toggle flipflop circuitry;

Fig. 6 illustrates a first embodiment of a toggle flipflop circuitry;

Fig. 7 illustrates embodiments of switch implementations;

Fig. 8 illustrates an embodiment of signal time courses in a toggle flipflop circuitry;

Fig. 9 illustrates a second embodiment of a toggle flipflop circuitry;

Fig. 10 illustrates a difference between a parallel and a serial coupling of a PMOS transistor and an NMOS transistor according to an embodiment;

Fig. 11 illustrates a third embodiment of a toggle flipflop circuitry;

Fig. 12 illustrates embodiments of a coupling of transistors;

Fig. 13 illustrates a fourth embodiment of a toggle flipflop circuitry;

Fig. 14 illustrates a fifth embodiment of a toggle flipflop circuitry;

Fig. 15 illustrates a sixth embodiment of a toggle flipflop circuitry;

Fig. 16 illustrates a seventh embodiment of a toggle flipflop circuitry; and

Fig. 17 illustrates an eighth embodiment of a toggle flipflop circuitry. DETAILED DESCRIPTION OF EMBODIMENTS

As mentioned in the outset, photons detected by a single-photon avalanche diode (SPAD) may be counted with a ripple counter that includes toggle flipflops, and the ripple counter may be included in an image sensor for counting photons detected by the image sensor.

For example, the ripple counter may be included in a photon counting or quanta burst imaging device that has an array of SPAD-based photosensitive elements (pixels). The pixels may require some form of counting, e.g., per pixel and/or per macropixel (group of pixels).

For example, the ripple-counter may be included in a real-time updatable histogram. The realtime updatable histogram may include arrays of ripple counters that may be addressed and incremented. The real-time updatable histogram may, for example, be included in a direct time- of-flight (dToF) sensor.

Fig. 1 illustrates an embodiment of an image sensor 10. The image sensor 10 is configured as a photon counting device for a quanta burst imaging (QB I) device and includes a plurality of photosensitive elements that are arranged in a two-dimensional (2D) array.

Each photosensitive element includes a SPAD 11 and a circuit section 12. The circuit section 12 includes a ripple counter circuit 13 and may further include a quenching circuit, a time-to-digital converter (TDC) etc.

The SPAD 11 is configured to detect single photons and to generate a photon detection signal (e.g., an electrical signal) that indicates a detected photon as a ripple (e.g., peak). The ripple counter circuit 13 is configured to receive the photon detection signal as a ripple signal and to count the ripples (i.e., the detected photons).

The photosensitive elements may be configured as devices that are able to be sensitive to a single photon and to produce an informative signal for such a detection. The photosensitive elements of the image sensor 10 include, in some embodiments, a jot that may or may not include the SPAD 11.

The image sensor 10 is, in some embodiments, configured as a direct time-of-flight (dToF) sensor (in addition or alternatively to a QBI sensor), wherein each ripple counter circuit 13 is configured to receive, from the corresponding SPAD 11 (jot), a photon detection signal as the ripple signal. For example, the image sensor 10 may include a plurality of ripple counter circuits 13 per photosensitive element, wherein each of the plurality of ripple counter circuits 13 may be associated with a predefined histogram bin (time slot) and may be configured to count photons detected by the corresponding photosensitive element within the predefined histogram bin. For example, the image sensor 10 may include a counter array.

Fig. 2 illustrates an embodiment of a counter array 20. The counter array 20 is configured as a histogram array, e.g., for a dToF sensor and/or for general counting applications. The counter array 20 includes a plurality of ripple counter circuits 21 arranged in 2D, a count signal generation circuit 22 and a readout circuit 23.

The count signal generation circuit 22 generates count signals. The count signals are configured as ripple signals in which each ripple (e.g., peak) represents an event that should be counted. The events represented by the ripples may correspond to detected photons, detected light pulses, clock cycles, current peaks, voltage peaks, etc.

The ripple counter circuits 21 are configured to receive the count signal and to count the ripples (events) of the count signal. For example, each ripple counter circuit 21 may be associated with a certain photosensitive element (e.g., pixel; e.g., SPAD or jot) and/or time slot (e.g., histogram bin), may receive from the count signal generation circuit 22 a count signal that corresponds to the associated photosensitive element and/or time slot, and may count events represented by this count signal.

The readout circuit 23 reads out the event counts from the ripple counter circuits 21 for further processing.

However, the counter array 20 is not limited to a histogram array and may be generally used as a counter array.

Fig. 3 illustrates an embodiment of a ripple counter circuitry 30. The ripple counter circuitry 30 is an example of the ripple counter circuits 13 of Fig. 1 and of the ripple counter circuits 21 of Fig. 2.

The ripple counter circuitry 30 includes toggle flipflops 31 to 33. A number of toggleflipflops 31 to 33 corresponds to a bit depth of the ripple counter circuitry 30. Each toggle flipflop 31 to 33 can have a logical high state or a logical low state and represents one bit. Each toggle flipflop 31 to 33 outputs a value that corresponds to its current state (logical high or logical low) at an output labeled “Q”, and outputs a value that corresponds to a negation (logical inversion) of its current state at a negated output labeled “Q”. I.e., if a current state of a toggle flipflop 31 to 33 corresponds to logical high (which may, e.g., correspond to logical 1), the toggle flipflop 31 to 33 outputs logical high at Q and outputs logical low at Q, and if a current state of a toggle flipflop 31 to 33 corresponds to logical low (which may, e.g., correspond to logical 0), the toggle flipflop 31 to 33 outputs logical low at Q and outputs logical high at Q.

The toggle flipflops 31 to 33 further have a count (e.g., clock) signal input (marked with a triangle in Fig. 3) to which a count signal is inputted, and a negated count signal input (marked with a triangle and a circle in Fig. 3) to which a negation of the count signal is inputted. When the count signal performs a predefined change (e.g., switches from logical low to logical high (rising edge), or switches from logical high to logical low (falling edge), a so-called positive or negative edge-triggered flipflop, respectively), the toggle flipflop 31 to 33 changes its current state (from logical low to logical high, or from logical high to logical low) and, thus, toggles its state between logical low and logical high based on the count signal.

The toggle flipflops 31 to 33 also have a negated reset input (labeled as “R” and with a circle). When a predefined value (e.g., logical low or logical high) is inputted at R, the current state of the toggle flipflop 31 to 33 is reset to a predefined state (e.g., to a negation of the value inputted at R, e.g., logical high or logical low). Thus, via the reset input R, a count value stored in the ripple counter circuitry 30 can be erased and the toggle flipflops 31 to 33 can be initialized for a new counting period. For example, initializing the toggle flipflops 31 to 33 may cause the ripple counter circuitry 30 to represent a count value of zero. It is noted that, in some embodiments, the toggle-flipflops 31 to 33 have a non-negated reset input instead of or in addition to the negated reset input R.

For example, the ripple counter circuitry 30 provides a ripple signal 35 as a count signal to the count signal input of the toggle flipflop 31 and provides a negation 36 of the ripple signal 35 as a negated count signal to the negated count signal input of the toggle flipflop 31.

The ripple signal 35 indicates events that should be counted (e.g., detected photons) as ripples (e.g., transient changes of a value indicated by the count signal). For example, when a SPAD associated with the ripple counter circuitry 30 detects a photon, the count signal 35 changes from logical high to logical low, and when an avalanche current in the SPAD is quenched, the count signal 35 changes back from logical low to logical high. Thus, when the count signal 35 changes back to logical high (rising edge of a ripple) after the SPAD has detected a photon, the toggle flipflop 31 toggles its state as well as its output Q and its negated output Q.

The output Q of the toggle flipflop 31 or 32 is connected to the negated input of the respective subsequent toggle flipflop 32 or 33, and the negated output Q of the toggle flipflop 31 or 32 is connected to the input of the respective subsequent toggle flipflop 32 or 33. Therefore, the ripple counter circuitry 30 is configured to provide a path signal from the output Q of the toggle flipflop 31 as a negated count signal to the toggle flipflop 32, and to provide a path signal from the negated output Q of the toggle flipflop 31 as a count signal to the toggle flipflop 32.

For example, if the toggle flipflops 31 to 33 are reset to logical 0 (e.g., logical low) and the count signal 35 indicates a ripple (e.g., detected photon), the toggle flipflop 31 switches its state to logical 1 (e.g., logical high), while the toggle flipflops 32 to 33 keep the state of logical 0. Thus, the ripple counter circuitry 30 represents a count value of one, with the toggle flipflop 31 representing a least significant bit. When the count signal 35 then indicates a second ripple (e.g., detected photon), the toggle flipflop 31 switches its state back to logical 0 accordingly, which in turn causes the toggle flipflop 32 to switch its state to logical 1, while the toggle flipflop 33 keeps the state of logical 0. Thus, the ripple counter circuitry 30 represents a count value of two.

This way, the ripple counter circuitry 30 counts, based on the toggle flipflops 31 to 33, the number of ripples represented by the count signal 35.

Examples of the toggle flipflops 31 to 33 include the toggle flipflop circuitries 100, 120, 130, 140, 150, 160, 170 and 180 described below.

In some embodiments, applications (e.g., photon counting in image sensors with a single-photon avalanche diode (SPAD)) require implementation of integrated digital counters in a very small area. There may be a tradeoff between area requirements and a bit depth of a counter. For example, a higher bit depth may require more toggle flipflops, which may occupy a larger area.

Toggle flipflops may be configured as dynamic circuits or as static circuits. While in a static circuit, all nodes may be actively maintained at a defined potential in both states of the toggle flipflop, a dynamic circuit may include a node that is disconnected from a defined potential in a state of the toggle flipflop.

In some embodiments, a relatively long retention time (e.g., due to a long exposure time) prohibits the use of dynamic circuits because dynamic circuits, even if they may be very small, may lose the counting state due to leakage, which may be even worse in circuits exposed to light. In some embodiments, a counter is also used in other area-critical, toggle-flipflop intensive circuits like automatically updating histograms that include counter arrays.

Fig. 4 illustrates an example of a static toggle flipflop circuitry 40. In Fig. 4, “CK” denotes a count signal input, “CKn” denotes a negated count signal input, “Q” denotes an output, “Qn” denotes a negated output, “Rn” denotes a negated reset input, and “D” denotes a data input.

The static toggle flipflop circuitry 40 may be used as part of a ripple counter. It is configured as a D-flipflop, wherein Qn is fed back into the data input D. To save area, extra buffers are removed. The static toggle flipflop circuitry 40 has a transistor count of 20 MOSFETs (metal-oxide- semiconductor field-effect transistors). For example, each inverter may include two MOSFETs and each NOR gate may include four MOSFETs.

Fig. 5 illustrates an example of a dynamic toggle flipflop circuitry 50. “CK” denotes a count signal input, “CKn” denotes a negated count signal input, “Q” denotes an output, “Qn” denotes a negated output, and “Rn” denotes a negated reset input.

The dynamic toggle flipflop circuitry 50 provides a very small implementation of a toggle flipflop, potentially requiring only 13 MOSFETs (when assuming that each inverter includes two MOSFETs). Thus, the dynamic toggle flipflop circuitry 50 occupies less area than the static toggle flipflop circuitry 40 (if a same MOSFET size is used for the dynamic toggle flipflop circuitry 50 and for the static toggle flipflop circuitry 40).

However, the dynamic toggle flipflop circuitry 50 has a dynamic state when logical high is inputted at CK and logical low is inputted at CKn. In such a case, a reset node 51 is not actively kept at a defined potential and, thus, is in a floating state. In the floating state, the reset node 51 may change from logical low to logical high or from logical high to logical low because of leakage. Thus, e.g., a count value of a ripple counter that includes the dynamic toggle flipflop circuitry 50 may be corrupted. It is noted that the dynamic toggle-flipflop circuitry 50 may also be referred to as a pseudostatic toggle flipflop circuitry because it has one state that is dynamic (logical high at CK) and one state that is static (logical low at CK).

Therefore, a dynamic toggle flipflop, which has a dynamic state, is unacceptable in some embodiments.

It has been recognized that it is desirable to convert the dynamic state into a static state.

Fig. 6 illustrates a first embodiment of a toggle flipflop circuitry 100. The toggle flipflop circuitry 100 is an example of any one of the toggle flipflops 31 to 33 of Fig. 3.

The toggle flipflop circuitry 100 includes a first count switch 101 that is configured to be switched in accordance with a count signal (denoted as “CK”). The first count switch 101 is configured to couple an input node 102 (denoted as “I”) to a first output node 103 during a first count signal level (e.g., logical high) of the count signal CK. A path signal at the first output node 103 corresponds to a negation of an output signal (denoted as “Qn”) of the toggle flipflop circuitry 100.

The toggle flipflop circuitry 100 further includes a first inverter 104 that is configured to couple a second output node 105 to the first output node 103. The first inverter 104 is configured to invert (logically negate) a path signal at the first output node 103 such that a path signal at the second output node 105 corresponds to a (non-negated) output signal (denoted as “Q”) of the toggle flipflop circuitry 100.

The toggle flipflop circuitry 100 further includes a second count switch 106 that is configured to selectively couple the input node 102 to the second output node 105 during a second count signal level (e.g., logical low) of the count signal CK. The second count signal level corresponds to a negation of the first count signal level. Therefore, when the count signal CK has the second count signal level, a negation of the count signal (denoted as “CKn”) has the first count signal level, and the second count switch 106 establishes an electrical connection between the second output node 105 and the input node 102 when the negated count signal CKn has the first count signal level.

The toggle flipflop circuitry 100 further includes a second inverter 107 that is configured to generate a path signal at the first output node 103.

The toggle flipflop circuitry 100 further includes a third inverter 108 and a third count switch 109. The third inverter 108 is configured to invert a path signal at the input node 102. The third count switch 109 is configured to couple (an input node of) the second inverter 107 to (an output node of) the third inverter 108 during the first count signal level of the count signal CK such that, when the count signal CK has the first count signal level, the second inverter 107 inverts the path signal inverted by the third inverter 109 and, thus, provides to the first output node 103 a path signal that corresponds to a path signal at the input node 102.

Accordingly, the third inverter 108, the third count switch 109 and the second inverter 107 provide a first switchable active feedback loop that is configured to selectively propagate a path signal from the input node 102 to the first output node 103 during the first count signal level (i.e., when the count signal CK has the first count signal level), and to block a propagation of a path signal from the input node 102 to the first output node 103 during the second count signal level (i.e., when the count signal CK has the second count signal level).

The toggle flipflop circuitry 100 further includes a fourth count switch 110 that is configured to establish an electrical connection between the second output node 105 and (the input node of) the second inverter 107 when the count signal CK has the second count signal level and, thus, the negated count signal CKn has the first count signal level.

Accordingly, the fourth count switch 110 and the second inverter 107 provide a second switchable active feedback loop that is configured to selectively propagate a negation of a path signal from the second output node 105 to the first output node 103 during the second count signal level (i.e., when the count signal CK has the second count level and the negated count signal CKn has the first count signal level) , and to block a propagation of a path signal from the second output node 105 to the first output node 103 during the first count signal level (i.e., when the count signal CK has the first count signal level).

The first switchable active feedback loop and the second switchable active feedback loop share the second inverter 107. The second inverter 107 receives (at its input node), when the count signal CK has the first count signal level, via the third count switch 109 a path signal generated by the third inverter 108 and, when the negated count signal CKn has the first count signal level, via the fourth count switch 110 a path signal from the second output node 105.

The inverters 104, 107 and 108 generate path signals with a defined potential (e.g., by electrically connecting their output nodes to a potential such as ground or Vres) and, thus, actively maintain a defined path signal. Accordingly, the first switchable active feedback loop and the second switchable active feedback loop are active because of the inverters 107 and 108.

The toggle flipflop circuitry 100 further includes an input switch 111 that is configured to set a predefined path signal level at the input node 102. The input switch 111 receives a reset signal RES and, when the reset signal RES has a predefined reset signal level, the input switch 111 establishes an electrical connection between the input node 102 and a predefined voltage Vres such that the toggle flipflop circuitry 100 can be reset, irrespective of a current state of the toggle flipflop circuitry 100, to a state that corresponds to Vres.

As mentioned, the second count signal level (e.g., logical low) corresponds to a negation of the first count signal level (e.g. logical high), and the count signal CK is configured to switch between the first count signal level and the second count signal level. Likewise, the negated count signal CKn is configured to switch between the first count signal level and the second count signal level, wherein the negated count signal CKn switches to the second count signal level when the count signal CK switches to the first count signal level, and the negated count signal CKn switches to the first count signal level when the count signal CK switches to the second count signal level. Thus, the count signal CK and the negated count signal CKn are complementary digital signals and, as such, switch in complementary way between two logic states (logical low and logical high).

The toggle flipflop circuitry 100 is configured to receive the count signal CK and the negated count signal CKn to switch the count switches 101, 106, 109 and 110 (and, thus, also the first switchable active feedback loop and the second switchable active feedback loop) in accordance with the count signal CK (and with the negated count signal CKn). It is noted that, in some embodiments, the toggle flipflop circuitry 100 receives only one of the count signal CK and the negated count signal CKn, and generates the other one of the count signal CK and the negated count signal CKn by inverting (e.g., with a further inverter) the received one of the count signal CK and the negated count signal CKn.

The first count switch 101 is configured to retard a path signal propagation from the first output node 103 to the input node 102 by a predetermined delay after a change of the count signal CK from the second count signal level to the first count signal level. The predetermined delay is at least as long as a time required by the first switchable active feedback loop for propagating, after the count signal CK has changed from the second count signal level to the first count signal level, a path signal from the input node 102 to the first output node 103.

Thus, when the count signal CK changes from logical low to logical high (and the negated count signal CKn changes from logical high to logical low), the second and fourth count switches 106 and 110 switch to a blocking mode and the first and third count switches 101 and 109 switch to a non-blocking mode. Accordingly, a floating state of the input node 102 is avoided by the first count switch 101, which establishes an electrical connection between the first output node 103 and the input node 102 when the second count switch 106 interrupts an electrical connection between the second output node 105 and the input node 102.

Therefore, a dynamic state, which is present in the dynamic toggle flipflop circuitry 50 of Fig. 5, is transformed into a static state by connecting the input node 102 (which can be floating in the dynamic toggle flipflop circuitry 50 of Fig. 5) to a fixed output (i.e., to the first output node 103) after two inversions, creating an inverter latch.

When the count signal CK changes from the second count signal value to the first count signal value (and the input switch 111 has not been closed), a path signal at the input node 102 corresponds to a path signal at the second output node 105, which is opposite to a path signal at the first output node 103. The first switchable active feedback loop propagates the path signal from the input node 102 to the first output node 103, thus inverting a path signal level at the first output node 103. However, if the first count switch 101 propagates the path signal from the first output node 103 to the input node 102 before the first switchable active feedback loop has propagated the path signal from the input node 102 to the first output node 103, the path signal at the input node 102 may be overwritten by the path signal from the first output node 103, and a toggling of a state of the toggle switch circuitry 100 (e.g., from logical low to logical high or from logical high to logical low) may be wrongly prevented. For avoiding such a race condition, the first count switch 101 is configured to retard the path signal propagation from the first output node 103 to the input node 102 with the predefined delay such that the first switchable active feedback loop propagates the path signal from the input node 102 to the first output node 103, thus inverting a path signal at the first output node 103, and the first count switch 101 propagates the inverted path signal to the input node 102 without overwriting the path signal at the input node 102.

Thus, by the predefined delay, a floating state of the input node 102 can be avoided without introducing a race condition. Accordingly, a signal race condition is avoided by realizing the first count switch 101 as a slow switch so that the second inverter 107 can change a state of the toggle flipflop circuitry 100 (e.g., a path signal at the first output node 103) before (an input node of) the third inverter 108 is updated by the (slow) first count switch 101.

A reset operation by the input switch 111 can be flexibly changed to reset to logical low or set to logical high by setting the potential Vres accordingly. A reset switch (e.g., the input switch 111) may need to be properly sized to be stronger than other imposed values (e.g., stronger than a path signal generated by the second inverter 107 and propagated by the first count switch 101 (e.g., when the count signal CK is logical high), and stronger than a path signal generated by the first inverter 104 and propagated by the second count switch 106(e.g., when the negated count signal CKn is logical high)). In a case where the reset signal causes a reset operation to be performed while the count signal CK is logical low (and the negated count signal CKn is logical high), the reset operation is a complementary reset operation, because it forces the output Q to Vres. Thus, if Vres is logical high, the reset operation may result in a “set” operation that may bring the output Q to logical high.

Thus, the toggle flipflop circuitry 100 provides a static toggle flipflop with reset.

Regarding an implementation of the switches 101, 106, 109, 110 and 111, it is noted that the switches 101, 106, 109, 110 and 111 can be realized as NMOS (n-type metal-oxide semiconductor), PMOS (p-type metal-oxide semiconductor), or CMOS (complementary metal- oxide-semiconductor) switches, or a mixture of the above, e.g., depending on signal range, conductivity, etc. (as the skilled person may know from established digital and/or analog design practices).

Fig. 7 illustrates embodiments of switch implementations.

A switch that is switched in accordance with the count signal CK (e.g., the count switches 101 and 109 of Fig. 6), as shown in A of Fig. 7, may be implemented as a transmission gate, in which a NMOS transistor with the count signal CK as gate signal and a PMOS transistor with the negated count signal CKn as gate signal are connected in parallel, as illustrated in B of Fig. 7, as a NMOS transistor with the count signal CK as gate signal, as illustrated in C of Fig. 7, and/or as a PMOS transistor with the negated count signal CKn as gate signal, as illustrated in D of Fig. 7.

A switch that is switched in accordance with the negated count signal CKn (e.g., the count switches 106 and 110 of Fig. 6), as shown in E of Fig. 7, may be implemented as a transmission gate, in which a PMOS transistor with the count signal CK as gate signal and a NMOS transistor with the negated count signal CKn as gate signal are connected in parallel, as illustrated in F of Fig. 7, as a NMOS transistor with the negated count signal CKn as gate signal, as illustrated in G of Fig. 7, and/or as a PMOS transistor with the count signal CK as gate signal, as illustrated in H of Fig. 7.

The input switch 111 may be implemented accordingly, depending on a level of the reset signal RES at which the input switch 111 should electrically connect the input node 102 to Vres.

A polarity of signals may need to be adapted according to a switch type (e.g. when using a PMOS switch for a reset switch such as the input switch 111, a gate of the reset switch may have to be driven by a negated reset signal).

A size of transistors may need to undergo optimization, as is known in circuit design practice.

Fig. 8 illustrates an embodiment of signal time courses in the toggle flipflop circuitry 100 of Fig. 6.

At t₀, the toggle flipflop circuitry 100 is reset for initialization. Therefore, a reset signal RES is set to logical high (denoted as “H” in Fig. 8), such that the input switch 111 is in a non-blocking mode and establishes an electrical connection between the input node 102 and Vres.

Accordingly, a path signal at the input node 102 (denoted as “I” in Fig. 8) is set to logical high in accordance with Vres. Further, the count signal CK is logical high (an example of the first count signal level) and the negated count signal CKn is logical low (denoted as “L”; an example of the second count signal level). Thus, the first switchable active feedback loop propagates the path signal from the input node 102 to the first output node 103, such that a path signal at the first output node 103 (which corresponds to the negated output signal Qn) is set to logical high, and the first inverter 104 sets a path signal at the second output node 105 (which corresponds to the (non-negated) output signal Q) to logical low.

At G, the reset signal RES is set to logical low, and the input switch 111 switches to a blocking mode, such that the input node 102 is electrically disconnected from Vres. At t₂, a count event occurs, which is indicated by the count signal CK switching from logical high to logical low and, accordingly, by the negated count signal CKn switching from logical low to logical high. Thus, the second count switch 106 couples the input node 102 to the second output node 105, such that the path signal I at the input node 111 changes to logical low.

At t₃, the count signal CK switches back to logical high and, accordingly, the negated count signal CKn switches back to logical low. Therefore, the first switchable active feedback loop propagates the path signal I from the input node 102 to the first output node 103, such that the path signal Qn at the first output node 103 changes to logical low. In response, the first inverter 104 sets the path signal Q at the second output node 105 to logical high. Thus, a toggling operation is realized.

At t₄, a further count event occurs, as indicated by the count signal CK switching to logical low and the negated count signal CKn switching to logical high. The second count switch 106 couples the input node 102 to the second output node 105, and the path signal I at the input node 102 changes to logical high accordingly.

At t₅, the count signal CK switches back to logical high and the negated count signal CKn back to logical low. Thus, the first switchable active feedback loop propagates the path signal I from the input node 102 to the first output node 103, such that the path signal Qn at the first output node 103 changes to logical high and the path signal Q at the second output node 105 changes to logical low.

Therefore, the toggle flipflop circuitry 100 toggles its state (e.g., its output signal Q and its negated output signal Qn) when the count signal CK switches from logical low to logical high, e.g., at an end of a ripple (such as a ripple between t₂ and t₃ as well as a ripple between t₄ and t₅) that indicates a count event.

Fig. 9 illustrates a second embodiment of a toggle flipflop circuitry 120. The toggle flipflop circuitry 120 is an example of the toggle flipflop circuitry 100 of Fig. 6. Features taken from the toggle flipflop circuitry 100 of Fig. 6 have the same reference signs as in Fig. 6.

In the toggle flipflop circuitry 120, the count switches 101, 106, 109 and 110 as well as the input switch 111 of Fig. 6 are realized as NMOS and/or PMOS transistors.

The first count switch 101 is realized as a series of an NMOS transistor 121a that is configured to receive the count signal CK at its gate and a PMOS transistor 121b that is configured to receive the negated count signal CKn at its gate. The second count switch 106 is realized as a transmission gate, in which a PMOS transistor 122a and an NMOS transistor 122b are connected in parallel. The PMOS transistor 122a is configured to receive the count signal CK at its gate, and the NMOS transistor 122b is configured to receive the negated count signal CKn at its gate.

The third count switch 109 is realized as a transmission gate, in which a PMOS transistor 123a and an NMOS transistor 123b are connected in parallel. The PMOS transistor 123a is configured to receive the negated count signal CKn at its gate, and the NMOS transistor 123b is configured to receive the count signal CK at its gate.

The fourth count switch 110 is realized as a transmission gate, in which a PMOS transistor 124a and an NMOS transistor 124b are connected in parallel. The PMOS transistor 124a is configured to receive the count signal CK at its gate, and the NMOS transistor 124b is configured to receive the negated count signal CKn at its gate.

The input switch 111 is realized as a PMOS transistor 125 that is configured to receive a negated reset signal Rn (an example of the reset signal RES of Fig. 6) at its gate.

The remaining features of the toggle flipflop circuitry 120 correspond to the features in Fig. 6 with the same reference signs.

Accordingly, in the toggle flipflop circuitry 120, a portion that provides the first count switch 101 includes transistors 121a and 121b of opposite conductivity types (p-type and n- type). Further, as mentioned, the portion of the toggle flipflop circuitry 120 that provides the first count switch 101 includes the NMOS transistor 121a and the PMOS transistor 121b, which are coupled serially, wherein a conductivity type of the NMOS transistor 121a (n-type) is opposite to a conductivity type of the PMOS transistor 121b (p-type). The NMOS transistor 121a is configured to receive the count signal CK as gate signal and to switch to a non-blocking mode when the count signal CK has the first count signal level (logical high), and the PMOS transistor 121b is configured to receive the negated count signal CKn as gate signal and to switch to a non-blocking mode when the negated count signal CKn has a negation (logical low) of the first count signal level.

The toggle flipflop circuitry 120 provides a static toggle flipflop with reset that includes 15 MOSFETs (wherein each inverter 104, 107 and 108 includes two MOSFETs).

In the toggle flipflop circuitry 120, the dynamic state is transformed into a static state by connecting (by the transistors 121a and 121b) the floating node 102 to a fixed output (i.e., the first output node 103) after two inversions (i.e., the inverters 108 and 107), such that an inverter latch is created.

A series of transistors 121a and 121b is used to avoid race conditions that might erase the stored state, and to make the cell (i.e., the toggle flipflop circuitry 120) more robust against CK-CKn misalignment.

Fig. 10 illustrates a difference between a parallel and a serial coupling of a PMOS transistor and an NMOS transistor according to an embodiment.

A of Fig. 10 shows a PMOS transistor and an NMOS transistor coupled in parallel as a transmission gate, whereas B of Fig. 10 shows a PMOS transistor and an NMOS transistor coupled serially.

In both A and B of Fig. 10, the PMOS transistor is configured to receive the negated count signal CKn as gate signal, and the NMOS transistor is configured to receive the (non-negated) count signal CK as gate signal.

Thus, both the parallel coupling and the serial coupling of the PMOS transistor and the NMOS transistor switch to a non-blocking state (“on”) when the count signal CK switches to logical high and the negated count signal switches to logical low, and switch to a blocking state (“off’) when the count signal CK switches to logical low and the negated count signal CKn switches to logical high.

In more detail, the NMOS transistor is switched on during a rising edge of the count signal CK and is switched off during a falling edge of the count signal CK, whereas the PMOS transistor is switched on during a falling edge of the negated count signal CKn and is switched off during a rising edge of the negated count signal CKn.

However, in some embodiments, one of the count signal CK and the negated count signal CKn is delayed with respect to the other one of the count signal CK and the negated count signal CKn. For example, as shown in Fig. 10, in a case where the negated count signal CKn is generated by inverting the count signal CK, the inverting (e.g., propagating through an inverter) may take some time, such that the negated count signal CKn may be delayed with respect to the count signal CK. Likewise, in a case where the count signal CK is generated by inverting the negated count signal CKn, the count signal CK may be delayed with respect to the negated count signal CKn due to the inverting. Thus, the count signal CK and the negated count signal CKn may be (slightly) desynchronized. Due to the desynchronization of the count signal CK and the negated count signal CKn, the NMOS transistor, which is controlled by the “earlier” count signal CK, is switched on before the PMOS transistor, which is controlled by the delayed negated count signal CKn, is switched on. Likewise, the NMOS transistor is switched off before the PMOS transistor is switched off.

The parallel coupling shown in A of Fig. 10 becomes conductive (non-blocking) during the rising edge of the “earlier” count signal CK (when the NMOS transistor is switched on, while the PMOS transistor is still off) and becomes non-conductive (blocking) during the rising edge of the negated count signal CKn (when the PMOS transistor is switched off, while the NMOS transistor is already off).

In contrast, the serial coupling shown in B of Fig. 10 becomes conductive during the falling edge of the negated count signal CKn (when the PMOS transistor is switched on, while the NMOS transistor is already on) and becomes non-conductive during the falling edge of the count signal CK (when the NMOS transistor is switched off, while the PMOS transistor is still on).

Thus, the parallel coupling has a longer “on” period, whereas the serial coupling has a shorter “on” period.

Further, the parallel coupling has a lower switch resistance, whereas the serial coupling has a higher switch resistance.

Accordingly, the parallel coupling can be used for promoting a path signal propagation, whereas the serial coupling can be used for retarding a path signal propagation.

Therefore, the toggle flipflop circuitry 120 includes a slow switch 101 with an NMOS-PMOS series 121b and 121b, such that a path signal propagation through the serial transistors 121a and 121b is retarded with respect to the parallel transistors 123a and 123b of the first switchable active feedback loop.

Thus, in some embodiments, the first count switch 101, which is provided by the serial transistors 121a and 121b, becomes conductive only after the first switchable active feedback loop with the third count switch 109, which is provided by the parallel transistors 123a and 123b, has propagated a path signal from the input node 102 to the first output node 103. Accordingly, a race condition between the first count switch 101 and the third count switch 109 can be avoided.

However, the serial coupling shown in B of Fig. 10, which is realized with the transistors 121a and 121b, may not provide a full swing due to threshold voltages of the NMOS transistor 121a and the PMOS transistor 121b coupled in series. For example, the NMOS transistor may pass a strong “0” but a weak “1” (e.g., about one threshold voltage VTH away from a supply VDD, i.e., VDD-VTH), and the PMOS transistor may pass a strong “1” but a weak “0” (e.g., about one threshold voltage away from the supply, i.e. GND+VTH).

Fig. 11 illustrates a third embodiment of a toggle flipflop circuitry 130. The toggle flipflop circuitry 130 is a modification of the toggle flipflop circuitry 120 of Fig. 9 increased to full swing.

In the toggle flipflop circuitry 130, the first count switch 101 is realized as a series of a transmission gate provided by an NMOS transistor 131 and a PMOS transistor 132 and a transmission gate provided by a PMOS transistor 133 and an NMOS transistor 134. The NMOS transistors 131 and 134 are configured to receive the count signal CK at their gates, and the PMOS transistors 132 and 133 are configured to receive the negated count signal CKn at their gates.

Accordingly, a portion of the toggle flipflop circuitry 130 that provides the first count switch 101 includes the NMOS transistors 131 and 134 that are coupled in series and have a first conductivity type (n-type), and the PMOS transistors 132 and 133 that are coupled in series and have a second conductivity type (p-type) opposite to the first conductivity type, wherein the series of the NMOS transistors 131 and 134 is coupled in parallel to the series of the PMOS transistors 132 and 133.

In Fig. 11, the series of the NMOS transistors 131 and 134 and the series of the PMOS transistors 132 and 133 are electrically connected at a node between the NMOS transistors 131 and 134 and a node between the PMOS transistors 132 and 133. However, there are embodiments in which the node between the NMOS transistors 131 and 134 is not electrically connected to the node between the PMOS transistors 132 and 133, as described with respect to Fig. 12.

The NMOS transistors 131 and 134 are both configured to receive the count signal CK as gate signal and to switch to a non-blocking mode (“on”) when the count signal CK has the first count signal level (logical high), and the PMOS transistors 132 and 133 are both configured to receive the negated count signal CKn as gate signal and to switch to a non-blocking mode (“on”) when the negated count signal CKn has a negation (logical low) of the first count signal level.

The remaining features of the toggle flipflop circuitry 130 correspond to the features of Fig. 9 with the same reference signs.

Accordingly, by using a series of CMOS switches (provided by the transistors 131, 132, 133 and 134), it is possible to recover the full swing in the toggle flipflop circuitry 130. A resistance of the CMOS switches provided by the transistors 131, 132, 133 and 134 in a nonblocking (“on”) state is however higher than a resistance of the first switchable active feedback loop provided by the inverters 107 and 108 and by the transistors 123a and 123b, such that a race condition can be avoided and a proper operation of the toggle flipflop circuitry 130 can be ensured. Accordingly, a path signal propagation through a first path 135 (which corresponds to the first switchable active feedback loop provided by the inverters 107 and 108 and by the transistors 123a and 123b) is faster than a path signal propagation through a second path 136 (which corresponds to the CMOS switches provided by the transistors 131, 132, 133 and 134) because the path signal propagation is retarded by the higher resistance of the transistors 131, 132, 133 and 134.

Thus, the toggle flipflop circuitry 130 provides a static toggle flipflop with reset provided by 17 MOSFETs (wherein each inverter 104, 107 and 108 is provided by two MOSFETs). In some embodiments, an area increase (depending on technology) is negligible or zero in the toggle flipflop circuitry 130 due to parallel poly gate constraints and/or diffusion sharing.

Fig. 12 illustrates embodiments of a coupling of transistors. For realizing the first count switch 101, the transistors 131, 132, 133 and 134 can be coupled as series-of-parallel, as shown in Fig. 11 and in A of Fig. 12, or as parallel-of-series, as shown in Fig. 12.

In A of Fig. 12, a node between the NMOS transistors, which are connected in series, is electrically connected to a node between the PMOS transistors, which are also connected in series, such that each pair of an NMOS transistor and a PMOS transistor is coupled in parallel, and the two pairs of an NMOS transistor and a PMOS transistor are coupled in series. Such a configuration may be referred to as “series-of-parallel”.

In B of Fig. 12, the node between the NMOS transistors, which are connected in series, is not electrically connected to the node between the PMOS transistors, such that the series of NMOS transistors is coupled in parallel to the series of PMOS transistors. Such a configuration may be referred to as “parallel-of-series”.

As mentioned, transistors of the first count switch 101 (e.g., the transistors 131, 132, 133 and 134 of Fig. 11) may be coupled as series-of-parallel, as shown in A of Fig. 12, or as parallel-of- series, as shown in B of Fig. 12.

Fig. 13 illustrates a fourth embodiment of a toggle flipflop circuitry 140. The toggle flipflop circuitry 140 is a modification of the toggle flipflop circuitry 130 of Fig. 11, in which a PMOS transistor 141 is provided instead of the PMOS transistor 133, and an NMOS transistor 142 is provided instead of the NMOS transistor 134. The remaining features of Fig. 13 correspond to features of Fig. 11 with the same reference signs.

The PMOS transistor 141 and the NMOS transistor 142 are coupled in parallel. The PMOS transistor 141 is configured to receive a predefined potential Vbp, and the NMOS transistor 142 is configured to receive a predefined potential Vbn. The predefined potentials Vbp and Vbn are configured as constant signal levels that do not change with the count signal CK or with the negated count signal CKn.

Vbp is configured such that a resistance of the PMOS transistor 141 is higher than a resistance of the PMOS transistor 132 when the negated count signal CKn is logical low, and Vbn is configured such that a resistance of the NMOS transistor 142 is higher than a resistance of the NMOS transistor 131 when the count signal CK is logical high.

Thus, in the toggle flipflop circuitry 140, the CMOS switch provided by the transistors 133 and 134 is converted to an always on resistive switch provided by the transistors 141 and 142.

Vbp and Vbn are chosen such that, when the first count switch 101 (which is provided by the transistors 131, 132, 141 and 142) is in a non-blocking state and couples the input node 102 to the first output node 103, and when the first switchable active feedback loop (which is provided by the inverters 107 and 108 and the transistors 123a and 123b) propagates a path signal from the input node 102 to the first output node 103, a resistance of the first count switch 101 is higher than a resistance of the first switchable active feedback loop, such that a path signal propagation through the first count switch 101 is retarded by the predetermined delay with respect to a path signal propagation through the first switchable active feedback loop. Therefore, a race condition between the first count switch 101 and the first switchable active feedback loop can be avoided.

Vbn and Vbp may be equal, e.g., a mid supply reference Vmid=Vbn=Vbp, which may simplify design and/or layout. For example, Vmid may correspond to a middle value between a logical high and a logical low of the count signal CK and of the negated count signal CKn. However, the disclosure is not limited to Vbn=Vbp, and there are embodiments in which Vbn and Vbp differ from each other.

Accordingly, the NMOS transistor 131 is configured to receive the count signal CK as gate signal and to switch to a non-blocking mode (“on”) when the count signal CK has the first count signal level (logical high), whereas the NMOS transistor 142 is configured to receive the predefined gate signal Vbn at which the resistance of the NMOS transistor 142 is higher than the resistance of the NMOS transistor 131 when the count signal CK has the first count signal level (logical high). Likewise, the PMOS transistor 132 is configured to receive the negated count signal CKn as gate signal and to switch to a non-blocking mode (“on”) when the negated count signal CKn has a negation (logical low) of the first count signal level, and the PMOS transistor 141 is configured to receive the predefined gate signal Vbp at which the resistance of the PMOS transistor 141 is higher than the resistance of the PMOS transistor 132 when the negated count signal CKn has the negation (logical low) of the first count signal level.

In some embodiments, an intention of the slow (first count) switch 101 (provided by the transistors 131, 132, 141 and 142) is latching, not speed.

In some embodiments, the toggle flipflop circuitry 140 does not bring criticalities on transistors sizing and/or is robust against process comers and variations. Thus, in some embodiments, a robustness is increased in the toggle flipflop circuitry 140 with respect to the toggle flipflop circuitry 130 of Fig. 11.

The toggle flipflop circuitry 140 provides a static toggle flipflop with reset provided by 17 MOSFETs (wherein each inverter 104, 107 and 108 is provided by two MOSFETs).

It is noted that, in the toggle flipflop circuitry 140, a node between the NMOS transistors 131 and 142 may or may not be electrically connected with a node between the PMOS transistors 132 and 141. Thus, the transistors 131, 132, 141 and 142 may be arranged as series- of-parallel or as parallel-of-series, as discussed with respect to Fig. 12. It is further noted that, in some embodiments, the PMOS transistor 141 is provided instead of the PMOS transistor 132 and is serially coupled to the PMOS transistor 133, and/or the NMOS transistor 142 is provided instead of the NMOS transistor 131 and is serially coupled to the NMOS transistor 134.

Fig. 14 illustrates a fifth embodiment of a toggle flipflop circuitry 150. The toggle flipflop circuitry 150 is a modification of the toggle flipflop circuitry 120 of Fig. 9, in which the fourth count switch 110 is provided by a PMOS transistor 151 and an NMOS transistor 152 instead of the transistors 124a and 124b. The remaining features of Fig. 14 correspond to features of Fig. 9 with the same reference signs.

The toggle flipflop circuitry 150 provides a static toggle flipflop with reset provided by 15 MOSFETs (wherein each inverter 104, 107 and 108 is provided by two MOSFETs).

The PMOS transistor 151 is configured to receive the count signal CK at its gate, and the NMOS transistor 152 is configured to receive the negated count signal CKn at its gate. The transistors 151 and 152 are coupled in series, such that the second switchable active feedback loop is configured to propagate a path signal from the second output node 105 to the first output node 103 when the count signal CK has the second count signal level (logical low) and the negated count signal CKn has the first count signal level (logical high).

Thus, with the transistors 151 and 152, the toggle flipflop circuitry 150 includes a series switch also for another static state, when the count signal CK has the second count signal level (logical low).

In the toggle flipflop circuitry 150, a possibility of race conditions may be reduced also in the other static state. A function of the transistors 151 and 152 is to keep a value of the toggle flipflop circuitry 150.

However, the toggle flipflop circuitry 150 may provide no full swing, and there may be a risk of nodes settling to intermediate values, which may cause more power consumption. Further, in some embodiments, a layout of series switches is not advantageous in terms of area.

Fig. 15 illustrates a sixth embodiment of a toggle flipflop circuitry 160. The toggle flipflop circuitry 160 is a modification of the toggle flipflop circuitry 120 of Fig. 9, in which the first count switch 101 is provided by a PMOS transistor 161 and an NMOS transistor 162 instead of the transistors 121a and 121b. The remaining features of Fig. 15 correspond to features of Fig. 9 with the same reference signs.

The toggle flipflop circuitry 160 provides a static toggle flipflop with reset provided by 15 MOSFETs (wherein each inverter 104, 107 and 108 is provided by two MOSFETs).

The PMOS transistor 161 is configured to receive a ground potential gnd at its gate, and the NMOS transistor 162 is configured to receive a supply potential vdd at its gate. The transistors 161 and 162 are coupled in series.

Accordingly, with the transistors 161 and 162, the toggle flipflop circuitry 160 includes an always on loop between the first output node 103 and the input node 102.

In the toggle flipflop circuitry 160, a layout may be simplified with a common connection of the gates of the series transistors 161 and 162 to supplies gnd and vdd, respectively, and a load of the input signals CK and CKn may be decreased (less dynamic consumption, more speed).

However, the serial coupling of the transistors 161 and 162 may provide no full swing, and there may be a risk of nodes settling to intermediate values, such that more power consumption may be caused. Further, a power consumption may be high in a state when the count signal CK is logical low. Fig. 16 illustrates a seventh embodiment of a toggle flipflop circuitry 170. The toggle flipflop circuitry 170 is a modification of the toggle flipflop circuitry 160 of Fig. 15, in which the fourth count switch 110 is provided by a PMOS transistor 171 and an NMOS transistor 172 instead of the transistors 124a and 124b. The remaining features of Fig. 16 correspond to features of Fig. 15 with the same reference signs.

The toggle flipflop circuitry 170 provides a static toggle flipflop with reset provided by 15 MOSFETs (wherein each inverter 104, 107 and 108 is provided by two MOSFETs).

The PMOS transistor 171 is configured to receive a ground potential gnd at its gate and the NMOS transistor 172 is configured to receive a supply potential vdd at its gate. The transistors 171 and 172 are coupled in series.

Accordingly, in the toggle flipflop circuitry 170, both latched loops are configured as “always on” loops.

In the toggle flipflop circuitry 170, a layout may be further simplified by the common connection of the gates of the series transistors 171 and 172 to the respective supplies gnd and vdd, and a load of the input signals CK and CKn may be further decreased (less dynamic consumption, more speed).

However, the serial coupling of the transistors 171 and 172 may provide no full swing, and there may be a risk of nodes settling to intermediate values, such that more power consumption may be caused. Further, a power consumption may be high in a state when the count signal CK is logical low. Also, a layout of the series switches 171 and 172 may be not advantageous in terms of area in some embodiments.

Fig. 17 illustrates an eighth embodiment of a toggle flipflop circuitry 180. The toggle flipflop circuitry 180 is a modification of the toggle flipflop circuitry 120 of Fig. 9, in which the third inverter 108 and the third count switch 109 are provided by an inverter 181, a PMOS transistor 182 and an NMOS transistor 183 instead of the inverter 108 and the transistors 123a and 123b. The remaining features of Fig. 17 correspond to features of Fig. 9 with the same reference signs.

The toggle flipflop circuitry 180 provides a static toggle flipflop with reset provided by 15 MOSFETs (wherein each inverter 104, 107 and 181 is provided by two MOSFETs).

In the toggle flipflop circuitry 180, the third count switch 109 is provided by the transistors 182 and 183, and is integrated into the inverter 108. The PMOS transistor 182 is configured to receive the negated count signal CKn at its gate and is coupled between the inverter 181 and a supply (e.g., Vres) associated with a logical high, such that the inverter 181 is electrically connected, via the PMOS transistor 182, to the supply associated with a logical high when the negated count signal CKn is logical low. Likewise, the NMOS transistor 183 is configured to receive the count signal CK at its gate and is coupled between the inverter 181 and a supply (e.g., gnd) associated with a logical low, such that the inverter 181 is electrically connected, via the NMOS transistor 183, to the supply associated with a logical low when the count signal CK is logical high. Thus, the inverter 181 together with the transistors 182 and 183 provides a tristate. It is noted that, in some embodiments, positions of inverter and tristate transistors are swapped in the tristate, e.g., by connecting the tristate transistors 182 and 183 near to the first output node 103 instead of to supply nodes, while internal inverter transistors are moved towards the supply nodes.

In the toggle flipflop circuitry 180, a layout may be simplified due to diffusion sharing of the inverter 181 and the tristate.

However, it may be more difficult in the toggle flipflop circuitry 180 to meet a timing criterion that a path through the first switchable active feedback loop (provided by the inverters 107 and 181 and the transistors 182 and 183) is faster than a path through the first count switch 101 (provided by the transistors 121a and 121b).

It is noted that the tristate provided by the inverter 181 and the transistors 182 and 183 may be provided in the toggle flipflop circuitry 130, 140, 150, 160 or 170 instead of the inverter 108. In such a case, the transistors 123a and 123b may be omitted, too.

Some embodiments of the toggle flipflop circuitry 100, 120, 130, 140, 150, 160, 170 or 180 may provide advantages with respect to other solutions. Such advantages may include a solution of a toggle flipflop circuitry that is smaller (from 15 to 17 transistors) than other solutions while keeping a static operation (infinite retention time) due to actively controlling a potential at each node, reduced power consumption because of the reduced number of switching components, and/or higher speed due to the reduced number of components.

Applications of a toggle flipflop circuitry according to the disclosure may include counters in photon counting sensors, counters in quanta burst imaging sensors, toggle logic for SPAD frontends encoding information into edge, and/or counters for integrated histogram arrays.

Consequently, some embodiments pertain to a toggle flipflop circuitry that includes: a first count switch that is configured to couple an input node to a first output node during a first count signal level, wherein the first count switch is configured to retard a path signal propagation from the first output node to the input node by a predetermined delay; a first inverter that is configured to couple a second output node to the first output node; a first switchable active feedback loop that is configured to selectively propagate a path signal from the input node to the first output node during the first count signal level; a second switchable active feedback loop that is configured to propagate a negation of a path signal from the second output node to the first output node during a second count signal level different from the first count signal level; and a second count switch that is configured to selectively couple the input node to the second output node during the second count signal level.

The toggle flipflop circuitry may be configured to toggle a state (e.g., switch between two defined states) in accordance with a count signal. For example, the toggle flipflop circuitry may be configured to toggle the state at a rising edge or at a falling edge of the count signal. The state of the toggle flipflop circuitry may correspond to an output signal outputted from the toggle flipflop circuitry, and toggling the state may include switching the output signal from logical low to logical high or from logical high to logical low.

The count signal may be configured as a signal that changes between a first count signal level and a second count signal level in accordance with a count event that should be counted by the toggle flipflop circuitry (e.g., by toggling its state). For example, the count signal may change from the first count signal level to the second count signal level when the count event starts, and may change from the second count signal level to the first count signal level when the count event ends, or vice versa. The count event may correspond to a cycle of a count signal, to a detected photon, to a detected voltage or current peak or drop, or the like. The count signal may indicate the count event as a ripple (e.g., as a change from the first count signal level to the second count signal level and back to the first count signal level). Thus, the count signal may also be referred to as a ripple signal.

The first count signal level may correspond to a potential at which count switches (e.g., the first count switch, and/or a third count switch included in the first switchable active feedback loop) of the toggle flipflop circuitry, when receiving the first count signal level at their gate, are in a nonblocking (“on”) mode. The second count signal level may correspond to a potential at which count switches (e.g., the second count switch, and/or a fourth count switch included in the second switchable active feedback loop) of the toggle flipflop circuitry, when receiving the second count signal level at their gate, are in a non-blocking (“on”) mode. Count switches of the toggle flipflop circuitry that are configured to be in the non-blocking mode during the first count signal level may be configured to be in a blocking (“off’) mode during the second count signal level, and count switches of the toggle flipflop circuitry that are configured to be in the non- blocking mode during the second count signal level may be configured to be in a blocking (“off’) mode during the first count signal level. For example, the first count signal level may correspond to logical high and the second count signal level may correspond to logical low, or vice versa.

The toggle flipflop circuit may further receive and/or generate (e.g., via an inverter) a negation of the count signal (negated count signal), which may correspond to an inverse of the count signal. Thus, when the count signal has the first count signal level, the negated count signal may have the second count signal level, and when the count signal has the second count signal level, the negated count signal may have the first count signal level.

The first output node and the second output node may correspond to nodes from which output signals of the toggle flipflop circuitry may be outputted, wherein an output signal from the first output node may be an inverse (e.g., a negation) of an output signal from the second output node. The first inverter may receive a path signal from the first output node, generate an inverse (e.g., a negation) of the path signal from the first output node, and provide the negated path signal to the second output node. Thus, when a path signal at the first output node is logical low, a path signal at the second output node may be logical high, and vice versa.

The input node may be configured to be connected (e.g., in accordance with a reset signal) to a predefined potential (e.g., ground, supply potential, or the like), such that the toggle flipflop circuitry may be set to a defined state via the input node, e.g., for initializing the toggle flipflop circuitry.

Any count switch of the toggle flipflop circuitry may be provided by a transistor (e.g., a metal- oxide-semiconductor field-effect transistor (MOSFET), such as an NMOS transistor or a PMOS transistor, or a junction field-effect transistor (JFET)), by two or more transistors coupled in series (e.g., of different conductivity types / dopings, such as n-type and p-type MOSFETs), and/or by coupling transistors of opposite conductivity types (e.g., NMOS and PMOS transistors) in parallel (e.g., as transmission gates, as series-of-parallel (e.g., serial transmission gates), as parallel-of-series etc.). The transistor(s) may be of an enhancement mode and/or of a depletion mode. The transistor(s) may receive the count signal or a negation of the count signal as gate signal, e.g., at its/their gate, such that a non-blocking (conducting, “on”) mode and a blocking (isolating, “off’) mode of the transistor(s) may correspond to a level of the (negated) count signal.

Transistors of some count switches (e.g., the first count switch and/or the fourth count switch) of the toggle flipflop circuitry may receive, at their gates, a predefined, constant potential (e.g., gnd, vdd, or a potential between gnd and vdd) such that they may be always in an on state and may have a predefined resistance during operation of the toggle flipflop circuitry.

The first count switch may retard the path signal propagation from the first output node to the input node with respect to a path signal propagation from the input node to the first output node through the first switchable active feedback loop. For example, the first count switch may be configured to change, when the count signal changes from the second count signal level to the first count signal level, to a non-blocking (“on”) state by the predetermined delay later than (a switch/transistor of) the first switchable active feedback loop. For example, a resistance of the first count switch, when the count signal has the first count signal level, may be so high that a change of a path signal at the input node caused by a path signal propagation through the first count switch does not reach, within a time that corresponds to the predefined delay after the count signal has switched to the first count signal level, a threshold at which an inverter of the first switchable active feedback loop changes its output.

However, when charges leak from the input node, the first count switch may compensate the leakage and may cause the path signal at the input node to have a defined potential. Thus, a dynamic state, in which the input node becomes floating, may be avoided.

The first switchable active feedback loop may include a third count switch (which may be provided by one or more transistors, as described above) that may be configured to receive the count signal and/or the negated count signal at a gate and to be in a non-blocking (“on”) state when the count signal has the first count signal level and/or when the negated count signal has the second count signal level, such that the third count switch may allow a path signal propagation from the input node through the first switchable active feedback loop to the first output node when the count signal has the first count signal level, and may block a path signal propagation from the input node through the first switchable active feedback loop to the first output node when the count signal has the second count signal level. Thus, the first switchable active feedback loop may be switched, via the third count switch, in accordance with the count signal.

The first switchable active feedback loop may further include two inverters, which may be coupled in series (e.g., with the third count switch in between, or, in some embodiments, before or after the third count switch). The two serial inverters of the first switchable active feedback loop may cause a path signal from the input node to be inverted twice, such that a path signal provided from the first switchable active feedback loop to the first output node may correspond to the path signal at the input node. Further, the inverters of the first switchable active feedback loop may output a path signal that may correspond to a predefined potential, such that the first switchable active feedback loop may actively set a defined potential at the first output node. Due to setting the path signal at the first output node based on the path signal at the input node (which may be based on the path signal of the first output node via the first count switch), the first switchable active feedback loop may close a loop around the first output node for providing feedback to the first output node.

The second switchable active feedback loop may include a fourth count switch (which may be provided by one or more transistors, as described above) that may be configured to receive the count signal and/or the negated count signal at its gate and to be in a non-blocking (“on”) state when the count signal has the second count signal level and/or when the negated count signal has the first count signal level. Thus, the second switchable active feedback loop may switch according to the negated count signal. The second switchable active feedback loop may further include an inverter that may be configured to receive a path signal from the second output node, generate an inverse (negation) of the path signal from the second output node, and provide the negation of the path signal from the second output node to the first output node. Thus, the second switchable active feedback loop may actively set a path signal at the first output node. Due to setting the path signal at the first output node based on the path signal at the second output node (which may be based on the path signal of the first output node via the first inverter), the second switchable active feedback loop may close a loop around the first output node for providing feedback to the first output node.

The second count switch may be provided by one or more transistors, as described above, and may be configured to allow a path signal propagation from the second output node to the input node when the count signal has the second count signal level and/or when the negated count signal has the first count signal level. The path signal propagated through the second count switch from the second output node to the input node when the count signal has the second count signal value may be propagated by the first switchable active feedback loop from the input node to the first output node when the count signal changes to the first count signal value, such that the state of the toggle flipflop circuitry may be toggled.

In some embodiments, after a change from the second count signal level to the first count signal level, the predetermined delay is at least as long as a time required by the first switchable active feedback loop for propagating a path signal from the input node to the first output node.

The predetermined delay may be so long that a race condition between the first count switch and the first switchable active feedback loop may be avoided. For example, the predetermined delay may be so long that, after the count signal has switched to the first count signal level, a path signal from the input node may be propagated by the first switchable active feedback loop to the first output node before a path signal propagated from the first output node through the first count switch to the input node can change the path signal at the input node by such an amount that an inverter of the first switchable active feedback loop changes its output.

In some embodiments, the first count switch includes transistors of opposite conductivity types.

The first count switch may include at least one NMOS transistor and at least one PMOS transistor. The transistors of opposite conductivity types may be configured to receive inverted signals at their gates. For example, the NMOS transistor may be configured to receive the count signal at its gate, and the PMOS transistor may be configured to receive the negated count signal at its gate. Thus, a period during which the NMOS transistor is in an “on” state may correspond to a period during which the PMOS transistor is in an “on” state.

In some embodiments, the first count switch includes a first transistor and a second transistor coupled serially, wherein a conductivity type of the first transistor is opposite to a conductivity type of the second transistor.

For example, the first transistor may be of an n-channel type (NMOS transistor) and the second transistor may be of a p-channel type (PMOS transistor).

In some embodiments, the first transistor is configured to receive a count signal as gate signal and to switch to a non-blocking mode when the count signal has the first count signal level; and the second transistor is configured to receive a negated count signal as gate signal and to switch to a non-blocking mode when the negated count signal has a negation of the first count signal level.

As mentioned, the first transistor may be configured as an NMOS transistor, and the second transistor may be configured as a PMOS transistor. A period in which the count signal has the first count signal level may correspond to a period in which the negated count signal has the negation (e.g., the second count signal level) of the first count signal level.

Thus, a period during which the first transistor is in the non-blocking mode (“on” state) may correspond to a period during which the second transistor is in the non-blocking mode (“on” state), such that the first count switch (provided by the first and second transistor coupled in series) may be in an “on” state and, accordingly, couple the input node to the first output node when the count signal has the first count signal level. In some embodiments, the first count switch includes: a first transistor and a second transistor that are coupled in series and have a first conductivity type; and a third transistor and a fourth transistor that are coupled in series and have a second conductivity type opposite to the first conductivity type; wherein a series of the first transistor and the second transistor is coupled in parallel to a series of the third transistor and the fourth transistor.

The first transistor and the second transistor may be of an n-channel type (NMOS transistors), and the third transistor and the fourth transistor may be of a p-channel type (PMOS transistors).

Thus, the series of the first transistor and the second transistor may be configured to conduct electrons, and the series of the third transistor and the fourth transistor may be configured to conduct holes.

The first, second, third and fourth transistors may be arranged as “series-of-parallel”, wherein a node between the first and the second transistor may be electrically connected to a node between the third and the fourth transistor (e.g., as a series of two transmission gates), or may be arranged as “parallel-of-series”, wherein the node between the first and the second transistor may be not electrically connected to the node between the third and the fourth transistor, e.g., as discussed with respect to Fig. 12.

The disclosure is not limited to only two NMOS transistors coupled in series and only two PMOS transistors coupled in series. Any suitable number of NMOS transistors (e.g., 1, 2, 3, 4, 5, or more) may be coupled in series, and any suitable number of PMOS transistors (e.g., 1, 2, 3, 4, 5, or more) may be coupled in series, e.g., based on a resistance of the NMOS/PMOS transistors. A number of NMOS transistors coupled in series may be equal to or differ from a number of PMOS transistors coupled in series. For example, a number of NMOS transistors coupled in series and a number of PMOS transistors coupled in series may be chosen such that a resistance of the series of NMOS transistors and a resistance of the series of PMOS transistors causes the first count switch to retard the path signal propagation from the first output node to the input node by the predetermined delay. Also a size of the transistors, where allowed by a used technology, may be changed in order to achieve a desired resistance value.

In some embodiments, at least one of the first transistor and the second transistor is configured to receive a count signal as gate signal and to switch to a non-blocking mode when the count signal has the first count signal level; and at least one of the third transistor and the fourth transistor is configured to receive a negated count signal as gate signal and to switch to a non-blocking mode when the negated count signal has a negation of the first count signal level. As mentioned, a period in which the count signal has the first count signal level may correspond to a period in which the negated count signal has the negation (e.g., the second count signal level) of the first count signal level.

Thus, a period during which the at least one of the first transistor and the second transistor is in the non-blocking mode (“on” state) may correspond to a period during which the at least one of the third transistor and the fourth transistor is in the non-blocking mode (“on” state), such that the first count switch (provided by the first, second, third and fourth transistors) may be in an “on” state and, accordingly, couple the input node to the first output node when the count signal has the first count signal level.

In some embodiments, both the first transistor and the second transistor are configured to receive the count signal as gate signal and to switch to a non-blocking mode when the count signal has the first count signal level; and both the third transistor and the fourth transistor are configured to receive the negated count signal as gate signal and to switch to a non-blocking mode when the negated count signal has a negation of the first count signal level.

In such embodiments, the first count switch may retard the path signal propagation from the first output node to the input node due to an increased resistance caused by the series of the first transistor and the second transistor and by the series of the third transistor and the fourth transistor.

As mentioned, the disclosure is not limited to only two NMOS transistors coupled in series and is not limited to only two PMOS transistors coupled in series. Any suitable number of NMOS transistors may be coupled in series and may be configured to receive the count signal as gate signals, and any suitable number of PMOS transistors may be coupled in series and may be configured to receive the negated count signal as gate signals.

In some embodiments, the second transistor is configured to receive a predefined gate signal at which a resistance of the second transistor is higher than a resistance of the first transistor when the count signal has the first count signal level; and the fourth transistor is configured to receive a predefined gate signal at which a resistance of the fourth transistor is higher than a resistance of the third transistor when the negated count signal has the negation of the first count signal level.

Thus, while the first transistor may receive the count signal as gate signal and may be switched “on” or “off’ in accordance with the count signal, the second transistor may be configured as an “always on” resistive switch. Likewise, while the third transistor may receive the negated count signal as gate signal and may be switched “on” or “off’ in accordance with the negated count signal, the fourth transistor may be configured as an “always on” resistive switch. Gate signals of the second transistor and of the fourth transistor may be configured such that a resistance of the second transistor and a resistance of the fourth transistor causes the path signal propagation from the first output node to the input node to be retarded by the predetermined delay.

For example, the gate signal of the second transistor may have a lower potential than the first count signal level, and the gate signal of the fourth transistor may have a higher potential than the negation (e.g., the second count signal level) of the first count signal level.

For example, the predefined gate signal of the second transistor may have a same potential as the predefined gate signal of the fourth transistor, e.g., a potential that may correspond to a mid supply reference. However, the predefined gate signal of the second transistor may as well have a potential that may be higher or lower than a potential of the predefined gate signal of the fourth transistor.

In a case where more than two NMOS transistors are coupled in series in the first count switch, any suitable number of the NMOS transistors coupled in series may be configured to receive the count signal as gate signal, and the remaining NMOS transistors of the NMOS transistors coupled in series may be configured to receive the predefined gate signal of the second transistor.

Likewise, in a case where more than two PMOS transistors are coupled in series in the first count switch, any suitable number of the PMOS transistors coupled in series may be configured to receive the negated count signal as gate signal, and the remaining PMOS transistors of the PMOS transistors coupled in series may be configured to receive the predefined gate signal of the fourth transistor.

In some embodiments, the first switchable active feedback loop and the second switchable active feedback loop share a second inverter.

The second inverter (e.g., its output node) may be coupled to the first output node, such that the second inverter may be configured to set a path signal at the first output node.

The second inverter may be configured to receive (e.g., at its input node) a path signal of the first switchable active feedback loop when the count signal has the first count signal level, and to receive (e.g., at its input node) a path signal of the second switchable active feedback loop when the count signal has the second count signal level. For example, the second inverter may be electrically connected (e.g., at its input node) to an output node of the third count switch in the first switchable active feedback loop and to an output node of the fourth count switch in the second switchable active feedback loop.

Thus, a further inverter may be avoided, and an area occupied by the toggle flipflop circuitry may be reduced.

In some embodiments, the toggle flipflop circuitry further includes an input switch that is configured to set a predefined path signal level at the input node.

As mentioned, the input switch may be configured to receive a reset signal (or a negated reset signal) at its gate, and to electrically connect the input node to a potential that may correspond to the predefined path signal level (e.g., logical low, such as gnd; or logical high, such as Vres) in accordance with the reset signal (or the negated reset signal).

The input switch may include a JFET, a MOSFET, an NMOS transistor, a PMOS transistor, a transmission gate, or the like. The input switch may be in a blocking mode (“off” state) unless controlled otherwise by the (negated) reset signal, such that the input node may be isolated from the potential unless the (negated) reset signal controls the input switch to set the predefined path signal at the input node.

With the input switch, the toggle flipflop circuitry may be initialized to a defined state (e.g., logical low or logical high), e.g., when a new counting period starts.

The toggle flipflop circuitry may include a further input switch, wherein, for example, the input switch may be configured to set a path signal at the input node to logical low, and the further input switch may be configured to set a path signal at the input node to logical high (or vice versa) in accordance with the (negated) count signal.

In some embodiments, the second count signal level corresponds to a negation of the first count signal level.

For example, the second count signal level may correspond to logical low, and the first count signal level may correspond to logical high. For example, the first count signal level may correspond to logical low, and the second count signal level may correspond to logical high.

The skilled person may appreciate that, depending on a polarity of the count signal and the negated count signal (e.g., which of the first count signal level and the second count signal level corresponds to logical low and which corresponds to logical high), and depending on whether a depletion type or an enhancement type is used, NMOS transistors in the toggle flipflop circuitry may be configured to receive a first one of the count signal and the negated count signal, and PMOS transistors of the toggle flipflop circuitry may be configured to receive a second one of the count signal and the negated count signal.

In some embodiments, the toggle flipflop circuitry is further configured to: receive a count signal that is configured to switch between the first count signal level and the second count signal level; and switch the first count switch, the second count switch, the first switchable active feedback loop and the second switchable active feedback loop in accordance with the count signal.

Thus, a state of the toggle flipflop circuitry (e.g., an output signal outputted at the first output node and/or at the second output node) may be changed (e.g., toggled) in accordance with the count signal (and the negated count signal), e.g., when the (negated) count signal indicates a count event.

Some embodiments pertain to a ripple counter circuitry that includes: a first toggle flipflop circuitry according to any configuration of a toggle flipflop circuitry described above; and a second toggle flipflop circuitry according to any configuration of a toggle flipflop circuitry described above; wherein the ripple counter circuitry is configured to: provide a ripple signal as a count signal to the first toggle flipflop circuitry; and provide a path signal from one of the first output node of the first toggle flipflop circuitry and the second output node of the first toggle flipflop circuitry as a count signal to the second toggle flipflop circuitry.

The ripple signal may be configured to change between a two levels (e.g., logical low and logical high), and a ripple may correspond to a period in which the ripple signal has a specific one of the two levels. The ripples of the ripple signal may indicate count events that should be counted by the ripple counter. As mentioned, the count events may correspond to a detected photon, to a detected light pulse, to a clock cycle (e.g., of a clock signal), to a voltage or current peak or drop, or the like.

The first toggle flipflop circuitry may toggle its state (e.g., between logical low and logical high) at each ripple of the ripple signal (e.g., at a falling edge or at a rising edge of the ripple signal) and, thus, may provide a least-significant bit of the ripple counter circuitry.

The path signal from the one of the first output node and the second output node of the first toggle flipflop circuitry may be toggled (e.g., switched between logical low and logical high) at every second ripple of the ripple signal provided to the first toggle flipflop circuitry. The second toggle flipflop circuitry may toggle its state (e.g., between logical low and logical high) at each ripple (e.g., at a falling edge or at a rising edge of the ripple) of the path signal from the one of the first and second output node of the first toggle flipflop circuitry. Thus, the second toggle flipflop circuitry may provide a second-to-least-significant bit of the ripple counter circuitry. The ripple counter circuitry may include further toggle flipflop circuitries according to any configuration of a toggle flipflop circuitry described above, and may provide, to each of the further toggle flipflop circuitries, a path signal from one of the first and second output node of the respective preceding toggle flipflop circuitry as a count signal.

Thus, each toggle flipflop circuitry of the ripple counter circuitry may represent one bit, and a count value stored in the bits (toggle flipflop circuitries) of the ripple counter circuitry may be incremented at each ripple inputted to the first toggle flipflop circuitry.

For resetting the ripple counter circuitry (e.g., setting all bits of the ripple counter circuitry to zero), for example, when a new counting period starts, a reset signal may be applied to input switches of each toggle flipflop circuitry of the ripple counter circuitry, such that a path signal at the input nodes of the toggle flipflop circuitries may be set to a path signal level that may correspond to a reset value (e.g., zero).

In some embodiments, the ripple counter circuitry is further configured to: provide a negation of the ripple signal as a negated count signal to the first toggle flipflop circuitry; and provide a path signal from the other one of the first output node of the first toggle flipflop circuitry and the second output node of the first toggle flipflop circuitry as a negated count signal to the second toggle flipflop circuitry.

Thus, the toggle flipflop circuitries of the ripple counter circuitry may be provided with both a count signal and a negated count signal, such that a further inverter for generating a negated count signal based on a received count signal may not be necessary in the toggle flipflop circuitries, and an area occupied by the toggle flipflop circuitries may be reduced.

Some embodiments pertain to an image sensor that includes: the ripple counter circuitry according to any configuration described above; and a photosensitive element that is configured to detect single photons; wherein the ripple counter circuitry is configured to receive, from the photosensitive element, a photon detection signal as the ripple signal.

The image sensor may be configured as a photon counting (PC) sensor, a quanta burst imaging (QBI) sensor, a direct time-of-flight (dToF) sensor, an event-based vision sensor (EVS) or the like. The photosensitive element may include a single-photon avalanche diode (SPAD). The photosensitive element may be configured as a jot (which may or may not include a SPAD). The photosensitive element may be configured to output a photon detection signal. The photon detection signal may be configured as an electrical signal that may include a ripple (e.g., voltage or current peak or drop) when a photon is detected at the photosensitive element. Thus, a detected photon may cause a ripple that the ripple counter circuitry may count. The image sensor may include a plurality of ripple counter circuitries and a plurality of photosensitive elements, wherein each of the plurality of ripple counter circuitries may be associated with one or more of the plurality of photosensitive elements (e.g., with a predefined logic combination of photosensitive elements, from which the ripple counter circuitry may receive photon detection signals), such that each of the plurality of ripple counter circuitries may count photons detected by its associated photosensitive element(s). The image sensor may generate an image signal with a plurality of pixels, wherein each pixel may have a value that is based on a number of photons counted by one of the plurality of ripple counter circuitries.

The image sensor may be included in a camera, in a smartphone, in a tablet, in a notebook, in smartglasses, in a head-mounted display, in a vehicle (e.g., for a driver assistance system and/or for an autonomous driving system), in a drone, or the like.

It should be recognized that the embodiments are provided with an exemplary ordering of circuit elements. The specific ordering of circuit elements is, however, given for illustrative purposes only and should not be construed as binding. For example, the ordering of the transistors 121a and 121b in Fig. 9, 14 and/or 17 may be exchanged. Also, the ordering of the transmission gate provided by the transistors 131 and 132 and of the transmission gate provided by the transistors 133 and 134 in Fig. 11 may be exchanged. Further, the ordering of the transmission gate provided by the transistors 131 and 132 and of the transmission gate provided by the transistors 141 and 142 in Fig. 13 may be exchanged. Also, the ordering of the transistors 161 and 162 in Fig. 15 and/or may be exchanged, and/or the ordering of the transistors 171 and 172 in Fig. 16 may be exchanged. Other changes of the ordering of circuit elements may be apparent to the skilled person.

It should be recognized that all switches and/or transistors described in the embodiments may be provided by MOSFETs, by NMOS transistors, by PMOS transistors, by transmission gates, by JFETs, by enhancement-type transistors, by depletion-type transistors, by a series of two or more transistors, by a series-of-parallel or a parallel-of-series coupling of transistors, or the like, and that a decision whether a count signal or a negated count signal is provided at a gate of a specific transistor and/or a decision whether the first count signal level corresponds to logical low or to logical high (and, accordingly, the second count signal level corresponds to logical high or logical low, respectively) may depend on a characteristic of the specific transistor, as may be apparent to the skilled person. It is noted that features of the various embodiments described above may be combined in any suitable manner. It is further noted that a toggle flipflop circuitry according to the disclosure may include further circuit elements that are not described above.

All units and entities described in this specification and claimed in the appended claims can, if not stated otherwise, be implemented as integrated circuit logic, for example on a chip, and functionality provided by such units and entities can, in some cases, be implemented by software.

Note that the present technology can also be configured as described below.

(1) A toggle flipflop circuitry, comprising: a first count switch configured to couple an input node to a first output node during a first count signal level, wherein the first count switch is configured to retard a path signal propagation from the first output node to the input node by a predetermined delay; a first inverter configured to couple a second output node to the first output node; a first switchable active feedback loop configured to selectively propagate a path signal from the input node to the first output node during the first count signal level; a second switchable active feedback loop configured to propagate a negation of a path signal from the second output node to the first output node during a second count signal level different from the first count signal level; and a second count switch configured to selectively couple the input node to the second output node during the second count signal level.

(2) The toggle flipflop circuitry of (1), wherein, after a change from the second count signal level to the first count signal level, the predetermined delay is at least as long as a time required by the first switchable active feedback loop for propagating a path signal from the input node to the first output node.

(3) The toggle flipflop circuitry of (1) or (2), wherein the first count switch includes transistors of opposite conductivity types.

(4) The toggle flipflop circuitry of any one of (1) to (3), wherein the first count switch includes a first transistor and a second transistor coupled serially, wherein a conductivity type of the first transistor is opposite to a conductivity type of the second transistor.

(5) The toggle flipflop circuitry of (4), wherein the first transistor is configured to receive a count signal as gate signal and to switch to a non-blocking mode when the count signal has the first count signal level; and wherein the second transistor is configured to receive a negated count signal as gate signal and to switch to a non-blocking mode when the negated count signal has a negation of the first count signal level.

(6) The toggle flipflop circuitry of any one of (1) to (3), wherein the first count switch includes: a first transistor and a second transistor that are coupled in series and have a first conductivity type; and a third transistor and a fourth transistor that are coupled in series and have a second conductivity type opposite to the first conductivity type; wherein a series of the first transistor and the second transistor is coupled in parallel to a series of the third transistor and the fourth transistor.

(7) The toggle flipflop circuitry of (6), wherein at least one of the first transistor and the second transistor is configured to receive a count signal as gate signal and to switch to a non-blocking mode when the count signal has the first count signal level; and wherein at least one of the third transistor and the fourth transistor is configured to receive a negated count signal as gate signal and to switch to a non-blocking mode when the negated count signal has a negation of the first count signal level.

(8) The toggle flipflop circuitry of (6) or (7), wherein the second transistor is configured to receive a predefined gate signal at which a resistance of the second transistor is higher than a resistance of the first transistor when the count signal has the first count signal level; and wherein the fourth transistor is configured to receive a predefined gate signal at which a resistance of the fourth transistor is higher than a resistance of the third transistor when the negated count signal has the negation of the first count signal level.

(9) The toggle flipflop circuitry of any one of (1) to (8), wherein the first switchable active feedback loop and the second switchable active feedback loop share a second inverter.

(10) The toggle flipflop circuitry of any one of (1) to (9), further comprising an input switch configured to set a predefined path signal level at the input node. (11) The toggle flipflop circuitry of any one of (1) to (10), wherein the second count signal level corresponds to a negation of the first count signal level.

(12) The toggle flipflop circuitry of any one of (1) to (11), wherein the toggle flipflop circuitry is further configured to: receive a count signal configured to switch between the first count signal level and the second count signal level; and switch the first count switch, the second count switch, the first switchable active feedback loop and the second switchable active feedback loop in accordance with the count signal.

(13) A ripple counter circuitry, comprising: a first toggle flipflop circuitry according to any one of (1) to (12); and a second toggle flipflop circuitry according to any one of (1) to (12); wherein the ripple counter circuitry is configured to: provide a ripple signal as a count signal to the first toggle flipflop circuitry; and provide a path signal from one of the first output node of the first toggle flipflop circuitry and the second output node of the first toggle flipflop circuitry as a count signal to the second toggle flipflop circuitry.

(14) The ripple counter circuitry of (13), further configured to: provide a negation of the ripple signal as a negated count signal to the first toggle flipflop circuitry; and provide a path signal from the other one of the first output node of the first toggle flipflop circuitry and the second output node of the first toggle flipflop circuitry as a negated count signal to the second toggle flipflop circuitry.

(15) An image sensor, comprising: the ripple counter circuitry according to (13) or (14); and a photosensitive element configured to detect single photons; wherein the ripple counter circuitry is configured to receive, from the photosensitive element, a photon detection signal as the ripple signal.

Claims

1. A toggle flipflop circuitry, comprising: a first count switch configured to couple an input node to a first output node during a first count signal level, wherein the first count switch is configured to retard a path signal propagation from the first output node to the input node by a predetermined delay; a first inverter configured to couple a second output node to the first output node; a first switchable active feedback loop configured to selectively propagate a path signal from the input node to the first output node during the first count signal level; a second switchable active feedback loop configured to propagate a negation of a path signal from the second output node to the first output node during a second count signal level different from the first count signal level; and a second count switch configured to selectively couple the input node to the second output node during the second count signal level.

2. The toggle flipflop circuitry of claim 1, wherein, after a change from the second count signal level to the first count signal level, the predetermined delay is at least as long as a time required by the first switchable active feedback loop for propagating a path signal from the input node to the first output node.

3. The toggle flipflop circuitry of claim 1, wherein the first count switch includes transistors of opposite conductivity types.

4. The toggle flipflop circuitry of claim 1, wherein the first count switch includes a first transistor and a second transistor coupled serially, wherein a conductivity type of the first transistor is opposite to a conductivity type of the second transistor.

5. The toggle flipflop circuitry of claim 4, wherein the first transistor is configured to receive a count signal as gate signal and to switch to a non-blocking mode when the count signal has the first count signal level; and wherein the second transistor is configured to receive a negated count signal as gate signal and to switch to a non-blocking mode when the negated count signal has a negation of the first count signal level.

6. The toggle flipflop circuitry of claim 1, wherein the first count switch includes: a first transistor and a second transistor that are coupled in series and have a first conductivity type; and a third transistor and a fourth transistor that are coupled in series and have a second conductivity type opposite to the first conductivity type; wherein a series of the first transistor and the second transistor is coupled in parallel to a series of the third transistor and the fourth transistor.

7. The toggle flipflop circuitry of claim 6, wherein at least one of the first transistor and the second transistor is configured to receive a count signal as gate signal and to switch to a non-blocking mode when the count signal has the first count signal level; and wherein at least one of the third transistor and the fourth transistor is configured to receive a negated count signal as gate signal and to switch to a non-blocking mode when the negated count signal has a negation of the first count signal level.

8. The toggle flipflop circuitry of claim 6, wherein the second transistor is configured to receive a predefined gate signal at which a resistance of the second transistor is higher than a resistance of the first transistor when the count signal has the first count signal level; and wherein the fourth transistor is configured to receive a predefined gate signal at which a resistance of the fourth transistor is higher than a resistance of the third transistor when the negated count signal has the negation of the first count signal level.

9. The toggle flipflop circuitry of claim 1, wherein the first switchable active feedback loop and the second switchable active feedback loop share a second inverter.

10. The toggle flipflop circuitry of claim 1, further comprising an input switch configured to set a predefined path signal level at the input node.

11. The toggle flipflop circuitry of claim 1, wherein the second count signal level corresponds to a negation of the first count signal level.

12. The toggle flipflop circuitry of claim 1, wherein the toggle flipflop circuitry is further configured to: receive a count signal configured to switch between the first count signal level and the second count signal level; and switch the first count switch, the second count switch, the first switchable active feedback loop and the second switchable active feedback loop in accordance with the count signal.

13. A ripple counter circuitry, comprising: a first toggle flipflop circuitry that includes: a first count switch configured to couple a first input node to a first output node during a first count signal level, wherein the first count switch is configured to retard a path signal propagation from the first output node to the first input node by a predetermined delay; a first inverter configured to couple a second output node to the first output node; a first switchable active feedback loop configured to selectively propagate a path signal from the first input node to the first output node during the first count signal level; a second switchable active feedback loop configured to propagate a negation of a path signal from the second output node to the first output node during a second count signal level different from the first count signal level; and a second count switch configured to selectively couple the first input node to the second output node during the second count signal level; and a second toggle flipflop circuitry that includes: a third count switch configured to couple a second input node to a third output node during a first count signal level, wherein the third count switch is configured to retard a path signal propagation from the third output node to the second input node by a predetermined delay; a third inverter configured to couple a fourth output node to the third output node; a third switchable active feedback loop configured to selectively propagate a path signal from the second input node to the third output node during the first count signal level; a fourth switchable active feedback loop configured to propagate a negation of a path signal from the fourth output node to the third output node during a second count signal level different from the first count signal level; and a fourth count switch configured to selectively couple the second input node to the fourth output node during the second count signal level; wherein the ripple counter circuitry is configured to: provide a ripple signal as a count signal to the first toggle flipflop circuitry; and provide a path signal from one of the first output node of the first toggle flipflop circuitry and the second output node of the first toggle flipflop circuitry as a count signal to the second toggle flipflop circuitry.

14. The ripple counter circuitry of claim 13, further configured to: provide a negation of the ripple signal as a negated count signal to the first toggle flipflop circuitry; and provide a path signal from the other one of the first output node of the first toggle flipflop circuitry and the second output node of the first toggle flipflop circuitry as a negated count signal to the second toggle flipflop circuitry.

15. An image sensor, comprising: a ripple counter circuitry that includes: a first toggle flipflop circuitry that includes: a first count switch configured to couple a first input node to a first output node during a first count signal level, wherein the first count switch is configured to retard a path signal propagation from the first output node to the first input node by a predetermined delay; a first inverter configured to couple a second output node to the first output node; a first switchable active feedback loop configured to selectively propagate a path signal from the first input node to the first output node during the first count signal level; a second switchable active feedback loop configured to propagate a negation of a path signal from the second output node to the first output node during a second count signal level different from the first count signal level; and a second count switch configured to selectively couple the first input node to the second output node during the second count signal level; and a second toggle flipflop circuitry that includes: a third count switch configured to couple a second input node to a third output node during a first count signal level, wherein the third count switch is configured to retard a path signal propagation from the third output node to the second input node by a predetermined delay; a third inverter configured to couple a fourth output node to the third output node; a third switchable active feedback loop configured to selectively propagate a path signal from the second input node to the third output node during the first count signal level; a fourth switchable active feedback loop configured to propagate a negation of a path signal from the fourth output node to the third output node during a second count signal level different from the first count signal level; and a fourth count switch configured to selectively couple the second input node to the fourth output node during the second count signal level; wherein the ripple counter circuitry is configured to: provide a ripple signal as a count signal to the first toggle flipflop circuitry; provide a path signal from one of the first output node of the first toggle flipflop circuitry and the second output node of the first toggle flipflop circuitry as a count signal to the second toggle flipflop circuitry; and a photosensitive element configured to detect single photons; wherein the ripple counter circuitry is configured to receive, from the photosensitive element, a photon detection signal as the ripple signal.