WO2025112486A1 - 一种内存容量调整方法、装置、电子设备和存储介质 - Google Patents

一种内存容量调整方法、装置、电子设备和存储介质 Download PDF

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Publication number
WO2025112486A1
WO2025112486A1 PCT/CN2024/100746 CN2024100746W WO2025112486A1 WO 2025112486 A1 WO2025112486 A1 WO 2025112486A1 CN 2024100746 W CN2024100746 W CN 2024100746W WO 2025112486 A1 WO2025112486 A1 WO 2025112486A1
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Prior art keywords
memory
value
memory bank
bank value
detection data
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PCT/CN2024/100746
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English (en)
French (fr)
Inventor
孙秀强
成珊
刘宝俊
张炳会
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Suzhou Metabrain Intelligent Technology Co Ltd
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Suzhou Metabrain Intelligent Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating
    • G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files

Definitions

  • the present application relates to the field of computer systems and storage technology, and in particular to a memory capacity adjustment method, a memory capacity adjustment device, an electronic device and a storage medium.
  • embodiments of the present application are proposed to provide a memory capacity adjustment method, a memory capacity adjustment device, an electronic device and a storage medium that overcome the above problems or at least partially solve the above problems.
  • an embodiment of the present application discloses a memory capacity adjustment method, which is applied to a server, wherein the server is provided with at least one central processing unit, the central processing unit is connected to at least one memory stick, the central processing unit is deployed with a basic input and output system, and the basic input and output system stores the total memory capacity corresponding to the memory stick, and the method comprises:
  • the memory setting value is obtained
  • the control basic input output system starts based on the updated configuration serial detection data.
  • the step of generating the first memory bank value according to the configuration serial detection data of the memory bar includes:
  • the address of the memory bar is read to generate a configuration serial detection structure
  • the bank number value in the serial probe data will be configured as the first bank value.
  • determining the configuration serial detection data according to the configuration serial detection structure includes:
  • the configuration serial detection data is generated according to the data of each message position of the configuration serial detection structure.
  • the step of determining the second memory bank value according to the memory setting value, the total memory capacity and the first memory bank value is:
  • the second memory bank value is determined according to the adjustment multiple value and the first memory bank value.
  • the second memory bank value is a memory bank value that meets user requirements.
  • the step of determining the adjustment multiple value according to the memory setting value and the total memory capacity includes:
  • the step of determining the second memory bank value according to the adjustment multiple value and the first memory bank value includes:
  • a second memory bank value is calculated according to the adjustment factor value and the first memory bank value.
  • the adjustment direction is determined according to the adjustment multiple value, including:
  • Adjusting the multiplier has a temporary effect and reduces the number of memory banks.
  • the step of calculating the second memory bank value according to the adjustment multiple value and the first memory bank value includes:
  • the product of the adjustment multiple value and the first memory bank value is calculated as a second memory bank value, and the second memory bank value is smaller than the first memory bank value.
  • the step of calculating the second memory bank value according to the adjustment multiple value and the first memory bank value includes:
  • the product of the adjustment multiple value and the first memory bank value is calculated as a second memory bank value, and the second memory bank value is greater than the first memory bank value.
  • the step of updating the first memory bank value according to the second memory bank value to update the configuration serial detection data includes:
  • the first memory bank value is replaced with the second memory bank value.
  • controlling the basic input and output system to start based on the updated configuration serial detection data includes:
  • the memory is set.
  • the step of updating the first memory bank value according to the second memory bank value to update the configuration serial detection data further includes:
  • the updated first memory bank value is written into the configuration serial detection data.
  • the method further comprises:
  • the first memory bank value is determined as the default restored memory bank value.
  • the preset restore memory bank value is pre-set data for restoring the number of memory banks; the size of the preset restore memory bank value is set according to the architecture of the server.
  • the method further comprises:
  • the method further comprises:
  • the memory setting value is modified.
  • an embodiment of the present application discloses a memory capacity adjustment device, which is applied to a server, wherein the server is provided with at least one central processing unit, the central processing unit is connected to at least one memory stick, the central processing unit is deployed with a basic input and output system, and the basic input and output system stores the total memory capacity corresponding to the memory stick, and the device comprises:
  • An acquisition module is used to acquire a memory setting value during the startup of the basic input and output system, where the memory setting value is a multiple of the total memory capacity;
  • a first memory bank value determination module configured to generate a first memory bank value according to the configuration serial detection data of the memory bar
  • a second memory bank value determination module used to determine a second memory bank value according to a memory setting value, a total memory capacity and a first memory bank value
  • An updating module used for updating the first memory bank value according to the second memory bank value, so as to update the configuration serial detection data
  • the startup module is used to control the basic input and output system to start based on the updated configuration serial detection data.
  • an embodiment of the present application discloses an electronic device, including a processor, a memory, and a computer program stored in the memory and capable of running on the processor, and when the computer program is executed by the processor, the steps of the above memory capacity adjustment method are implemented.
  • an embodiment of the present application discloses a computer non-volatile readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above memory capacity adjustment method are implemented.
  • the embodiment of the present application obtains a memory setting value during the startup of a basic input/output system; generates a first memory bank value according to the configuration serial detection data of a memory stick; determines a second memory bank value according to the memory setting value, the total memory capacity and the first memory bank value; updates the first memory bank value according to the second memory bank value to update the configuration serial detection data; controls the basic input/output system to start based on the updated configuration serial detection data; and adjusts the memory bank value of the memory capacity based on the memory setting value when initializing the basic input/output system during the startup of the server to achieve automatic dynamic adjustment of the memory capacity of the entire server, thereby meeting the actual business needs of customers, increasing the service life of the memory and reducing the operation and maintenance costs.
  • FIG1 is a flowchart of a memory capacity adjustment method according to an embodiment of the present invention.
  • FIG2 is a flowchart of another memory capacity adjustment method embodiment of the present application.
  • FIG3 is a schematic diagram of a memory physical link diagram of an example of a memory capacity adjustment method of the present application.
  • FIG4 is a flowchart of an example of a method for adjusting memory capacity of the present application.
  • FIG5 is a timing diagram of the execution of steps of an example of a memory capacity adjustment method of the present application.
  • FIG6 is a memory schematic diagram of an example of a memory capacity adjustment method of the present application.
  • FIG7 is a memory schematic diagram of another memory capacity adjustment method example of the present application.
  • FIG8 is a structural block diagram of an embodiment of a memory capacity adjustment device of the present application.
  • FIG9 is a structural block diagram of an electronic device provided in an embodiment of the present application.
  • FIG. 10 is a structural block diagram of a storage medium provided in an embodiment of the present application.
  • the memory capacity adjustment method is applied to a server.
  • the server is provided with at least one central processing unit, the central processing unit is connected to at least one memory stick, the central processing unit is deployed with a basic input and output system, and the basic input and output system stores the total memory capacity corresponding to the memory stick.
  • the memory capacity adjustment method may specifically include the following steps:
  • Step 101 during the basic input and output system startup process, obtaining a memory setting value
  • a memory setting value can be obtained, which is in a multiple relationship with the total memory capacity; for example, the memory setting value is twice the total memory capacity; the total memory capacity is twice the memory setting value, that is, the memory setting value is half of the total memory capacity.
  • Step 102 generating a first memory bank value according to the configuration serial detection data of the memory bar
  • the server can read the configuration serial detection data of the memory module, and the configuration serial detection data is SPD (Serial Presence Detect) data.
  • SPD is a memory on the memory module, which is used to store the parameter information of the memory module. This information is read and saved to the motherboard chipset when the computer starts, so that the system can correctly configure the memory controller.
  • the memory bank value recorded therein is determined to be the first memory bank value.
  • the memory bank value is the number value of the Bank in the memory.
  • Step 103 determining a second memory bank value according to a memory setting value, a total memory capacity, and a first memory bank value
  • the memory bank value to be changed namely the second memory bank value, is determined according to the memory setting value, the total memory capacity and the first memory bank value, wherein the second memory bank value is the memory bank value that meets the user's needs.
  • Step 104 updating the first memory bank value according to the second memory bank value to update the configuration serial detection data
  • the first memory bank value is updated according to the second memory bank value
  • the second memory bank value is used as the memory bank value in this startup initialization
  • the second memory bank value is updated to the configuration serial detection data to update the configuration serial detection data.
  • Step 105 controlling the basic input and output system to start based on the updated configuration serial detection data.
  • the basic input and output system is controlled to start based on the updated configuration serial detection data, so that the content capacity of the memory after the initialization startup can meet the user's needs without affecting the operating efficiency.
  • the embodiment of the present application obtains a memory setting value during the startup of a basic input/output system; generates a first memory bank value according to the configuration serial detection data of a memory stick; determines a second memory bank value according to the memory setting value, the total memory capacity and the first memory bank value; updates the first memory bank value according to the second memory bank value to update the configuration serial detection data; controls the basic input/output system to start based on the updated configuration serial detection data; and adjusts the memory bank value of the memory capacity based on the memory setting value when initializing the basic input/output system during the startup of the server to achieve automatic dynamic adjustment of the memory capacity of the entire server, thereby meeting the actual business needs of customers, increasing the service life of the memory and reducing the operation and maintenance costs.
  • the memory capacity adjustment method is applied to a server, the server is provided with at least one central processing unit, the central processing unit is connected to at least one memory stick, the central processing unit is deployed with a basic input and output system and a memory stick, the basic input and output system stores The total memory capacity corresponding to the memory stick.
  • the server is provided with at least one central processing unit. As shown in FIG3 , two central processing units (CPUs) may be provided, each of which is connected to at least one memory stick, and the number of memory sticks connected to each central processing unit is the same.
  • the central processing unit is deployed with a basic input output system (BIOS) and a memory stick.
  • BIOS basic input output system
  • the memory stick is used by the server to store data.
  • the basic input output system stores the total memory capacity corresponding to the memory stick to process data within the limitation of the total memory capacity.
  • the memory adjustment capacity adjustment method may specifically include the following steps:
  • Step 201 during the basic input and output system startup process, obtain the memory setting value.
  • the memory setting value preset by the user can be obtained during the basic input and output system startup process.
  • the method further includes:
  • Step S1 in response to an input instruction for a memory setting value, modify the memory setting value.
  • an input instruction for the memory setting value can be sent to the server.
  • the input instruction includes the adjustment value of the memory setting value.
  • the memory setting value is modified to the adjustment value to meet the user's real-time adjustment needs.
  • Step 202 Generate a first memory bank value according to the configuration serial detection data of the memory bank.
  • the memory stick configuration serial detection data can be read from the address of the memory stick, and the structure of the configuration serial detection data is consistent for each memory.
  • the data corresponding to the memory bank quantity flag can be read from the memory stick configuration serial detection data and determined as the first memory bank value.
  • the step of generating a first memory bank value based on the configuration serial detection data of the memory stick includes: reading the address of the memory stick through a bidirectional two-wire synchronous serial bus protocol to generate a configuration serial detection structure; determining the configuration serial detection data based on the configuration serial detection structure; and setting the memory bank quantity value in the configuration serial detection data as the first memory bank value.
  • the address of the memory stick can be read through the I2C protocol, that is, the data in the I2C address of the memory stick is read to generate a configuration serial detection structure. Then, based on the data of each message position of the configuration serial detection structure, the configuration serial detection data is generated, and the memory bank quantity value recorded in the configuration serial detection data is determined as the first memory bank value.
  • the first memory bank value is the memory bank value of the current memory.
  • Step 203 determining a second memory bank value according to the memory setting value, the total memory capacity and the first memory bank value.
  • the increase or decrease of memory is determined based on the memory setting value and the total memory capacity; the increase or decrease range is determined in combination with the first memory bank value, and then the second memory bank value is determined. That is, the second memory bank value is the adjusted memory bank value.
  • the step of determining the second memory bank value according to the memory setting value, the total memory capacity and the first memory bank value includes:
  • Sub-step S2031 determining an adjustment multiple value according to the memory setting value and the total memory capacity
  • the adjustment multiple value can be determined based on the mathematical relationship between the memory setting value and the total memory capacity to determine the direction of adjustment. If the memory setting value is several times the total memory capacity, the number of memory banks will be increased; conversely, if the memory setting value is one-half of the total memory capacity, the number of memory banks will be reduced.
  • the step of determining the adjustment multiple value according to the memory setting value and the total memory capacity includes: calculating the ratio of the memory setting value to the total memory capacity, and determining the ratio as the adjustment multiple value.
  • the ratio of the memory setting value to the total memory capacity can be calculated and the ratio can be determined as the adjustment multiple value. That is, when the ratio is greater than 1, the number of memory banks is increased; conversely, when the ratio is less than 1, the number of memory banks is reduced; and when the ratio is 1, the number of memory banks remains unchanged.
  • Sub-step S2032 determining the second memory bank value according to the adjustment multiple value and the first memory bank value.
  • the adjustment range is determined according to the adjustment multiple value and the first memory bank value, and the second memory bank value is determined.
  • the step of determining the second memory bank value based on the adjustment multiple value and the first memory bank value includes: judging whether the adjustment multiple is one; in response to the adjustment multiple being one, determining that the second memory bank value is equal to the first memory bank value; in response to the adjustment multiple not being one, calculating the second memory bank value based on the adjustment multiple value and the first memory bank value.
  • the second memory bank value it may be first determined whether the adjustment multiple is one. When the adjustment multiple is one, that is, the number of memory banks remains unchanged. In response to the adjustment multiple being one, it may be determined that the second memory bank value is equal to the first memory bank value, and the number of memory banks remains unchanged. When the adjustment multiple is not one, that is, the number of memory banks needs to be increased or decreased, the second memory bank value may be calculated based on the adjustment multiple value and the first memory bank value.
  • the step of calculating the second memory bank value according to the adjustment multiple value and the first memory bank value includes: calculating the product of the adjustment multiple value and the first memory bank value as the second memory bank value, and the second memory bank value is less than the first memory bank value.
  • the product of the adjustment multiple value and the first memory bank value can be calculated as the second memory bank value, and the second memory bank value is less than the first memory bank value.
  • the step of calculating the second memory bank value according to the adjustment multiple value and the first memory bank value includes: calculating the product of the adjustment multiple value and the first memory bank value as the second memory bank value, and the second memory bank value is greater than the first memory bank value.
  • the product of the adjustment multiple value and the first memory bank value can be calculated as the second memory bank value, and the second memory bank value is greater than the first memory bank value.
  • Step 204 updating the first memory bank value according to the second memory bank value to update the configuration serial detection data.
  • the first memory bank value is updated according to the second memory bank value so that the second memory bank value can be used to set the memory, and the set first memory bank value is written back to the configuration serial detection data to update the configuration serial detection data.
  • the step of updating the first memory bank value according to the second memory bank value to update the configuration serial detection data includes:
  • Step 2041 replacing the first memory bank value with the second memory bank value.
  • the second memory bank value may be used to replace the position of the first memory bank value in the configuration serial detection data to update the first memory bank value, thereby updating the configuration serial detection data.
  • step of updating the first memory bank value according to the second memory bank value to update the configuration serial detection data further includes: writing the updated first memory bank value into the configuration serial detection data.
  • the first memory bank value may be written into the configuration serial detection data to update the serial detection data.
  • Step 205 controlling the basic input and output system to start based on the updated configuration serial detection data.
  • the basic input and output system can be controlled to start based on the updated configuration serial detection data, so as to set the memory when the server is powered on and initialized.
  • Step 206 receiving a memory restoration setting instruction.
  • the server receives the memory restoration setting instruction.
  • Step 207 determine the first memory bank value as the preset restored memory bank value.
  • the current first memory bank value in the configuration serial detection data can be set as a preset restoration memory bank value.
  • the preset restoration memory bank value is pre-set data for restoring the number of memory banks.
  • the size of the preset restoration memory bank value can be set according to the architecture of the server, and the embodiment of the present application does not limit this.
  • Step 208 using the preset restored memory library value to update the configuration serial detection data.
  • the preset restoration memory library value can be written into the configuration serial detection data to update the configuration serial detection data, so that when the service is started, the new configuration serial detection data can be obtained to set the memory.
  • the BIOS when the server is started, the BIOS, as the startup management firmware, first obtains the memory setting value of the memory capacity set by the BIOS, and then makes further adjustments based on the memory setting value. If the memory setting value is not the maximum capacity setting, the BIOS needs to read the SPD data structure of each memory I2C address through the I2C protocol, and dynamically modulate the memory bank value in the obtained SPD data structure accordingly, such as 1 corresponds to 1 Bank, 2 corresponds to 2 Banks, and 4 corresponds to 4 Banks. The memory bank value is set according to actual needs, and the SPD data of the set memory bank value is written back to the SPD data structure of each memory.
  • BIOS obtains the SPD data structure of the I2C address of each memory stick through the I2C protocol, and adjusts the memory bank value of the memory in the SPD data structure to implement unmanned dynamic disassembly of the server memory stick, thereby dynamically adjusting the memory capacity of the entire server and meeting the actual business needs of customers, increasing the service life of the memory and reducing operation and maintenance costs, and is not restricted by any server architecture, thereby increasing the scope of application.
  • the server is equipped with two CPUs (Central Processing Units), and each CPU (CPU1, CPU2) is connected to its own memory stick through the I2C protocol.
  • CPUs Central Processing Units
  • CPU1, CPU2 Central Processing Units
  • FIG4 shows a step flow chart of an example of a memory adjustment capacity adjustment method of the present application
  • FIG5 shows a step execution sequence chart of an example of a memory adjustment capacity adjustment method of the present application.
  • BIOS After BIOS obtains the preset value of the total memory capacity, it determines whether the preset value of the total memory capacity is the maximum value. If the preset value of the total memory capacity is the maximum value, BIOS does not make any adjustment or change to the SPD data structure of the memory on the server, and boots according to the SPD default data of each memory;
  • BIOS If the preset value of the total memory capacity obtained by BIOS is one-half, BIOS reads the data of each memory SPD address through the I2C bus at the beginning of memory initialization, modifies the Bank value of the obtained SPD data from 4 banks to 2 banks and writes it back to the SPD data; continues to start the server and enter the operating system; the modified memory can be referred to Figure 6.
  • BIOS If the preset value of the total memory capacity obtained by BIOS is one quarter, BIOS reads the data of each memory SPD address through the I2C bus at the beginning of memory initialization, modifies the Bank value (memory library value) of the obtained SPD data from 4 banks (libraries) to 1 Bank value and writes it back to the SPD data; continues to start the server and enter the operating system; the modified memory can be referred to Figure 7.
  • step 3 or 4 If the customer wants to restore the memory capacity from the modified value to the maximum value, follow step 3 or 4 to modify the memory bank value of the memory.
  • the memory capacity adjustment device is applied to a server.
  • the server is provided with at least one central processing unit, the central processing unit is connected to at least one memory stick, the central processing unit is deployed with a basic input and output system, and the basic input and output system stores the total memory capacity corresponding to the memory stick.
  • the memory capacity adjustment device may specifically include the following modules:
  • the acquisition module 801 is used to acquire the memory setting value during the basic input and output system startup process
  • a first memory bank value determination module 802 configured to generate a first memory bank value according to the configuration serial detection data of the memory bank
  • a second memory bank value determination module 803, configured to determine a second memory bank value according to a memory setting value, a total memory capacity and a first memory bank value;
  • An updating module 804 configured to update the first memory bank value according to the second memory bank value, so as to update the configuration serial detection data
  • the startup module 805 is used to control the basic input and output system to start based on the updated configuration serial detection data.
  • the first memory bank value determination module 802 includes:
  • the reading submodule is used to read the address of the memory stick through a bidirectional two-wire synchronous serial bus protocol and generate a configuration serial detection structure;
  • the configuration serial detection data submodule is used to determine the configuration serial detection data according to the configuration serial detection structure
  • the first memory bank value determination submodule is used to configure the memory bank quantity value in the serial detection data as the first memory bank value.
  • the second memory bank value determination module 803 includes:
  • An adjustment multiple value determination submodule is used to determine the adjustment multiple value according to the memory setting value and the total memory capacity
  • the second memory bank value determination submodule is used to determine the second memory bank value according to the adjustment multiple value and the first memory bank value.
  • the adjustment multiple value determination submodule includes:
  • the first calculation unit is used to calculate the ratio of the memory setting value to the total memory capacity
  • the adjustment multiple value determining unit is used to determine the ratio as the adjustment multiple value.
  • the second memory bank value determination submodule includes:
  • a judging unit used to judge whether the adjustment multiple is one
  • a first response unit configured to determine that the second memory bank value is equal to the first memory bank value in response to the adjustment multiple being one
  • the second response unit is used for calculating the second memory bank value according to the adjustment multiple value and the first memory bank value in response to the adjustment multiple being different from one.
  • the second response unit when the adjustment multiple is less than one, includes:
  • the second calculation subunit is used to calculate the product of the adjustment multiple value and the first memory bank value as a second memory bank value, and the second memory bank value is smaller than the first memory bank value.
  • the second response unit when the adjustment multiple is greater than one, includes:
  • the third calculation subunit is used to calculate the product of the adjustment multiple value and the first memory bank value to be the second memory bank value, The second memory bank value is greater than the first memory bank value.
  • the updating module 804 includes:
  • the replacement submodule is used to replace the first memory bank value with the second memory bank value.
  • the update module 804 further includes:
  • the updated first memory bank value is written into the configuration serial detection data.
  • the device further comprises:
  • a receiving module used for receiving a memory restoration setting instruction
  • the restored memory bank value determination module is used to determine the first memory bank value as a preset restored memory bank value.
  • the device further comprises:
  • the restore module is used to update the configuration serial detection data using a preset restore memory library value.
  • the device further comprises:
  • the modification module is used to modify the memory setting value in response to an input instruction for the memory setting value.
  • the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.
  • an embodiment of the present application further provides an electronic device, including:
  • a processor 901 and a storage medium 902 stores a computer program executable by the processor 901, and when the electronic device is running, the processor 901 executes the computer program to perform a memory capacity adjustment method as in any one of the embodiments of the present application.
  • the memory capacity adjustment method is applied to a server, the server is provided with at least one central processing unit, the central processing unit is connected to at least one memory stick, the central processing unit is deployed with a basic input and output system and a memory stick, the basic input and output system stores the total memory capacity corresponding to the memory stick, and the method includes:
  • the memory setting value is obtained
  • the control basic input output system starts based on the updated configuration serial detection data.
  • the step of generating the first memory bank value according to the configuration serial detection data of the memory bar includes:
  • the address of the memory bar is read to generate a configuration serial detection structure
  • the bank number value in the serial probe data will be configured as the first bank value.
  • the step of determining the second memory bank value according to the memory setting value, the total memory capacity and the first memory bank value is:
  • the second memory bank value is determined according to the adjustment multiple value and the first memory bank value.
  • the step of determining the adjustment multiple value according to the memory setting value and the total memory capacity includes:
  • the step of determining the second memory bank value according to the adjustment multiple value and the first memory bank value includes:
  • a second memory bank value is calculated according to the adjustment factor value and the first memory bank value.
  • the step of calculating the second memory bank value according to the adjustment multiple value and the first memory bank value includes:
  • the product of the adjustment multiple value and the first memory bank value is calculated as a second memory bank value, and the second memory bank value is smaller than the first memory bank value.
  • the step of calculating the second memory bank value according to the adjustment multiple value and the first memory bank value includes:
  • the product of the adjustment multiple value and the first memory bank value is calculated as a second memory bank value, and the second memory bank value is greater than the first memory bank value.
  • the step of updating the first memory bank value according to the second memory bank value to update the configuration serial detection data includes:
  • the first memory bank value is replaced with the second memory bank value.
  • the step of updating the first memory bank value according to the second memory bank value to update the configuration serial detection data further includes:
  • the updated first memory bank value is written into the configuration serial detection data.
  • the method further comprises:
  • the first memory bank value is determined as the default restored memory bank value.
  • the method further comprises:
  • the method further comprises:
  • the memory setting value is modified.
  • the memory may include a random access memory (RAM) or a non-volatile memory, such as at least one disk storage.
  • the memory may also be at least one storage device located away from the aforementioned processor.
  • processors can be general-purpose processors, including central processing units (CPU), network processors (NP), etc.; they can also be digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.
  • CPU central processing units
  • NP network processors
  • DSP digital signal processors
  • ASIC application specific integrated circuits
  • FPGA field programmable gate arrays
  • the embodiment of the present application further provides a computer non-volatile readable storage medium 1001, on which a computer program is stored, and when the computer program is run by a processor, a memory capacity adjustment method as in any one of the embodiments of the present application is executed.
  • the memory capacity adjustment method is applied to a server, wherein the server is provided with at least one central processing unit, the central processing unit is connected to at least one memory stick, the central processing unit is deployed with a basic input and output system, and the basic input and output system stores the total memory capacity corresponding to the memory stick, and the method comprises:
  • a memory setting value is obtained, and the memory setting value is in a multiple relationship with the total memory capacity
  • the control basic input output system starts based on the updated configuration serial detection data.
  • the step of generating the first memory bank value according to the configuration serial detection data of the memory bar includes:
  • the address of the memory bar is read to generate a configuration serial detection structure
  • the bank number value in the serial probe data will be configured as the first bank value.
  • the step of determining the second memory bank value according to the memory setting value, the total memory capacity and the first memory bank value is:
  • the second memory bank value is determined according to the adjustment multiple value and the first memory bank value.
  • the step of determining the adjustment multiple value according to the memory setting value and the total memory capacity includes:
  • the step of determining the second memory bank value according to the adjustment multiple value and the first memory bank value includes:
  • a second memory bank value is calculated according to the adjustment factor value and the first memory bank value.
  • the step of calculating the second memory bank value according to the adjustment multiple value and the first memory bank value includes:
  • the product of the adjustment multiple value and the first memory bank value is calculated as a second memory bank value, and the second memory bank value is smaller than the first memory bank value.
  • the step of calculating the second memory bank value according to the adjustment multiple value and the first memory bank value includes:
  • the product of the adjustment multiple value and the first memory bank value is calculated as a second memory bank value, and the second memory bank value is greater than the first memory bank value.
  • the step of updating the first memory bank value according to the second memory bank value to update the configuration serial detection data includes:
  • the first memory bank value is replaced with the second memory bank value.
  • the step of updating the first memory bank value according to the second memory bank value to update the configuration serial detection data further includes:
  • the updated first memory bank value is written into the configuration serial detection data.
  • the method further comprises:
  • the first memory bank value is determined as the default restored memory bank value.
  • the method further comprises:
  • the method further comprises:
  • the memory setting value is modified.
  • the embodiments of the present application can be provided as methods, devices, or computers. Therefore, the embodiments of the present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM (Compact Disc Read-Only Memory), optical storage, etc.) containing computer-usable program codes.
  • computer-usable storage media including but not limited to disk storage, CD-ROM (Compact Disc Read-Only Memory), optical storage, etc.
  • each process and/or box in the flowchart and/or block diagram, and the combination of the process and/or box in the flowchart and/or block diagram can be realized by computer program instructions.
  • These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device produce a device for realizing the function specified in one process or multiple processes in the flowchart and/or one box or multiple boxes in the block diagram.
  • These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce computer-implemented processing, so that the instructions executed on the computer or other programmable terminal device provide steps for implementing the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.

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Abstract

一种内存容量调整方法、装置、电子设备和存储介质，在基本输入输出系统启动过程中，获取内存设置值；依据内存条的配置串行探测数据，生成第一内存库值；依据内存设置值、内存总容量和第一内存库值，确定第二内存库值；依据第二内存库值更新第一内存库值，以更新配置串行探测数据；控制基本输入输出系统基于更新后的配置串行探测数据进行启动。

Description

一种内存容量调整方法、装置、电子设备和存储介质
相关申请的交叉引用
本申请要求在2023年12月1日提交中国专利局、申请号为202311639474.6、名称为“一种内存容量调整方法、装置、电子设备和存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及计算机系统及存储技术领域，特别是涉及一种内存容量调整方法、一种内存容量调整装置、一种电子设备和一种存储介质。
背景技术
在计算机系统中，所有的数据信息均需要运行在内存上，即使部分处理器会支持一定容量的缓存功能，但这些缓存功能也只是为处理器开机运行时提供的基本指令运行需求而已。同样的BIOS(Basic Input Output System，基本输入输出系统)镜像运行也需要运行在一定的内存空间上，服务器开机启动的自检程序及系统下运行的应用程序均需要一定数量的内存进行支持，所以，内存是任何架构计算机产品中必须存在的物理设备。内存在服务器运行中内存容量的大小影响着运行效率，因此为了提高运行效率，常内存最大化配置，即数据中心的服务器均是内存最大化配置。但是这样的配置存在内存的浪费，容易导致耗电量增加，以及降低内存的使用寿命。
发明内容
鉴于上述问题，提出了本申请实施例以便提供一种克服上述问题或者至少部分地解决上述问题的一种内存容量调整方法、一种内存容量调整装置、一种电子设备和一种存储介质。
为了解决上述问题，在本申请的第一个方面，本申请实施例公开了一种内存容量调整方法，应用于服务器，服务器设置至少一路中央处理器，中央处理器与至少一个内存条连接，中央处理器部署有基本输入输出系统，基本输入输出系统存储有内存条对应的内存总容量，方法包括：
在基本输入输出系统启动过程中，获取内存设置值；
依据内存条的配置串行探测数据，生成第一内存库值；
依据内存设置值、内存总容量和第一内存库值，确定第二内存库值；
依据第二内存库值更新第一内存库值，以更新配置串行探测数据；
控制基本输入输出系统基于更新后的配置串行探测数据进行启动。
可选地，依据内存条的配置串行探测数据，生成第一内存库值的步骤包括：
通过双向二线制同步串行总线协议，读取内存条的地址，生成配置串行探测结构体；
依据配置串行探测结构体确定配置串行探测数据；
将配置串行探测数据中的内存库数量值为第一内存库值。
可选地，依据配置串行探测结构体确定配置串行探测数据，包括：
依据配置串行探测结构体的各个报文位置的数据，生成配置串行探测数据。
可选地，依据内存设置值、内存总容量和第一内存库值，确定第二内存库值的步骤：
依据内存设置值和内存总容量确定调整倍数值；
依据调整倍数值和第一内存库值，确定第二内存库值。
可选地，第二内存库值为满足用户需求的内存库值。
可选地，依据内存设置值和内存总容量确定调整倍数值的步骤包括：
计算内存设置值和内存总容量的比值，
确定比值为调整倍数值。
可选地，依据调整倍数值和第一内存库值，确定第二内存库值的步骤包括：
判断调整倍数是否为一；
响应于调整倍数为一，确定第二内存库值与第一内存库值等同；
响应于调整倍数不为一，依据调整倍数值和第一内存库值计算第二内存库值。
可选地依据调整倍数值，确定调整方向，包括：
调整倍数大于一时，增加内存库数量；
调整倍数效于一时，减少内存库数量。
可选地，调整倍数小于一时，依据调整倍数值和第一内存库值计算第二内存库值的步骤包括：
计算调整倍数值与第一内存库值的乘积值为第二内存库值，第二内存库值小于第一内存库值。
可选地，调整倍数大于一时，依据调整倍数值和第一内存库值计算第二内存库值的步骤包括：
计算调整倍数值与第一内存库值的乘积值为第二内存库值，第二内存库值大于第一内存库值。
可选地，依据第二内存库值更新第一内存库值，以更新配置串行探测数据的步骤包括：
采用第二内存库值替换第一内存库值。
可选地，控制基本输入输出系统基于更新后的配置串行探测数据进行启动，包括：
在服务器开机初始化时，对内存进行设置。
可选地，依据第二内存库值更新第一内存库值，以更新配置串行探测数据的步骤还包括：
将更新后的第一内存库值写入配置串行探测数据。
可选地，方法还包括：
接收内存还原设置指令；
将第一内存库值确定为预设还原内存库值。
可选地，预设还原内存库值为预先设置的用于还原内存库数量的数据；预设还原内存库值的大小根据服务器的架构进行设置。
可选地，方法还包括：
采用预设还原内存库值更新配置串行探测数据。
可选地，方法还包括：
响应于针对内存设置值的输入指令，修改内存设置值。
在本申请的第二个方面，本申请实施例公开了一种内存容量调整装置，应用于服务器，服务器设置至少一路中央处理器，中央处理器与至少一个内存条连接，中央处理器部署有基本输入输出系统，基本输入输出系统存储有内存条对应的内存总容量，装置包括：
获取模块，用于在基本输入输出系统启动过程中，获取内存设置值，内存设置值与内存总容量呈倍数关系；
第一内存库值确定模块，用于依据内存条的配置串行探测数据，生成第一内存库值；
第二内存库值确定模块，用于依据内存设置值、内存总容量和第一内存库值，确定第二内存库值；
更新模块，用于依据第二内存库值更新第一内存库值，以更新配置串行探测数据；
启动模块，用于控制基本输入输出系统基于更新后的配置串行探测数据进行启动。
在本申请的第三个方面，本申请实施例公开了一种电子设备，包括处理器、存储器及存储在存储器上并能够在处理器上运行的计算机程序，计算机程序被处理器执行时实现如上的内存容量调整方法的步骤。
在本申请的第四个方面，本申请实施例公开了一种计算机非易失性可读存储介质，计算机非易失性可读存储介质上存储计算机程序，计算机程序被处理器执行时实现如上的内存容量调整方法的步骤。
本申请实施例包括以下优点：
本申请实施例通过在基本输入输出系统启动过程中，获取内存设置值；依据内存条的配置串行探测数据，生成第一内存库值；依据内存设置值、内存总容量和第一内存库值，确定第二内存库值；依据第二内存库值更新第一内存库值，以更新配置串行探测数据；控制基本输入输出系统基于更新后的配置串行探测数据进行启动；通过在服务器启动过程中，初始化基本输入输出系统时，基于内存设置值调整内存容量的内存库值，以实现自动的服务器整机的内存容量进行动态调整，满足客户的实际业务需求，提高了内存的使用年限及降低了运维成本。
附图说明
为了更清楚地说明本申请实施例，下面将对实施例中所需要使用的附图做简单的介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请的一种内存容量调整方法实施例的步骤流程图；
图2是本申请的另一种内存容量调整方法实施例的步骤流程图；
图3是本申请的一种内存容量调整方法示例的内存物理链接图示意图；
图4是本申请的一种内存容量调整方法示例的步骤流程图；
图5是本申请的一种内存容量调整方法示例的步骤执行时序图；
图6是本申请的一种内存容量调整方法示例的内存示意图；
图7是本申请的另一种内存容量调整方法示例的内存示意图；
图8是本申请的一种内存容量调整装置实施例的结构框图；
图9是本申请实施例提供的一种电子设备的结构框图；
图10是本申请实施例提供的一种存储介质的结构框图。
具体实施例
为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合附图和具体实施方式对本申请作进一步详细的说明。
参照图1，示出了本申请的一种内存容量调整方法实施例的步骤流程图，内存容量调整方法应用于服务器，服务器设置至少一路中央处理器，中央处理器与至少一个内存条连接，中央处理器部署有基本输入输出系统，基本输入输出系统存储有内存条对应的内存总容量，内存调整容量调整方法具体可以包括如下步骤：
步骤101，在基本输入输出系统启动过程中，获取内存设置值；
在基本输入输出系统启动过程中，可以获取到内存设置值，该内存设置值与内存总容量呈倍数关系；如内存设置值为内存总容量的2倍；内存总容量为内存设置值的2倍，即内存设置值为内存总容量的二分之一。
步骤102，依据内存条的配置串行探测数据，生成第一内存库值；
在本申请实施例中，服务器可以去读取内存条的配置串行探测数据，配置串行探测数据为SPD(Serial Presence Detect，配置串行探测器)数据。SPD为内存模块上的一种存储器，用来存储内存模块的参数信息，这些信息在计算机启动时被读取并保存到主板芯片组中，以便系统能够正确地配置内存控制器。
基于读取到的内存条的配置串行探测数据，确定其中的记载的内存库值为第一内存库值。内存库值即为内存中Bank(库)的数量值。
步骤103，依据内存设置值、内存总容量和第一内存库值，确定第二内存库值；
依据内存设置值、内存总容量和第一内存库值确定出需要更改的内存库值，即第二内存库值。其中，第二内存库值即为为满足用户需求的内存库值。
步骤104，依据第二内存库值更新第一内存库值，以更新配置串行探测数据；
依据第二内存库值更新第一内存库值，以第二内存库值作为本次启动初始化中的内存库值，将第二内存库值更新到配置串行探测数据中，以更新配置串行探测数据。
步骤105，控制基本输入输出系统基于更新后的配置串行探测数据进行启动。
然后再控制基本输入输出系统基于更新后的配置串行探测数据进行启动，以使得初始化启动后内存的内容容量可以满足用户需求，且不影响运行效率。
本申请实施例通过在基本输入输出系统启动过程中，获取内存设置值；依据内存条的配置串行探测数据，生成第一内存库值；依据内存设置值、内存总容量和第一内存库值，确定第二内存库值；依据第二内存库值更新第一内存库值，以更新配置串行探测数据；控制基本输入输出系统基于更新后的配置串行探测数据进行启动；通过在服务器启动过程中，初始化基本输入输出系统时，基于内存设置值调整内存容量的内存库值，以实现自动的服务器整机的内存容量进行动态调整，满足客户的实际业务需求，提高了内存的使用年限及降低了运维成本。
参照图2，示出了本申请的另一种内存容量调整方法实施例的步骤流程图，内存调整容量调整方法应用于服务器，服务器设置至少一路中央处理器，中央处理器与至少一个内存条连接，中央处理器部署有基本输入输出系统和内存条，基本输入输出系统存储有 内存条对应的内存总容量。在本申请中，服务器设置至少一路中央处理器，如图3所示，可以设置两路中央处理器(CPU)，每一个中央处理器连接有至少一个内存条，每个中央处理器连接的内存条数量相同。中央处理器部署有基本输入输出系统(Basic Input Output System，BIOS)和内存条。该内存条供服务器进行存储数据。基本输入输出系统存储有内存条对应的内存总容量，以在内存总容量的限定下进行数据的处理。内存调整容量调整方法具体可以包括如下步骤：
步骤201，在基本输入输出系统启动过程中，获取内存设置值。
在本申请实施例中，可以在基本输入输出系统启动过程中，获取用户预先设置的内存设置值。
在本申请的一些可选实施例中，方法还包括：
步骤S1，响应于针对内存设置值的输入指令，修改内存设置值。
当用户需要对预先设置的内存设置值进行实时的调整时，可以向服务器发起针对内存设置值的输入指令。输入指令包括内存设置值的调整值。响应于针对内存设置值的输入指令，修改内存设置值为该调整值。以满足用户的实时调整需求。
步骤202，依据内存条的配置串行探测数据，生成第一内存库值。
由于内存条配置串行探测数据(SPD数据)的结构体是记载有内存库值，可以从内存条的地址中读取内存条的配置串行探测数据，且配置串行探测数据的结构体对于每个内存而言都是一致的，可以从内存条的配置串行探测数据中，读取对应内存库数量标志位的数据，确定为第一内存库值。
具体地，依据内存条的配置串行探测数据，生成第一内存库值的步骤包括：通过双向二线制同步串行总线协议，读取内存条的地址，生成配置串行探测结构体；依据配置串行探测结构体确定配置串行探测数据；将配置串行探测数据中的内存库数量值为第一内存库值。
由于内存条与服务器是基于双向二线制同步串行总线协议(Inter-Integrated Circuit，I2C)连接。可以通过I2C协议，读取内存条的地址，即读取内存条的I2C地址中数据，生成配置串行探测结构体。再依据配置串行探测结构体的各个报文位置的数据，生成配置串行探测数据，将配置串行探测数据中记载的内存库数量值确定为第一内存库值。第一内存库值为当前内存的内存库值。
步骤203，依据内存设置值、内存总容量和第一内存库值，确定第二内存库值。
依据内存设置值和内存总容量，确定内存的增减；再结合第一内存库值，确定增减的幅度，进而确定第二内存库值。即第二内存库值为调整后的内存库值。
在本申请的一些可选实施例中，依据内存设置值、内存总容量和第一内存库值，确定第二内存库值的步骤包括：
子步骤S2031，依据内存设置值和内存总容量确定调整倍数值；
首先可以根据内存设置值和内存总容量之间数学关系，确定调整倍数值，以确定调整的方向。如内存设置值为内存总容量的若干倍，即增加内存库数量；反之，内存设置值为内存总容量的若干分之一，即减少内存库数量。
具体地，述依据内存设置值和内存总容量确定调整倍数值的步骤包括：计算内存设置值和内存总容量的比值，确定比值为调整倍数值。
可以计算内存设置值和内存总容量的比值，将该比值确定为比值为调整倍数值，即比值大于1，即增加内存库数量；反之，比值小于1，即减少内存库数量，还有比值为1时，即内存库数量不变。
子步骤S2032，依据调整倍数值和第一内存库值，确定第二内存库值。
再依据调整倍数值和第一内存库值，确定调整的幅度，确定第二内存库值。
具体地，依据调整倍数值和第一内存库值，确定第二内存库值的步骤包括：判断调整倍数是否为一；响应于调整倍数为一，确定第二内存库值与第一内存库值等同；响应于调整倍数不为一，依据调整倍数值和第一内存库值计算第二内存库值。
在确定第二内存库值时，可以首先判断调整倍数是否为一。当调整倍数为一，即内存库数量不变。可以响应于调整倍数为一，确定第二内存库值与第一内存库值等同，保持内存库数量不变。当调整倍数不为一，即内存库数量需要增减，可以根据调整倍数值和第一内存库值计算第二内存库值。
进一步地，调整倍数小于一时，依据调整倍数值和第一内存库值计算第二内存库值的步骤包括：计算调整倍数值与第一内存库值的乘积值为第二内存库值，第二内存库值小于第一内存库值。
在整倍数小于一时，即是需要减少内存库数量，可以计算调整倍数值与第一内存库值的乘积值为第二内存库值，第二内存库值小于第一内存库值。
进一步地，调整倍数大于一时，依据调整倍数值和第一内存库值计算第二内存库值的步骤包括：计算调整倍数值与第一内存库值的乘积值为第二内存库值，第二内存库值大于第一内存库值。
在整倍数大于一时，即是需要增加内存库数量，可以计算调整倍数值与第一内存库值的乘积值为第二内存库值，第二内存库值大于第一内存库值。
步骤204，依据第二内存库值更新第一内存库值，以更新配置串行探测数据。
依据第二内存库值更新第一内存库值，以使得可以采用第二内存库值来设置内存，并将设置后的第一内存库值，写回配置串行探测数据，以更新配置串行探测数据。
在本申请的一些可选实施例中，依据第二内存库值更新第一内存库值，以更新配置串行探测数据的步骤包括：
步骤2041，采用第二内存库值替换第一内存库值。
可以采用第二内存库值替换第一内存库值在配置串行探测数据中的位置，以更新第一内存库值，从而更新配置串行探测数据。
进一步地，依据第二内存库值更新第一内存库值，以更新配置串行探测数据的步骤还包括：将更新后的第一内存库值写入配置串行探测数据。
在更新第一内存库值后，可以将第一内存库值写入配置串行探测数据中，以更新串行探测数据。
步骤205，控制基本输入输出系统基于更新后的配置串行探测数据进行启动。
得到更新后的配置串行探测数据后，可以控制基本输入输出系统基于更新后的配置串行探测数据进行启动，以在服务器开机初始化时，对内存进行设置。
步骤206，接收内存还原设置指令。
当用户需要对服务器的内存条对应的内存库进行还原时，可以向服务器发送内存还 原设置指令。服务器接收内存还原设置指令。
步骤207，将第一内存库值确定为预设还原内存库值。
可以将配置串行探测数据中当前的第一内存库值设置为预设还原内存库值。预设还原内存库值为预先设置的用于还原内存库数量的数据。预设还原内存库值的大小可以根据服务器的架构进行设置，本申请实施例对此不作限定。
步骤208，采用预设还原内存库值更新配置串行探测数据。
然后可以采用预设还原内存库值写入到配置串行探测数据中，以更新配置串行探测数据，便于服务在启动时，获取新的配置串行探测数据进行内存的设置。
本申请实施例采取服务器启动时，BIOS作为启动管理固件先获取BIOS对内存容量的内存设置值，根据内存设置值数再做进一步的调整，若内存设置值数不是最大容量设置则需要BIOS通过I2C协议读取每个内存I2C地址的SPD数据结构体，将获取的SPD数据结构体中的内存库值进行相应的动态调制，如1对应1个Bank、2对应2个Bank、4对应4个Bank，根据实际需求进行内存库值设置，将设置完毕内存库值的SPD数据回写到每个内存的SPD数据结构中，因同一厂商、同一序列号、同一批次的内存SPD数据结构体参数均一致，可极大降低修改每根内存SPD数据的难度。BIOS通过I2C协议获取每根内存I2C地址的SPD数据结构，对SPD的数据结构中内存的内存库值进行设置调整，以实现无人为动态对服务器内存条的拆卸功能，即可满足对服务器整机的内存容量进行动态调整，满足客户的实际业务需求，提高了内存的使用年限及降低了运维成本，并且不受任何服务器架构限制，可以提高适用范围。
为了使本领域技术人员可以更清楚本申请实施例的实时过程，以下用示例进行说明：
首先，本示例的原始内存链接如图3所示，服务器设置有两路CPU(Central Processing Unit，中央处理器)，每个CPU(CPU1、CPU2)通过I2C协议与各自的内存条进行连接。
对于实施过程可以参照图4，示出了本申请的一种内存调整容量调整方法示例的步骤流程图；参照图5，示出了本申请的一种内存调整容量调整方法示例的步骤执行时序图。
1)BIOS启动过程中，获取BIOS关于内存总容量的预设值参数，预设值分为最大、二分之一和四分之一三个数值；
2)BIOS获取内存总容量预设值后，判断内存总容量预设值是否为最大值设置，若内存总容量预设值为最大值设置则BIOS不对服务器上内存的SPD数据结构做任何调整与改变，按照每个内存的SPD默认数据启动即可；
3)若是BIOS获取的内存总容量预设值为二分之一，则BIOS在内存初始化开始时通过I2C总线读取每个内存SPD地址的数据，将获取的SPD数据的Bank值由4个bank修改为2个Bank值并回写到SPD数据中；继续启动服务器并进入操作系统；修改后的内存可以参照图6。
4)若是BIOS获取的内存总容量预设值为四分之一，则BIOS在内存初始化开始时通过I2C总线读取每个内存SPD地址的数据，将获取的SPD数据的Bank值(内存库值)由4个bank(库)修改为1个Bank值并回写到SPD数据中；继续启动服务器并进入操作系统；修改后的内存可以参照图7。
5)若是客户想将内存容量由修改的值还原到最大值，按照步骤3或者4将内存的内存库值进行修改。
需要说明的是，对于方法实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本申请实施例并不受所描述的动作顺序的限制，因为依据本申请实施例，某些步骤可以采用其他顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例属于优选实施例，所涉及的动作并不一定是本申请实施例所必须的。
参照图8，示出了本申请的一种内存容量调整装置实施例的结构框图，内存容量调整装置应用于服务器，服务器设置至少一路中央处理器，中央处理器与至少一个内存条连接，中央处理器部署有基本输入输出系统，基本输入输出系统存储有内存条对应的内存总容量，内存调整容量调整装置具体可以包括如下模块：
获取模块801，用于在基本输入输出系统启动过程中，获取内存设置值；
第一内存库值确定模块802，用于依据内存条的配置串行探测数据，生成第一内存库值；
第二内存库值确定模块803，用于依据内存设置值、内存总容量和第一内存库值，确定第二内存库值；
更新模块804，用于依据第二内存库值更新第一内存库值，以更新配置串行探测数据；
启动模块805，用于控制基本输入输出系统基于更新后的配置串行探测数据进行启动。
在本申请的一些可选实施例中，第一内存库值确定模块802包括：
读取子模块，用于通过双向二线制同步串行总线协议，读取内存条的地址，生成配置串行探测结构体；
配置串行探测数据子模块，用于依据配置串行探测结构体确定配置串行探测数据；
第一内存库值确定子模块，用于将配置串行探测数据中的内存库数量值为第一内存库值。
在本申请的一些可选实施例中，第二内存库值确定模块803包括：
调整倍数值确定子模块，用于依据内存设置值和内存总容量确定调整倍数值；
第二内存库值确定子模块，用于依据调整倍数值和第一内存库值，确定第二内存库值。
在本申请的一些可选实施例中，调整倍数值确定子模块包括：
第一计算单元，用于计算内存设置值和内存总容量的比值，
调整倍数值确定单元，用于确定比值为调整倍数值。
在本申请的一些可选实施例中，第二内存库值确定子模块包括：
判断单元，用于判断调整倍数是否为一；
第一响应单元，用于响应于调整倍数为一，确定第二内存库值与第一内存库值等同；
第二响应单元，用于响应于调整倍数不为一，依据调整倍数值和第一内存库值计算第二内存库值。
在本申请的一些可选实施例中，调整倍数小于一时，第二响应单元包括：
第二计算子单元，用于计算调整倍数值与第一内存库值的乘积值为第二内存库值，第二内存库值小于第一内存库值。
在本申请的一些可选实施例中，调整倍数大于一时，第二响应单元包括：
第三计算子单元，用于计算调整倍数值与第一内存库值的乘积值为第二内存库值， 第二内存库值大于第一内存库值。
在本申请的一些可选实施例中，更新模块804包括：
替换子模块，用于采用第二内存库值替换第一内存库值。
在本申请的一些选实施例中，更新模块804还包括：
将更新后的第一内存库值写入配置串行探测数据。
在本申请的一些选实施例中，装置还包括：
接收模块，用于接收内存还原设置指令；
还原内存库值确定模块，用于将第一内存库值确定为预设还原内存库值。
在本申请的一些选实施例中，装置还包括：
还原模块，用于采用预设还原内存库值更新配置串行探测数据。
在本申请的一些选实施例中，装置还包括：
修改模块，用于响应于针对内存设置值的输入指令，修改内存设置值。
对于装置实施例而言，由于其与方法实施例基本相似，所以描述的比较简单，相关之处参见方法实施例的部分说明即可。
参照图9，本申请实施例还提供了一种电子设备，包括：
处理器901和存储介质902，存储介质902存储有处理器901可执行的计算机程序，当电子设备运行时，处理器901执行计算机程序，以执行如本申请实施例任一项的内存容量调整方法。内存容量调整方法应用于服务器，服务器设置至少一路中央处理器，中央处理器与至少一个内存条连接，中央处理器部署有基本输入输出系统和内存条，基本输入输出系统存储有内存条对应的内存总容量，方法包括：
在基本输入输出系统启动过程中，获取内存设置值；
依据内存条的配置串行探测数据，生成第一内存库值；
依据内存设置值、内存总容量和第一内存库值，确定第二内存库值；
依据第二内存库值更新第一内存库值，以更新配置串行探测数据；
控制基本输入输出系统基于更新后的配置串行探测数据进行启动。
可选地，依据内存条的配置串行探测数据，生成第一内存库值的步骤包括：
通过双向二线制同步串行总线协议，读取内存条的地址，生成配置串行探测结构体；
依据配置串行探测结构体确定配置串行探测数据；
将配置串行探测数据中的内存库数量值为第一内存库值。
可选地，依据内存设置值、内存总容量和第一内存库值，确定第二内存库值的步骤：
依据内存设置值和内存总容量确定调整倍数值；
依据调整倍数值和第一内存库值，确定第二内存库值。
可选地，依据内存设置值和内存总容量确定调整倍数值的步骤包括：
计算内存设置值和内存总容量的比值，
确定比值为调整倍数值。
可选地，依据调整倍数值和第一内存库值，确定第二内存库值的步骤包括：
判断调整倍数是否为一；
响应于调整倍数为一，确定第二内存库值与第一内存库值等同；
响应于调整倍数不为一，依据调整倍数值和第一内存库值计算第二内存库值。
可选地，调整倍数小于一时，依据调整倍数值和第一内存库值计算第二内存库值的步骤包括：
计算调整倍数值与第一内存库值的乘积值为第二内存库值，第二内存库值小于第一内存库值。
可选地，调整倍数大于一时，依据调整倍数值和第一内存库值计算第二内存库值的步骤包括：
计算调整倍数值与第一内存库值的乘积值为第二内存库值，第二内存库值大于第一内存库值。
可选地，依据第二内存库值更新第一内存库值，以更新配置串行探测数据的步骤包括：
采用第二内存库值替换第一内存库值。
可选地，依据第二内存库值更新第一内存库值，以更新配置串行探测数据的步骤还包括：
将更新后的第一内存库值写入配置串行探测数据。
可选地，方法还包括：
接收内存还原设置指令；
将第一内存库值确定为预设还原内存库值。
可选地，方法还包括：
采用预设还原内存库值更新配置串行探测数据。
可选地，方法还包括：
响应于针对内存设置值的输入指令，修改内存设置值。
其中，存储器可以包括随机存取存储器(Random Access Memory，简称RAM)，也可以包括非易失性存储器(non-volatile memory)，例如至少一个磁盘存储器。可选的，存储器还可以是至少一个位于远离前述处理器的存储装置。
上述的处理器可以是通用处理器，包括中央处理器(Central Processing Unit，简称CPU)、网络处理器(Network Processor，简称NP)等；还可以是数字信号处理器(Digital Signal Processing，简称DSP)、专用集成电路(Application Specific Integrated Circuit，简称ASIC)、现场可编程门阵列(Field－Programmable Gate Array，简称FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。
参照图10，本申请实施例还提供了一种计算机非易失性可读存储介质1001，计算机非易失性可读存储介质1001上存储有计算机程序，计算机程序被处理器运行时执行如本申请实施例任一项的内存容量调整方法。内存容量调整方法应用于服务器，服务器设置至少一路中央处理器，中央处理器与至少一个内存条连接，中央处理器部署有基本输入输出系统，基本输入输出系统存储有内存条对应的内存总容量，方法包括：
在基本输入输出系统启动过程中，获取内存设置值，内存设置值与内存总容量呈倍数关系；
依据内存条的配置串行探测数据，生成第一内存库值；
依据内存设置值、内存总容量和第一内存库值，确定第二内存库值；
依据第二内存库值更新第一内存库值，以更新配置串行探测数据；
控制基本输入输出系统基于更新后的配置串行探测数据进行启动。
可选地，依据内存条的配置串行探测数据，生成第一内存库值的步骤包括：
通过双向二线制同步串行总线协议，读取内存条的地址，生成配置串行探测结构体；
依据配置串行探测结构体确定配置串行探测数据；
将配置串行探测数据中的内存库数量值为第一内存库值。
可选地，依据内存设置值、内存总容量和第一内存库值，确定第二内存库值的步骤：
依据内存设置值和内存总容量确定调整倍数值；
依据调整倍数值和第一内存库值，确定第二内存库值。
可选地，依据内存设置值和内存总容量确定调整倍数值的步骤包括：
计算内存设置值和内存总容量的比值，
确定比值为调整倍数值。
可选地，依据调整倍数值和第一内存库值，确定第二内存库值的步骤包括：
判断调整倍数是否为一；
响应于调整倍数为一，确定第二内存库值与第一内存库值等同；
响应于调整倍数不为一，依据调整倍数值和第一内存库值计算第二内存库值。
可选地，调整倍数小于一时，依据调整倍数值和第一内存库值计算第二内存库值的步骤包括：
计算调整倍数值与第一内存库值的乘积值为第二内存库值，第二内存库值小于第一内存库值。
可选地，调整倍数大于一时，依据调整倍数值和第一内存库值计算第二内存库值的步骤包括：
计算调整倍数值与第一内存库值的乘积值为第二内存库值，第二内存库值大于第一内存库值。
可选地，依据第二内存库值更新第一内存库值，以更新配置串行探测数据的步骤包括：
采用第二内存库值替换第一内存库值。
可选地，依据第二内存库值更新第一内存库值，以更新配置串行探测数据的步骤还包括：
将更新后的第一内存库值写入配置串行探测数据。
可选地，方法还包括：
接收内存还原设置指令；
将第一内存库值确定为预设还原内存库值。
可选地，方法还包括：
采用预设还原内存库值更新配置串行探测数据。
可选地，方法还包括：
响应于针对内存设置值的输入指令，修改内存设置值。
本说明书中的各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。
本领域内的技术人员应明白，本申请实施例的实施例可提供为方法、装置、或计算 机程序产品。因此，本申请实施例可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请实施例可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM((Compact Disc Read-Only Memory只读光盘))、光学存储器等)上实施的计算机程序产品的形式。
本申请实施例是参照根据本申请实施例的方法、终端设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理终端设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理终端设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理终端设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理终端设备上，使得在计算机或其他可编程终端设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程终端设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
尽管已描述了本申请实施例的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例做出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本申请实施例范围的所有变更和修改。
最后，还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者终端设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者终端设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括要素的过程、方法、物品或者终端设备中还存在另外的相同要素。
以上对本申请所提供的一种内存容量调整方法、装置、电子设备和存储介质，进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种内存容量调整方法，其特征在于，应用于服务器，所述服务器设置至少一路中央处理器，所述中央处理器与至少一个内存条连接，所述中央处理器部署有基本输入输出系统，所述基本输入输出系统存储有所述内存条对应的内存总容量，所述方法包括：
    在所述基本输入输出系统启动过程中，获取内存设置值；
    依据所述内存条的配置串行探测数据，生成第一内存库值；
    依据所述内存设置值、所述内存总容量和所述第一内存库值，确定第二内存库值；
    依据所述第二内存库值更新所述第一内存库值，以更新所述配置串行探测数据；
    控制所述基本输入输出系统基于更新后的配置串行探测数据进行启动。
  2. 根据权利要求1所述的方法，其特征在于，所述依据所述内存条的配置串行探测数据，生成第一内存库值的步骤包括：
    通过双向二线制同步串行总线协议，读取所述内存条的地址，生成配置串行探测结构体；
    依据所述配置串行探测结构体确定配置串行探测数据；
    将所述配置串行探测数据中的内存库数量值为所述第一内存库值。
  3. 根据权利要求2所述的方法，其特征在于，所述依据所述配置串行探测结构体确定配置串行探测数据，包括：
    依据所述配置串行探测结构体的各个报文位置的数据，生成所述配置串行探测数据。
  4. 根据权利要求1所述的方法，其特征在于，所述依据所述内存设置值、所述内存总容量和所述第一内存库值，确定第二内存库值的步骤包括：
    依据所述内存设置值和所述内存总容量确定调整倍数值；
    依据所述调整倍数值和所述第一内存库值，确定所述第二内存库值。
  5. 根据权利要求4所述的方法，其特征在于，所述第二内存库值为满足用户需求的内存库值。
  6. 根据权利要求4所述的方法，其特征在于，所述依据所述内存设置值和所述内存总容量确定调整倍数值的步骤包括：
    计算所述内存设置值和所述内存总容量的比值，
    确定所述比值为所述调整倍数值。
  7. 根据权利要求4所述的方法，其特征在于，所述依据所述调整倍数值和所述第一内存库值，确定所述第二内存库值的步骤包括：
    判断所述调整倍数是否为一；
    响应于所述调整倍数为一，确定所述第二内存库值与所述第一内存库值等同；
    响应于所述调整倍数不为一，依据所述调整倍数值和所述第一内存库值计算所述第二内存库值。
  8. 根据权利要求4所述的方法，其特征在于，依据所述调整倍数值，确定调整方向，包括：
    所述调整倍数大于一时，增加内存库数量；
    所述调整倍数效于一时，减少内存库数量。
  9. 根据权利要求7所述的方法，其特征在于，所述调整倍数小于一时，所述依据所述调整倍数值和所述第一内存库值计算所述第二内存库值的步骤包括：
    计算所述调整倍数值与所述第一内存库值的乘积值为所述第二内存库值，所述第二内存库值小于所述第一内存库值。
  10. 根据权利要求7所述的方法，其特征在于，所述调整倍数大于一时，所述依据所述调整倍数值和所述第一内存库值计算所述第二内存库值的步骤包括：
    计算所述调整倍数值与所述第一内存库值的乘积值为所述第二内存库值，所述第二内存库值大于所述第一内存库值。
  11. 根据权利要求1所述的方法，其特征在于，所述依据所述第二内存库值更新所述第一内存库值，以更新所述配置串行探测数据的步骤包括：
    采用所述第二内存库值替换所述第一内存库值。
  12. 根据权利要求1所述的方法，其特征在于，所述控制所述基本输入输出系统基于更新后的配置串行探测数据进行启动，包括：
    在所述服务器开机初始化时，对内存进行设置。
  13. 根据权利要求11所述的方法，其特征在于，所述依据所述第二内存库值更新所述第一内存库值，以更新所述配置串行探测数据的步骤还包括：
    将更新后的第一内存库值写入所述配置串行探测数据。
  14. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    接收内存还原设置指令；
    将所述第一内存库值确定为预设还原内存库值。
  15. 根据权利要求14所述的方法，其特征在于，所述预设还原内存库值为预先设置的用于还原内存库数量的数据；所述预设还原内存库值的大小根据所述服务器的架构进行设置。
  16. 根据权利要求14所述的方法，其特征在于，所述方法还包括：
    采用所述预设还原内存库值更新所述配置串行探测数据。
  17. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    响应于针对所述内存设置值的输入指令，修改所述内存设置值。
  18. 一种内存容量调整装置，其特征在于，应用于服务器，所述服务器设置至少一路中央处理器，所述中央处理器与至少一个内存条连接，所述中央处理器部署有基本输入输出系统，所述基本输入输出系统存储有所述内存条对应的内存总容量，所述装置包括：
    获取模块，用于在所述基本输入输出系统启动过程中，获取内存设置值，所述内存设置值与所述内存总容量呈倍数关系；
    第一内存库值确定模块，用于依据所述内存条的配置串行探测数据，生成第一内存库值；
    第二内存库值确定模块，用于依据所述内存设置值、所述内存总容量和所述第一内存库值，确定第二内存库值；
    更新模块，用于依据所述第二内存库值更新所述第一内存库值，以更新所述配置串行探测数据；
    启动模块，用于控制所述基本输入输出系统基于更新后的配置串行探测数据进行启动。
  19. 一种电子设备，其特征在于，包括处理器、存储器及存储在所述存储器上并能够在所述处理器上运行的计算机程序，所述计算机程序被所述处理器执行时实现如权利要求1至17中任一项所述的内存容量调整方法的步骤。
  20. 一种计算机非易失性可读存储介质，其特征在于，所述计算机非易失性可读存储介质上存储计算机程序，所述计算机程序被处理器执行时实现如权利要求1至17中任一项所述的内存容量调整方法的步骤。
PCT/CN2024/100746 2023-12-01 2024-06-21 一种内存容量调整方法、装置、电子设备和存储介质 Pending WO2025112486A1 (zh)

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