WO2025065254A1 - 滤波自混频器 - Google Patents

滤波自混频器 Download PDF

Info

Publication number
WO2025065254A1
WO2025065254A1 PCT/CN2023/121613 CN2023121613W WO2025065254A1 WO 2025065254 A1 WO2025065254 A1 WO 2025065254A1 CN 2023121613 W CN2023121613 W CN 2023121613W WO 2025065254 A1 WO2025065254 A1 WO 2025065254A1
Authority
WO
WIPO (PCT)
Prior art keywords
cmos tube
mixer
resonator
bias voltage
input signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2023/121613
Other languages
English (en)
French (fr)
Inventor
左成杰
刘京松
林福宏
邱茂洋
袁颖
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Science and Technology of China USTC
Original Assignee
University of Science and Technology of China USTC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Science and Technology of China USTC filed Critical University of Science and Technology of China USTC
Priority to PCT/CN2023/121613 priority Critical patent/WO2025065254A1/zh
Publication of WO2025065254A1 publication Critical patent/WO2025065254A1/zh
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements

Definitions

  • the present disclosure relates to the technical field of radio frequency wireless communication, and in particular to a filtering self-mixer for waking up a receiver.
  • the wake-up receiver can monitor the channel with extremely low power consumption, and wake up the main receiver when the wake-up receiver receives the wake-up signal, thereby reducing the standby power consumption of the wireless communication system.
  • wake-up receivers require lower power consumption, higher sensitivity, and higher anti-interference capabilities.
  • low-power wake-up receivers In order to eliminate the high power consumption (>20 microwatts) introduced by the oscillator, low-power wake-up receivers often use a self-mixing architecture to down-convert the RF signal, thereby reducing the system power consumption to below microwatts.
  • the existing self-mixer will down-convert all input signals in the previous passband to the baseband, and the self-mixing output spectrum of the interference and signal will be aliased in the baseband and difficult to distinguish. Therefore, it is difficult for traditional low-power wake-up receivers to suppress interference signals in the passband of the previous circuit, and its anti-interference ability depends on the passband bandwidth and out-of-band suppression of the previous circuit.
  • the RF passband bandwidth of the wake-up receiver mainly depends on the matching or filtering network.
  • the matching network based on off-chip high-Q inductors has low loss, low power consumption and high sensitivity. Its relative fractional bandwidth is large (about 10%), so its anti-interference ability is poor.
  • a filter based on a micro-electromechanical resonator can be inserted into the inductor matching network, or a matching network with an off-chip RF micro-electromechanical resonator as the core can be used. Thanks to the high Q value of the micro-electromechanical resonator (>1000), the relative fractional bandwidth of the system can be greatly reduced (about 0.5%).
  • the anti-interference capability of the traditional low-power wake-up receiver depends on the bandwidth and out-of-band suppression of the previous filter matching network.
  • the current filter matching network bandwidth and out-of-band suppression capability are insufficient, and the existing self-mixer structure cannot provide filtering, thus limiting the anti-interference performance of the wake-up receiver.
  • the present disclosure provides a filter self-mixer, which is configured to improve the anti-interference performance of a wake-up receiver.
  • the filter self-mixer includes: an input signal terminal, an energy detection circuit unit, a bias voltage unit, a coupling branch unit, and a micro-electromechanical resonator branch. Among them:
  • the input signal terminal is configured to receive a wake-up signal and an interference signal as input signals;
  • the energy detection circuit unit includes at least one CMOS tube, which is configured to mix the input signal through a secondary effect and output a baseband signal;
  • the bias voltage unit is configured to provide a gate voltage of the CMOS tube to adjust the channel impedance of the CMOS tube;
  • the coupling branch unit is arranged at Between the input signal terminal and the energy detection circuit unit, the input signal is coupled to the drain or source of the CMOS tube in the energy detection circuit unit;
  • the micro-electromechanical resonator branch is arranged between the input signal terminal and the bias voltage unit, and can output different gate signals at different frequencies to adjust the secondary effect, thereby filtering out interference signals in the input signal.
  • the energy detection circuit is a triode type energy detection circuit
  • the CMOS tube in the energy detection circuit unit is selected from an N-type CMOS tube and a P-type CMOS tube.
  • the bias voltage unit includes at least one bias voltage branch, and each bias voltage branch includes a bias voltage source and a bias resistor connected in sequence.
  • the coupling branch unit includes at least one coupling branch, each coupling branch includes a coupling capacitor connected to the input signal terminal, and the coupling capacitor is connected to the drain or source of the corresponding CMOS tube.
  • the MEMS resonator branch includes a MEMS resonator and a DC blocking capacitor.
  • One end of the MEMS resonator is connected to the input signal end, and the other end is connected to the gate of the CMOS tube; the DC blocking capacitor is connected to the MEMS resonator and is configured to isolate the DC level of the CMOS tube.
  • the relative fractional bandwidth of the filter self-mixer is less than 0.5%, and the out-of-band suppression capability is greater than 40Db; and the operating frequency of the filter self-mixer is the anti-resonance frequency of the micro-electromechanical resonator.
  • the micro-electromechanical resonator is equivalent to an equivalent capacitor.
  • the capacitance of the equivalent capacitor is adjusted by adjusting the geometric structure of the resonator to adjust the size of the gate signal coupled to the gate of the CMOS tube, so that the gate and drain or the secondary effects of the drain of the transistor cancel each other out, thereby not outputting a baseband signal.
  • the type of the MEMS resonator is selected from a thin film bulk acoustic wave resonator, a lateral vibration piezoelectric resonator, a bulk acoustic wave resonator, a surface acoustic wave resonator, a Lamb wave resonator, a shear piezoelectric resonator, and a quartz crystal resonator.
  • the CMOS tube arrangement form in the energy detection circuit unit includes a single-stage form, a multi-stage cascade form or a multi-stage cascade form of a pseudo-differential form.
  • the bias voltage source provides a gate DC bias voltage through a gate bias circuit, or provides a gate DC bias voltage through a drain or source of a transistor.
  • the filter self-mixer disclosed in the present invention utilizes the different impedance characteristics of the micro-electromechanical resonator at different frequencies, realizes narrowband filtering on the self-mixer, and improves the anti-interference ability of the wake-up receiver; by offsetting the secondary effects of the transistor gate and drain, extremely high out-of-band suppression is achieved, and the suppression of out-of-band interference by the wake-up receiver is improved; the filter self-mixer has the characteristics of narrowband and high out-of-band suppression, so that the anti-interference performance of the wake-up receiver based on the filter self-mixer no longer depends on the matching network of the previous stage; therefore, the matching network can adopt a topological structure and circuit parameters with higher bandwidth but lower loss, so as to improve the sensitivity of the wake-up receiver without reducing the anti-interference ability; the filter self-mixer operates at the anti-resonance frequency of the micro-electromechanical resonator.
  • the filtering method disclosed in the present invention has a higher Q value, a narrower passband, and a higher anti-interference ability. better.
  • FIG1 is a circuit diagram of a filtering self-mixer according to an embodiment of the present disclosure.
  • FIG. 2 is a circuit diagram of a conventional self-mixer.
  • C1, C2, CC coupling capacitors
  • RB1 , RB2 bias resistors
  • V GN, V GP bias voltage source
  • V ed ,out baseband output signal.
  • FIG1 is a circuit diagram of a filtering self-mixer according to an embodiment of the present disclosure.
  • the present invention provides a filter self-mixer, wherein the CMOS tube included in the filter self-mixer is configured to provide a secondary effect to self-mix the input signal; the micro-electromechanical resonator changes the impedance at different frequencies, so that the filter self-mixer has narrow-band and high out-of-band suppression filtering characteristics; the coupling capacitor couples the input signal to the corresponding CMOS tube; the bias resistor biases the gate voltage of the transistor; and the DC isolation capacitor is configured to isolate the DC level of different transistors.
  • the filter self-mixer disclosed in the present invention has a lower passband bandwidth ( ⁇ 0.5%) and a very high out-of-band suppression capability (>40dB). Its operating frequency is the anti-resonance frequency of the filter.
  • the inventors found that the existing self-mixer structure (a typical four-stage self-mixer structure as shown in FIG2 ) inputs the AC input signal to the drain of the CMOS tube of the energy detection circuit unit through the coupling capacitor CC , and uses the secondary effect of the weak inversion region transistor to mix, and generates a corresponding baseband output signal ( Ved , out) at the output end, thereby self-mixing the input signal to the baseband.
  • the gate end of the transistor is connected to an appropriate gate voltage ( VGN , VGP shown in FIG2 ) to adjust the channel resistance of the transistor so that it can match the previous stage circuit.
  • the impedance of the coupling capacitor The input resistance is much smaller than the channel resistance of the transistor, so the input resistance and the drain of the transistor are equivalent to an AC short circuit. Therefore, any signal in the passband of the previous circuit will be mixed by the CMOS tube and output the baseband signal. Therefore, the existing self-mixer does not have a filtering function. In addition, since the out-of-band suppression of the filter matching network of the micro-electromechanical resonator is general, the wake-up receiver based on the existing self-mixer cannot effectively suppress the high-power out-of-band interference signal.
  • the present disclosure provides a filtered self-mixer having both relatively low passband bandwidth ( ⁇ 0.5%) and extremely high out-of-band rejection capability (>40 dB).
  • a filter self-mixer comprises: an input signal terminal IN, an energy detection circuit unit 10, a bias voltage unit, a coupling branch unit, and a micro-electromechanical resonator branch.
  • the input signal terminal IN is configured to receive a wake-up signal and an interference signal as input signals;
  • the energy detection circuit unit 10 comprises at least one CMOS tube, preferably 30 to 50 CMOS tubes, and FIG1 shows four CMOS tubes, which are respectively N-type CMOS tube 11, P-type CMOS tube 12, N-type CMOS tube 13, and P-type CMOS tube 14 four CMOS tubes connected in sequence.
  • the energy detection circuit unit 10 is configured to mix the input signal through the secondary effect of the CMOS tube and output the baseband signal;
  • the bias voltage unit is configured to provide the gate voltage of the CMOS tube to adjust the channel impedance of the CMOS tube;
  • the coupling branch unit is arranged between the input signal terminal and the energy detection circuit unit, and couples the input signal to the drain or source of the CMOS tube in the energy detection circuit unit, as shown in FIG1 , and couples the input signal to the drain of the four CMOS tubes through the coupling capacitor C1 and the coupling capacitor C2 respectively;
  • the micro-electromechanical resonator branch is arranged between the input signal terminal IN and the bias voltage unit and the energy detection circuit unit 10, and can output different gate signals at different frequencies to adjust the secondary effect, so as to filter out the interference signal in the input signal.
  • a coupling capacitor CC is also connected between the signal output terminal OUT and the source of the N-type CMOS tube 11 and is grounded, and the sources of the N-type CMOS tube 11 and the P-type CMOS tube 12 are connected to the coupling capacitor CC and are grounded.
  • the source of the P-type CMOS tube 14 is connected to the common mode level VC.
  • the energy detection circuit is a triode type energy detection circuit
  • the CMOS tube in the energy detection circuit unit is selected from an N-type CMOS tube and a P-type CMOS tube
  • the CMOS tube in the energy detection circuit unit is arranged in a single-stage form, a multi-stage cascade form, or a multi-stage cascade form of a pseudo-differential form.
  • the N-type CMOS tube and the P-type CMOS tube exist at the same time, the N-type CMOS tube and the P-type CMOS tube are alternately connected, such as N-P-N-P or P-N-P-N and other connection forms.
  • the bias voltage unit includes at least one bias voltage branch, and each bias voltage branch includes a bias voltage source and a bias resistor connected in sequence.
  • the bias voltage unit includes two bias voltage branches, namely, a bias voltage source V GN for providing gate voltage to two N-type CMOS transistors 11 and 13 and a bias resistor RB1 connected to the bias voltage source V GN; and a bias voltage source V GN for providing gate voltage to two P-type CMOS transistors 12 and 14.
  • a bias voltage source V GP and a bias resistor RB2 connected to the bias voltage source V GP .
  • the coupling branch unit includes at least one coupling branch, each coupling branch includes a coupling capacitor connected to the input signal terminal, and the coupling capacitor is connected to the drain or source of the corresponding CMOS tube.
  • the coupling branch unit includes two coupling branches, one end of which is connected to the input signal terminal IN, and the other end is connected to the drain of the N-type CMOS tube 11 and the P-type CMOS tube 12 through the coupling capacitor C1; the other coupling branch has one end connected to the input signal terminal IN, and the other end is connected to the drain of the N-type CMOS tube 13 and the P-type CMOS tube 14 through the coupling capacitor C2.
  • the micro-electromechanical resonator branch includes a micro-electromechanical resonator 21 and a DC blocking capacitor 22.
  • One end of the micro-electromechanical resonator 21 is connected to the input signal terminal IN, and the other end is connected to the gate of the CMOS tube.
  • the other end of the micro-electromechanical resonator 21 is connected to the gate of the N-type CMOS tube 11 and the N-type CMOS tube 13; one end of the DC blocking capacitor 22 is connected to the micro-electromechanical resonator 21, and the other end is connected to the gate of the CMOS tube, and is configured to isolate the DC level of the CMOS tube.
  • the other end of the DC blocking capacitor 22 is connected to the gate of the P-type CMOS tube 12 and the P-type CMOS tube 14.
  • the relative fractional bandwidth of the filter self-mixer is less than 0.5%, and the out-of-band suppression capability is greater than 40Db;
  • the operating frequency of the filter self-mixer is the anti-resonance frequency of the micro-electromechanical resonator.
  • the micro-electromechanical resonator 21 when the frequency of the interference signal in the input signal is far away from the anti-resonance frequency of the micro-electromechanical resonator 21, the micro-electromechanical resonator 21 is equivalent to an equivalent capacitor.
  • the capacitance of the equivalent capacitor is adjusted by adjusting the geometric structure of the resonator to adjust the size of the gate signal coupled to the gate of the CMOS tube, so that the gate and drain or the secondary effects of the drain of the transistor cancel each other out, thereby not outputting a baseband signal.
  • the type of the MEMS resonator 21 is selected from a thin film bulk acoustic wave resonator, a lateral vibration piezoelectric resonator, a bulk acoustic wave resonator, a surface acoustic wave resonator, a Lamb wave resonator, a shear piezoelectric resonator, and a quartz crystal resonator.
  • the bias voltage source (V GN , V GP ) may provide a gate DC bias voltage through a gate bias circuit, or provide a gate DC bias voltage through a drain or source of a transistor.
  • the number of stages of the filter self-mixer is 4 (i.e., the number of cascaded CMOS tubes is 4). In actual use, other numbers of stages may be used, preferably 30 or 40 stages, and a pseudo-differential cascade mode may also be used).
  • a micro-electromechanical resonator 21 is introduced between the gate and drain of the CMOS tube, and the channel resistance of the transistor is adjusted and isolated by a bias resistor and a DC isolation capacitor.
  • the RF micro-electromechanical resonator 21 exhibits a high-impedance characteristic near the anti-resonance frequency, and the filter self-mixer is equivalent to a traditional self-mixer.
  • the impedance of the micro-electromechanical resonator decreases, which reduces the input impedance of the self-mixer, destroys the matching condition with the previous stage, and reduces the input signal size of the self-mixer. Therefore, for input signals of the same size, the output signal generated by the input at the anti-resonance frequency is greater than that of other frequencies, and the self-mixer achieves a filtering effect. Since the Q value of the micro-electromechanical resonator at the anti-resonance frequency is high, a lower passband bandwidth can be obtained.
  • the resonator is equivalent to a capacitor, and this equivalent capacitance can be adjusted by adjusting the geometric structure of the resonator.
  • the signal coupled to the gate of the CMOS tube can be adjusted, so that the secondary effects of the gate and drain of the transistor cancel each other out and no baseband output signal is generated. Therefore, the input signal far away from the anti-resonance frequency hardly generates an output signal.
  • the above-mentioned filter self-mixer has a low passband bandwidth ( ⁇ 0.5%) and a very high out-of-band suppression capability (>40dB). Its operating frequency is the anti-resonance frequency of the filter.
  • the present disclosure provides a filtering self-mixer, which introduces a micro-electromechanical resonator into the self-mixer circuit, down-converts the input signal, and has excellent filtering performance (bandwidth ⁇ 0.5%, out-of-band suppression > 50dB), thereby improving the anti-interference performance of the wake-up receiver.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Networks Using Active Elements (AREA)

Abstract

本公开提供一种滤波自混频器，包括：输入信号端，能量探测电路单元，偏置电压单元，耦合支路单元，微机电谐振器支路。输入信号端被配置用于接收唤醒信号及干扰信号作为输入信号；能量探测电路单元包括至少一个CMOS管，被配置用于通过二次效应对输入信号进行混频并输出基带信号；偏置电压单元被配置用于提供CMOS管的栅压以调整CMOS管的沟道阻抗；耦合支路单元设置于所述输入信号端和能量探测电路单元之间，将所述输入信号耦合至能量探测电路单元中的CMOS管的漏极或源极；微机电谐振器支路设置于所述输入信号端和偏置电压单元之间，能够在不同的频率下输出不同的栅极信号以调整二次效应，实现对输入信号中干扰信号的滤除。

Description

滤波自混频器 技术领域
本公开涉及射频无线通信技术领域，具体涉及一种用于唤醒接收机的滤波自混频器。
背景技术
唤醒接收机能够以极低的功耗监听信道，当唤醒接收机接收到唤醒信号时唤醒主接收机，从而可以降低无线通信系统的待机功耗。
随着无线通信技术的发展，唤醒接收机需求更低的功耗，更高的灵敏度以及更高的抗干扰能力。为了消除振荡器引入的高功耗(>20微瓦)，低功耗唤醒接收机常采用自混频架构来对射频信号下变频，从而使系统功耗降至微瓦以下。而现有的自混频器会将前级通带内的所有输入信号下变频至基带，且干扰及信号的自混频输出频谱会在基带发生混叠且难以区分。因此传统的低功耗唤醒接收机难以抑制前级电路通带内的干扰信号，其抗干扰能力依赖于前级电路的通带带宽及带外抑制。
唤醒接收机的射频通带带宽主要取决于匹配或滤波网络。基于片外高Q值电感的匹配网络损耗较低，具备较低的功耗以及较高的灵敏度，其相对分数带宽大(10％左右)，因此抗干扰能力差。为降低系统的带宽，可在电感匹配网络中插入基于微机电谐振器的滤波器或采用以片外射频微机电谐振器为核心的匹配网络。得益于微机电谐振器的高Q值(>1000)，可大幅降低系统的相对分数带宽较(约为0.5％)。但其带外抑制(约为20dB)不足以抑制较大的带外干扰信号，同时受限于MEMS谐振器的高损耗，其功耗和灵敏度都差于电感匹配网络。
综上所述，传统的低功耗唤醒接收机抗干扰能力依赖于前级的滤波匹配网络的带宽及带外抑制，而当前的滤波匹配网络带宽及带外抑制能力不足，而现有的自混频器结构又无法提供滤波，因此限制了唤醒接收机的抗干扰性能。
发明内容
本公开提供了一种滤波自混频器，被配置用于提升唤醒接收机的抗干扰性能，滤波自混频器包括：输入信号端，能量探测电路单元，偏置电压单元，耦合支路单元，微机电谐振器支路。其中：
输入信号端被配置用于接收唤醒信号及干扰信号作为输入信号；能量探测电路单元包括至少一个CMOS管，被配置用于通过二次效应对输入信号进行混频并输出基带信号；偏置电压单元被配置用于提供CMOS管的栅压以调整CMOS管的沟道阻抗；耦合支路单元设置于 输入信号端和能量探测电路单元之间，将输入信号耦合至能量探测电路单元中的CMOS管的漏极或源极；微机电谐振器支路设置于输入信号端和偏置电压单元之间，能够在不同的频率下输出不同的栅极信号以调整二次效应，实现对输入信号中干扰信号的滤除。
可选地，能量探测电路为三极管型能量探测电路，能量探测电路单元中的CMOS管选自N型CMOS管和P型CMOS管。
可选地，偏置电压单元包括至少一条偏置电压支路，每条偏置电压支路包括依次相连的偏置电压源和偏置电阻。
可选地，耦合支路单元包括至少一条耦合支路，每条耦合支路包括与输入信号端相连的耦合电容，耦合电容连接至对应的CMOS管的漏极或源极。
可选地，微机电谐振器支路包括微机电谐振器，隔直电容。微机电谐振器的一端连接至输入信号端，另一端连接至CMOS管的栅极；隔直电容与微机电谐振器相连，被配置用于隔离CMOS管的直流电平。
可选地，滤波自混频器相对分数带宽<0.5％，带外抑制能力>40Db；滤波自混频器的工作频率为微机电谐振器的反谐振频率。
可选地，当输入信号中的干扰信号频率远离反谐振频率时，微机电谐振器相当于一个等效电容，通过调整谐振器的几何结构调整等效电容的容值，以调整耦合到CMOS管栅极的栅极信号的大小，使晶体管的栅极与漏极或漏极的二次效应相互抵消，从而不输出基带信号。
可选地，微机电谐振器的类型选自薄膜体声波谐振器，横向振动压电谐振器，体声波谐振器，声表面波谐振器，兰姆波谐振器，剪切压电谐振器，石英晶体谐振器。
可选地，能量探测电路单元中的CMOS管设置形式包括单级形式，多级级联形式或伪差分形式的多级级联形式。
可选地，偏置电压源通过栅压偏置电路提供栅极直流偏置电压，或通过晶体管的漏极或源极来提供栅极直流偏置电压。
本公开滤波自混频器利用微机电谐振器在不同频率呈现不同的阻抗特性，在自混频器上实现了窄带滤波，提升了唤醒接收机的抗干扰能力；用晶体管栅极与漏极二次效应相抵消的方式，实现了极高的带外抑制，提升了唤醒接收机对带外干扰的抑制；滤波自混频器具有窄带、高带外抑制的特性，使得基于滤波自混频器的唤醒接收机的抗干扰性能不再依赖于前级的匹配网络；因此匹配网络可采用较高带宽但损耗更低的拓扑结构以及电路参数，在不降低抗干扰能力的情况下，提升唤醒接收机的灵敏度；滤波自混频器工作在微机电谐振器的反谐振频率，由于射频微机电谐振器的反谐振频率Q值高于谐振频率Q值，因此相较于工作在微机电谐振器的谐振频率处的滤波方式，本公开的滤波方式Q值更高，通带更窄，抗干扰能力 更好。
附图说明
图1为本公开实施例的滤波自混频器的电路示意图。
图2为现有的自混频器的电路示意图。
附图标记：
10：能量探测电路单元；
11、13：N型CMOS管；
12、14：P型CMOS管；
21：微机电谐振器；
22：隔直电容；
C1、C2、CC：耦合电容；
RB1、RB2：偏置电阻；
VGN、VGP：偏置电压源；
VC：共模电平；
Ved,out：基带输出信号。
具体实施方式
下面结合附图对本公开的实施方式作进一步说明。
图1为本公开实施例的滤波自混频器的电路示意图。
本公开提供了一种滤波自混频器，该滤波自混频器中包括的CMOS管被配置用于提供二次效应，将输入信号自混频；微机电谐振器通过不同频率下阻抗的变化，使得滤波自混频器具有窄带、高带外抑制的滤波特性；耦合电容将输入信号耦合至对应的CMOS管上；偏置电阻偏置晶体管的栅压；隔直电容被配置用于隔离不同晶体管的直流电平。使得本公开的滤波自混频器具有较低的通带带宽(<0.5％)，同时具备极高的带外抑制能力(>40dB)。其工作频率为滤波器的反谐振频率。
在实现本公开的过程中发明人发现，现有的自混频器结构(如图2所示的一种典型的四级自混频器结构)通过耦合电容CC将交流输入信号输入到能量探测电路单元CMOS管的漏极，利用弱反型区晶体管的二次效应混频，在输出端产生相应的基带输出信号(Ved,out)，从而将输入信号自混频至基带。晶体管的栅端接入一个适当的栅压(图2中所示的VGN、VGP)，来调整晶体管的沟道电阻使其可与前级电路相匹配。在前级电路的通带内，耦合电容的阻抗 都远小于晶体管的沟道电阻，因此输入电阻与晶体管的漏极之间等效交流短路。所以在前级电路通带内的任何信号都会被CMOS管混频并输出基带信号。因此已有的自混频器不具备滤波功能。此外，由于微机电谐振器的滤波匹配网络的带外抑制一般，基于现有自混频器的唤醒接收机也不能有效抑制较大功率的带外干扰信号。
因此，本公开提供了一种同时具有较低的通带带宽(<0.5％)，和极高的带外抑制能力(>40dB)滤波自混频器。
为使本公开的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本公开进一步详细说明。
在本公开实施例中，提供一种滤波自混频器，如图1所示，滤波自混频器，包括：输入信号端IN，能量探测电路单元10，偏置电压单元，耦合支路单元，微机电谐振器支路。输入信号端IN被配置用于接收唤醒信号及干扰信号作为输入信号；能量探测电路单元10包括至少一个CMOS管，优选为30至50个CMOS管，图1中为四个CMOS管，分别为依次相连的N型CMOS管11、P型CMOS管12、N型CMOS管13、以及P型CMOS管14四个CMOS管。能量探测电路单元10被配置用于通过CMOS管的二次效应对输入信号进行混频并输出基带信号；偏置电压单元被配置用于提供CMOS管的栅压以调整CMOS管的沟道阻抗；耦合支路单元设置于输入信号端和能量探测电路单元之间，将输入信号耦合至能量探测电路单元中的CMOS管的漏极或源极，如图1中所示，通过耦合电容C1和耦合电容C2分别将输入信号耦合至四个CMOS管的漏极；微机电谐振器支路设置于输入信号端IN和偏置电压单元、能量探测电路单元10之间，能够在不同的频率下输出不同的栅极信号以调整二次效应，实现对输入信号中干扰信号的滤除。在信号输出端OUT和N型CMOS管11的源极之间还连接有耦合电容CC并接地，N型CMOS管11和P型CMOS管12的源极连接有耦合电容CC并接地。P型CMOS管14的源极连接有共模电平VC。
根据本公开实施例，能量探测电路为三极管型能量探测电路，能量探测电路单元中的CMOS管选自N型CMOS管和P型CMOS管；能量探测电路单元中的CMOS管设置形式包括单级形式，多级级联形式或伪差分形式的多级级联形式。当同时存在N型CMOS管和P型CMOS管时，N型CMOS管和P型CMOS管交替连接，例如N-P-N-P或P-N-P-N等连接形式。
根据本公开实施例，偏置电压单元包括至少一条偏置电压支路，每条偏置电压支路包括依次相连的偏置电压源和偏置电阻。如图1所示，偏置电压单元包括两条偏置电压支路，分别为向两个N型CMOS管11、N型CMOS管13提供栅压的偏置电压源VGN及与偏置电压源VGN相连的偏置电阻RB1；以及向两个P型CMOS管12、P型CMOS管14提供栅压的偏 置电压源VGP及与偏置电压源VGP相连的偏置电阻RB2。
根据本公开实施例，耦合支路单元包括至少一条耦合支路，每条耦合支路包括与输入信号端相连的耦合电容，耦合电容连接至对应的CMOS管的漏极或源极。如图1所示，耦合支路单元包括两条耦合支路，其中一条耦合支路一端连接至输入信号端IN，另一端通过耦合电容C1连接至N型CMOS管11和P型CMOS管12的漏极；另一条耦合支路一端连接至输入信号端IN，另一端通过耦合电容C2连接至N型CMOS管13和P型CMOS管14的漏极。
根据本公开实施例，微机电谐振器支路包括微机电谐振器21，隔直电容22。微机电谐振器21的一端连接至输入信号端IN，另一端连接至CMOS管的栅极，如图1中所示，微机电谐振器21的另一端连接至N型CMOS管11、N型CMOS管13的栅极；隔直电容22一端与微机电谐振器21相连，两一端连接至CMOS管的栅极，被配置用于隔离CMOS管的直流电平。如图1中所示，隔直电容22的另一端连接至P型CMOS管12，P型CMOS管14的栅极。
根据本公开实施例，滤波自混频器相对分数带宽<0.5％，带外抑制能力>40Db；滤波自混频器的工作频率为微机电谐振器的反谐振频率。
根据本公开实施例，当输入信号中的干扰信号频率远离，微机电谐振器21的反谐振频率时，微机电谐振器21相当于一个等效电容，通过调整谐振器的几何结构调整等效电容的容值，以调整耦合到CMOS管栅极的栅极信号的大小，使晶体管的栅极与漏极或漏极的二次效应相互抵消，从而不输出基带信号。
根据本公开实施例，微机电谐振器21的类型选自薄膜体声波谐振器，横向振动压电谐振器，体声波谐振器，声表面波谐振器，兰姆波谐振器，剪切压电谐振器，石英晶体谐振器。
根据本公开实施例，偏置电压源(VGN、VGP)可以通过栅压偏置电路提供栅极直流偏置电压，或通过晶体管的漏极或源极来提供栅极直流偏置电压。
根据本公开实施例，如图1所示，滤波自混频器的级数为4级(即级联的CMOS管数量为4)，实际使用中可采用其他级数，优选为30级或40级，也可采用伪差分的级联方式)。在CMOS管的栅极和漏极之间引入了一个微机电谐振器21，并通过偏置电阻以及隔直电容来调整晶体管的沟道电阻并隔直。射频微机电谐振器21在反谐振频率附近呈现高阻特性，滤波自混频器等效于传统的自混频器。在反谐振频率以外，微机电谐振器的阻抗减小，这使得自混频器的输入阻抗降低，破坏了与前级的匹配条件，减小了自混频器的输入信号大小。因此，相同大小的输入信号，反谐振频率处的输入产生的输出信号大于其他频率，自混频器实现了滤波作用。由于微机电谐振器在反谐振频率处的Q值较高，因此可获得较低的通带带宽。在远离反谐振频率处，谐振器等效于一个电容，通过调整谐振器的几何结构即可调整此等效电 容的容值。通过调整容值，即可调整耦合到CMOS管栅极的信号大小，使晶体管栅极与漏极的二次效应相互抵消，不产生基带的输出信号。因此在远离反谐振频率处的输入信号几乎不产生输出信号。
上述滤波自混频器具有较低的通带带宽(<0.5％)，同时具备极高的带外抑制能力(>40dB)。其工作频率为滤波器的反谐振频率。对归一化的不同频率输入信号的输出进行仿真可知，滤波自混频器可在自混频的同时，实现高Q值、高带外抑制的滤波。有利于提升唤醒接收机的抗干扰能力、灵敏度以及鲁棒性。
综上所述，本公开提供了一种滤波自混频器，通过在自混频器电路中引入微机电谐振器。对输入信号下变频的同时，具备极佳的滤波性能(带宽<0.5％，带外抑制>50dB)，从而提升唤醒接收机的抗干扰性能。
以上所述本公开的具体实施方式，并不构成对本公开保护范围的限定。任何根据本公开的技术构思所作出的各种其他相应的改变与变形，均应包含在本公开权利要求的保护范围内。

Claims (10)

  1. 一种滤波自混频器，包括：
    输入信号端，被配置用于接收唤醒信号及干扰信号作为输入信号；
    至少一个CMOS管组成的能量探测电路单元，被配置用于通过二次效应对输入信号进行混频并输出基带信号；
    偏置电压单元，被配置用于提供CMOS管的栅压以调整CMOS管的沟道阻抗；
    耦合支路单元，设置于所述输入信号端和能量探测电路单元之间，将所述输入信号耦合至能量探测电路单元中的CMOS管的漏极或源极；以及
    微机电谐振器支路，设置于所述输入信号端和偏置电压单元之间，能够在不同的频率下输出不同的栅极信号以调整二次效应，实现对输入信号中干扰信号的滤除。
  2. 根据权利要求1所述的滤波自混频器，其中，所述能量探测电路为三极管型能量探测电路，能量探测电路单元中的CMOS管选自N型CMOS管和P型CMOS管。
  3. 根据权利要求2所述的滤波自混频器，其中，所述偏置电压单元包括至少一条偏置电压支路，每条所述偏置电压支路包括依次相连的偏置电压源和偏置电阻。
  4. 根据权利要求2所述的滤波自混频器，其中，所述耦合支路单元包括至少一条耦合支路，每条所述耦合支路包括与输入信号端相连的耦合电容，所述耦合电容连接至对应的CMOS管的漏极或源极。
  5. 根据权利要求4所述的滤波自混频器，其中，所述微机电谐振器支路包括：
    微机电谐振器，一端连接至输入信号端，另一端连接至CMOS管的栅极；以及
    隔直电容，与微机电谐振器相连，被配置用于隔离CMOS管的直流电平。
  6. 根据权利要求1所述的滤波自混频器，其相对分数带宽<0.5％，带外抑制能力>40Db；滤波自混频器的工作频率为微机电谐振器的反谐振频率。
  7. 根据权利要求1所述的滤波自混频器，当输入信号中的干扰信号频率远离反谐振频率时，微机电谐振器相当于一个等效电容，通过调整谐振器的几何结构调整等效电容的容值，以调整耦合到CMOS管栅极的栅极信号的大小，使晶体管的栅极与漏极或漏极的二次效应相 互抵消，从而不输出基带信号。
  8. 根据权利要求5所述的滤波自混频器，其中，所述微机电谐振器的类型选自薄膜体声波谐振器，横向振动压电谐振器，体声波谐振器，声表面波谐振器，兰姆波谐振器，剪切压电谐振器，石英晶体谐振器。
  9. 根据权利要求1所述的滤波自混频器，其中，所述能量探测电路单元中的CMOS管设置形式包括单级形式，多级级联形式或伪差分形式的多级级联形式。
  10. 根据权利要求3所述的滤波自混频器，其中，所述偏置电压源通过栅压偏置电路提供栅极直流偏置电压，或通过晶体管的漏极或源极来提供栅极直流偏置电压。
PCT/CN2023/121613 2023-09-26 2023-09-26 滤波自混频器 Pending WO2025065254A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2023/121613 WO2025065254A1 (zh) 2023-09-26 2023-09-26 滤波自混频器

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2023/121613 WO2025065254A1 (zh) 2023-09-26 2023-09-26 滤波自混频器

Publications (1)

Publication Number Publication Date
WO2025065254A1 true WO2025065254A1 (zh) 2025-04-03

Family

ID=95204463

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/121613 Pending WO2025065254A1 (zh) 2023-09-26 2023-09-26 滤波自混频器

Country Status (1)

Country Link
WO (1) WO2025065254A1 (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110024812A1 (en) * 2007-12-11 2011-02-03 Dana Weinstein Resonant body transistor and oscillator
CN106603014A (zh) * 2016-12-28 2017-04-26 杭州迦美信芯通讯技术有限公司 一种低功耗低成本高线性的电压模式无源混频器
WO2020142792A1 (en) * 2019-01-04 2020-07-09 The Trustees Of Columbia University In The City Of New York Circuits and methods for wake-up receivers

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110024812A1 (en) * 2007-12-11 2011-02-03 Dana Weinstein Resonant body transistor and oscillator
CN106603014A (zh) * 2016-12-28 2017-04-26 杭州迦美信芯通讯技术有限公司 一种低功耗低成本高线性的电压模式无源混频器
WO2020142792A1 (en) * 2019-01-04 2020-07-09 The Trustees Of Columbia University In The City Of New York Circuits and methods for wake-up receivers

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
MANGAL VIVEK; KINGET PETER R.: "An ultra-low-power wake-up receiver with voltage-multiplying self-mixer and interferer-enhanced sensitivity", 2017 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), IEEE, 30 April 2017 (2017-04-30), pages 1 - 4, XP033130548, DOI: 10.1109/CICC.2017.7993615 *
MANGAL, V. ET AL.: "A Wake-Up Receiver With a Multi-Stage Self-Mixer and With Enhanced Sensitivity When Using an Interferer as Local Oscillator", IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 54, no. 3, 4 January 2019 (2019-01-04), pages 808 - 820, XP011711333, DOI: 10.1109/JSSC.2018.2884919 *

Similar Documents

Publication Publication Date Title
CN114614845B (zh) 唤醒接收机
KR20020026836A (ko) 파워 증폭기
JP2004503975A (ja) バルク音波フィルタ
Khorshidian et al. An inductor-less all-passive higher-order N-path filter based on rotary clocking in N-path filters
CN104124923A (zh) 一种低噪声混频器电路
WO2016127823A1 (zh) 一种射频高q值带通滤波器
CN109309480B (zh) 一种低噪声开关跨导混频器
CN110661508B (zh) 一种双工器、多工器、高频前端电路以及通信装置
CN116996081B (zh) 带内干扰抑制唤醒接收机射频电路
CN100448168C (zh) 跨导电容滤波器和抑制该滤波器引入的有害信号的方法
CN116803005A (zh) 用于实现多个滤波器频率响应的具有多个输出或输入的滤波器
WO2021227347A1 (zh) 带通滤波电路和多工器
US11601115B2 (en) Electronic RF filter
WO2025065254A1 (zh) 滤波自混频器
EP2773041B1 (en) A two stage source-follower based filter
CN116996026B (zh) 滤波自混频器
CN106487352A (zh) 数字可变电容电路、谐振电路、放大电路和发送器
CN116996080B (zh) 唤醒接收机射频电路
CN116996082B (zh) 差分输出的唤醒接收机射频电路
WO2024159675A1 (zh) 基于ipd技术的nb系统无源芯片电路及芯片模组
CN116599540A (zh) 一种输入三阶交调点27.6dBm带宽100MHz的射频接收机
JP2003163606A (ja) スイッチ半導体集積回路
US20250240043A1 (en) Wake-up receiver
JP2006345533A (ja) 複数の音響共振器を用いて信号をバンドパスフィルタリングするバンドパスフィルタネットワーク及び方法
JPH053923B2 (zh)

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23953414

Country of ref document: EP

Kind code of ref document: A1