WO2025024607A1

WO2025024607A1 - Superconductive nanoscale magnetic sensors and applications including quantum computing

Info

Publication number: WO2025024607A1
Application number: PCT/US2024/039432
Authority: WO
Inventors: Ivan P. Nevirkovets; Oleg A. Mukhanov
Original assignee: SeeQC, Inc.
Priority date: 2023-07-24
Filing date: 2024-07-24
Publication date: 2025-01-30

Abstract

This patent document provides superconducting magnetic sensors for sensing magnetic fields and for being used in various applications including quantum computing. One example of such a sensor includes a multilayer structure that includes at least one magnetic layer and at least one non-magnetic layer; and two superconducting electrodes coupled to the multilayer structure so that the multilayer structure and the two superconducting electrodes transmit a superconducting current through the multilayer structure.

Description

SUPERCONDUCTIVE NANOSCALE MAGNETIC SENSORS AND APPLICATIONS INCLUDING QUANTUM COMPUTING

Priority Claim and Related Patent Application

This patent document claims the priority and benefits of U.S. Provisional Patent Application No. 63/528,549 filed by Applicant SEEQC, Inc. on July 24, 2023, which is entitled “SUPERCONDUCTIVE NANOSCALE MAGNETIC SENSORS AND APPLICATIONS INCLUDING QUANTUM COMPUTING” and lists inventors Ivan P. Nevirkovets and Oleg A. Mukhanov. The entire disclosure of U.S. Provisional Patent Application No. 63/528,549 is incorporated by reference as part of this patent document.

Technical Field

This patent document relates to magnetic sensors for sensing magnetic fields and their applications.

Background

Magnetic sensors are devices for measuring magnetic fields. Examples of magnetic sensors include Hall magnetic sensors and magnetic sensors based on Superconducting Quantum Interference Devices (SQUIDs) that measure an electrical signal from such a sensor that is dependent of the strength of the magnetic field.

Summary

The disclosed sensitive cell for detection of very low fields comprises a Josephson junction that comprises two or more superconductive electrodes and a multilayer structure that includes interleaved or alternative magnetic and non-magnetic layers. The multilayer structure as a whole has hysteresis-free response to the external magnetic field swept within a small range, which allows the sensitive cell to serve as a sensor of weak fields. The sensing area of the sensitive cell can be made very small, well below 1 pm², which allows the sensitive cell to be incorporated into a scanning device with very high spatial resolution. The read head of a scanning device is disclosed. The read head transforms the magnetic field being sensed with the said sensitive cell into electnc signal.

In one aspect, the disclosed technology can be implemented to provide a superconducting device that includes, a magnetic sensor for sensing a magnetic field that includes a multilayer structure that includes at least one magnetic layer and at least one non- magnetic layer; and two superconducting electrodes coupled to the multilayer structure so that the multilayer structure and the two superconducting electrodes transmit a current through the multilayer structure. In some implementations, the device can further include a cantilever that includes a cantilever tip on which the magnetic sensor is located, and a scanning mechanism coupled to the cantilever to move the cantilever to scan the magnetic sensor over a sample for measuring the sample.

In another aspect, the disclosed technology can be implemented to provide a superconducting quantum interference device that includes a superconducting loop comprising a first superconducting layer, a second superconducting layer, and at least one Josephson junction formed between the first superconducting layer and the second superconducting layer; and a multilayer stack situated inside the superconducting loop and structured to include at least one magnetic layer and at least one non-magnetic layer.

In yet another aspect, the disclosed technology' can be implemented to provide a system capable of information processing based on both quantum computing using different quantum states of quantum bits and classical digital computing using digital processors. This system includes a cryostat system structured to include different cryogenic stages operable to provide a low cryogenic temperature and higher cryogenic temperatures; a quantum computing module enclosed by the cry ostat system at the low cry ogenic temperature and structured to include different quantum bit circuits that exhibit different quantum states and perform quantum computing operations; a quantum bit management circuit module enclosed by the cryostat system, located adjacent to the quantum computing module to include quantum bit control circuits that direct control signals to control the quantum bit circuits of the quantum computing module, and quantum bit readout circuits that respectively interact with and output readout signals indicative of quantum states of the quantum bit circuits, respectively, from, the quantum bit circuits; and a plurality of superconducting magnetic sensors enclosed by the cryostat system and located within the different cryogenic stages, each superconducting magnetic sensor structured to sense a local magnetic field.

The above and other features and their specific implementations are described in detail in the description and the drawings and the claims.

Brief Description of Drawings

Fig. 1 includes Figs. 1A-1E illustrating examples of various implementations of nanoscale magnetic sensor cells based on the disclosed technology⁷. Fig. 1 A shows also one example of the direction of the bias current for one of the magnetic sensor cells and direction of an external magnetic field being detected by the magnetic sensor cell.

Fig. 2 includes Figs. 2A, 2B and 2C showing different probe tips of scanners.

Fig. 3 shows an example of a cantilever comprising a probe with a nano-scale magnetic sensor cell or a disclosed SQUID for scanning a sample in scanning superconducting quantum interference device (SQUID) microscopy devices.

Fig. 4 shows an example of a plot of Josephson critical current vs. magnetic field dependence for aNb/Ni/(Al/Ni)14/Nb lateral Josephson junction measured at 1 K.

Fig. 5 shows an example of a plot of Josephson critical current vs. magnetic field dependence for a micro-SQUID whose loop is vertically-oriented with respect to the substrate and filled with (Al/Py)10 multilayer (Py is 80% Ni - 20% Fe alloy). Arrows show the direction of magnetic field sweeping.

FIGS. 6A, 6B, 6C, 6D and IE show examples of quantum classical computing systems which can be used to implement the disclosed nano-scale magnetic sensors for quantum computing operations.

FIG. 7 illustrate an example of a 3-D magnetic sensor or detector module with 3 magnetic sensors to measure components of a magnetic field in three different directions.

FIGS. 8 and 9 show examples of the installation of 3-D magnetic sensor or detector modules in the quantum computer systems shown in FIGS. 6A and 6B, respectively.

Detailed Description

The technology disclosed in this patent document can be implemented to provide superconductive nanoscale magnetic sensors for various applications including quantum computing devices and systems.

The disclosed nanoscale magnetic sensors can be used to provide high-sensitivity detection of weak magnetic fields from small objects including small spin systems such as magnetic nanoparticles, single-molecule magnets, and nanometer-scale electronic devices in semiconductor- and superconductor-based circuits. Uses for such devices include magnetic field detection with high spatial resolution. Such devices can be used for study the role of flux trapping and vortices in the performance of large-scale quantum and classical superconducting integrated circuits, monitor residual magnetic field on chip, study new quantum materials, etc.

A Superconducting Quantum Interference Device (SQUID) can be used for sensing magnetic fields and various devices and applications. A SQUID can be constructed by, for example, a superconducting ring interrupted by one or two Josephson junction(s). Operation of SQUID is based on the magnetic-flux quantization in superconducting ring, which, in combination with weak phase-sensitive superconductivity across the Josephson junction (JJ), allows for highly sensitive measurement of all physical quantities which can be converted to magnetic flux. SQUID converts local magnetic flux to an electrical signal measurable with external electronics. To improve the sensitivity and spatial resolution, the lateral dimensions of the detection loop of the SQUID should approach the size of the probed nanoparticle and the advantage of a conventional SQUID over a single Josephson junction (JJ) diminishes. When the size of the superconducting loop shrinks, ultimately, the sensing area will be determined mainly by the London penetration depth, similar to that of a single SIS JJ (here S and I denote a superconductor and an insulator, respectively). Therefore, at the nanoscale, a single JJ can compete as a sensitive magnetic field sensor. This disclosure proposes a promising junction design for nanoscale field sensing.

The extremely compact vertically-oriented SQUID designs disclosed here can be comparable in lateral dimensions with a single Josephson junction, and can be used as a sensitive magnetic field detector and for other applications. In the nano-SQUID design disclosed herein, the magnetic multilayer serving for the flux concentration is inserted directly into the vertically oriented SQUID loop, which enhances the field sensitivity of the SQUID and makes its lateral dimensions very small, scalable to nm size.

Figs. 1A-1E show perspective views of examples of five embodiments of hybrid superconductive-magnetic sensor cells 1 through 5 in accordance with the disclosed technology in this patent document. Such a hybrid superconductive-magnetic sensor cell may include a magnetic multilayer 11 and superconducting electrodes 12 which can be arrandged in different geometries in the examples of designs 1 - 4 as shown in Figs. 1 A-1D, respectively.

The magnetic multilayer 11 includes alternating layers of a non-magnetic material 13 and a magnetic material 14. The non-magnetic material 13 can be a dielectric, a semiconductor, or a metal. In some implementations, the non-magnetic material 13 may be or include a metal such as Al. Ag, Au, Cu, Pt, Hf, Nb, Ti, Ta, V, W or other metals. The magnetic material 14 can be or include a suitable soft magnetic material that is characterized by non-hysteretic dependence of the magnetic moment, AT, as function of an applied magnetic field, H, at temperatures of the device operation (i.e., when the electrodes 12 are in the superconducting state). Examples of the magnetic material 14 include, but are not limited to, ferromagnetic elements Fe, Co. Ni. and their alloys with non-magnetic materials such as noble metals like, Pt, Cu and Pd: PcLFei-r, PcLNii-x, CuxFei-x, CmNii-r, PtvCoi-x, and others. An advantage of the multilayer magnetic material structure 11 as compared to a thick one layer strucutre is that thin films may prevent undesired domain formation in the direction perpendicular to the layer plane, provide better control of the

dependence, and better control of the magnetic interaction between the layers.

The superconducting electrodes 12 can be made or structured to include Nb, NbN, MoGe, MgB2, or other superconductors including high-temperature superconductors such as a Yttrium barium copper oxide that includes YBaiCmCh-.v and others. The superconducting electrodes 12 serve to provide a bias current I to the sensor cell and to read out the signal from the sensor cell by the way of measuring the voltage across the multilayer barrier 11. In various implementaitons of the design depicted in Fig. 1A-D, the bias current I can be suppled to flow mostly parallel to the layers of the multilayer magnetic material structure 11. as is shown schematically in Fig. 1 A, which constitues lateral junctions. In other impelemntations, the bias current I may also flow mostly across the layers in the multilayer magnetic material structure 11

In superconducting small-scale devices, the flux quantization, tunneling effect, and Josephson effect are the basic physical phenomena which determine the device performance. In the sensor cell embodiments depicted in Figs. 1A-1D, the entire sensor cell serves as a Josephson junction, wherein the weak link, or the barrier, between the superconducting banks or electrodes 12 is represented by the multilayer 11. The superconductivity of this device is ensured oving to the proximity effect between the superconducting banks or electrodes 12 and the multilayer 11. The principle of operation of the devices depicted in Figs. 1 A-1D is based on the I AH) dependence displaying very' narrow' maxima. An example of

dependence for a Nb/Ni/(A1/Ni)i4/Nb device with the sensing area of A_m - 5- 10‘¹⁴ m² is shown in Fig. 4. A magnetic field is applied as is shown in Fig. 1A in the plane of the structure and perpendicular to the current flow. If the junction w as an SNS junction with N being a non-magnetic, normal metal, the period of the diffraction pattern IJ would be AH = o/A = 41 mT, where <bo = 2.07-10’¹⁵ Wb is the flux quantum. The magnetic multilayer in the barrier enhances the magnetic flux in the junction in an applied magnetic field by contributing the flux O_m = 47t mAf, where M is the magnetic moment M=y H. The w idth of the peak in Fig. 4 is about 10 mT. Assuming that the peak is the central lobe of a standard Fraunhofer pattern, one infers the field of 5 mT corresponding to <bo. This is considerably smaller value than that expected for the SNS junction with the same sensing area. Therefore, lateral multilayer junctions involving alternating magnetic and normal-metal layers (cf. Fig 1A-1D) can serve as efficient magnetic field sensors that, in accordance with the disclosed technology in this document, are more sensitive to the magnetic field than similar devices not involving a magnetic multilayer.

In one aspect of the disclosed technology, the thicknesses of the magnetic layers, or the thicknesses of the non-magnetic layers, or the thicknesses of both magnetic and non-magnetic layers are intentionally made different, in which case the effect analogous to that obtained in Superconducting Quantum Interference Filters (SQIFs) can be achieved, i. e., the width of the central lobe of the diffraction pattern is expected be very narrow, resulting in improved field sensitivity and ability to measure the absolute value of magnetic field. An example of such a SQIF is described in a publication entitled “Superconducting Multiple Loop Quantum Interferometers” by Oppenlander et al. published in IEEE Trans. Appl. Supercond. 11(1), 11271-1274 (2001) which is incorporated by reference as part of this patent document.

Fig. IE shows an example of another design of a nano-SQUID sensor cell 5 which includes weak links 15 formed between the top superconducting electrode 12 and the bottom superconducting electrode 12'. The weak links 15 sen e as Josephson junctions.

The superconducting electrodes 12 and 12' together with the Josephson junctions 15 form a SQUID. In this example, the weak links or Josephson junctions 15 are formed on the side walls of the bottom superconducting electrode 12', which makes this device very compact in comparioson with various other planar SQUIDs. The weak links or Josephson junctions 15 may have tunneling, direct, or resonant conductivity. In some implementations, the weak links or Josephson junctions 15 may have tunneling conductivity in order to provide a relatively high (on the order of 1 mV) critical voltage L/ \. where is the Josephson critical current, and / \ is the junction normal state resistance.

Fig. 5 shows an example of the experimental

dependence measured at 4.2 K for a micro-SQUID (cf. Fig. IE) whose loop is filled with (Al/Py)io multilayer (Py is 80% Ni - 20% Fe alloy). The measurements of the 7c(77) dependence demonstrate the SQUID response. The sensing area of this device is 2.02-10"¹³ m², which includes the London depth, XL, of 91 nm for Nb. Therefore, the measurements of this experiment confirm the feasi bi 1 i ty of a nano-SQUID with the loop filled with a magnetic multilayer to enhance its response to the external magnetic field, in accordance with the disclosed technology in this document.

Figs. 2A-2C show perspective views of examples of three embodiments 200 - 202 of the probe tips of scanners involving some of the sensor cells based on the disclosed technology. The probe tip comprises one of the sensor cells in FIGS. 1 A- IE or similar cells involving the magnetic multilayer, as in case of the embodiment 201 in FIG. 2B. The cell is fabricated together with the proper wiring on the substrate 20; typically, the substrate 20 is a Si substrate, either oxidized or not oxidized, but it can be made of other material such as. e.g., AI2O3 or MgO. In some implementations, as shown for the probe tips 201 (FIG. 2B) and 202 (FIG. 2C), the structure may include an insulating layer 21 that serves to electrically separate the superconducting wires 12 and 12'. The insulating layer 21 can be made of or include, SiCh or other insulator that can be deposited in the thin-fdm form by using conventional deposition methods. One of advantages of the probe tips disclosed in the this document is their small size in x - y plane (cf. Fig. 2), and therefore, a high spatial resolution of the scanner that exploits them, can be achieved owing to small lateral dimensions of the sensor cells and their sensing plane being oriented perpendicular to the substrate 20 plane. As a result, the area of the tip is determined, in the y direction, by the cross-sectional size of the sensor cell and the thickness of the substrate tip that holds the sensor cell, and, in the perpendicular (x) direction, by the width of the multilayer 11 and the thickness of the superconducting wire 12. Using various fabrication techniques, including some commonly available fabrication techniques, the dimensions of the sensor cell in both x andy direction can be made small, e.g.. smaller than 1 pm in some designs.

Fig. 3 shows a schematic view of an example of a cantilever 300 using one of the probes 200, 201, 202 in FIGS. 2A, 2B and 2C or similar probe designs for scanning a sample 301 in scanning superconducting quantum interference device (SQUID) microscopy devices. The cantilever 300 includes a cantilever tip on which the magnetic sensor is located, and a scanning mechanism is coupled to the cantilever 300 to scan or move cantilever to position the magnetic sensor over different positions over the sample 301for measuring the sample 301. This example illustrates the benefits of exploiting the compact size of the sensor cell and the probe tip.

The disclosed technical features can be used in various devices and applications, including, for example, scanners analogous to those exploiting conventional SQUIDs in order to improve the field sensitivity and spatial resolution in various fault location techniques, e. g., for detection of shorts in conventional integrated circuits. Other use cases include local current distributions, magnetic properties, superconducting vortices and uniformity of superconductors, study the role of flux trapping and vortices in the performance of quantum and classical superconducting integrated circuits.

The following are examples of implementations of nano-scale magnetic sensors or sensor cells.

Example 1 A sensor cell for magnetic field detection includes a multilayer comprising at least one magnetic layer and at least one non-magnetic layer, the multilayer situated between the two superconducting electrodes, the multilayer and the said electrodes and arranged to pass the superconducting current through the multilayer.

In Example 1, the multilayer and the two superconducting electrodes are arranged to pass the superconducting current along the layers of the multilayer.

In Example 1, the multilayer comprises a plurality of the alternating magnetic and non-magnetic layers.

In Example 1 , the multilayer comprises at least one ferromagnetic layer and at least one non-ferromagnetic layer.

In Example 1, the multilayer comprises a plurality of alternating magnetic and metal non-magnetic and non-superconducting layers.

In Example 1, the multilayer comprises a plurality of the alternating magnetic and superconducting layers.

In Example 1, the multilayer comprises magnetic layers of different thicknesses.

In Example 1, the multilayer comprises non-magnetic layers of different thicknesses.

In Example 1, the multilayer comprises magnetic layers of different thicknesses and non-magnetic layers of different thicknesses.

In Example 1, the multilayer is configured to have non-hysteretic dependence of the total magnetic moment versus an applied magnetic field.

The sensor cell in Example 1 can be used for constructing a probe tip of a scanner comprising a substrate on which the sensor cell is fabricated. The probe tip includes wiring to provide a bias current to the sensor cell and to read out a response signal from the sensor cell. The sensor cell is situated at the edge of the substrate, and the probe tip is configured in such a way that the multilayer is vertically stacked with respect to the substrate plane.

Example 2:

A superconducting quantum interference device includes a superconducting loop comprising a first superconducting layer, a second superconducting layer, and at least one Josephson junction formed between the first superconducting layer and the second superconducting layer, and a multilayer stack situated inside the superconducting loop, the multilayer stack comprising at least one magnetic layer and at least one non-magnetic layer.

In Example 2, the multilayer stack comprises a plurality of alternating magnetic and non-magnetic layers. In Example 2, the multilayer stack comprises at least one ferromagnetic layer and at least one non-ferromagnetic layer.

In Example 2, the superconducting loop comprises two Josephson junctions formed between the first superconducting layer and the sidewalls of the second superconducting layer.

In Example 2, the multilayer stack is configured to have non-hysteretic dependence of the total magnetic moment versus an applied magnetic field.

A probe tip of a scanner can be constructed to include a substrate, a superconducting quantum interference device in Example 2 fabricated on the substrate, and wiring to provide a bias current to the superconducting quantum interference device and to read out a response signal from the superconducting quantum interference device. The superconducting quantum interference device is situated at the edge of the substrate, the probe tip is configured in such a way that the loop plane of the superconducting quantum interference device is oriented perpendicular with respect to the substrate plane.

The above disclosed nano-scale magnetic sensors can be implemented in various applications in which a magnetic field is measured or monitored. The following sections describe quantum computing devices or systems that implement disclosed nano-scale magnetic sensors.

Classical digital computers are designed to perform computations based on Boolean logic. Computing technologies based on Boolean logic have revolutionized a wide range of industries and technologies for recent decades but have also exhibited certain limitations in performing highly complex or large numbers of computations, such as modeling of molecular structures and properties of chemical compounds or biological structures, cryptography, or modeling of complex systems for weather forecast, climate changes and others. Various new computation techniques have been investigated to supplement or replace Boolean logic based digital computing.

Quantum-mechanical systems can be used to construct new computation systems for complex information processing. A quantum system suitable for quantum computing has an ensemble of subsystems exhibiting different quantum states where subsystems are correlated or ‘’entangled” with one another due to quantum coherence, including long-range quantum coherence. In various implementations for quantum computers, each subsystem in the ensemble of subsystems may be a quantum system exhibiting two or more different quantum states to operate as a fundamental quantum device and information can be represented, stored, processed, and transmitted by superposition and correlation of quantum states of different fundamental quantum devices. One example of such a fundamental quantum device is a two-state device known as a quantum bit (“qubit”). Some examples of implementations of qubits include superconducting qubits based on superconducting Josephson junctions developed at IBM, Google, Intel and others, ion trap devices based on electromagnetic trapping fields by laser beams developed at Honeywell and lonQ, and semiconductor-based quantum dots and other devices capable of quantum computing operations.

FIGS. 6A, 6B, 6C, 6D and 6E show examples of quantum computing systems and various features in a multistage cryogenic system.

The computing systems disclosed in this patent document include a quantum processing unit (QPU) system that carry out computations by using quantum states of an ensemble of subsystems each exhibiting two or more different quantum states to operate as a fundamental quantum device so that information can be represented, stored, processed, and transmitted by superposition and correlation of quantum states of different fundamental quantum devices. Such a fundamental quantum device can be a quantum bit circuit in various configurations, including a superconducting circuit operable at a sufficiently low cryogenic temperature to exhibit two or more different quantum states.

In general, QPU systems can be based on various QPU technologies including, e.g., superconducting Josephson junctions, ion trap devices based on electromagnetic trapping fields by laser beams, or semiconductor-based quantum dots. The examples of QPU systems below are implemented by using superconductor-based quantum computing modules (e.g.. superconducting Josephson junctions) and by combining quantum computing modules or devices and classical digital computing modules or devices in ways that allow the systems to be scalable for complex computing applications. One of the features of the disclosed scalable hybrid quantum-classical computing systems is to strategically partition a system into different quantum and classical digital computing modules, devices or components at various cryogenic stages at different cryogenic temperatures. Such implementations of the disclosed technology can be used to simplify and reduce the complex and bulky cryogenic systems commonly used in various quantum computer systems using superconducting quantum computing devices and to reduce the use or level of use of complex superconducting cabling systems for linking different computing or processing modules. Implementations of the disclosed technology can be devised to allow for commercially scalable fabrication using integrated circuit (IC) fabrication processes and equipment in manufacturing key modules or devices for quantum computer systems based on superconducting Josephson junctions. The technology disclosed in this patent document can be implemented to provide special interconnection designs for connecting hardware components within a multi-stage cryogenic system to provide fast communications between the quantum computing module and its controller and classical digital computing modules, including GPUs while allowing efficient management of wiring with other modules.

FIG. 6A shows an example of a quantum computing system 110 to produce scalable hybrid quantum-classical computing systems for various computing applications. The quantum computing system 110. as its name implies, includes multiple qubit circuits and performs computing operations based on quantum states of the qubit circuits and is in communications with external computers or computing systems 130 via the communication links or networks 120. The communication links and networks 120 may include circuits where signals are transferred in the form of electromagnetic signals, including for example, electric signals carried by electrically conductive wires and/or optical signals. In operation, the quantum computing system 110 receives computation requests or tasks from one or more external computers or computing systems 130, performs the requested computation operations and sends the computation results back to the one or more requesting external computers or computing systems 130. The communications and/or interactions between the quantum computing system 110 and external computers or computing systems 130 are via the communication links or networks 120 and may constitute the longest communication cycle in time in the operations of the quantum computing system 110 and is labeled as the long communication links or loops. As further explained below, the quantum computing system 1 10 is structured to partition different internal computing modules so that those internal computing modules communicate via internal shorter communication links or loops such as medium communication links or loops with medium delays in time and fast communication links or loops with the shortest delays in time.

The quantum computing system 110 includes a multi-stage cryogenic system to provide different cryogenic stages at different locations and to maintain at different cryogenic temperatures for keeping different modules or devices at their respective desired temperatures (e.g., Tl, T2. T3 and T4 as shown). In some implementations, the different cryogenic stages may be designed to produce temperatures from milli Kelvins to tens of Kelvins. This example system 110 includes one or more quantum computing modules 102 and each quantum computing modules 102 includes multiple qubit circuits or devices as the quantum qubit ensemble to perform desired quantum computing operations via their respective qubit states. In many implementations, the quantum computing module 102 is engaged or coupled to a cryogenic stage at a low cryogenic temperature Tl to ensure that qubit circuits or devices are under the desired superconducting condition and under acceptable quantum computing operating conditions at which the noise level and interference level are sufficiently low. A quantum bit management circuit module 104 is provided to be in communications with the quantum computing module 102 to provide control signals to the individual qubit circuits or devices of the quantum computing module 102 and to read out the individual qubit circuits or devices and may be implemented by using non-quantum mechanical processing circuitry such as digital circuitry or analogy circuitry or a combination of digital and analog circuitry. The quantum bit management circuit module 104 may be implemented with superconducting circuitry and is coupled to a cryogenic stage at a cry ogenic temperature T2 which may be different from the low cryogenic temperature T1 in some implementations or be the same as the temperature T1 in other implementations. As further explained below, in some designs, the quantum computing module 102 and quantum bit management circuit module 104 may be engaged to share a common cryogenic stage so that both modules are kept at the same cryogenic temperature. The quantum bit management circuit module 104 can be structured to include (1) quantum bit control circuits to direct control signals to the quantum bit circuits to control the quantum bit circuits, respectively, and (2) quantum bit readout circuits to output readout signals from the quantum bit circuits, respectively. In this example, the quantum computing module 102 and quantum bit management circuit module 104 together form the “heart” or “core” of the quantum computing system 110 in part because the quantum computing operations are performed within the quantum computing module 102 based on the control signals to qubit circuits from the quantum bit management circuit module 104 and the readouts of the qubit circuits are performed by the quantum bit management circuit module 104. The communications between the quantum computing module 102 and quantum bit management circuit module 104 are essential to the quantum computing operations in terms of the qualify and speed of such communications. Accordingly, in implementations, the quantum computing module 102 and quantum bit management circuit module 104 can be placed or positioned physically close to or adjacent to each other to shorten signal paths between the two modules 102 and 104 and to reduce any interference or noise to such communications. In addition, the functions or operations of the quantum bit management circuit module 104 may, by an intentional design, be limited to certain core functions or operations in connection with the quantum computations performed by the quantum computing module 102 so that the quantum bit management circuit module 104 can achieve a short or fast response or processing time to ensure fast input/output signaling at the quantum computing module 102. This intentional reduced function design consideration for the quantum bit management circuit module 104 is also based on the desire to reduce the power consumption and energy dissipation by the quantum bit management circuit module 104 to its surroundings in light of its close proximity to the quantum computing module 102, the noise or interference by the quantum bit management circuit module 104 to the quantum computing module 102 and the need for maintaining proper cryogenic conditions at the both the quantum bit management circuit module 104 and the adjacent quantum computing module 102. Based on the above and other considerations, the interconnections and signal paths between the two modules 102 and 104 are designed to form the fast communication link or loop with the shortest delay in time for the quantum computing system 110. For example, in some implementations, the quantum computing module 102 may include at least one integrated chip supporting one or plurality of quantum bit circuits, and the quantum bit management circuit module 104 may be formed on another integrated chip which is directly coupled to the integrated chip with the quantum bit circuits, mechanically and electrically, as a multichip module via superconducting bumps, capacitive coupling, or magnetic coupling via vacuum to transfer control signals and readout signals therebetween. This multichip module formed by the two modules 102 and 104 can be coupled to the same cryogenic stage at the low cryogenic temperature Tl. This design can be commercially important because the chip fabrication for the multi chip module formed by the two modules 102 and 104 is a scalable platform to allow a wide range of quantum bit circuits to be fabricated and included in the quantum computing module 102 and, similarly, the quantum bit management circuit module 104 may also be scaled based on the number of quantum bit circuits present.

The quantum computing system 110 in FIG. 6A further includes a digital processing module 108 that provides certain signal and data processing functions or operations for the quantum computing system 110 in connection with quantum computations performed by the quantum computing module 102 via the quantum bit management circuit module 104. In this regard, the digital processing module 108 forms the core processing module for non-quantum computation and/or processing functions within the quantum computing system 110 and thus is designed with much more complex circuitry’ and higher processing capabilities than the quantum bit management circuit module 104. Specifically, certain functions and/or processing operations that cannot be built into the quantum bit management circuit module 104 may be included in the circuitry' of the digital processing module 108. In addition, the digital processing module 108 also functions as an interface between the quantum computing system 110 and one or more external computers or computing systems 130 via the communication links or networks 120. As such, the digital processing module 108 is designed to further include processing functions associated with communications and interactions between the quantum computing system 110 and external computers or computing systems 130. Therefore, different from the placement and design of the quantum bit management circuit module 104, the digital processing module 108 is designed to be a complex and capable classical counterpart and co-processor of the quantum computing module 102 of the quantum computing system 110. The increased functions and/or processing operations and processing capabilities packed into the digital processing module 108 add to the complexity and size of the circuitry of the digital processing module 108 and further increase the power consumption and energy dissipation of the digital processing module 108. Therefore, it is desirable to place the digital processing module 108 physically away from the quantum computing module 102 and its adjacent neighbor quantum bit management circuit module 104 to reduce the noise and interference that the digital processing module 108 may impose onto the quantum computing module 102. The digital processing module 108 may be designed with various functions and capabilities, including, e.g., error correction functions for the quantum computing system 110, and non-quantum computation and/or processing functions within the quantum computing system 110, including, e.g., functions in connection with the control of and readout of the quantum computing module 102 performed by the quantum bit management circuit module 104, and management of data of the quantum computations performed by the quantum computing module 102. In some implementations, the digital processing module 108 may be coupled to a cryogenic stage at a temperature T4 higher than those for the quantum computing module 102 (at Tl) and quantum bit management circuit module 104 (at T1 or T2). The digital processing module 108 may be designed to include superconducting circuitry and is enclosed within the multi-stage cryogenic system of the quantum computing system 110.

The intentional design for placing the digital processing module 108 away from the quantum bit management circuit module 104 leads to longer signal paths or links between the digital processing module 108 and the quantum bit management circuit module 104. Within the enclosure of the multi-stage cryogenic system, such signal paths or links may be formed by using superconducting wires or cables. Notably, the long lengths of such signal paths or links may cause a certain degree of signal degradation and one option for addressing this is to add one or more interconnection repeaters or signal conditioning circuits 106 between the digital processing module 108 and the quantum bit management circuit module 104 to condition the signals. Like other modules within the multi-stage cryogenic system, each interconnection repeater or signal conditioning circuit 106 may be engaged or coupled to a cryogenic stage at a temperature T3 higher than the temperature of the quantum bit management circuit module 104 (at T1 or T2) and lower than the temperature of the digital processing module 108 (at T4). For example, a digital signal conditioning circuit module 106 may include a superconducting circuit which conditions the control signals or the readout signals.

In some implementations, the quantum computing system 110 may further include a digital processing subsystem 109 outside the multistage cryogenic system or the cryostat system to communicate with the digital processing module 108 to perform an operation associated with supporting execution of quantum or quantum-classical algorithms and/or communication with one or more other computers or networks 130. This is shown in the examples in FIGS. 1C and ID. This digital processing subsystem 109 outside the cryostat system may include one or more CMOS digital processors, one or more field-programmable gate arrays (FPGAs), or one or more application specific integrated circuits (ASICs), or one or more central processing units (CPUs), or one or more graphics processing unit (GPU) processors.

The quantum processing performed by the quantum computing module 102 is the core of the quantum computing system 110 and the signaling and communications between the quantum computing module 102 and the rest of the system 110 play a significant role in the overall computing speed and performance of the system 110. The latencies in the signaling and communications between the quantum computing module 102 and the rest of the system 1 10 are important parameters to optimize in order to achieve scalable hybrid quantum-classical computing systems for commercial applications. During operation, information is passed between the quantum computing module 102 and the other processing modules and computing entities involved in the computation performed in the quantum computing system 110. As illustrated, different communication links and/or feedback loops are formed between the quantum computing module 102 and the non-quantum modules and others in the system 110. The fastest link/loop, labelled as the short loop in FIG. 6A, is between the quantum computing module 102 and the quantum bit management circuit module 104. This link/loop can be compared with the communication link/loop formed between the quantum computing module 102 and the digital processing module 108, which experiences a longer latency as 1) communication between these modules must traverse a longer distance, including passing through the quantum bit management module 104 which may perform its own operations on the data cycling between the quantum computing module 102 and digital processing module 108, and 2) the digital processing module 108 in general performs more complex processing operations. Thus, in FIG. 6A, communication between 102 and 108 is labelled as a medium communication link/loop. An even longer latency occurs between the quantum computing module 102 and external computers or computing systems 130, labelled as a long communication link/loop in FIG. 6A, again due to increased distance (encompassing both the communication paths and possible operations of the short and medium loops plus the communication links or networks 120) and complexity of processing operations as compared to the medium link/loop.

Therefore, the example of the quantum computing system 1 10 in FIG. 6 A includes special design features to provide a hybrid computing environment that combines processing functions and/or operations by the quantum computing part (e.g., the quantum computing module 102) and non-quantum classical processing part (e.g.. the quantum bit management circuit module 104 and digital processing module 108) and to strategically partition and allocate different amounts and types of processing functions and/or operations of the nonquantum classical processing part between the quantum bit management circuit module 104 and the digital processing module 108 in light of the intentional design for placing the quantum bit management circuit module 104 physically placed close to the quantum computing module 102 while distancing the quantum computing module 102 from the digital processing module 108.

In some implementations, the digital processing module 108 may be designed to include two or more different processing modules to optimize the computation speed and performance of the digital processing module 108. For example, the digital processing module 108 may be further divided into a series of modules, as show n in FIG. 6B, with different temperature stages of the cryogenic system housing one or more such modules. In general, the design of the quantum computing system 110 in FIG. 6A allows for optimization in placement of each module within the cryogenic system so as to balance its particular needs with respect to low latency (which favors close proximity to the quantum module 102) and ability to handle dissipation during processing operations (which favors higher temperature stages that are placed further away from the quantum module 102), as well as to make efficient use of the volume of the cryogenic system.

FIG. 6C shows an example for executing certain processing operations at different modules in the system 110 in FIG. 6A, specifically showing processing operations in the digital processing module 108, processing operations in the additional digital processing module 109 operated at a higher temperature than that of the digital processing module 108 and processing operations in the quantum bit management circuit module 104. As a specific example, FIG. 6C shows that desired quantum gate sequences produced by the additional digital processing module 109 based on information from the digital processing module 108 in light of the qubit readout from the quantum bit management circuit module 104 are sent to, and are processed by, the digital processing module 108 to generate SFQ control pulse patterns. The quantum bit management circuit module 104 receives such SFQ control pulse patterns to apply the received SFQ control pulse patterns and/or flux biases to the quantum module 102 to set the relevant qubits into the quantum gate sequences. This is an example for implementing the medium communication loop in FIG. 6A, communication between quantum computing module 102 and digital processing module 108 that includes the links with the quantum bit management module 104 or any interconnection module 106 between the modules 102 and 108. FIG. 6C further shows an example for implementing the short communication loop between the quantum bit management module 104 and the quantum computing module 102 where the qubit readout obtained from reading out the quantum computing module 102 is digitally processed by the quantum bit management module 104 and the processed information is further used by the quantum bit management circuit module 104 to apply SFQ control pulse patterns and/or flux biases to the quantum module 102.

In various implementations, the quantum computing module 102 and non-quantum classical processing part (e.g., the quantum bit management circuit module 104 and the digital processing module 108) are structured to include superconducting circuits or devices coupled to different cryogenic stages of the multistage cryogenic system and superconducting interconnection wires 112, 1 14 and 116 are provided and maintained at temperatures at different locations to transfer signals between different modules or stages. The multi-stage cryogenic system for the quantum computing system 110 may be implemented in various configurations including multi-stage dilution refrigerators whose operation principle is based on mixing of helium-3 and helium-4 to provide the different cryogenic stages at the different graded cryogenic temperatures. In some implementations, the cryostat system may include a nuclear demagnetization refrigerator or adiabatic demagnetization refrigerator.

The modules within the quantum computing system 110 may be implemented in various configurations. For example, each quantum bit circuit for the qubits in the quantum computing module 102 may include a superconducting Josephson junction circuit or a switching superconducting circuit different from a Josephson junction circuit. For example, the quantum bit management circuit module 104 may be implemented to include a superconducting Josephson junction circuit or single flux quantum (SFQ) logic circuit, or a quantum flux parametron circuit such as an adiabatic quantum flux parametron circuit, or a nanowire switch, or a superconducting ferromagnetic transistor, or a superconducting spintronic device, or a field-effect superconducting device. The digital processing module 108 may be implemented to include SFQ circuitry, field-programmable gate arrays (FPGAs), or one or more application specific integrated circuits (ASICs).

In the system in FIG. 6A, optical communication links may be used for transfer of signals, either as a replacement for certain electrically conductive wires or cables or as additional links in combination with electrically conductive wires or cables. An optical communication link can provide faster data transmission and increase the communication bandwidth. For example, optical communication can be used between the cryogenic stage with the highest temperature stage (e.g., the module 108 in FIG. 6A) and a room temperature stage. In implementations, optical transmitter and receiver devices are provided in such stages or circuit modules to enable transmission and reception of optical signals between the cryogenic stages situated at the highest temperature of the cry ostat system and the room temperature electronics to provide communications therebetween. In some implementations, such optical communication links may be implemented between the module 108 and the CMOS FPGA subsystem.

FIG. 6D shows an example of a quantum computing system that is capable of information processing based at least in part on quantum computing using quantum states of quantum bits based on the design in FIG. 6A. The cryostat system in this example is structured and operable to provide different cryogenic stages at different temperatures - 20mK, 0.1K, 0.7K, and 3K. Different circuit modules at the different cry ogenic stages are interconnected by superconducting wires such as NbTi/Kapton ( or NbTi/polyamide) strips. The quantum computing module enclosed by the cry ostat system includes a first integrated chip structured to support quantum bit circuits. Each quantum bit circuit is structured as a superconducting circuit to exhibit different quantum states as a quantum bit and to quantum mechanically interact with other quantum bit circuits via quantum entanglement to cause superposition or correlation of different quantum states of the quantum bit circuits. The quantum bit management circuit 104 module is located adjacent to the quantum computing module 102 and is coupled to be maintained at the same low cryogenic temperature as with the quantum computing module. The quantum bit management circuit includes a second integrated chip, quantum bit control circuits supported by the second integrated chip and structured to direct control signals to the quantum bit circuits to control the quantum bit circuits, respectively, and quantum bit readout circuits supported by the second integrated chip and structured to output readout signals from the quantum bit circuits, respectively. In operation, the readout signals represent quantum states of the quantum bit circuits, respectively, the quantum bit control circuits and quantum bit readout circuits are structured to include superconducting circuits and operable to operate with the control signals and readout signals based on digital processing and in a non-quantum classical manner. Notably, the second integrated chip is engaged to the first integrated chip to form a multichip module (MCM) to transfer control signals and readout signals.

FIG. 6E shows an example for implementing interconnections that link different hardware components of classical and quantum circuits in the example in FIG. 6A, 6C or 6D. The system example in FIG. 6E includes at least one classical non-quantum digital processing module 108 labelled as “Classical Processor Chip.” at least one SFQ repeater as part of the interconnection circuitry or module 106, at least one classical superconducting controller as part of the quantum bit management circuit module 104, which controls the quantum computing processor or module 102 with multiple qubit circuits or devices.

The interconnections in FIG. 6E are designed to include superconducting connection nodes or pads 140 and superconducting connection cables 150 for connecting the classical circuits 104, 106 and 108 and the quantum computing processor or module 102. As illustrated, superconducting connection nodes or pads 140 may be implemented as superconducting bumps in direct contact with one or more hardware components (102, 104, 106, 108) to be connected and can be used to provide connection between a hardware component and a superconducting cable. As explained with reference to FIG. 6A, the quantum computing module 102 and the quantum bit management circuit module 104 can be placed adjacent to each other to allow short connection paths between them for fast intermodule communications and can be thermally coupled to the same cryogenic stage at the same low cryogenic temperature. Notably, the communication links or loops between the classical superconducting controller as part of the quantum bit management circuit module 104 and the quantum processor chip 102 should be fast communication links or loops and superconducting bumps can be used for interconnecting the two modules 102 and 104 to enable fast exchange of information for quantum computing operations and readout. In some implementations, the quantum bit management circuit module 104 containing the classical controller chip can be positioned on the cold plate of a cryocooler immediately above or below the quantum computing module 102 to reduce noise and interference to the quantum computing operations by the qubit circuits or devices inside the quantum computing module 102. In some implementations, superconducting bumps can be configured or used in the form of fences or walls which produce compartments separating strip or microstrip lines or other on-chip transmission lines, as well as qubits or systems of multiple qubits from each other, in order to reduce the mutual crosstalk between the superconducting electronic elements or systems and to improve the quality factors of resonators.

In addition to direct electrical connections between the quantum computing module 102 and the quantum bit management circuit module 104, non-contact connections may be used to achieve the fast communications, including, for example, the differential capacitive coupling between the qubits and the passive transmission lines and magnetic coupling, both of which provide communication links without direct connections and allow for compensation of the geometric misalignments between the modules 102 and 104 and other components as a result of the fabrication process.

In the examples of two-state qubit circuits, quantum computing operations by qubit circuits or devices inside the quantum computing module 102 are different from a classical computer based on a deterministic Turing machine and Boolean bits of “0” and “1” binary qubit states and use quantum-mechanical phenomena such as superposition of binary “0"’ and “1” qubit states, entanglement between qubits, and interference between probability amplitudes of non-deterministic measurement outcomes to perform computing operations. Superconducting qubits inside the quantum computing module 102 can be implemented by superconducting Josephson junctions. A Josephson junction is a system consisting of weakly coupled superconductors exhibiting correlated, or coherent, states and behaves like anon- linear inductor which allows for building a quantum anharmonic oscillator. The two discrete energy level states of this anharmonic oscillator and their quantum superposition are used to create a qubit. Using Josephson junctions, several versions of superconducting qubits can be constructed, such as transmon, xmon, quantronim, fluxonium, etc.

The state of a qubit is controlled by applying a microwave signal to the qubit. In various implementations, the microwave signal generators may be room-temperature devices, whereas the quantum circuits comprising qubits operate at very low cryogenic temperatures in order to reduce undesired decoherence of qubits. Specifically, the wiring needed to provide microwave signals to qubit circuits may involve different segments maintained different temperatures from the room temperature to the lowest temperature at the cryogenic stage where a quantum circuit is situated, and thus may cause or introduce undesired electric noise, or excessive heat load. Such wiring for a significant number of qubit circuits may occupy a lot of space. Those factors can lead to undesired decoherence of qubit quantum states and pose a significant problem for scaling up the quantum computer. In order to overcome this problem, various techniques may be used to control the qubits in a fully integrated, cryogenic, hybrid quantum-classical processor as shown in FIGS. 6A-6E, including, for example, integration of superconducting qubits with classical superconducting digital logic families such as reciprocal-quantum-logic (RQL) as disclosed by Quentin P. Herr and Anna Y. Herr in “Ultra-low-power superconductor logic,” J. Appl. Phys. 109, 103903 (2011), use of adiabatic quantum-flux-parametrons (AQFP) by O. Chen, R. Cai, Y. Wang, F. Ke, T. Yamae, R. Saito, N. Takeuchi, and N. Yoshikawa in “Adiabatic Quantum- Flux-Parametron: Towards Building Extremely Energy-Efficient Circuits and Systems,” Sci. Rep. 9, 10514 (2019), or the use of single-flux quantum (SFQ) technology by O. A. Mukhanov in “Energy -Efficient Single Flux Quantum Technology,” IEEE Trans. Appl. Supercond. 21, 760 (2011). As part of the interconnection design for the systems in FIGS. 1 A-1E. the control of qubits can be implemented via an SFQ system to control the state of a qubit by applying a sequence of the SFQ pulses without the conventional use of micro wave signals as disclosed in U. S. Patent No. 9,425,804. Techniques for applying flux to a quantum-coherent superconducting circuit in the U.S. Patent Application Publication No. US 2015/0263736A1 may also be implemented. The readout of qubits may be implemented by quantum electrodynamics measurements disclosed in U. S. Patent No. 9,692,423. Cryogenic CMOS (cryoCMOS) techniques may also be implemented in the systems in FIGS. 1 A-1E, e.g. for controlling superconducting qubits. See E. Charbon, F. Sebastiano, A. Vladimirescu, H. Homulle, S. Visser, L. Song, and R. M. Incandela. “Cryo-CMOS for quantum computing”, Technical Digest - International Electron Devices Meeting, IEDM (2017), pp. 1-13. doi: 10.1 109/IEDM.2016.7838410, and J. C. Bardin, E. Jeffrey, E. Lucero, T. Huang, O. Naaman, R. Barends, T. White, M. Giustina, D. Sank, P. Roushan, K. An a. B. Chiaro, J. Kelly, J. Chen, B. Burkett, Y. Chen, A. Dunsworth, A. Fowler, B. Foxen, C. Gidney. R. Graff, P. Klimov, J. Mutus, M. McEwen, A. MegranL M. Neeley, C. Neill. C. Quintana, A. Vainsencher, H. Neven, and J. Martinis. “A 28nm Bulk-CMOS 4-to-8GHz 2mW Cryogenic Pulse Modulator for Scalable Quantum Computing”, IEEE J. Solid-St. Circuits 54, 3043- 3060 (2019). Those references are incorporated by reference as part of the disclosure of this patent document.

Practical implementations of the systems in FIGS. 6A-6E require careful designs for the interconnections or interface between the quantum circuits of the quantum computing module 102 situated at a low cry ogenic temperature (e.g., a certain millikelvin temperature) and classical processing circuits situated at higher temperatures (including the liquid helium temperature). The interconnections in the example in FIG. 6E include placing the quantum computing module 102 and the quantum bit management circuit module 104 next to each other on the same cryogenic stage of the dilution refrigerator without using any superconducting cables or wires 150 between the modules 102 and 104. Instead, superconducting bumps or pads 140 are used to physically join or bind the two modules 102 and 104 together. The signal paths between the two modules 102 and 104 can be implemented in various ways, include signaling via conductive paths formed though the superconducting bumps or pads 140 between the modules 102 and 104, or signaling via capacitive and/or magnetic coupling between the modules 102 and 104. The signal paths between the two modules 102 and 104 are designed to minimize the signal transmission time (e.g., by reducing or eliminating the amount wiring between the modules 102 and 104) and to form the fast communication links or loops in the system as explained above with respect to FIG. 6A.

In implementations where the two modules 102 and 104 are supported by two IC chips, the two chips may be stacked over each other and bonded to form a multichip module (MCM) which is, as an integrated unit, coupled to the same low temperature cryogenic stage so both modules 102 and 104 are operated under the same low cryogenic temperature. Superconducting bumps or pads 140 may be used as part of the binding of the two IC chips or modules 102 and 104. The interconnections in the example in FIG. IE also implements combinations of superconducting bumps or pads 140 and superconducting cables or wires 150 where the superconducting bumps or pads 140 are used at terminals of the superconducting cables or wires 150 for connecting the wire terminals to devices. For example, in FIG. 6E, the quantum bit management circuit module 104 is shown to be connected to an interconnection circuitry or module 106 such as a digital signal conditioning circuit module via superconducting cables or wires 150 where two sets of superconducting bumps or pads 140 are used to join the two end terminals of each superconducting cable or wire 150 to the contacting points on the quantum bit management circuit module 104 and the corresponding interconnection circuitry or module 106. This use of superconducting bumps or pads 140 and superconducting cables or wires 150 can be applied to connections for other modules such as the connection between the digital processing module 108 and a corresponding interconnection circuitry or module 106 and a connection between different stages or digital signal conditioning circuit modules of the interconnection circuitry or module 106. As illustrated, such superconducting cables or wires 150 with superconducting bumps or pads 140 constitute part of the medium communication links and loops as explained above with respect to FIG. 6A. In the above examples of hybrid quantum-classical computing systems in FIGS. 6A through IE, the classical digital processing modules 108 and 109 may be implemented to include various classical digital processors such as central processing unit (CPU) processors, field-programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), and graphics processing unit (GPU) processors to share and to collaborate with the quantum computing in the quantum computing module 102 of the QPU system.

FIG. 7 illustrate an example of a 3D SQIF SFNS sensor module with 3 magnetic sensors to measure components of a magnetic field in three different directors as a 3-D magnetic sensor or detector module. Three separate Superconducting Quantum Interference Filter (SQIF) magnetic sensors are used to detect the Bx, By and Bz fields of a magnetic field B along the three orthogonal directions X. Y and Z. Referring to FIGS. 6A-6E, this 3-D magnetic sensor module can be installed in the vicinity of a superconducting chip mounted on a particular temperature stage of the cryostat. In one implementation, for example, the sensors may be attached to printed circuit boards (PCBs) which are then mounted on a 3D printed frame as a 3-D magnetic sensor module. Such 3-D magnetic sensor modules are installed on or in the close proximity to the superconducting chips. The purpose of these 3-D detectors is to measure magnetic field on each temperatures stage next to the mounted superconducting data processing chips to ensure the minimization of the residual magnetic field and magnetic flux trapping in the data processing chips.

FIGS. 8 and 9 show examples of the installation of 3-D magnetic sensor modules in the quantum computer systems shown in FIGS. 6A and 6B, respectively.

While this patent document contains many specifics, these should not be construed as limitations on the scope of any subject matter or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular techniques. Certain features that are described in this patent document in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

Only a few embodiments and their implementations and examples of the disclosed technology are described, enhancements and variations of the disclosed embodiments and other embodiments can be made based on what is described and illustrated in this patent document.

Claims

Claims What is claimed is what is disclosed and/or illustrated, including:

1. A superconducting device, comprising: a magnetic sensor for sensing a magnetic field that includes a multilayer structure that includes at least one magnetic layer and at least one non-magnetic layer; and two superconducting electrodes coupled to the multilayer structure so that the multilayer structure and the two superconducting electrodes transmit a current through the multilayer structure.

2. The device as in claim 1, wherein the one magnetic layer of the multilayer structure includes a ferromagnetic material that includes Fe, Co, or Ni, or an alloy of a ferromagnetic material with a non-magnetic metal material that includes Pd, Cu or Pt.

3. The device as in claim 1, wherein the one non-magnetic layer of the multilayer structure includes a metal including Al, Ag, Au, Cu, Pt, Hf, Nb, Ti, Ta, V, or W.

4. The device as in claim 1, wherein the two superconducting electrodes include Nb, NbN. MoGe, MgEh. or a Yttrium barium copper oxide that includesYBa2Cu3O7-x.

5. The device as in claim 1, further comprising a cantilever that includes a cantilever tip on which the magnetic sensor is located, and a scanning mechanism coupled to the cantilever to move the cantilever to scan the magnetic sensor over a sample for measuring the sample.

6. A superconducting quantum interference device, comprising: a superconducting loop comprising a first superconducting layer, a second superconducting layer, and at least one Josephson junction formed between the first superconducting layer and the second superconducting layer; and a multilayer stack situated inside the superconducting loop and structured to include at least one magnetic layer and at least one non-magnetic layer.

7. The device as in claim 6, wherein the one magnetic layer of the multilayer stack includes a ferromagnetic material that includes Fe, Co, or Ni, or an alloy of a ferromagnetic material with a non-magnetic metal material that includes Pd, Cu or Pt.

8. The device as in claim 6, wherein the one non-magnetic layer of the multilayer stack includes a metal including Al, Ag, Au, Cu, Pt. Hf. Nb, Ti. Ta. V, or W.

9. A system capable of information processing based on both quantum computing using different quantum states of quantum bits and classical digital computing using digital processors, comprising: a cryostat system structured to include different cryogenic stages operable to provide a low cryogenic temperature and higher cryogenic temperatures; a quantum computing module enclosed by the cryostat system at the low cryogenic temperature and structured to include different quantum bit circuits that exhibit different quantum states and perform quantum computing operations; a quantum bit management circuit module enclosed by the cryostat system, located adjacent to the quantum computing module to include quantum bit control circuits that direct control signals to control the quantum bit circuits of the quantum computing module, and quantum bit readout circuits that respectively interact with and output readout signals indicative of quantum states of the quantum bit circuits, respectively, from, the quantum bit circuits; and a plurality of superconducting magnetic sensors enclosed by the cry ostat system and located within the different cry ogenic stages, each superconducting magnetic sensor structured to sense a local magnetic field.

10. The system as in claim 9, wherein each superconducting magnetic sensor includes a Superconducting Quantum Interference Filter.

11. The system as in claim 9, wherein each superconducting magnetic sensor includes a Josephson junction that comprises two or more superconductive electrodes and a multilayer structure that includes alternative magnetic and non-magnetic layers.

12. The system as in claim 9, wherein: the quantum computing module includes a first integrated chip structured to support the quantum bit circuits, wherein each quantum bit circuit is structured as a superconducting circuit at the low cryogenic temperature to exhibit different quantum states as a quantummechanical system and to quantum-mechanically interact with other quantum bit circuits via quantum entanglement to cause superposition or correlation of different quantum states of the quantum bit circuits; and the quantum bit management circuit module is supported by a second integrated chip which is engaged to the first integrated chip to form a multichip module to transfer control signals and readout signals therebetween.

13. The system as in claim 9, further comprising one or more additional quantum computing modules enclosed by the cryostat system at the low cryogenic temperature, wherein each quantum computing module is structured to include different quantum bit circuits that perform quantum computing operations.

14. The system as in claim 9, further comprising: hierarchical circuit modules enclosed by the cryostat system at the higher cryogenic temperatures and structured to communicate with the quantum bit management circuit module in connection with the control signals and readout signals, wherein the hierarchical circuit modules are structured to include hierarchical quantum error correction decoding and hybrid quantum-classical co-processing circuit modules exhibiting increasing processing latencies and increasing decoding complexity levels along a direction of the different cryogenic stages as the different higher cry ogenic temperatures increase.

15. The system as in claim 9, wherein the superconducting magnetic sensors includes a superconducting magnetic sensor that includes a multilayer structure that includes at least one magnetic layer and at least one non-magnetic layer; and two superconducting electrodes coupled to the multilayer structure so that the multilayer structure and the two superconducting electrodes transmit a current through the multilayer structure.

16. The system as in claim 15, wherein the one magnetic layer of the multilayer structure includes a ferromagnetic material that includes Fe, Co, or Ni, or an alloy of a ferromagnetic material with a non-magnetic metal material that includes Pd, Cu or Pt.

17. The system as in claim 15, wherein the one non-magnetic layer of the multilayer structure includes a metal including Al, Ag, Au. Cu, Pt. Hf. Nb, Ti. Ta. V, or W.

18. The system as in claim 14, wherein the two superconducting electrodes include Nb, NbN, MoGe, MgEh. or a Yttrium barium copper oxide that includesYBa2Cu3O7-x.