WO2025002283A1 - 显示处理系统和电子设备 - Google Patents

显示处理系统和电子设备 Download PDF

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Publication number
WO2025002283A1
WO2025002283A1 PCT/CN2024/102109 CN2024102109W WO2025002283A1 WO 2025002283 A1 WO2025002283 A1 WO 2025002283A1 CN 2024102109 W CN2024102109 W CN 2024102109W WO 2025002283 A1 WO2025002283 A1 WO 2025002283A1
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WO
WIPO (PCT)
Prior art keywords
switch
integrated circuit
image processing
display
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2024/102109
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English (en)
French (fr)
Inventor
单昌鹏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Vivo Mobile Communication Co Ltd
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Vivo Mobile Communication Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vivo Mobile Communication Co Ltd filed Critical Vivo Mobile Communication Co Ltd
Priority to EP24830915.5A priority Critical patent/EP4738325A1/en
Publication of WO2025002283A1 publication Critical patent/WO2025002283A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/1423—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/005—Adapting incoming signals to the display format of the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/04—Display device controller operating with a plurality of display units
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit

Definitions

  • the present application belongs to the field of communication technology, and specifically relates to a display processing system and an electronic device.
  • the resolution of the display screen of most electronic devices is greater than the resolution supported by the display driver chip (DDIC), so at least two DDICs need to be connected in series.
  • DDIC display driver chip
  • the image processing chip can usually only be interconnected with one DDIC. Therefore, the electronic device cannot realize the coexistence of the image processing chip and multiple DDICs, so that the final display quality cannot reach the best.
  • the purpose of the embodiments of the present application is to provide a display processing system and an electronic device, which can solve the problem that the display quality of the electronic device cannot reach the best.
  • an embodiment of the present application provides a display processing system, including:
  • An image processing integrated circuit at least two display driver integrated circuits, and a bridge integrated circuit connecting the image processing integrated circuit and the at least two display driver integrated circuits;
  • the bridge integrated circuit is used for cropping the first display data output by the image processing integrated circuit, and transmitting each of the plurality of second display data obtained after cropping to one of the display driver integrated circuits.
  • an embodiment of the present application provides an electronic device, comprising the display processing system as described in the first aspect.
  • the bridge integrated circuit of the display processing system can crop the first display data output by the image processing integrated circuit, and then transmit each of the plurality of second display data obtained after cropping to one of the display driver integrated circuits, so that the image processing circuit and the plurality of display driver integrated circuits coexist, which not only ensures the maximum application of the resolution supported by the display screen, but also enables the display data to be processed by the image, thereby achieving the best display quality.
  • FIG1 is a schematic diagram of a display processing system according to an embodiment of the present application.
  • FIG2 is a second schematic diagram of a display processing system according to an embodiment of the present application.
  • FIG3 is a third schematic diagram of a display processing system according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of the structure of an electronic device according to an embodiment of the present application.
  • first, second, etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first”, “second”, etc. are generally of one type, and the number of objects is not limited.
  • the first object can be one or more.
  • “and/or” in the specification and claims represents at least one of the connected objects, and the character “/" generally indicates that the objects associated with each other are in an "or” relationship.
  • a display processing system includes:
  • An image processing integrated circuit at least two display driver integrated circuits, and a bridge integrated circuit connecting the image processing integrated circuit and the at least two display driver integrated circuits;
  • the bridge integrated circuit is used for cropping the first display data output by the image processing integrated circuit, and transmitting each of the plurality of second display data obtained after cropping to one of the display driver integrated circuits.
  • the display processing system of the embodiment of the present application because the bridge integrated circuit can crop the first display data output by the image processing integrated circuit, and then transmit each of the multiple second display data obtained after cropping to one of the display driver integrated circuits, enables the coexistence of the image processing circuit and multiple display driver integrated circuits, which not only ensures the maximum application of the resolution supported by the display screen, but also enables the display data to be processed by the image, thereby achieving the best display quality.
  • the image processing integrated circuit is also called an image processing chip
  • the bridge integrated circuit is also called a bridge chip (Mobile Industry Processor Interface, MIPI)
  • the display driver integrated circuit is also called a display driver chip (DDIC).
  • the display processing system further includes:
  • a main control integrated circuit connected to the image processing integrated circuit.
  • the main control integrated circuit (also called the main control chip) can pre-process the source display data and then transmit it to the image processing integrated circuit for subsequent processing.
  • the receiving end of the main control integrated circuit is connected to the camera of the electronic device using the display processing system of the present application, and after the content captured by the camera is directly transmitted to the main control integrated circuit for preprocessing, the main control integrated circuit transmits the preprocessed captured content to the image processing integrated circuit.
  • the receiving end of the main control integrated circuit can also receive source display data other than the content captured by the camera.
  • the bridge integrated circuit includes a decoding component, a storage component and a cutting component;
  • the decoding component is used to decode the first display data
  • the storage component is used to store the decoded first display data
  • the cropping component is used to crop the decoded first display data.
  • the bridge integrated circuit can decode the first display data through the decoding component and store it through the storage component.
  • the cropping component can directly crop the first display data decoded by the decoding component, or extract the decoded first display data from the storage component for cropping.
  • each of the at least two display driver integrated circuits drives a different display area.
  • the display processing system includes two display driver integrated circuits, which are used to drive the left screen and the right screen of the display screen respectively.
  • the bridge integrated circuit of the display processing system After receiving the first display data, the bridge integrated circuit of the display processing system cuts it into left half screen and right half screen data, and then transmits it to the two display driver integrated circuits, thereby achieving high-quality display of the first display data on the display screen.
  • the first receiving end of the image processing integrated circuit is connected to the first transmitting end of the main control integrated circuit
  • the second receiving end of the image processing integrated circuit is connected to the second transmitting end of the main control integrated circuit
  • the first transmitting end of the image processing integrated circuit is connected to the first receiving end of the bridge integrated circuit
  • the second transmitting end of the image processing integrated circuit is connected to the first receiving end of the main control integrated circuit.
  • the content captured by the camera of the electronic device using the display processing system of the present application is recorded as the first type of source display data
  • other source display data is recorded as the second type of source display data.
  • the main control integrated circuit will transmit different types of source display data to the image processing integrated circuit through different ports.
  • the image processing integrated circuit can output the first display data to the bridge integrated circuit through the first transmitting end on the one hand, and can also output the fifth display data to the main control integrated circuit through the second transmitting end on the other hand.
  • the fifth display data is data obtained by processing the first type of source display data by the image processing chip, so as to ensure that the display of the screenshot or screen recording image output by the main control integrated circuit is consistent with what the user sees when shooting.
  • the image processing integrated circuit includes:
  • a first selection circuit a data processing component, and a second selection circuit
  • the first selection circuit is used to transmit the third display data to the first transmitting end of the image processing integrated circuit or the data processing component, and the third display data includes data received by at least one of the first receiving end and the second receiving end of the image processing integrated circuit;
  • the data processing component is used for performing corresponding data processing on the third display data according to the processing requirements of the third display data;
  • the second selection circuit is used to transmit the fourth display data output by the data processing component to the first sending end or the second sending end of the image processing integrated circuit.
  • data received by at least one of the first receiving end and the second receiving end of the image processing integrated circuit can be directly output to the bridge integrated circuit through the first selection circuit; or the data can be transmitted to the data processing component through the first selection circuit, and then processed according to corresponding processing requirements, and then output to the bridge integrated circuit or the main control integrated circuit through the second selection circuit.
  • the fourth display data is the first display data; if the fourth display data is transmitted to the second transmitting end of the image processing integrated circuit, the fourth display data is the fifth display data.
  • the data processing component supports at least one of the following processes:
  • the data processing supported by the data processing component is not limited to the above-mentioned processing contents, which will not be listed one by one here.
  • the processing requirement is used to indicate what processing the data processing component needs to perform.
  • different types of display data have different processing requirements, such as the second type of source display data does not require noise reduction.
  • the first selection circuit includes a first switch and a second switch
  • first end of the first switch is connected to the first receiving end of the image processing integrated circuit, and the second end of the first switch is connected to the first transmitting end of the image processing integrated circuit;
  • the first end of the second switch is connected to the first receiving end of the image processing integrated circuit
  • the second end of the second switch is connected to the second receiving end of the image processing integrated circuit
  • the third end of the second switch is connected to the input end of the data processing component.
  • the first switch can be used to control whether the data is transmitted to the first transmitting end of the image processing integrated circuit; on the other hand, the second switch can be used to control whether the data is transmitted to the data processing component of the image processing integrated circuit.
  • the second switch can also be used to control whether the data is transmitted to the data processing component of the image processing integrated circuit.
  • the second selection circuit includes a third switch and a fourth switch
  • the first end of the third switch is connected to the third end of the fourth switch, and the second end of the third switch is connected to the first transmitting end of the image processing integrated circuit;
  • a first end of the fourth switch is connected to the output end of the data processing component, and a second end of the fourth switch is connected to the second transmitting end of the image processing integrated circuit.
  • the fourth switch can be used to control whether the data is transmitted to the second transmitting end of the image processing integrated circuit or to the first end of the third switch; on the other hand, the third switch can be used to control whether the data is transmitted to the first transmitting end of the image processing integrated circuit.
  • the first switch when the first switch is closed, the second switch is opened and the first end of the second switch is connected to the third end, the third switch is opened, the fourth switch is opened and the first end of the fourth switch is connected to the third end, the data received by the first receiving end of the image processing integrated circuit is transmitted to the data processing component through the second switch, and then transmitted to the first sending end of the image processing integrated circuit via the data processing component, the fourth switch and the third switch in sequence, and is sent from the first sending end of the image processing integrated circuit to the bridge integrated circuit.
  • the first switch when the first switch is turned on, the second switch is turned off, the third switch is turned off, and the fourth switch is turned off, data received by the first receiving end of the image processing integrated circuit is transmitted to the first transmitting end of the image processing integrated circuit through the first switch, and is sent by the first transmitting end of the image processing integrated circuit to the bridge integrated circuit.
  • the first switch when the first switch is turned off, the second switch is turned on and the second end of the second switch is connected to the third end, and the third switch is turned off, the fourth switch is turned on and the first end of the fourth switch is connected to the second end, the data received by the second receiving end of the image processing integrated circuit is transmitted to the data processing component through the second switch, and then transmitted to the second sending end of the image processing integrated circuit via the data processing component and the fourth switch in sequence, and is sent from the second sending end of the image processing integrated circuit to the main control integrated circuit.
  • the main control integrated circuit can transmit the data processed by the image processing integrated circuit to the first receiving end of the image processing integrated circuit.
  • the first switch is turned on and the second switch is turned off, and the first receiving end of the image processing integrated circuit is connected to the first transmitting end of the image processing integrated circuit via the first switch, so that the data received by the first receiving end of the image processing integrated circuit is output through analog bypass in the image processing integrated circuit, and finally transmitted from the first transmitting end of the image processing integrated circuit to the bridge chip.
  • the third switch can also be a single-pole double-throw switch, whose fixed end is connected to the first transmitting end of the image processing integrated circuit, whose first active end is connected to the third end of the fourth switch, and whose second active end is connected to the second end of the first switch, so as to realize the transmission of data output by the data processing component of the image processing integrated circuit or data received by the first receiving end of the image processing integrated circuit to the first transmitting end of the image processing integrated circuit through the control of the third switch.
  • the second selection circuit further includes a fifth switch and a sixth switch
  • a first end of the fifth switch is connected to the output end of the data processing component, and a second end of the fifth switch is connected to the first transmitting end of the image processing integrated circuit;
  • the first end of the sixth switch is connected to the output end of the data processing component, and the second end of the sixth switch is connected to the second sending end of the image processing integrated circuit.
  • the sixth switch can be used to control whether the data is transmitted to the second transmitting end of the image processing integrated circuit; on the other hand, the fifth switch can be used to control whether the data is transmitted to the first transmitting end of the image processing integrated circuit.
  • the data received by the second receiving end of the image processing integrated circuit is transmitted to the data processing component through the second switch, and then transmitted to the first transmitting end of the image processing integrated circuit via the data processing component and the fifth switch in sequence, and then sent from the first transmitting end of the image processing integrated circuit to the bridge integrated circuit.
  • the data output by the data processing component can also be sent to the main control integrated circuit via the second sending end of the image processing integrated circuit.
  • the data output by the data processing component will be transmitted to the second sending end of the image processing integrated circuit through the sixth switch, and then sent to the main control integrated circuit.
  • the data processed by the data processing component needs to be stored in the storage space through the main control integrated circuit.
  • the first switch when the first switch is turned on, the second switch is turned off, the fifth switch is turned off, and the sixth switch is turned off, data received by the first receiving end of the image processing integrated circuit is transmitted to the first transmitting end of the image processing integrated circuit through the first switch, and is sent by the first transmitting end of the image processing integrated circuit to the bridge integrated circuit.
  • the fifth switch can also be a single-pole double-throw switch, whose fixed end is connected to the first transmitting end of the image processing integrated circuit, whose first active end is connected to the output end of the data processing component, and whose second active end is connected to the second end of the first switch, so as to realize the transmission of data output by the data processing component of the image processing integrated circuit or data received by the first receiving end of the image processing integrated circuit to the first transmitting end of the image processing integrated circuit through the control of the seventh switch.
  • FIG. 2 and FIG. 3 The specific structure implementation of the display processing system of the embodiment of the present application is described below using FIG. 2 and FIG. 3 as examples:
  • FIG. 2 and FIG. 3 only part of the camera serial interface transmitter (Camera Serial Interface Transmition, CSI-TX) and part of the camera serial interface receiver (Camera serial interface Receiver, CSI-RX), as well as part of the display serial interface transmitter (Display Serial Interface Transmition, DSI-TX) and part of the display serial interface receiver (Display serial interface Receiver, DSI-RX) are illustrated, and the DSI-TX, DSI-RX, CSI-TX and CSI-RX of each integrated circuit are not limited to those shown in the figure.
  • DDIC1 and DDIC2 are set in the display processing system.
  • CSI-TX1 the second transmitting end of the image processing integrated circuit
  • CSI-RX1 the first receiving end of the main control integrated circuit
  • CSI-TX2 the output end of the camera
  • CSI-RX2 the second receiving end of the main control integrated circuit
  • DSI-TX3 the first transmitting end of the main control integrated circuit
  • DSI-TX4 the second transmitting end of the main control integrated circuit
  • DSI-RX4 the second receiving end of the image processing integrated circuit
  • DSI-TX5 the first transmitting end of the image processing integrated circuit
  • DSI-RX5 the first receiving end of the bridge integrated circuit
  • DSI-TX6 the first transmitting end of the bridge integrated circuit
  • DSI-RX6 the receiving end of DDIC1
  • DSI-TX7 the second transmitting end of the bridge integrated circuit
  • DSI-RX7 the receiving end of DDIC1
  • the display content (the first display data output) processed by the image processing chip is transmitted to the bridge chip (such as the Mobile Industry Processor Interface (MIPI) bridge chip) through TX5.
  • the bridge chip such as the Mobile Industry Processor Interface (MIPI) bridge chip
  • MIPI Mobile Industry Processor Interface
  • Switch 4 the fourth switch. Select to be connected with switch 3 or CSI-TX1; Switch 5: the fifth switch.
  • the display content (the first display data output) processed by the image processing chip is transmitted to the MIPI bridge chip through TX5.
  • the switches are all single-pole single-throw switches.
  • DSI-TX3 mainly transmits the second type of source display data
  • DSI-TX4 mainly transmits the first type of source display data.
  • the main control chip transmits the content to be displayed on the display screen (the second type of source display data) to the DSI-RX3 of the image processing chip through the DSI-TX3 of the main control chip.
  • switch 1 is closed and switch 2 is turned on.
  • the DSI-RX3 of the image processing chip transmits the display content to the data processing component inside the image processing chip.
  • the data processing component can choose to perform super-resolution, interpolation and high-dynamic range (HDR) processing on the data according to the processing requirements (which can be scene-defined).
  • HDR processing screen will have better contrast and color display effects.
  • both switches 3 and 4 are turned on, and the display content processed by the image processing chip is connected to switch 3 through switch 4.
  • switch 3 After switch 3 is turned on, it is transmitted to the DSI-RX5 of the MIPI bridge chip through DSI-TX5.
  • the MIP bridge chip will crop the received display content into left and right half-screen data.
  • the data of the left half screen is transmitted to DDIC1 through DSI-TX6, and the data of the right half screen is transmitted to DDIC 2 through DSI-TX7. After being processed by DDIC1 and DDIC 2, the data is displayed on the display screen.
  • the main control chip transmits the content to be displayed on the display screen (second type of source display data) to the DSI-RX3 of the image processing chip through the DSI-TX3 of the main control chip.
  • switches 2, 3 and 4 are closed, and switch 1 is opened.
  • the display content is transmitted to the analog bypass path inside the image processing chip through the DSI-RX3 of the image processing chip, and then transmitted to the DSI-RX5 of the MIPI bridge chip through DSI-TX5.
  • the MIPI bridge chip will crop the received display content into left and right half-screen data.
  • the left half-screen data is transmitted to DDIC1 through DSI-TX6, and the right half-screen data is transmitted to DDIC2 through DSI-TX7.
  • the data After being processed by DDIC1 and DDIC 2, the data is displayed on the display screen.
  • the main control chip can also use a similar method to realize the display of the first type of source display data on the display screen.
  • the video and pictures (first type of source display data) taken by the camera are transmitted to the main control chip through CSI-TX2, and the main control chip transmits the received video and pictures to the image processing chip DXI-RX4 through DSI-TX4.
  • switch 1 is closed, switch 2 is turned on and connected to the image processing chip DXI-RX4, and the content shot by the mobile phone is transmitted to the internal data processing component of the image processing chip.
  • the captured content can be processed by noise reduction, frame insertion, and HDR. After passing through the data processing component, the content shot at night will become clearer.
  • switch 4 is turned on and connected to the image processing chip CSI-TX1.
  • the captured content processed by the image processing chip is transmitted to the CSI-RX1 of the main control chip through CSI-TX1, and the main control chip transmits the video and pictures processed by the image processing chip to the DSI-RX3 of the image processing chip through the DSI-TX3 of the main control chip.
  • switch 1 is turned on
  • switch 2 is turned off
  • switch 3 is turned off.
  • the DSI-RX3 of the image processing chip and the analog bypass inside the image processing chip are transmitted to the DSI-RX5 of the MIPI bridge chip through the image processing chip DSI-TX5.
  • the MIPI bridge chip will crop the received display content into left and right half-screen data.
  • the left half-screen data is transmitted to DDIC1 through DSI-TX6, and the right half-screen data is transmitted to DDIC2 (display driver chip 2) through DSI-TX7.
  • DDIC1 and DDIC2 After being processed by DDIC1 and DDIC2, it is displayed in real time on the display screen, realizing what you see is what you get.
  • the CSI-RX1 of the main control chip receives the video or picture processed by the image processing chip.
  • the main control chip can choose to store the processed video or picture in the storage space for later viewing.
  • the content captured by screenshots or screen recordings also undergoes noise reduction by the independent graphics card, solving the problem of no noise reduction in the screenshots or screen recordings when users take photos.
  • Scene 4 as shown in Figure 3, the video and pictures (first type of source display data) taken by the camera are transmitted to the main control chip through CSI-TX2, and the main control chip transmits the received video and pictures to the image processing chip DXI-RX4 through DSI-TX4.
  • switch 1 is closed, switch 2 is opened and connected to the image processing chip DXI-RX4, and the content shot by the mobile phone is transmitted to the internal data processing component of the image processing chip.
  • the internal projection of the shot can be selected for noise reduction, frame insertion, and HDR processing. After these processes, the content shot at night will become clearer.
  • switch 6 is closed, switch 5 is opened, and the image processed by the image processing chip is transmitted to the DSI-RX5 of the MIPI bridge chip through the image processing chip DSI-TX5.
  • the MIPI bridge chip will crop the received display data into left and right half-screen data.
  • the left half-screen data is transmitted to DDIC1 through DSI-TX6, and the right half-screen data is transmitted to DDIC2 through DSI-TX7.
  • DDIC After being processed by DDIC, it is displayed in real time on the display screen, that is, what you see is what you get.
  • switch 6 is turned on, and the content processed by the image processing chip is transmitted to CSI-RX1 of the main control chip through CSI-TX1.
  • the main control chip stores the processed image data in the storage space for later viewing.
  • Scene 5 The video and pictures (first type of source display data) taken by the camera are transmitted to the main control chip through CSI-TX2, and the main control chip transmits the received video and pictures to the image processing chip DXI-RX3 through DSI-TX3.
  • switches 2, 5, and 6 are closed, and switch 1 is turned on and connected to the image processing chip DXI-RX3, and the content shot by the mobile phone is transmitted to the analog bypass inside the image processing chip, and then transmitted to the DSI-RX5 of the MIP bridge chip through the image processing chip DSI-TX5.
  • the MIPI bridge chip will crop the received display data into left and right half-screen data.
  • the left half-screen data is transmitted to DDIC1 through DSI-TX6, and the right half-screen data is transmitted to DDIC2 through DSI-TX7.
  • DDIC After being processed by DDIC, it is displayed in real time on the display screen.
  • the main control chip can also choose to store the video or pictures taken by the camera in the storage space for later viewing.
  • a similar method can also be used to realize the display of the second type of source display data on the display screen.
  • the main control chip transmits the content to be displayed on the display screen (second type of source display data) to the DSI-RX3 of the image processing chip through the DSI-TX3 of the main control chip.
  • switch 1 is closed and switch 2 is opened.
  • the DSI-RX3 of the image processing chip transmits the display content to the data processing component inside the image processing chip.
  • the data processing component can choose to perform super-resolution, interpolation and HDR processing on the data according to the processing requirements (which can be scene-defined). The processed data will become clearer, the video will become smoother, and the HDR processing screen contrast and color display effect will be better.
  • switch 5 is turned on and switch 6 is turned off.
  • the display content processed by the image processing chip is transmitted to the DSI-RX5 of the MIPI bridge chip through switch 5 DSI-TX5.
  • the MIP bridge chip will crop the received display content into left and right half-screen data.
  • the data of the left half-screen is transmitted to DDIC1 through DSI-TX6, and the data of the right half-screen is transmitted to DDIC 2 through DSI-TX7. After being processed by DDIC1 and DDIC 2, the data is displayed on the display screen.
  • the video interpolation, video super-resolution, HDR processing and other functions of the independent image processing integrated circuit can be used, and the pictures and videos taken by the camera have better clarity and better user experience after noise reduction and super-resolution processing.
  • An embodiment of the present application also provides an electronic device, comprising the display processing system as described above.
  • the electronic device may be a terminal or other device other than a terminal.
  • the electronic device may be a mobile phone, a tablet computer, a laptop computer, a PDA, a vehicle-mounted electronic device, a mobile Internet device (MID), an augmented reality (AR)/virtual reality (VR) device, a robot, a wearable device, an ultra-mobile personal computer (UMPC), a netbook or a personal digital assistant (PDA), etc.
  • It may also be a server, a network attached storage (NAS), a personal computer (PC), a television (TV), a teller machine or a self-service machine, etc., and the embodiments of the present application are not specifically limited.
  • the display screen of this electronic device is a folding screen.
  • the electronic device provided in the embodiment of the present application can implement each process implemented by the display processing system embodiment of Figures 1 to 3, and will not be described again here to avoid repetition.
  • FIG. 4 is a schematic diagram of the hardware structure of an electronic device implementing an embodiment of the present application.
  • the electronic device 400 includes but is not limited to components such as a radio frequency unit 401 , a network module 402 , an audio output unit 403 , an input unit 404 , a sensor 405 , a display unit 406 , a user input unit 407 , an interface unit 408 , a memory 409 , and a processor 410 .
  • the electronic device 400 may also include a power source (such as a battery) for supplying power to each component, and the power source may be logically connected to the processor 410 through a power management system, so that the power management system can manage charging, discharging, and power consumption.
  • a power source such as a battery
  • the electronic device structure shown in FIG4 does not constitute a limitation on the electronic device, and the electronic device may include more or fewer components than shown, or combine certain components, or arrange components differently, which will not be described in detail here.
  • the electronic device also includes the display processing system as described above.
  • the input unit 404 may include a graphics processing unit (GPU) 4041 and a microphone 4042, and the graphics processor 4041 processes the image data of the static picture or video obtained by the image capture device (such as a camera) in the video capture mode or the image capture mode.
  • the display unit 406 may include a display panel 4061, and the display panel 4061 may be configured in the form of a liquid crystal display, an organic light emitting diode, etc.
  • the user input unit 407 includes a touch panel 4071 and at least one of other input devices 4072.
  • the touch panel 4071 is also called a touch screen.
  • the touch panel 4071 may include two parts: a touch detection device and a touch controller.
  • Other input devices 4072 may include, but are not limited to, a physical keyboard, function keys (such as a volume control key, a switch key, etc.), a trackball, a mouse, and a joystick, which will not be repeated here.
  • the memory 409 can be used to store software programs and various data.
  • the memory 409 may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, an application program or instructions required for at least one function (such as a sound playback function, an image playback function, etc.), etc.
  • the memory 409 may include a volatile memory or a non-volatile memory, or the memory 409 may include both volatile and non-volatile memories.
  • the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory.
  • the volatile memory may be a random access memory (RAM), a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDRSDRAM), an enhanced synchronous dynamic random access memory (ESDRAM), a synchronous link dynamic random access memory (SLDRAM) and a direct memory bus random access memory (DRRAM).
  • the memory 409 in the embodiment of the present application includes but is not limited to these and any other suitable types of memory.
  • the processor 410 may include one or more processing units; optionally, the processor 410 integrates an application processor and a modem processor, wherein the application processor mainly processes operations related to an operating system, a user interface, and application programs, and the modem processor mainly processes wireless communication signals, such as a baseband processor. It is understandable that the modem processor may not be integrated into the processor 410.
  • main control chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.
  • the technical solution of the present application can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM/RAM, a disk, or an optical disk), and includes a number of instructions for a terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present application.
  • a storage medium such as ROM/RAM, a disk, or an optical disk
  • a terminal which can be a mobile phone, a computer, a server, or a network device, etc.

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Abstract

本申请公开了一种显示处理系统和电子设备，属于通信技术领域。本申请的显示处理系统包括：图像处理集成电路、至少两个显示驱动集成电路以及连接所述图像处理集成电路和所述至少两个显示驱动集成电路的桥接集成电路；其中，所述桥接集成电路用于对所述图像处理集成电路输出的第一显示数据进行裁剪，并将经裁剪所得的多个第二显示数据中的每个所述第二显示数据传输至一个所述显示驱动集成电路。

Description

显示处理系统和电子设备
相关申请的交叉引用
本申请要求在2023年6月30日提交中国专利局、申请号为202310801219.0、名称为“显示处理系统和电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请属于通信技术领域，具体涉及一种显示处理系统和电子设备。
背景技术
目前，大多电子设备的显示屏的分辨率大于显示驱动芯片(Display Driver Integrated Circuit，DDIC)支持的分辨率，故，需要将至少两个DDIC串联使用。
然而，图像处理芯片往往仅能与一个DDIC互联，因此，电子设备无法实现图像处理芯片和多个DDIC的共存，使得最终显示的质量不能达到最佳。
发明内容
本申请实施例的目的是提供一种显示处理系统和电子设备，能够解决电子设备显示的质量不能达到最佳的问题。
第一方面，本申请实施例提供了一种显示处理系统，包括：
图像处理集成电路、至少两个显示驱动集成电路以及连接所述图像处理集成电路和所述至少两个显示驱动集成电路的桥接集成电路；
其中，所述桥接集成电路用于对所述图像处理集成电路输出的第一显示数据进行裁剪，并将经裁剪所得的多个第二显示数据中的每个所述第二显示数据传输至一个所述显示驱动集成电路。
第二方面，本申请实施例提供了一种电子设备，包括如第一方面所述的显示处理系统。
在本申请实施例中，显示处理系统的桥接集成电路能够对所述图像处理集成电路输出的第一显示数据进行裁剪，然后将经裁剪所得的多个第二显示数据中的每个所述第二显示数据传输至一个所述显示驱动集成电路，使得图像处理电路和多个显示驱动集成电路的共存，不仅保证了显示屏所支持的分辨率的最大应用，而且显示数据也能够经过图像处理，实现了显示质量的最佳。
附图说明
图1是本申请实施例的显示处理系统示意图之一；
图2是本申请实施例的显示处理系统示意图之二；
图3是本申请实施例的显示处理系统示意图之三；
图4是本申请实施例的电子设备的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚地描述， 显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书和权利要求书中的术语“第一”、“第二”等是用于区别类似的对象，而不用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便本申请的实施例能够以除了在这里图示或描述的那些以外的顺序实施，且“第一”、“第二”等所区分的对象通常为一类，并不限定对象的个数，例如第一对象可以是一个，也可以是多个。此外，说明书以及权利要求中“和/或”表示所连接对象的至少其中之一，字符“/”，一般表示前后关联对象是一种“或”的关系。
下面结合附图，通过具体的实施例及其应用场景对本申请实施例提供的显示处理系统进行详细地说明。
如图1所示，本申请实施例的一种显示处理系统，包括：
图像处理集成电路、至少两个显示驱动集成电路以及连接所述图像处理集成电路和所述至少两个显示驱动集成电路的桥接集成电路；
其中，所述桥接集成电路用于对所述图像处理集成电路输出的第一显示数据进行裁剪，并将经裁剪所得的多个第二显示数据中的每个所述第二显示数据传输至一个所述显示驱动集成电路。
如此，本申请实施例的显示处理系统，由于桥接集成电路能够对所述图像处理集成电路输出的第一显示数据进行裁剪，然后将经裁剪所得的多个第二显示数据中的每个所述第二显示数据传输至一个所述显示驱动集成电路，使得图像处理电路和多个显示驱动集成电路的共存，不仅保证了显示屏所支持的分辨率的最大应用，而且显示数据也能够经过图像处理，实现了显示质量的最佳。
应该知道的是，该实施例中，图像处理集成电路也称为图像处理芯片，桥接集成电路也称为桥接芯片(Mobile Industry Processor Interface，MIPI)，显示驱动集成电路也称为显示驱动芯片(DDIC)。
可选地，如图1所示，所述显示处理系统还包括：
与所述图像处理集成电路连接的主控集成电路。
主控集成电路(也称为主控芯片)能够将源显示数据进行预处理后，传输至所述图像处理集成电路进行后续处理。
例如，主控集成电路的接收端与应用本申请显示处理系统的电子设备的摄像头连接，在摄像头拍摄的内容直接传输给主控集成电路进行预处理后，主控集成电路将经预处理的拍摄的内容传输至图像处理集成电路。当然，主控集成电路的接收端还可以接收该摄像头拍摄的内容之外的源显示数据。
可选地，所述桥接集成电路包括解码组件、存储组件和裁剪组件；
所述解码组件用于对所述第一显示数据进行解码；
所述存储组件用于对解码后的所述第一显示数据进行存储；
所述裁剪组件用于对解码后的所述第一显示数据进行裁剪。
如此，桥接集成电路在接收第一显示数据后，能够通过解码组件先对第一显示数据进行解码，并由存储组件存储。而裁剪组件可以对解码组件解码后的第一显示数据直接进行裁剪，或者从存储组件中提取解码后的第一显示数据进行裁剪。
可选地，所述至少两个显示驱动集成电路中的各个显示驱动集成电路驱动不同的显示区域。
例如，显示处理系统包括两个显示驱动集成电路，分别用于驱动显示屏的左屏和右屏，显示处理系统的桥接集成电路在接收第一显示数据后，将其裁剪为左半屏和右半屏数据，然后传输给这两个显示驱动集成电路，实现第一显示数据在显示屏的高质量显示。
可选地，该实施例中，所述图像处理集成电路的第一接收端与所述主控集成电路的第一发送端连接，所述图像处理集成电路的第二接收端与所述主控集成电路的第二发送端连接，所述图像处理集成电路的第一发送端与所述桥接集成电路的第一接收端连接，所述图像处理集成电路的第二发送端与所述主控集成电路的第一接收端连接。
这里，考虑到不同数据的使用，应用本申请显示处理系统的电子设备的摄像头拍摄的内容记为第一类源显示数据，将其他源显示数据记为第二类源显示数据，主控集成电路会通过不用端口传输不同类型的源显示数据至图像处理集成电路。而图像处理集成电路一方面可以经第一发送端输出第一显示数据至桥接集成电路，另一方面还可以将经第二发送端输出第五显示数据至主控集成电路。
作为一种实施方式，第五显示数据是第一类源显示数据经图像处理芯片处理后的数据，以实现主控集成电路输出的截屏或录屏图像的显示与用户拍摄时所见一致。
可选地，所述图像处理集成电路包括：
第一选择电路，数据处理组件，以及第二选择电路；
其中，所述第一选择电路用于将第三显示数据传输至所述图像处理集成电路的第一发送端或者所述数据处理组件，所述第三显示数据包括所述图像处理集成电路的第一接收端和第二接收端中至少一者接收到的数据；
所述数据处理组件用于根据所述第三显示数据的处理要求，对所述第三显示数据进行对应的数据处理；
所述第二选择电路用于将所述数据处理组件输出的第四显示数据传输至所述图像处理集成电路的第一发送端或者第二发送端。
这样，图像处理集成电路的第一接收端和第二接收端中至少一者接收到的数据，能够通过第一选择电路，实现数据直接输出至桥接集成电路；或者通过第一选择电路，将数据传输至数据处理组件按照相应的处理要求进行数据处理后，再通过第二选择电路输出至桥接集成电路或主控集成电路。
其中，若第四显示数据传输至图像处理集成电路的第一发送端，该第四显示数据即上述的第一显示数据；若第四显示数据传输至图像处理集成电路的第二发送端，该第四显示数据即上述的第五显示数据。
可选地，所述数据处理组件支持以下至少一项处理：
降噪；
插帧；
高动态范围；
超分。
当然，数据处理组件支持的数据处理不限于上述处理内容，在此不再一一列举。
需要了解的是，该实施例中，处理要求用于表明数据需要数据处理组件执行哪些处理。具体的，不同类型的显示数据的处理要求不同，如第二类源显示数据无需降噪。
可选地，所述第一选择电路包括第一开关和第二开关；
其中，所述第一开关的第一端与所述图像处理集成电路的第一接收端连接，所述第一开关的第二端与所述图像处理集成电路的第一发送端连接；
所述第二开关的第一端与所述图像处理集成电路的第一接收端连接，所述第二开关的第二端与所述图像处理集成电路的第二接收端连接，所述第二开关的第三端与所述数据处理组件的输入端连接。
故，对于图像处理集成电路的第一接收端接收到的数据，一方面能够通过第一开关，控制是否将该数据传输到图像处理集成电路的第一发送端；另一方面能够通过第二开关，控制是否将该数据传输到图像处理集成电路的数据处理组件。对于图像处理集成电路的第二接收端接收到的数据，也能够通过第二开关，控制是否将该数据传输到图像处理集成电路的数据处理组件。
可选地，所述第二选择电路包括第三开关和第四开关；
其中，所述第三开关的第一端与所述第四开关的第三端连接，所述第三开关的第二端与所述图像处理集成电路的第一发送端连接；
所述第四开关的第一端与所述数据处理组件的输出端连接，所述第四开关的第二端与所述图像处理集成电路的第二发送端连接。
即，对于图像处理集成电路的数据处理组件的输出数据，一方面能够通过第四开关，控制将该数据传输到图像处理集成电路的第二发送端，还是传输到第三开关的第一端；另一方面能够通过第三开关，控制是否将该数据传输到图像处理集成电路的第一发送端。
可选地，所述第一开关关闭，所述第二开关打开且所述第二开关的第一端与第三端连通，所述第三开关打开，所述第四开关打开且所述第四开关的第一端与第三端连通的情况下，所述图像处理集成电路的第一接收端接收到的数据通过所述第二开关传输到所述数据处理组件后，依次经所述数据处理组件、所述第四开关和所述第三开关传输至所述图像处理集成电路的第一发送端，并由所述图像处理集成电路的第一发送端发送至所述桥接集成电路。
可选地，所述第一开关打开，所述第二开关关闭，所述第三开关关闭，所述第四开关关闭的情况下，所述图像处理集成电路的第一接收端接收到的数据通过所述第一开关传输至所述图像处理集成电路的第一发送端，并由所述图像处理集成电路的第一发送端发送至所述桥接集成电路。
可选地，所述第一开关关闭，所述第二开关打开且所述第二开关的第二端与第三端连通，所述第三开关关闭，所述第四开关打开且所述第四开关的第一端与第二端连通的情况下，所述图像处理集成电路的第二接收端接收到的数据通过所述第二开关传输至所述数据处理组件后，依次经所述数据处理组件和所述第四开关传输至所述图像处理集成电路的第二发送端，并由所述图像处理集成电路的第二发送端发送至所述主控集成电路。
这里，主控集成电路在获取到图像处理集成电路的第二发送端发送的数据后，能够将图像处理集成电路处理后的数据传输至图像处理集成电路的第一接收端，此时第一开关打开，第二开关关闭，图像处理集成电路的第一接收端经第一开关连通图像处理集成电路的第一发送端，实现图像处理集成电路的第一接收端接收的数据在图像处理集成电路内通过模拟绕过(analog bypass)输出，最终由图像处理集成电路的第一发送端传输到桥接芯片。
当然，该实施例中，第三开关也可以为单刀双掷开关，其固定端与所述图像处理集成电路的第一发送端连接，其第一活动端与第四开关的第三端连接，其第二活动端与所述第一开关的第二端连接，以实现通过第三开关控制将图像处理集成电路的数据处理组件输出的数据或者图像处理集成电路的第一接收端接收的数据传输至图像处理集成电路的第一发送端。
可选地，该实施例中，所述第二选择电路还包括第五开关和第六开关；
其中，所述第五开关的第一端与所述数据处理组件的输出端连接，所述第五开关的第二端与所述图像处理集成电路的第一发送端连接；
所述第六开关的第一端与所述数据处理组件的输出端连接，所述第六开关的第二端与所述图像处理集成电路的第二发送端连接。
即，对于图像处理集成电路的数据处理组件的输出数据，一方面能够通过第六开关，控制是否将该数据传输到图像处理集成电路的第二发送端；另一方面能够通过第五开关，控制是否将该数据传输到图像处理集成电路的第一发送端。
可选地，所述第一开关关闭，所述第二开关打开且所述第二开关的第二端与第三端连通，所述第五开关打开的情况下，所述图像处理集成电路的第二接收端接收到的数据通过所述第二开关传输到所述数据处理组件后，依次经所述数据处理组件和所述第五开关传输至所述图像处理集成电路的第一发送端，并由所述图像处理集成电路的第一发送端发送至所述桥接集成电路。
可选地，在所述第六开关打开的情况下，所述数据处理组件输出的数据还能够经所述图像处理集成电路的第二发送端发送至所述主控集成电路。
即，第一开关关闭，第二开关打开且所述第二开关的第二端与第三端连通，第六开关打开时，数据处理组件输出的数据会通过第六开关传输至图像处理集成电路的第二发送端，然后发送至主控集成电路。例如数据处理组件处理后的数据需要经主控集成电路存储在存储空间的场景。
可选地，所述第一开关打开，所述第二开关关闭，所述第五开关关闭，所述第六开关关闭的情况下，所述图像处理集成电路的第一接收端接收到的数据通过所述第一开关传输至所述图像处理集成电路的第一发送端，并由所述图像处理集成电路的第一发送端发送至所述桥接集成电路。
当然，该实施例中，第五开关也可以为单刀双掷开关，其固定端与所述图像处理集成电路的第一发送端连接，其第一活动端与数据处理组件的输出端连接，其第二活动端与所述第一开关的第二端连接，以实现通过第七开关控制将图像处理集成电路的数据处理组件输出的数据或者图像处理集成电路的第一接收端接收的数据传输至图像处理集成电路的第一发送端。
下面以图2和图3为例，说明本申请实施例的显示处理系统的具体结构实现：
在图2和图3中，仅示意了部分摄像头串行接口发送端(Camera Serial Interface Transmition，CSI-TX)和部分摄像头串行接口接收端(Camera serial interface Receiver，CSI-RX)，以及部分显示串行接口发送端(Display Serial Interface Transmition，DSI-TX)和部分显示串行接口接收端(Display serial interface Receiver，DSI-RX)，各集成电路的DSI-TX、DSI-RX、CSI-TX和CSI-RX不限于图中所示。图2和图3中，显示处理系统均设置了DDIC1和DDIC2。
图2、图3中，CSI-TX1：图像处理集成电路的第二发送端；CSI-RX1：主控集成电路的第一接收端；CSI-TX2：摄像头的输出端；CSI-RX2：主控集成电路的第二接收端；DSI-TX3：主控集成电路的第一发送端；DSI-RX3图像处理集成电路的第一接收端；DSI-TX4：主控集成电路的第二发送端；DSI-RX4：图像处理集成电路的第二接收端；DSI-TX5：图像处理集成电路的第一发送端；DSI-RX5：桥接集成电路的第一接收端；DSI-TX6：桥接集成电路的第一发送端；DSI-RX6：DDIC1的接收端；DSI-TX7：桥接集成电路的第二发送端；DSI-RX7：DDIC2的接收端；开关1：第一开关，打开状态时，DSI-RX3和analog bypass连通，关闭状态时，DSI-RX3和analog bypass断开；开关2：第二开关，选择和DSI-RX3或者DSI-RX4接通；开关3：第三开关，打开状态时，图像处理芯片处理后显示内容(输出的第一显示数据)通过TX5传输给桥接芯片(如移动行业处理器接口(Mobile Industry Processor Interface，MIPI)桥接芯片)，关闭状态时，图像处理芯片处理后的显示内容不通过TX5传输给MIPI桥接芯片；开关4：第四开关，选择和开关3或者CSI-TX1接通；开关5：第五开关，打开状态时，图像处理芯片处理后显示内容(输出的第一显示数据)通过TX5传输给MIPI桥接芯片，关闭状态时，图像处理芯片处理后的显示内容不通过TX5传输给MIPI桥接芯片；开关6：打开状态时，图像处理芯片处理后显示内容(输出的第一显示数据)通过TX1传输给主控芯片，关闭状态时，图像处理芯片处理后的显示内容不通过TX1传输给主控芯片。
其中，开关均为单刀单掷开关。DSI-TX3主要传输第二类源显示数据，DSI-TX4主要是传输第一类源显示数据。
场景一、如图2所示，主控芯片将要在显示屏上显示的内容(第二类源显示数据)通过主控芯片的DSI-TX3传输给图像处理芯片的DSI-RX3。此时开关1关闭，开关2打开，图像处理芯片的DSI-RX3将显示内容传输给图像处理芯片内部的数据处理组件，数据处理组件可以根据处理要求(可以是场景定义的)选择对数据进行超分、插帧以及高动态范围(High-Dynamic Range，HDR)处理，经过处理后的数据会变得更清晰，视频会变得更流畅，HDR处理画面对比度和色彩显示效果更好。此时开关3和开关4都打开，图像处理芯片处理后的显示内容经过开关4接到开关3，开关3打开后再经过DSI-TX5传输给MIPI桥接芯片的DSI-RX5,MIP桥接芯片内部会将接收到的显示内容裁剪成左右半屏数据。左半屏的数据经过DSI-TX6传输给DDIC1,右半屏的数据经过DSI-TX7传输给DDIC 2，经过DDIC1和DDIC 2处理后数据在显示屏屏上进行显示。
场景二、如图2所示，主控芯片将要在显示屏上显示的内容(第二类源显示数据)通过主控芯片的DSI-TX3传输给图像处理芯片的DSI-RX3，此时开关2、开关3以及开关4关闭，开关1打开，经过图像处理芯片的DSI-RX3将显示内容传输给图像处理芯片内部的analog bypass通路，再经过DSI-TX5传输给MIPI桥接芯片的DSI-RX5,MIPI桥接芯片内部会将接收到的显示内容裁剪成左右半屏数据，左半屏的数据经过DSI-TX6传输给DDIC1,右半屏的数据经过DSI-TX7传输给DDIC2，经过DDIC1和DDIC 2处理后数据在显示屏屏上进行显示。当然，对于摄像头拍摄的视频和图片(第一类源显示数据)，在摄像头通过CSI-TX2传输给主控芯片后，主控芯片也能够采用类似方式实现第一类源显示数据在显示屏上的显示。
场景三、如图2所示，摄像头拍摄的视频和图片(第一类源显示数据)通过CSI-TX2传输给主控芯片，主控芯片将接收到的视频和图片通过DSI-TX4传输给图像处理芯片DXI-RX4。此时开关1关闭，开关2打开和图像处理芯片DXI-RX4连通，将手机拍摄后的内容传输给图像处理芯片内部数据处理组件，可以根据处理要求，选择对拍摄的内容进行降噪、插帧、HDR处理。经过数据处理组件后，尤其是在夜晚拍摄的内容会变得更清晰。此时开关4打开和图像处理芯片CSI-TX1连通。图像处理芯片处理后的拍摄内容经过CSI-TX1传输给主控芯片的CSI-RX1，主控芯片将图像处理芯片处理后的视频和图片经过主控芯片的DSI-TX3，传输给图像处理芯片的DSI-RX3。此时开关1打开，开关2关闭，开关3关闭，图像处理芯片的DSI-RX3和图像处理芯片内部的analog bypass，经过图像处理芯片DSI-TX5传输给MIPI桥接芯片的DSI-RX5,MIPI桥接芯片内部会将接收到的显示内容裁剪成左右半屏数据，左半屏的数据经过DSI-TX6传输给DDIC1,右半屏的数据经过DSI-TX7传输给DDIC2(显示驱动芯片2)，经过DDIC1和DDIC2处理后在显示屏上进行实时显示，实现所见即所得。经过主控芯片的CSI-RX1接收到图像处理芯片处理后的视频或者图片，主控芯片可以选择将处理后的视频或者图片存储在存储空间，方便后面查看。
在该场景中，截屏或者录屏截取的内容也经过了独显降噪，解决了用户拍照时截屏或者录屏的图像没有降噪的问题。
场景四、如图3所示，摄像头拍摄的视频和图片(第一类源显示数据)通过CSI-TX2传输给主控芯片，主控芯片将接收到的视频和图片通过DSI-TX4传输给图像处理芯片DXI-RX4。此时开关1关闭，开关2打开和图像处理芯片DXI-RX4连通，将手机拍摄后的内容传输给图像处理芯片内部数据处理组件，可以根据处理要求，选择对拍摄的内投进行降噪、插帧、HDR处理。经过这些处理后，尤其是在夜晚拍摄的内容会变得更清晰。此时开关6关闭，开关5打开，图像处理芯片处理后的图像经过图像处理芯片DSI-TX5传输给MIPI桥接芯片的DSI-RX5,MIPI桥接芯片内部会将接收到的显示数据裁剪成左右半屏数据，左半屏的数据经过DSI-TX6传输给DDIC1,右半屏的数据经过DSI-TX7传输给DDIC2，经过DDIC处理后在显示屏上进行实时显示，即所见即所得。如果主控芯片需要对处理后的图形资料做储存，开关6打开，图像处理芯片处理后的内容经过CSI-TX1传输给主控芯片的CSI-RX1，主控芯片将处理后的图像资料存储在存储空间，方便后面查看。
在该场景中，显示处理延时更低。
场景五、摄像头拍摄的视频和图片(第一类源显示数据)通过CSI-TX2传输给主控芯片，主控芯片将接收到的视频和图片通过DSI-TX3传输给图像处理芯片DXI-RX3。此时开关2、开关5、开关6关闭，开关1打开和图像处理芯片DXI-RX3连通，将手机拍摄后的内容传输给图像处理芯片内部analog bypass，再经过图像处理芯片DSI-TX5传输给MIP桥接芯片的DSI-RX5,MIPI桥接芯片内部会将接收到的显示数据裁剪成左右半屏数据，左半屏的数据经过DSI-TX6传输给DDIC1,右半屏的数据经过DSI-TX7传输给DDIC2，经过DDIC处理后在显示屏上进行实时显示。主控芯片也可以选择将摄像头拍摄的视频或者图片存储在存储空间存，方便后面查看。当然，对于将要在显示屏上显示的内容(第二类源显示数据)，也能够采用类似方式实现该第二类源显示数据在显示屏上的显示。
场景六、如图3所示，主控芯片将要在显示屏上显示的内容(第二类源显示数据)通过主控芯片的DSI-TX3传输给图像处理芯片的DSI-RX3。此时开关1关闭，开关2打开，图像处理芯片的DSI-RX3将显示内容传输给图像处理芯片内部的数据处理组件，数据处理组件可以根据处理要求(可以是场景定义的)选择对数据进行超分、插帧以及HDR处理，经过处理后的数据会变得更清晰，视频会变得更流畅，HDR处理画面对比度和色彩显示效果更好。此时开关5打开，开关6关闭，图像处理芯片处理后的显示内容经过开关5DSI-TX5传输给MIPI桥接芯片的DSI-RX5,MIP桥接芯片内部会将接收到的显示内容裁剪成左右半屏数据。左半屏的数据经过DSI-TX6传输给DDIC1,右半屏的数据经过DSI-TX7传输给DDIC 2，经过DDIC1和DDIC 2处理后数据在显示屏屏上进行显示。
综上所述，本申请实施例的显示处理系统，独立图像处理集成电路的视频插帧、视频超分、HDR处理等功能可以在使用，且摄像头拍摄的图片和视频，经过降噪和超分处理，清晰度更好，用户体验更好。
本申请实施例还提供一种电子设备，包括如上所述的显示处理系统。
该电子设备可以是终端，也可以为除终端之外的其他设备。示例性的，电子设备可以为手机、平板电脑、笔记本电脑、掌上电脑、车载电子设备、移动上网装置(Mobile Internet Device，MID)、增强现实(augmented reality，AR)/虚拟现实(virtual reality，VR)设备、机器人、可穿戴设备、超级移动个人计算机(ultra-mobile personal computer，UMPC)、上网本或者个人数字助理(personal digital assistant，PDA)等，还可以为服务器、网络附属存储器(Network Attached Storage，NAS)、个人计算机(personal computer，PC)、电视机(television，TV)、柜员机或者自助机等，本申请实施例不作具体限定。
当然，该电子设备的显示屏为折叠屏。
本申请实施例提供的电子设备能够实现图1至图3的显示处理系统实施例实现的各个过程，为避免重复，这里不再赘述。
图4为实现本申请实施例的一种电子设备的硬件结构示意图。
该电子设备400包括但不限于：射频单元401、网络模块402、音频输出单元403、输入单元404、传感器405、显示单元406、用户输入单元407、接口单元408、存储器409、以及处理器410等部件。
本领域技术人员可以理解，电子设备400还可以包括给各个部件供电的电源(比如电池)，电源可以通过电源管理系统与处理器410逻辑相连，从而通过电源管理系统实现管理充电、放电、以及功耗管理等功能。图4中示出的电子设备结构并不构成对电子设备的限定，电子设备可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置，在此不再赘述。
其中，所述电子设备还包括如上所述的显示处理系统。
应理解的是，本申请实施例中，输入单元404可以包括图形处理器(Graphics Processing Unit，GPU)4041和麦克风4042，图形处理器4041对在视频捕获模式或图像捕获模式中由图像捕获装置(如摄像头)获得的静态图片或视频的图像数据进行处理。显示单元406可包括显示面板4061，可以采用液晶显示器、有机发光二极管等形式来配置显示面板4061。用户输入单元407包括触控面板4071以及其他输入设备4072中的至少一种。触控面板4071，也称为触摸屏。触控面板4071可包括触摸检测装置和触摸控制器两个部分。其他输入设备4072可以包括但不限于物理键盘、功能键(比如音量控制按键、开关按键等)、轨迹球、鼠标、操作杆，在此不再赘述。
存储器409可用于存储软件程序以及各种数据。存储器409可主要包括存储程序或指令的第一存储区和存储数据的第二存储区，其中，第一存储区可存储操作系统、至少一个功能所需的应用程序或指令(比如声音播放功能、图像播放功能等)等。此外，存储器409可以包括易失性存储器或非易失性存储器，或者，存储器409可以包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(Read-Only Memory，ROM)、可编程只读存储器(Programmable ROM，PROM)、可擦除可编程只读存储器(Erasable PROM，EPROM)、电可擦除可编程只读存储器(Electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(Random Access Memory，RAM)，静态随机存取存储器(Static RAM，SRAM)、动态随机存取存储器(Dynamic RAM，DRAM)、同步动态随机存取存储器(Synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(Double Data Rate SDRAM，DDRSDRAM)、增强型同步动态随机存取存储器(Enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(Synch link DRAM，SLDRAM)和直接内存总线随机存取存储器(Direct Rambus RAM，DRRAM)。本申请实施例中的存储器409包括但不限于这些和任意其它适合类型的存储器。
处理器410可包括一个或多个处理单元；可选的，处理器410集成应用处理器和调制解调处理器，其中，应用处理器主要处理涉及操作系统、用户界面和应用程序等的操作，调制解调处理器主要处理无线通信信号，如基带处理器。可以理解的是，上述调制解调处理器也可以不集成到处理器410中。
应理解，本申请实施例提到的主控芯片还可以称为系统级芯片、系统芯片、芯片系统或片上系统芯片等。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。此外，需要指出的是，本申请实施方式中的方法和装置的范围不限按示出或讨论的顺序来执行功能，还可包括根据所涉及的功能按基本同时的方式或按相反的顺序来执行功能，例如，可以按不同于所描述的次序来执行所描述的方法，并且还可以添加、省去、或组合各种步骤。另外，参照某些示例所描述的特征可在其他示例中被组合。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到上述实施例方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分可以以计算机软件产品的形式体现出来，该计算机软件产品存储在一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端(可以是手机，计算机，服务器，或者网络设备等)执行本申请各个实施例所述的方法。
上面结合附图对本申请的实施例进行了描述，但是本申请并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本申请的启示下，在不脱离本申请宗旨和权利要求所保护的范围情况下，还可做出很多形式，均属于本申请的保护之内。

Claims (17)

  1. 一种显示处理系统，其中，包括：
    图像处理集成电路、至少两个显示驱动集成电路以及连接所述图像处理集成电路和所述至少两个显示驱动集成电路的桥接集成电路；
    其中，所述桥接集成电路用于对所述图像处理集成电路输出的第一显示数据进行裁剪，并将经裁剪所得的多个第二显示数据中的每个所述第二显示数据传输至一个所述显示驱动集成电路。
  2. 根据权利要求1所述的显示处理系统，其中，还包括：
    与所述图像处理集成电路连接的主控集成电路。
  3. 根据权利要求2所述的显示处理系统，其中，所述图像处理集成电路的第一接收端与所述主控集成电路的第一发送端连接，所述图像处理集成电路的第二接收端与所述主控集成电路的第二发送端连接，所述图像处理集成电路的第一发送端与所述桥接集成电路的第一接收端连接，所述图像处理集成电路的第二发送端与所述主控集成电路的第一接收端连接。
  4. 根据权利要求3所述的显示处理系统，其中，所述图像处理集成电路包括：
    第一选择电路，数据处理组件，以及第二选择电路；
    其中，所述第一选择电路用于将第三显示数据传输至所述图像处理集成电路的第一发送端或者所述数据处理组件，所述第三显示数据包括所述图像处理集成电路的第一接收端和第二接收端中至少一者接收到的数据；
    所述数据处理组件用于根据所述第三显示数据的处理要求，对所述第三显示数据进行对应的数据处理；
    所述第二选择电路用于将所述数据处理组件输出的第四显示数据传输至所述图像处理集成电路的第一发送端或者第二发送端。
  5. 根据权利要求4所述的显示处理系统，其中，所述第一选择电路包括第一开关和第二开关；
    其中，所述第一开关的第一端与所述图像处理集成电路的第一接收端连接，所述第一开关的第二端与所述图像处理集成电路的第一发送端连接；
    所述第二开关的第一端与所述图像处理集成电路的第一接收端连接，所述第二开关的第二端与所述图像处理集成电路的第二接收端连接，所述第二开关的第三端与所述数据处理组件的输入端连接。
  6. 根据权利要求5所述的显示处理系统，其中，所述第二选择电路包括第三开关和第四开关；
    其中，所述第三开关的第一端与所述第四开关的第三端连接，所述第三开关的第二端与所述图像处理集成电路的第一发送端连接；
    所述第四开关的第一端与所述数据处理组件的输出端连接，所述第四开关的第二端与所述图像处理集成电路的第二发送端连接。
  7. 根据权利要求5所述的显示处理系统，其中，所述第二选择电路还包括第五开关和第六开关；
    其中，所述第五开关的第一端与所述数据处理组件的输出端连接，所述第五开关的第二端与所述图像处理集成电路的第一发送端连接；
    所述第六开关的第一端与所述数据处理组件的输出端连接，所述第六开关的第二端与所述图像处理集成电路的第二发送端连接。
  8. 根据权利要求6所述的显示处理系统，其中，所述第一开关关闭，所述第二开关打开且所述第二开关的第一端与第三端连通，所述第三开关打开，所述第四开关打开且所述第四开关的第一端与第三端连通的情况下，所述图像处理集成电路的第一接收端接收到的数据通过所述第二开关传输到所述数据处理组件后，依次经所述数据处理组件、所述第四开关和所述第三开关传输至所述图像处理集成电路的第一发送端，并由所述图像处理集成电路的第一发送端发送至所述桥接集成电路。
  9. 根据权利要求6所述的显示处理系统，其中，所述第一开关打开，所述第二开关关闭，所述第三开关关闭，所述第四开关关闭的情况下，所述图像处理集成电路的第一接收端接收到的数据通过所述第一开关传输至所述图像处理集成电路的第一发送端，并由所述图像处理集成电路的第一发送端发送至所述桥接集成电路。
  10. 根据权利要求6所述的显示处理系统，其中，所述第一开关关闭，所述第二开关打开且所述第二开关的第二端与第三端连通，所述第三开关关闭，所述第四开关打开且所述第四开关的第一端与第二端连通的情况下，所述图像处理集成电路的第二接收端接收到的数据通过所述第二开关传输至所述数据处理组件后，依次经所述数据处理组件和所述第四开关传输至所述图像处理集成电路的第二发送端，并由所述图像处理集成电路的第二发送端发送至所述主控集成电路。
  11. 根据权利要求7所述的显示处理系统，其中，所述第一开关关闭，所述第二开关打开且所述第二开关的第二端与第三端连通，所述第五开关打开的情况下，所述图像处理集成电路的第二接收端接收到的数据通过所述第二开关传输到所述数据处理组件后，依次经所述数据处理组件和所述第五开关传输至所述图像处理集成电路的第一发送端，并由所述图像处理集成电路的第一发送端发送至所述桥接集成电路。
  12. 根据权利要求11所述的显示处理系统，其中，在所述第六开关打开的情况下，所述数据处理组件输出的数据还能够经所述图像处理集成电路的第二发送端发送至所述主控集成电路。
  13. 根据权利要求7所述的显示处理系统，其中，所述第一开关打开，所述第二开关关闭，所述第五开关关闭，所述第六开关关闭的情况下，所述图像处理集成电路的第一接收端接收到的数据通过所述第一开关传输至所述图像处理集成电路的第一发送端，并由所述图像处理集成电路的第一发送端发送至所述桥接集成电路。
  14. 根据权利要求1所述的显示处理系统，其中，所述桥接集成电路包括解码组件、存储组件和裁剪组件；
    所述解码组件用于对所述第一显示数据进行解码；
    所述存储组件用于对解码后的所述第一显示数据进行存储；
    所述裁剪组件用于对解码后的所述第一显示数据进行裁剪。
  15. 根据权利要求1所述的显示处理系统，其中，所述至少两个显示驱动集成电路中的各个显示驱动集成电路驱动不同的显示区域。
  16. 根据权利要求4所述的显示处理系统，其中，所述数据处理组件支持以下至少一项处理：
    降噪；
    插帧；
    高动态范围；
    超分。
  17. 一种电子设备，其中，包括如权利要求1至16任一项所述的显示处理系统。
PCT/CN2024/102109 2023-06-30 2024-06-27 显示处理系统和电子设备 Ceased WO2025002283A1 (zh)

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