WO2025002282A1 - 数据处理方法、装置、系统和电子设备 - Google Patents

数据处理方法、装置、系统和电子设备 Download PDF

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Publication number
WO2025002282A1
WO2025002282A1 PCT/CN2024/102106 CN2024102106W WO2025002282A1 WO 2025002282 A1 WO2025002282 A1 WO 2025002282A1 CN 2024102106 W CN2024102106 W CN 2024102106W WO 2025002282 A1 WO2025002282 A1 WO 2025002282A1
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WIPO (PCT)
Prior art keywords
data
chip
resolution
instruction
display
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PCT/CN2024/102106
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English (en)
French (fr)
Inventor
曹凯
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Vivo Mobile Communication Co Ltd
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Vivo Mobile Communication Co Ltd
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Application filed by Vivo Mobile Communication Co Ltd filed Critical Vivo Mobile Communication Co Ltd
Priority to EP24830914.8A priority Critical patent/EP4738095A1/en
Publication of WO2025002282A1 publication Critical patent/WO2025002282A1/zh
Priority to US19/426,289 priority patent/US20260112334A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/005—Adapting incoming signals to the display format of the display terminal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/147—Digital output to display device ; Cooperation and interconnection of the display device with other functional units using display panels
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T3/00—Geometric image transformations in the plane of the image
    • G06T3/40—Scaling of whole images or parts thereof, e.g. expanding or contracting
    • G06T3/4053—Scaling of whole images or parts thereof, e.g. expanding or contracting based on super-resolution, i.e. the output image resolution being higher than the sensor resolution
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/391—Resolution modifying circuits, e.g. variable screen formats
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
    • H04N21/4402—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display
    • H04N21/440263—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display by altering the spatial resolution, e.g. for displaying on a connected PDA
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
    • H04N21/4402—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display
    • H04N21/440281—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display by altering the temporal resolution, e.g. by frame skipping
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2350/00—Solving problems of bandwidth in display systems

Definitions

  • the present application belongs to the technical field of communication applications, and specifically relates to a data processing method, device, system and electronic equipment.
  • independent display chips can support the processing of image data, such as frame interpolation, to support the interpolation of low-frame game/video sources to high frame rates, allowing users to have a smoother visual experience; and, the system on chip (System on Chip, SoC) can be upgraded to support the display processor (Display Process Unit, DPU) magnification function, which can enlarge the Full High Definition (Full High Definition, FHD) game/video source to Wide Quad High Definition (WQHD) resolution for a clearer display effect.
  • DPU Display Process Unit
  • the independent graphics chip can only perform processing such as frame insertion for the low-resolution image data output by the SoC, and cannot be used with the improved SoC, thus reducing the display quality.
  • the purpose of the embodiments of the present application is to provide a data processing method, device, system and electronic device, which solves the problem that the existing independent display chip and the improved SoC are not applicable and affect the display quality.
  • an embodiment of the present application provides a data processing method, including:
  • the resolution of the acquired first data is reduced, and the first data with the reduced resolution is processed to obtain second data;
  • the first data is image data sent by the system-level chip, and a resolution of the first data is greater than or equal to a first threshold; and a resolution of the second data is less than the first threshold.
  • an embodiment of the present application provides a data processing method, including:
  • the resolution of the second data is increased to obtain third data
  • the resolution of the third data is equal to the resolution of the first data
  • the first data is image data sent by the system-level chip.
  • an embodiment of the present application provides a data processing method, including:
  • the first start instruction is used to instruct the independent display chip to reduce the resolution of the first data sent by the system-level chip and obtain the second data through processing;
  • the second start instruction is used to instruct the display driver chip to increase the resolution of the second data to obtain the third data;
  • the resolution of the first data is greater than or equal to a first threshold; the resolution of the second data is less than the first threshold; and the resolution of the third data is equal to the resolution of the first data.
  • an embodiment of the present application provides a data processing device, including:
  • a first receiving module used for receiving a first start instruction sent by the system-level chip
  • a first processing module configured to reduce the resolution of the acquired first data according to the first start instruction, and process the first data with the reduced resolution to obtain second data
  • a first sending module used for sending the second data to a display driver chip
  • the first data is image data sent by the system-level chip, and a resolution of the first data is greater than or equal to a first threshold; and a resolution of the second data is less than the first threshold.
  • an embodiment of the present application provides a data processing device, including:
  • a second receiving module used for receiving a second start instruction sent by the system-level chip
  • a second processing module configured to, according to the second start instruction, increase the resolution of the second data sent by the independent display chip to obtain third data
  • the resolution of the third data is equal to the resolution of the first data
  • the first data is image data sent by the system-level chip.
  • an embodiment of the present application provides a data processing device, including:
  • a second sending module used for sending a second start instruction to the display driver chip, and after sending the second start instruction, sending a first start instruction to the independent display chip;
  • the first start instruction is used to instruct the independent display chip to reduce the resolution of the first data sent by the system-level chip and obtain the second data through processing;
  • the second start instruction is used to instruct the display driver chip to increase the resolution of the second data to obtain the third data;
  • the resolution of the first data is greater than or equal to a first threshold; the resolution of the second data is less than the first threshold; and the resolution of the third data is equal to the resolution of the first data.
  • an embodiment of the present application provides a data processing system, including an independent display chip, a display driver chip, and a system-level chip;
  • the system-level chip is used to: send a second start instruction to the display driver chip, and after sending the second start instruction, send a first start instruction to the independent display chip;
  • the independent display chip is used to: after receiving the first start instruction, reduce the resolution of the acquired first data according to the first start instruction, and process the first data with the reduced resolution, Obtaining second data, and sending the second data to the display driver chip;
  • the display driver chip is used to: after receiving the second start instruction, according to the second start instruction, in the case of acquiring the second data sent by the independent display chip, increase the resolution of the second data to obtain the third data;
  • the first data is image data sent by the system-level chip, and the resolution of the first data is greater than or equal to a first threshold; the resolution of the second data is less than the first threshold; and the resolution of the third data is equal to the resolution of the first data.
  • an embodiment of the present application provides an electronic device, comprising the data processing system as described in the seventh aspect.
  • an embodiment of the present application provides a readable storage medium, on which a program or instruction is stored.
  • the program or instruction is executed by a processor, the steps of the method described in the first aspect, the second aspect, or the third aspect are implemented.
  • an embodiment of the present application provides a computer program product, which is stored in a storage medium and is executed by at least one processor to implement the method described in the first aspect, the second aspect, or the third aspect.
  • the independent display chip after receiving the first start-up instruction, can reduce the resolution of the first data sent by the SoC according to the first start-up instruction, and process the first data with reduced resolution to obtain second data; and then send the second data to the display driver chip.
  • the independent display chip can further implement image processing of the image data, thereby ensuring the adaptation of the SoC and the independent display chip and improving the display quality.
  • FIG1 is a schematic diagram of a data processing method according to an embodiment of the present application.
  • FIG2 is a second flow chart of the data processing method according to an embodiment of the present application.
  • FIG3 is a third flow chart of the data processing method according to an embodiment of the present application.
  • FIG4 is a schematic diagram of a structure of a data processing system according to an embodiment of the present application.
  • FIG5 is a second structural diagram of the data processing system according to an embodiment of the present application.
  • FIG6 is a schematic diagram of the module structure corresponding to FIG1;
  • FIG7 is a schematic diagram of the module structure corresponding to FIG2;
  • FIG8 is a schematic diagram of the module structure corresponding to FIG3;
  • FIG. 9 is a schematic diagram of the structure of an electronic device according to an embodiment of the present application.
  • first, second, etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first”, “second”, etc. are generally of one type, and the number of objects is not limited.
  • the first object can be one or more.
  • “and/or” in the specification and claims represents at least one of the connected objects, and the character “/" generally indicates that the objects associated with each other are in an "or” relationship.
  • DGPUs Independent display chips
  • DGPUs are widely used in personal computers.
  • They can bring display enhancement effects such as higher frame rate, higher resolution, color saturation and contrast.
  • display enhancement effects such as higher frame rate, higher resolution, color saturation and contrast.
  • an embodiment of the present application provides a data processing method, which is applied to an independent display chip.
  • the method includes:
  • Step 101 Receive a first start instruction sent by a system-on-chip.
  • the first enable instruction is an instruction sent by the SoC, instructing the independent display chip to reduce the resolution of the first data sent by the SoC, and to further process the first data with the reduced resolution.
  • Step 102 according to the first start instruction, reducing the resolution of the acquired first data, and processing the first data with the reduced resolution to obtain second data;
  • Step 103 sending the second data to a display driver chip
  • the first data is image data sent by the system-level chip, and a resolution of the first data is greater than or equal to a first threshold; and a resolution of the second data is less than the first threshold.
  • the independent display chip after receiving the first start-up instruction, can reduce the resolution of the first data sent by the SoC according to the first start-up instruction, and process the first data with reduced resolution to obtain second data; then send the second data to the display driver chip.
  • the independent display chip can further implement image processing of the image data, thereby ensuring the adaptation of the SoC and the independent display chip and improving the display quality.
  • the independent graphics chip since the independent graphics chip only needs to support image processing of low-resolution image data, the cost of the independent graphics chip is reduced.
  • the first threshold is preconfigured or defined.
  • the first data is wide quad high definition (WQHD) data
  • the second data is full high definition (FHD) data.
  • the SoC will first send a second startup instruction to the display driver chip (Display Driver Integrated Circuit, DDIC), instructing the DDIC to increase the resolution of the second data to obtain third data after receiving the second data; and then send a first startup instruction to the independent display chip, instructing the independent display chip to first reduce the resolution of the first data after receiving the first data, and then process the first data with the reduced resolution to obtain the second data and send it to the DDIC, to ensure that the third data obtained by the DDIC is restored to the original resolution, converted into a display panel (panel) drive signal, complete the display drive, and achieve higher quality display.
  • DDIC Display Driver Integrated Circuit
  • reducing the resolution of the acquired first data includes:
  • the first data is downsampled by turning on a downsampling component in the independent display chip.
  • the independent graphics chip is pre-configured with a downsampling component. After receiving the first start-up instruction, the independent graphics chip can start the downsampling component to downsample the received first data and reduce the resolution of the first data.
  • the first data after the resolution is reduced is processed by at least one of the following:
  • the independent graphics chip can also deploy image processing components, such as motion estimation and motion compensation (MEMC) components, low-power super-resolution (LDSR) components, etc., to achieve one or more of the above-mentioned processing.
  • image processing components such as motion estimation and motion compensation (MEMC) components, low-power super-resolution (LDSR) components, etc.
  • the processing method of the first data after the resolution is reduced will be determined in combination with the processing requirements of the first data, and will not be described in detail here.
  • the method further includes:
  • a first transmission instruction is sent to the system-on-chip, where the first transmission instruction is used to notify the system-on-chip to send the first data.
  • the independent display chip can transmit the first data to the downsampling component through the display data receiving component by connecting its own interface and the display data receiving component. After the independent display chip connects its input port with the display data receiving component, it informs the SoC to send the first data through the first transmission instruction, so that the resolution of the received first data can be timely and effectively reduced for subsequent processing.
  • the method further includes:
  • the output port of the independent display chip is connected to the independent display chip
  • the input port is directly connected
  • the input port of the independent display chip is connected to the output port of the system-level chip, and the output port of the independent display chip is connected to the input port of the display driver chip.
  • the SoC will send the first closing instruction to the independent graphics chip to instruct the independent graphics chip to directly connect its output port with the input port.
  • the independent graphics chip subsequently receives the first data from the SoC, it will not be output through the display data receiving component, but will be directly output to the DDIC through the analog bypass of the independent graphics chip.
  • the functional components inside the independent graphics chip can complete the power-off process to reduce power consumption.
  • the SoC will also send a second closing instruction to the DDIC, instructing the DDIC to close the upsampling component.
  • the DDIC closes the upsampling component, it will send a second transmission instruction to the SoC, instructing the SoC to send the first data.
  • the SoC will determine whether to send the first on instruction and the second on instruction, or send the first off instruction and the second off instruction according to the requirements of the first data to be sent.
  • first turn-on instruction and the first turn-off instruction can also be understood as the mode switching instructions of the independent display chip, that is, the independent display chip will work in the first mode after receiving the first turn-on instruction: the input port of the independent display chip is connected to the display data receiving component inside it, and the downsampling component and the image processing component are turned on; the independent display chip will work in the second mode after receiving the first turn-off instruction: the input port of the independent display chip is connected to its output port, and the downsampling component and the image processing component are turned off.
  • the second turn-on instruction and the second turn-off instruction can also be understood as the mode switching instructions of the DDIC, that is, the DDIC will work in the first mode after receiving the second turn-on instruction: the upsampling component is turned on; the DDIC will work in the second mode after receiving the second turn-off instruction: the upsampling component is turned off.
  • the embodiment of the present application further provides a data processing method, which is applied to a display driver chip, and the method includes:
  • Step 201 Receive a second start instruction sent by the system-on-chip.
  • the second enable instruction is an instruction sent by the SoC, instructing the DDIC to increase the resolution of the second data received from the independent display chip.
  • Step 202 when the second data sent by the independent display chip is obtained, the resolution of the second data is increased to obtain third data;
  • the resolution of the third data is equal to the resolution of the first data
  • the first data is image data sent by the system-level chip.
  • DDIC can increase the resolution of the second data based on the received second start-up instruction, so that the obtained third data is restored to the original resolution, converted into a panel drive signal, completes the display drive, and achieves higher quality display.
  • increasing the resolution of the second data includes:
  • the second data is up-sampled by turning on an up-sampling component in the display driver chip.
  • the DDIC is pre-configured with an upsampling component. After receiving the second start instruction, the DDIC can start the upsampling component to upsample the received second data to restore the original resolution.
  • the method further includes:
  • the second closing instruction closing the up-sampling component and sending a second transmission instruction, wherein the second transmission instruction is used to notify the system-level chip to send the first data;
  • the first data transmitted via the independent display chip is received.
  • DDIC turns off the upsampling component according to the second shutdown instruction, it can also notify SoC to send the first data by sending the second transmission instruction.
  • the independent display chip After receiving the first data, the independent display chip directly outputs it to DDIC through analog bypass. After receiving the first data, DDIC completes signal processing and display driving.
  • a display data receiving component is used to receive the first data or the second data sent by the independent display chip;
  • the signal processing unit includes an upsampling component, which can realize upsampling of the second data when turned on.
  • a data processing method is applied to a system-level chip, and the method includes:
  • Step 301 sending a second start instruction to the display driver chip
  • Step 302 after sending the second start instruction, sending a first start instruction to the independent display chip;
  • the first start instruction is used to instruct the independent display chip to reduce the resolution of the first data sent by the system-level chip and obtain the second data through processing;
  • the second start instruction is used to instruct the display driver chip to increase the resolution of the second data to obtain the third data;
  • the resolution of the first data is greater than or equal to a first threshold; the resolution of the second data is less than the first threshold; and the resolution of the third data is equal to the resolution of the first data.
  • the SoC will first send a second startup instruction to the DDIC, instructing the DDIC to increase the resolution of the second data to obtain the third data after receiving the second data; and then send a first startup instruction to the independent display chip, instructing the independent display chip to first reduce the resolution of the first data after receiving the first data, and then process the first data with the reduced resolution to obtain the second data and send it to the DDIC, ensuring that the third data obtained by the DDIC is restored to the original resolution, converted into a display panel drive signal, completes the display drive, and achieves higher quality display.
  • the method further comprises:
  • the first data is sent according to the first transmission instruction.
  • the SoC can send the first data to the independent graphics chip.
  • the independent graphics chip reduces the resolution of the first data, it further processes the first data to obtain the second data and sends it to the DDIC.
  • the method further comprises:
  • the first data is sent according to the second transmission instruction.
  • SoC can send the first data to the independent graphics chip.
  • the independent graphics chip After receiving the first data, the independent graphics chip directly outputs it to DDIC through analog bypass.
  • the method further comprises:
  • the first closing instruction is used to instruct the independent display chip to directly connect its output port with its input port.
  • the independent graphics chip can directly connect its output port with the input port according to the first shutdown instruction. In this way, when the independent graphics chip subsequently receives the first data from the SoC, it will not be output through the display data receiving component, but will be directly output to the DDIC via analog bypass.
  • the method further comprises:
  • the second shut-down instruction is used to instruct the display driver chip to shut down the up-sampling component.
  • the DDIC turns off the up-sampling component. In this way, after the DDIC receives the first data output by the independent display chip, it does not need up-sampling and directly completes the signal processing and display driving work.
  • an embodiment of the present application provides a data processing system, including an independent display chip, a display driver chip, and a system-level chip;
  • the system-level chip is used to: send a second start instruction to the display driver chip, and after sending the second start instruction, send a first start instruction to the independent display chip;
  • the independent display chip is used to: after receiving the first start instruction, reduce the resolution of the acquired first data according to the first start instruction, process the first data with the reduced resolution to obtain second data, and send the second data to the display driver chip;
  • the display driver chip is used to: after receiving the second start instruction, according to the second start instruction, in the case of acquiring the second data sent by the independent display chip, increase the resolution of the second data to obtain the third data;
  • the first data is image data sent by the system-level chip, and the resolution of the first data is greater than or equal to a first threshold; the resolution of the second data is less than the first threshold; and the resolution of the third data is equal to the resolution of the first data.
  • the SoC will first send a second startup instruction to the DDIC, instructing the DDIC to increase the resolution of the second data to obtain the third data after receiving the second data; and then send a first startup instruction to the independent graphics chip, instructing the independent graphics chip to first reduce the resolution of the first data after receiving the first data, and then process the first data with reduced resolution to obtain the second data and send it to the DDIC.
  • the DDIC obtains the second data, it can increase the resolution of the second data to obtain the third data.
  • the data processing system of the embodiment of the present application sends a resolution greater than or equal to the first
  • the first data of the threshold value because the independent graphics chip first reduces its resolution, the independent graphics chip can further realize image processing of the image data, ensure the adaptation of the SoC and the independent graphics chip, and improve the display quality; after the DDIC receives the second data, it will increase its resolution to restore it to the original resolution, and when it is converted into a panel drive signal to complete the display drive, a higher quality display is achieved.
  • the SoC includes a display data sending component DSI0 for sending data to the independent display chip.
  • the independent display chip includes an input port, a display data receiving component DSI RX0, a downsampling component, an independent display interpolation component (also called a motion estimation and motion compensation component), an upsampling component, a display data sending component DSI TX0, and an output port; wherein the input port can be connected to DSI RX0 or an output port through a switch, and the output port can be connected to the input port or DSI TX0 through a switch, and the upsampling component does not work when the downsampling component is turned on.
  • the independent display chip also includes a low-power super-resolution component.
  • the independent display chip can also include other image processing components.
  • the DDIC includes a display data receiving component DSIRX, a signal processing unit, and a source drive circuit; wherein the signal processing unit includes an upsampling component.
  • the source drive circuit of the DDIC is connected to the display panel.
  • the display driver chip is further used to: according to the received second shutdown instruction sent by the system-level chip, shut down the up-sampling component and send a second transmission instruction to the system-level chip, wherein the second transmission instruction is used to notify the system-level chip to send the first data;
  • the independent display chip is also used to: directly connect its own output port with the input port according to the received first shutdown instruction sent by the system-level chip, and directly send the first data to the display driver chip through its own output port when its own input port receives the first data.
  • the SoC will send a first shutdown instruction to the independent graphics chip, instructing the independent graphics chip to directly connect its output port with the input port, and the independent graphics chip will also shut down the internal functional components.
  • the independent graphics chip will subsequently receive the first data from the SoC and output the first data directly to the DDIC via analog bypass.
  • the SoC will also send a second shutdown instruction to the DDIC, instructing the DDIC to shut down the upsampling component.
  • the SoC can first send the first shutdown instruction, and then send the second shutdown instruction, to avoid the problem that the second data output by the independent display chip is displayed abnormally on the display panel after the upsampling component of the DDIC is turned off first. After the DDIC turns off the upsampling component, the second transmission instruction notifies the SoC to send the first data to ensure normal display.
  • the independent display chip is further used to downsample the first data by turning on a downsampling component in the independent display chip.
  • the independent display chip is further used to perform at least one of the following processing on the first data after the resolution is reduced:
  • the display driver chip is further used to: enable an upsampling group in the display driver chip
  • the device upsamples the second data.
  • the SoC when the image data output by the SoC needs to be processed by the independent graphics chip, the SoC will first send a second startup instruction to the DDIC. After receiving the second startup instruction, the DDIC will turn on the upsampling component and wait for the second data from the independent graphics chip. After sending the second startup instruction, the SoC sends a first startup instruction to the independent graphics chip. After receiving the first startup instruction, the independent graphics chip turns on the downsampling component and related components for image processing. Afterwards, the independent graphics chip will also send a first transmission instruction to the SoC to trigger the SoC to send the first data.
  • the independent graphics chip After receiving the first data, the independent graphics chip first reduces the resolution of the first data by downsampling, then performs image processing, and outputs the second data. After receiving the second data, the DDIC first restores it to the original resolution by upsampling, and then completes the display of the data.
  • the SoC When the image data output by the SoC does not require the independent graphics chip to perform image processing, the SoC will first send a first shutdown instruction to the independent graphics chip. After receiving the first shutdown instruction, the independent graphics chip will connect its own input port and output port, and shut down the downsampling component and related components of image processing. After sending the first shutdown instruction, the SoC sends a second shutdown instruction to the DDIC. After receiving the second start instruction, the DDIC shuts down the upsampling component. After that, the DDIC will also send a second transmission instruction to the SoC to trigger the SoC to send the first data. After receiving the first data, the independent graphics chip directly outputs the first data to the DDIC via analog bypass. After receiving the first data, the DDIC does not need upsampling and directly completes the signal processing and display driving work.
  • Scenario 1 WQHD resolution image data requires frame insertion processing by the independent graphics chip
  • the SoC before turning on the interpolation component of the independent graphics chip, the SoC needs to first send the display module initialization code and the second start-up instruction (such as the command to switch the screen resolution) to the DDIC, and then send the first start-up instruction to the independent graphics chip.
  • the WQHD 72Hz image data sent by the SoC is downsampled and interpolated inside the independent graphics card, and is not upsampled. It directly outputs FHD 144Hz image data to the DDIC, and the upsampling component inside the DDIC increases the image resolution to WQHD.
  • SoC stops outputting the first data
  • SoC outputs the FHD Panel initialization code (Operation code, referred to as OP code) and the second start command to DDIC. After receiving the second start command, DDIC starts the upsampling component;
  • the SoC sends a first start instruction to the independent graphics chip, and the independent graphics chip completes the switch from the bypass mode (the second mode) to the interpolation mode (the first mode).
  • the specific steps include:
  • the independent display chip switches the internal switch (mipi switch) to connect the DSI RX0 interface with the SoC DSI0 interface;
  • the DSI RX0 of the independent display chip sends a first transmission instruction (such as a TE signal) to the SoC to notify the SoC to output the first data;
  • a first transmission instruction such as a TE signal
  • SoC After receiving the first transmission instruction, SoC outputs WQHD 72Hz image data to the independent graphics chip. After receiving the WQHD 72Hz image data, the independent graphics chip first processes it into FHD 72Hz image data through the downsampling component, then inserts it into FHD 144Hz image data through the MEMC component, and finally outputs FHD 144Hz image data to DDIC through DSI TX0 without being processed by the upsampling component;
  • the DSI RX of DDIC After the DSI RX of DDIC receives the FHD 144Hz image data from the independent display chip, it is processed into WQHD 144Hz image data by the upsampling component of the signal processing unit and then converted into a panel drive signal to complete the display drive.
  • Scenario 2 WQHD resolution image data does not require frame insertion processing by the independent graphics chip
  • the SoC that has enabled the independent graphics interpolation function first sends a first shutdown instruction to the independent graphics chip and then sends a second shutdown instruction to the DDIC to disable the independent graphics interpolation function.
  • SoC stops outputting the first data
  • the SoC sends a first shutdown instruction to the independent graphics chip to complete the switch from the interpolation mode to the bypass mode.
  • the specific steps include:
  • the independent graphics chip stops DSI TX0 from outputting the first data and stops sending TE signals to the SoC;
  • the independent graphics chip switches the internal mipi switch to connect the DSI0 interface of the SoC with the DSI RX interface of the DDIC. In other words, the input port and output port of the independent graphics chip are connected, so that the subsequent first data does not pass through the functional components inside the independent graphics chip (the independent graphics chip enters the bypass mode);
  • the independent graphics chip turns off DSI RX0, DSI TX0, interpolation components, and upsampling components to complete the power-off process;
  • SoC outputs WQHD panel OP code and the second shutdown instruction (such as the command of screen resolution switching (FHD ⁇ WQHD)) to DDIC.
  • the second shutdown instruction such as the command of screen resolution switching (FHD ⁇ WQHD)
  • DDIC After receiving the second shutdown instruction, DDIC turns off the upsampling component and sends the second transmission instruction (such as TE signal) to SoC;
  • SoC receives the second transmission instruction and outputs the first data to DDIC via the DSI0 interface; wherein the first data is determined according to the screen resolution setting and the frame rate of the game/video source;
  • DDIC DDIC
  • the 144Hz interpolation function is implemented when the system resolution is set to WQHD.
  • the independent graphics chip After receiving WQHD resolution image data, the independent graphics chip first downsamples to FHD or lower resolution before subsequent processing, so that the amount of data that the independent graphics chip needs to process can be reduced and the output frame rate can be increased; after the independent graphics chip outputs low-resolution, high-frame rate image data to DDIC, DDIC performs upsampling processing. Since the independent graphics chip only needs to transmit low-resolution image data and the power consumption of the DDIC upsampling component is low, the power consumption of the independent graphics unit and the whole machine can be reduced when the interpolation function is turned on.
  • a low-power super-resolution component is added inside the independent graphics chip to perform anti-aliasing and sharpening processing on the image data to improve the image clarity.
  • the specific steps are the same as those in scenario 1, except that the interpolation component is turned on before the additional Enable a low power super-division component.
  • Scenario 4 WQHD resolution image data does not require frame insertion or super-resolution processing by the independent graphics chip
  • the data processing system can be used for mobile phone displays, and can also be adapted to tablets, laptops, car screens, watch screens, etc.
  • the data processing method provided in the embodiment of the present application can be executed by a data processing device.
  • the data processing device provided in the embodiment of the present application is described by taking the data processing method executed by the data processing device as an example.
  • a data processing device 600 includes:
  • a first receiving module 610 configured to receive a first start instruction sent by the system-level chip
  • a first processing module 620 configured to reduce the resolution of the acquired first data according to the first start instruction, and process the first data with the reduced resolution to obtain second data;
  • a first sending module 630 configured to send the second data to a display driver chip
  • the first data is image data sent by the system-level chip, and a resolution of the first data is greater than or equal to a first threshold; and a resolution of the second data is less than the first threshold.
  • the first processing module is further used for:
  • the first data is downsampled by turning on a downsampling component in the independent display chip.
  • the first processing module is further used to: perform at least one of the following processing on the first data after the resolution is reduced: frame insertion; super-resolution; noise reduction; color enhancement; color calibration.
  • the device further comprises:
  • a third processing module configured to connect the input port of the independent display chip to the display data receiving component of the independent display chip after receiving the first start instruction; wherein the display data receiving component is connected to the down-sampling component;
  • the third sending module is used to send a first transmission instruction to the system-level chip, where the first transmission instruction is used to notify the system-level chip to send the first data.
  • the device further comprises:
  • a third receiving module configured to receive a first closing instruction sent by the system-level chip after receiving the first opening instruction
  • a fourth processing module configured to directly connect the output port of the independent display chip to the input port of the independent display chip according to the first shutdown instruction
  • the input port of the independent display chip is connected to the output port of the system-level chip, and the output port of the independent display chip is connected to the input port of the display driver chip.
  • the data processing device provided in the embodiment of the present application can implement each process implemented by the method embodiment of Figure 1. To avoid repetition, it will not be described again here.
  • a data processing device 700 includes:
  • the second receiving module 710 is used to receive a second start instruction sent by the system-level chip
  • the second processing module 720 is configured to increase the resolution of the second data sent by the independent display chip according to the second start instruction to obtain third data;
  • the resolution of the third data is equal to the resolution of the first data
  • the first data is image data sent by the system-level chip.
  • the second processing module is further used for:
  • the second data is up-sampled by turning on an up-sampling component in the display driver chip.
  • the device further comprises:
  • a fourth receiving module configured to receive a second closing instruction sent by the system-level chip after receiving the second opening instruction
  • a fifth processing module configured to shut down the up-sampling component and send a second transmission instruction according to the second shut-down instruction, wherein the second transmission instruction is used to notify the system-level chip to send the first data;
  • the fifth receiving module is used to receive the first data transmitted via the independent display chip.
  • the data processing device provided in the embodiment of the present application can implement each process implemented by the method embodiment of Figure 2. To avoid repetition, it will not be described again here.
  • a data processing device 800 includes:
  • a second sending module 810 is used to send a second start instruction to the display driver chip, and after sending the second start instruction, send a first start instruction to the independent display chip;
  • the first start instruction is used to instruct the independent display chip to reduce the resolution of the first data sent by the system-level chip and obtain the second data through processing;
  • the second start instruction is used to instruct the display driver chip to increase the resolution of the second data to obtain the third data;
  • the resolution of the first data is greater than or equal to a first threshold; the resolution of the second data is less than the first threshold; and the resolution of the third data is equal to the resolution of the first data.
  • the device further comprises:
  • a fourth sending module used for sending a first closing instruction to the independent display chip
  • the first closing instruction is used to instruct the independent display chip to directly connect its output port with its input port.
  • the device further comprises:
  • a fifth sending module used for sending a second shutdown instruction to the display driver chip
  • the second shut-down instruction is used to instruct the display driver chip to shut down the up-sampling component.
  • the data processing device provided in the embodiment of the present application can implement each process implemented by the method embodiment of Figure 3. To avoid repetition, they will not be described here.
  • An embodiment of the present application also provides an electronic device, including the data processing system as described above.
  • the electronic devices in the embodiments of the present application include the mobile electronic devices and non-mobile electronic devices mentioned above.
  • FIG. 9 is a schematic diagram of the hardware structure of an electronic device implementing an embodiment of the present application.
  • the electronic device 900 includes but is not limited to: a radio frequency unit 901, a network module 902, an audio output unit 903, an input unit 904, a sensor 905, a display unit 906, a user input unit 907, an interface unit 908, a memory 909, and a processor 910 and other components.
  • the electronic device 900 may also include a power source (such as a battery) for supplying power to each component, and the power source may be logically connected to the processor 910 through a power management system, so that the power management system can manage charging, discharging, and power consumption.
  • a power source such as a battery
  • the electronic device structure shown in FIG9 does not constitute a limitation on the electronic device, and the electronic device may include more or fewer components than shown, or combine certain components, or arrange components differently, which will not be described in detail here.
  • the electronic device 900 further includes the data processing system as described above.
  • the SoC will first send a second startup instruction to the DDIC, instructing the DDIC to increase the resolution of the second data to obtain the third data after receiving the second data; then send a first startup instruction to the independent graphics chip, instructing the independent graphics chip to first reduce the resolution of the first data after receiving the first data, and then process the first data with reduced resolution to obtain the second data and send it to the DDIC.
  • the DDIC obtains the second data, it can increase the resolution of the second data to obtain the third data.
  • the independent graphics chip can further implement image processing of the image data, thereby ensuring the adaptation of the SoC and the independent graphics chip and improving the display quality; after the DDIC receives the second data, it will increase its resolution to restore it to the original resolution, and when it is converted into a panel drive signal to complete the display drive, a higher quality display can be achieved.
  • the input unit 904 may include a graphics processing unit (GPU) 9041 and a microphone 9042, and the graphics processor 9041 processes the image data of the static picture or video obtained by the image capture device (such as a camera) in the video capture mode or the image capture mode.
  • the display unit 906 may include a display panel 9061, and the display panel 9061 may be configured in the form of a liquid crystal display, an organic light emitting diode, etc.
  • the user input unit 907 includes a touch panel 9071 and at least one of other input devices 9072.
  • the touch panel 9071 is also called a touch screen.
  • the touch panel 9071 may include two parts: a touch detection device and a touch controller.
  • Other input devices 9072 may include, but are not limited to, a physical keyboard, function keys (such as a volume control key, a switch key, etc.), a trackball, a mouse, and a joystick, which will not be repeated here.
  • the memory 909 can be used to store software programs and various data.
  • the memory 909 may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, an application program or instructions required for at least one function (such as a sound playback function, an image playback function, etc.), etc.
  • the memory 909 may include a volatile memory or a non-volatile memory, or the memory 909 may include both volatile and non-volatile memories.
  • the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (ELPROM), or an electrically erasable programmable read-only memory (ELPROM).
  • ROM read-only memory
  • PROM programmable read-only memory
  • EPROM erasable programmable read-only memory
  • EPROM electrically erasable programmable read-only memory
  • ELPROM electrically erasable programmable read-only memory
  • ELPROM electrically erasable programmable read-only memory
  • ELPROM electrically erasable programmable read-only memory
  • Volatile memory can be random access memory (Random Access Memory, RAM), static random access memory (Static RAM, SRAM), dynamic random access memory (Dynamic RAM, DRAM), synchronous dynamic random access memory (Synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (Double Data Rate SDRAM, DDRSDRAM), enhanced synchronous dynamic random access memory (Enhanced SDRAM, ESDRAM), synchronous connection dynamic random access memory (Synch link DRAM, SLDRAM) and direct memory bus random access memory (Direct Rambus RAM, DRRAM).
  • RAM Random Access Memory
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • DRAM synchronous dynamic random access memory
  • SDRAM double data rate synchronous dynamic random access memory
  • Double Data Rate SDRAM Double Data Rate SDRAM
  • DDRSDRAM double data rate synchronous dynamic random access memory
  • Enhanced SDRAM, ESDRAM enhanced synchronous dynamic random access memory
  • Synch link DRAM, SLDRAM synchronous connection dynamic random access memory
  • the processor 910 may include one or more processing units; optionally, the processor 910 integrates an application processor and a modem processor, wherein the application processor mainly processes operations related to an operating system, a user interface, and application programs, and the modem processor mainly processes wireless communication signals, such as a baseband processor. It is understandable that the modem processor may not be integrated into the processor 910.
  • An embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored.
  • a program or instruction is stored.
  • the various processes of the above-mentioned data processing method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.
  • the processor is the processor in the electronic device described in the above embodiment.
  • the readable storage medium includes a computer readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk.
  • system-level chip mentioned in the embodiments of the present application can also be called a system chip, a chip system or a system-on-chip chip, etc.
  • An embodiment of the present application provides a computer program product, which is stored in a storage medium.
  • the program product is executed by at least one processor to implement the various processes of the above-mentioned data processing method embodiment and can achieve the same technical effect. To avoid repetition, it will not be repeated here.
  • the method can be implemented by means of software plus a necessary general hardware platform, or by hardware, but in many cases the former is a better implementation method.
  • the technical solution of the present application, or the part that contributes to the prior art can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM/RAM, disk, CD), and includes several instructions for a terminal (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

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Abstract

本申请公开了一种数据处理方法、装置、系统和电子设备，属于通信应用的技术领域。本申请的方法包括：接收系统级芯片发送的第一开启指令；根据所述第一开启指令，降低获取到的第一数据的分辨率，并对分辨率降低后的所述第一数据进行处理，得到第二数据；将所述第二数据发送至显示驱动芯片；其中，所述第一数据是所述系统级芯片发送的图像数据，所述第一数据的分辨率大于或等于第一阈值；所述第二数据的分辨率小于所述第一阈值。

Description

数据处理方法、装置、系统和电子设备
本申请要求在2023年6月30日提交中国专利局、申请号为202310801369.1、名称为“数据处理方法、装置、系统和电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请属于通信应用的技术领域，具体涉及一种数据处理方法、装置、系统和电子设备。
背景技术
目前，独立显示芯片(简称独显芯片)对图像数据的处理如插帧，能够支持将低帧游戏/视频源插帧到高帧率，让用户获得更流畅的视觉体验；且，系统芯片(System on Chip，SoC)通过提升，能够支持显示处理器(Display Process Unit，DPU)放大功能，可以将全高清(Full High Definition，FHD)的游戏/视频源放大到宽四高清(Wide Quad High Definition，WQHD)分辨率，获得更清晰的显示效果。
然而，独显芯片仅能够针对SoC输出的低分辨率图像数据的插帧等处理，无法与提升的SoC适用，降低了显示质量。
发明内容
本申请实施例的目的是提供一种数据处理方法、装置、系统和电子设备，解决了现有独显芯片与提升的SoC无法适用而影响显示质量的问题。
第一方面，本申请实施例提供了一种数据处理方法，包括：
接收系统级芯片发送的第一开启指令；
根据所述第一开启指令，降低获取到的第一数据的分辨率，并对分辨率降低后的所述第一数据进行处理，得到第二数据；
将所述第二数据发送至显示驱动芯片；
其中，所述第一数据是所述系统级芯片发送的图像数据，所述第一数据的分辨率大于或等于第一阈值；所述第二数据的分辨率小于所述第一阈值。
第二方面，本申请实施例提供了一种数据处理方法，包括：
接收系统级芯片发送的第二开启指令；
根据所述第二开启指令，在获取到独立显示芯片发送的第二数据的情况下，增大所述第二数据的分辨率，得到第三数据；
其中，所述第三数据的分辨率等于第一数据的分辨率，所述第一数据是所述系统级芯片发送的图像数据。
第三方面，本申请实施例提供了一种数据处理方法，包括：
向显示驱动芯片发送第二开启指令；
在发送所述第二开启指令之后，向独立显示芯片发送第一开启指令；
其中，所述第一开启指令用于指示所述独立显示芯片降低所述系统级芯片发送的第一数据的分辨率后通过处理得到第二数据；所述第二开启指令用于指示所述显示驱动芯片增大所述第二数据的分辨率得到第三数据；
所述第一数据的分辨率大于或等于第一阈值；所述第二数据的分辨率小于所述第一阈值；所述第三数据的分辨率等于所述第一数据的分辨率。
第四方面，本申请实施例提供了一种数据处理装置，包括：
第一接收模块，用于接收系统级芯片发送的第一开启指令；
第一处理模块，用于根据所述第一开启指令，降低获取到的第一数据的分辨率，并对分辨率降低后的所述第一数据进行处理，得到第二数据；
第一发送模块，用于将所述第二数据发送至显示驱动芯片；
其中，所述第一数据是所述系统级芯片发送的图像数据，所述第一数据的分辨率大于或等于第一阈值；所述第二数据的分辨率小于所述第一阈值。
第五方面，本申请实施例提供了一种数据处理装置，包括：
第二接收模块，用于接收系统级芯片发送的第二开启指令；
第二处理模块，用于根据所述第二开启指令，在获取到独立显示芯片发送的第二数据的情况下，增大所述第二数据的分辨率，得到第三数据；
其中，所述第三数据的分辨率等于第一数据的分辨率，所述第一数据是所述系统级芯片发送的图像数据。
第六方面，本申请实施例提供了一种数据处理装置，包括：
第二发送模块，用于向显示驱动芯片发送第二开启指令，并在发送所述第二开启指令之后，向独立显示芯片发送第一开启指令；
其中，所述第一开启指令用于指示所述独立显示芯片降低所述系统级芯片发送的第一数据的分辨率后通过处理得到第二数据；所述第二开启指令用于指示所述显示驱动芯片增大所述第二数据的分辨率得到第三数据；
所述第一数据的分辨率大于或等于第一阈值；所述第二数据的分辨率小于所述第一阈值；所述第三数据的分辨率等于所述第一数据的分辨率。
第七方面，本申请实施例提供了一种数据处理系统，包括独立显示芯片、显示驱动芯片和系统级芯片；
所述系统级芯片用于：向所述显示驱动芯片发送第二开启指令，并在发送所述第二开启指令之后，向所述独立显示芯片发送第一开启指令；
所述独立显示芯片用于：接收所述第一开启指令之后，根据所述第一开启指令，降低获取到的第一数据的分辨率，以及对分辨率降低后的所述第一数据进行处理， 得到第二数据，并向所述显示驱动芯片发送所述第二数据；
所述显示驱动芯片用于：接收所述第二开启指令之后，根据所述第二开启指令，在获取到独立显示芯片发送的第二数据的情况下，增大所述第二数据的分辨率，得到第三数据；
其中，所述第一数据是所述系统级芯片发送的图像数据，所述第一数据的分辨率大于或等于第一阈值；所述第二数据的分辨率小于所述第一阈值；所述第三数据的分辨率等于所述第一数据的分辨率。
第八方面，本申请实施例提供了一种电子设备，包括如第七方面所述的数据处理系统。
第九方面，本申请实施例提供了一种可读存储介质，所述可读存储介质上存储程序或指令，所述程序或指令被处理器执行时实现如第一方面或第二方面或第三方面所述的方法的步骤。
第十方面，本申请实施例提供一种计算机程序产品，该程序产品被存储在存储介质中，该程序产品被至少一个处理器执行以实现如第一方面或第二方面或第三方面所述的方法。
在本申请实施例中，独立显示芯片在接收到第一开启指令后，能够根据该第一开启指令，降低SoC发送的第一数据的分辨率，并对分辨率降低后的第一数据进行处理，得到第二数据；之后将该第二数据发送至显示驱动芯片。如此，对于SoC发送的分辨率大于或等于第一阈值的第一数据，由于先降低了其分辨率，使得该独立显示芯片可以进一步实现图像数据的图像处理，保证了SoC和独显芯片的适配，提升了显示质量。
附图说明
图1是本申请实施例的数据处理方法的流程示意图之一；
图2是本申请实施例的数据处理方法的流程示意图之二；
图3是本申请实施例的数据处理方法的流程示意图之三；
图4是本申请实施例的数据处理系统的结构示意图之一；
图5是本申请实施例的数据处理系统的结构示意图之二；
图6是图1对应的模块结构示意图；
图7是图2对应的模块结构示意图；
图8是图3对应的模块结构示意图；
图9是本申请实施例的电子设备的结构示意图。
具体实施例
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚地 描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书和权利要求书中的术语“第一”、“第二”等是用于区别类似的对象，而不用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便本申请的实施例能够以除了在这里图示或描述的那些以外的顺序实施，且“第一”、“第二”等所区分的对象通常为一类，并不限定对象的个数，例如第一对象可以是一个，也可以是多个。此外，说明书以及权利要求中“和/或”表示所连接对象的至少其中之一，字符“/”，一般表示前后关联对象是一种“或”的关系。
为使本领域技术人员能够更好地理解本申请实施例，首先进行如下说明：
独立显示芯片(独显芯片)在个人电脑中有广泛的应用，作为外置的专用图像处理单元可以带来更高帧率、更高分辨率、色彩饱和度及对比度等显示增强效果。随着移动互联网的爆发，游戏和影像需求也逐步扩充到移动智能终端，独显芯片在移动智能终端上也得到应用。
下面结合附图，通过具体的实施例及其应用场景对本申请实施例提供的显示驱动方法进行详细地说明。
如图1所示，本申请实施例提供了一种数据处理方法，应用于独立显示芯片，所述方法包括：
步骤101，接收系统级芯片发送的第一开启指令。
这里，第一开启指令是SoC发送的，指示独立显示芯片降低SoC发送的第一数据的分辨率，并对分辨率降低后的第一数据进一步处理的指令。
步骤102，根据所述第一开启指令，降低获取到的第一数据的分辨率，并对分辨率降低后的所述第一数据进行处理，得到第二数据；
步骤103，将所述第二数据发送至显示驱动芯片；
其中，所述第一数据是所述系统级芯片发送的图像数据，所述第一数据的分辨率大于或等于第一阈值；所述第二数据的分辨率小于所述第一阈值。
该实施例中，按照上述步骤101-103，独立显示芯片在接收到第一开启指令后，能够根据该第一开启指令，降低SoC发送的第一数据的分辨率，并对分辨率降低后的第一数据进行处理，得到第二数据；之后将该第二数据发送至显示驱动芯片。如此，对于SoC发送的分辨率大于或等于第一阈值的第一数据，由于先降低了其分辨率，使得该独立显示芯片可以进一步实现图像数据的图像处理，保证了SoC和独显芯片的适配，提升了显示质量。
而且，因独显芯片只需要支持低分辨率的图像数据的图像处理，降低了独显芯片的成本。
该实施例中，第一阈值是预配置或定义的。作为一种可选的实现方式，第一数据是宽四高清(Wide Quad High Definition，WQHD)数据，第二数据是全高清(Full High Definition，FHD)数据。
应该知道的是，该实施例中，SoC会先向显示驱动芯片(Display Driver Integrated Circuit，DDIC)发送第二启动指令，指示DDIC在接收到第二数据后，增大所述第二数据的分辨率得到第三数据；然后向独显芯片发送第一启动指令，指示独显芯片在接收到第一数据后，先降低第一数据的分辨率，然后对分辨率降低的第一数据进行处理后得到第二数据发送给DDIC，确保DDIC得到的第三数据恢复到原分辨率，转换为显示面板(panel)驱动信号，完成显示驱动，实现更高质量的显示。
可选地，该实施例中，降低获取到的第一数据的分辨率包括：
通过开启所述独立显示芯片内的下采样组件对所述第一数据进行下采样。
即，独显芯片预先配置有下采样(Downscale)组件，独显芯片接收到第一开启指令后，就能够开启该下采样组件，对接收的第一数据进行下采样，降低该第一数据的分辨率。
可选地，该实施例中，分辨率降低后的所述第一数据进行以下至少一项处理：
插帧；超分；降噪；色彩增强；色彩校准。
也就是说，独显芯片还可以部署图像处理组件，如运动估计与运动补偿(Motion Estimate and Motion Compensation，MEMC)组件、低功耗超分(Low Distortion Super Resolation，LDSR)组件等，实现上述一项或多项处理。
具体的，对分辨率降低后的所述第一数据的处理方式，会结合第一数据的处理需求确定，在此不再赘述。
需要知道的是，独显芯片的图像处理组件设置在下采样组件之后。
可选地，该实施例中，所述方法还包括：
在接收所述第一开启指令之后，将所述独立显示芯片的输入端口与所述独立显示芯片的显示数据接收组件连通；其中，所述显示数据接收组件与所述下采样组件连接；
向所述系统级芯片发送第一传输指令，所述第一传输指令用于通知所述系统级芯片发送所述第一数据。
这样，独显芯片通过连通自身的接口和显示数据接收组件，能够将第一数据经由显示数据接收组件传输到下采样组件。而独显芯片在连通其输入端口与显示数据接收组件后，再通过第一传输指令告知SoC发送第一数据，能够实现对接收到的第一数据，及时有效地降低该第一数据的分辨率，以进行后续处理。
可选地，该实施例中，所述方法还包括：
在接收所述第一开启指令之后，接收所述系统级芯片发送的第一关闭指令；
根据所述第一关闭指令，将所述独立显示芯片的输出端口与所述独立显示芯片 的输入端口直接连通；
其中，所述独立显示芯片的输入端口与所述系统级芯片的输出端口连接，所述独立显示芯片的输出端口与显示驱动芯片的输入端口连接。
也就是说，SoC在发送第一开启指令之后，会向独显芯片发送第一关闭指令，来指示独显芯片将自身的输出端口与输入端口直接连通。这样，独显芯片后续接收到SoC的第一数据，不会经显示数据接收组件输出，而是经由独显芯片的模拟绕路(analog bypass)，将第一数据直接输出到DDIC，此时独显芯片内部的功能组件可以完成下电流程，降低耗电。
当然，相应的，SoC也会向DDIC发送第二关闭指令，指示DDIC关闭上采样组件，而DDIC关闭上采样组件后，会向SoC发送第二传输指令，通知SoC发送第一数据。
还需要知道的是，该实施例中，SoC会根据待发送的第一数据的需求，确定发送第一开启指令和第二开启指令，还是发送第一关闭指令和第二关闭指令。
另外，第一开启指令和第一关闭指令还可以理解为独显芯片的模式切换指令，即独显芯片会在接收到第一开启指令后，工作在第一模式：独显芯片的输入端口与其内的显示数据接收组件连通，下采样组件、图像处理组件开启；独显芯片会在接收到第一关闭指令后，工作在第二模式：独显芯片的输入端口与其输出端口连通，下采样组件、图像处理组件关闭。而第二开启指令和第二关闭指令还可以理解为DDIC的模式切换指令，即DDIC会在接收到第二开启指令后，工作在第一模式：上采样组件开启；DDIC会在接收到第二关闭指令后，工作在第二模式：上采样组件关闭。
如图2所示，本申请实施例还提供了一种数据处理方法，应用于显示驱动芯片，所述方法包括：
步骤201，接收系统级芯片发送的第二开启指令。
这里，第二开启指令是SoC发送的，指示DDIC增大从独显芯片接收到的第二数据的分辨率的指令。
步骤202，根据所述第二开启指令，在获取到独立显示芯片发送的第二数据的情况下，增大所述第二数据的分辨率，得到第三数据；
其中，所述第三数据的分辨率等于第一数据的分辨率，所述第一数据是所述系统级芯片发送的图像数据。
如此，对于独显芯片发送的第二数据，DDIC能够基于接收的第二开启指令，增大该第二数据的分辨率，使得所得的第三数据恢复到原分辨率，转换为panel驱动信号，完成显示驱动，实现更高质量的显示。
可选地，该实施例中，增大所述第二数据的分辨率包括：
通过开启所述显示驱动芯片内的上采样组件对所述第二数据进行上采样。
也就是说，DDIC预先配置有上采样(Upscale)组件，DDIC接收到第二开启指令后，就能够开启该上采样组件，对接收的第二数据进行上采样，恢复到原分辨率。
可选地，该实施例中，所述方法还包括：
在接收所述第二开启指令之后，接收所述系统级芯片发送的第二关闭指令；
根据所述第二关闭指令，关闭所述上采样组件并发送第二传输指令，所述第二传输指令用于通知所述系统级芯片发送所述第一数据；
接收到经由所述独立显示芯片传输的所述第一数据。
故，DDIC按照第二关闭指令关闭上采样组件后，还能够通过发送第二传输指令，通知SoC发送第一数据，独显芯片接收到该第一数据后直接经analog bypass输出到DDIC，DDIC接收到该第一数据后，完成信号处理和显示驱动工作。
该实施例中，DDIC内配置显示数据接收组件、与该显示数据接收组件连接的信号处理单元、与该信号处理单元连接的源级驱动电路。其中，该显示数据接收组件用于接收独显芯片发送的第一数据或第二数据；该信号处理单元包括上采样组件，能够在开启时实现对第二数据的上采样。
如图3所示，本申请实施例的一种数据处理方法，应用于系统级芯片，所述方法包括：
步骤301，向显示驱动芯片发送第二开启指令；
步骤302，在发送所述第二开启指令之后，向独立显示芯片发送第一开启指令；
其中，所述第一开启指令用于指示所述独立显示芯片降低所述系统级芯片发送的第一数据的分辨率后通过处理得到第二数据；所述第二开启指令用于指示所述显示驱动芯片增大所述第二数据的分辨率得到第三数据；
所述第一数据的分辨率大于或等于第一阈值；所述第二数据的分辨率小于所述第一阈值；所述第三数据的分辨率等于所述第一数据的分辨率。
如此，按照上述步骤，SoC会先向DDIC发送第二启动指令，指示DDIC在接收到第二数据后，增大第二数据的分辨率得到第三数据；然后向独显芯片发送第一启动指令，指示独显芯片在接收到第一数据后，先降低第一数据的分辨率，然后对分辨率降低的第一数据进行处理后得到第二数据发送给DDIC，确保DDIC得到的第三数据恢复到原分辨率，转换为显示面板(panel)驱动信号，完成显示驱动，实现更高质量的显示。
可选地，所述方法还包括：
接收独显芯片发送的第一传输指令；
根据所述第一传输指令发送所述第一数据。
从而，SoC能够在独显芯片准备完成后，向独显芯片发送第一数据，独显芯片降低该第一数据的分辨率后，进一步进行处理得到第二数据，并发送至DDIC。
可选地，所述方法还包括：
接收DDIC发送的第二传输指令；
根据所述第二传输指令发送所述第一数据。
从而，SoC能够在DDIC关闭上采样组件后，向独显芯片发送第一数据，独显芯片接收到该第一数据后直接经analog bypass输出到DDIC。
可选地，所述方法还包括：
向所述独立显示芯片发送第一关闭指令；
其中，所述第一关闭指令用于指示所述独立显示芯片将自身的输出端口与输入端口直接连通。
即，使得独显芯片能够按照第一关闭指令将自身的输出端口与输入端口直接连通。这样，独显芯片后续接收到SoC的第一数据，不会经显示数据接收组件输出，而是经由analog bypass，将第一数据直接输出到DDIC。
可选地，所述方法还包括：
向所述显示驱动芯片发送第二关闭指令；
其中，所述第二关闭指令用于指示所述显示驱动芯片关闭上采样组件。
即，使得DDIC关闭上采样组件。这样，DDIC接收到的独显芯片输出的第一数据后，无需上采样，直接完成信号处理和显示驱动工作。
如图4所示，本申请实施例提供了一种数据处理系统，包括独立显示芯片、显示驱动芯片和系统级芯片；
所述系统级芯片用于：向所述显示驱动芯片发送第二开启指令，并在发送所述第二开启指令之后，向所述独立显示芯片发送第一开启指令；
所述独立显示芯片用于：接收所述第一开启指令之后，根据所述第一开启指令，降低获取到的第一数据的分辨率，以及对分辨率降低后的所述第一数据进行处理，得到第二数据，并向所述显示驱动芯片发送所述第二数据；
所述显示驱动芯片用于：接收所述第二开启指令之后，根据所述第二开启指令，在获取到独立显示芯片发送的第二数据的情况下，增大所述第二数据的分辨率，得到第三数据；
其中，所述第一数据是所述系统级芯片发送的图像数据，所述第一数据的分辨率大于或等于第一阈值；所述第二数据的分辨率小于所述第一阈值；所述第三数据的分辨率等于所述第一数据的分辨率。
故，SoC会先向DDIC发送第二启动指令，指示DDIC在接收到第二数据后，增大第二数据的分辨率得到第三数据；然后向独显芯片发送第一启动指令，指示独显芯片在接收到第一数据后，先降低第一数据的分辨率，然后对分辨率降低的第一数据进行处理后得到第二数据发送给DDIC。DDIC在获取到第二数据的情况下，就能够增大所述第二数据的分辨率得到第三数据。
这样，本申请实施例的数据处理系统，对于SoC发送的分辨率大于或等于第一 阈值的第一数据，由于独显芯片先降低了其分辨率，使得该独显芯片可以进一步实现图像数据的图像处理，保证了SoC和独显芯片的适配，提升了显示质量；而DDIC接收到第二数据后，会增大其分辨率恢复到原分辨率，在转换为panel驱动信号，完成显示驱动时，实现更高质量的显示。
可选地，如图4、图5所示，数据处理系统中，SoC包括显示数据发送组件DSI0，用于向独显芯片发送数据。
可选地，如图4、图5所示，数据处理系统中，独显芯片包括输入端口、显示数据接收组件DSI RX0、下采样组件、独显插帧组件(也称为运动估计与运动补偿组件)、上采样组件、显示数据发送组件DSI TX0、输出端口；其中，输入端口可以通过开关选择连通DSI RX0或输出端口，输出端口可以通过开关选择连通输入端口或DSI TX0，上采样组件在下采样组件开启时不工作。如图5所示，独显芯片还包括低功耗超分组件，当然，独显芯片还可以包括其它的图像处理组件。
可选地，如图4、图5所示，数据处理系统中，DDIC包括显示数据接收组件DSIRX、信号处理单元、源级驱动电路；其中，信号处理单元包括上采样组件。DDIC的源级驱动电路与显示面板连接。
可选地，该实施例中，
所述显示驱动芯片还用于：根据接收到的、所述系统级芯片发送的第二关闭指令，关闭上采样组件并向系统级芯片发送第二传输指令，所述第二传输指令用于通知所述系统级芯片发送所述第一数据；
所述独立显示芯片还用于：根据接收到的、所述系统级芯片发送的第一关闭指令，将自身的输出端口与输入端口直接连通，并在自身的输入端口接收到所述第一数据的情况下，直接通过自身的输出端口向所述显示驱动芯片发送所述第一数据。
也就是说，SoC会向独显芯片发送第一关闭指令，指示独显芯片将自身的输出端口与输入端口直接连通，且独显芯片还会关闭内部的功能组件。独显芯片后续接收到SoC的第一数据，将经由analog bypass将第一数据直接输出到DDIC。SoC也会向DDIC发送第二关闭指令，指示DDIC关闭上采样组件。
其中，SoC可以先发送第一关闭指令，再发送第二关闭指令，避免先关闭DDIC的上采样组件后，独显芯片输出的第二数据在显示面板出现显示异常的问题。DDIC关闭上采样组件后，再由第二传输指令通知SoC发送第一数据，保证正常显示。
可选地，所述独立显示芯片还用于：通过开启所述独立显示芯片内的下采样组件对所述第一数据进行下采样。
可选地，所述独立显示芯片还用于：对分辨率降低后的所述第一数据进行以下至少一项处理：
插帧；超分；降噪；色彩增强；色彩校准。
可选地，所述显示驱动芯片还用于：通过开启所述显示驱动芯片内的上采样组 件对所述第二数据进行上采样。
综上，本申请的数据处理系统中，在SoC输出的图像数据需要独显芯片进行图像处理的情况下，SoC会先向DDIC发送第二启动指令，DDIC接收到该第二启动指令后，开启上采样组件，等待独显芯片的第二数据。SoC在发送第二启动指令后，向独显芯片发送第一启动指令，独显芯片接收到该第一启动指令后，开启下采样组件以及图像处理的相关组件。之后，独显芯片还会向SoC发送第一传输指令，触发SoC发送第一数据。独显芯片接收第一数据后，先通过下采样降低第一数据的分辨率，然后进行图像处理，输出第二数据。DDIC接收第二数据后，先通过上采样恢复至原分辨率，然后完成数据的显示。
而在SoC输出的图像数据不需要独显芯片进行图像处理的情况下，SoC会先向独显芯片发送第一关闭指令，独显芯片接收到该第一关闭指令后，将自身的输入端口和输出端口连接，关闭下采样组件以及图像处理的相关组件。SoC在发送第一关闭指令之后，向DDIC发送第二关闭指令，DDIC接收到该第二启动指令后，关闭上采样组件。之后，DDIC还会向SoC发送第二传输指令，触发SoC发送第一数据。独显芯片接收第一数据后，直接经由analog bypass输出第一数据到DDIC。DDIC接收第一数据后，无需上采样，直接完成信号处理和显示驱动工作。
下面以SoC输出第一数据为WQHD分辨率图像数据，为例，在具体场景说明本申请实施例的数据处理系统的应用：
场景一、WQHD分辨率图像数据需要独显芯片的插帧处理
如图4所示，SoC在开启独显芯片的插帧组件前，需要先将显示模组初始化代码以及第二开启指令(如屏幕分辨率切换的命令)发送给DDIC，再发送第一开启指令给独显芯片。通过开启独显插帧功能，SoC发送的WQHD 72Hz图像数据在独显内部经过下采样和插帧处理后，不做上采样处理，直接输出FHD 144Hz图像数据给DDIC，由DDIC内部的上采样组件将图像分辨率提升到WQHD。
具体的，开启独显插帧功能的步骤如下：
1)SoC停止输出第一数据；
2)SoC输出FHD Panel初始化代码(Operation code，简称OP code)以及第二开启指令给DDIC，DDIC收到第二开启指令后启动上采样组件；
3)SoC向独显芯片发送第一开启指令，独显芯片完成bypass模式(第二模式)到插帧模式(第一模式)的切换，具体步骤包括：
i.独显芯片上电，初始化DSI RX0、DSI TX0、插帧组件和下采样组件；
ii.独显芯片切换内部开关(mipi switch)，将DSI RX0接口与SoC DSI0接口相连接；
iii.独显芯片的DSI RX0向SoC发送第一传输指令(如TE信号)，通知SoC输出第一数据；
4)SoC接到第一传输指令后，输出WQHD 72Hz图像数据给独显芯片，独显芯片接收WQHD 72Hz图像数据后，先经过下采样组件处理成FHD 72Hz图像数据，再由MEMC组件插帧至FHD 144Hz图像数据，最后不经过上采样组件处理，由DSI TX0输出FHD 144Hz图像数据给DDIC；
5)DDIC的DSI RX接收来自独显芯片的FHD 144Hz图像数据后，经过信号处理单元的上采样组件处理成WQHD 144Hz图像数据后再转换为面板驱动信号，完成显示驱动。
场景二、WQHD分辨率图像数据不需要独显芯片的插帧处理
如图4所示，已开启独显插帧功能的SoC，先向独显芯片发送第一关闭指令和后向DDIC发送第二关闭指令，关闭独显插帧功能。
具体的，关闭独显插帧功能的步骤如下：
1)SoC停止输出第一数据；
2)SoC向独显芯片发送第一关闭指令，完成插帧模式到bypass模式的切换，具体步骤包括：
i.独显芯片停止DSI TX0输出第一数据，停止向SoC发送TE信号；
ii.独显芯片切换内部mipi switch，将SoC的DSI0接口与DDIC的DSI RX接口相连，也就是说，独显芯片的输入端口和输出端口连通，如此后续第一数据可不经过独显芯片内部的功能组件(独显进入bypass模式)；
iii.独显芯片关闭DSI RX0、DSI TX0、插帧组件、上采样组件，完成下电流程；
3)SoC输出WQHD panel OP code以及第二关闭指令(如屏幕分辨率切换(FHD→WQHD)的命令)给DDIC，DDIC收到第二关闭指令后将上采样组件关闭，并发送第二传输指令(如TE信号)给SoC；
4)SoC接收第二传输指令，由DSI0接口输出第一数据给DDIC；其中，第一数据由根据屏幕分辨率设定以及游戏/视频源帧率确定；
5)DDIC的DSI RX接收来自SoC的第一数据，完成信号处理和显示驱动工作。
对于规格上不支持WQHD 144Hz输出的独显芯片在系统分辨率设置为WQHD时实现144Hz插帧功能。
独显芯片接收WQHD分辨率图像数据后，通过先做下采样到FHD或更低分辨率再做后续处理，这样独显芯片需要处理的数据量可以降低，输出帧率可以提升；独显芯片输出低分辨率、高帧率图像数据给DDIC后，由DDIC做上采样处理。由于独显芯片仅需传输低分辨率图像数据，且DDIC上采样组件的功耗较低，插帧功能开启时独显单体功耗和整机功耗都可以降低。
场景三、WQHD分辨率图像数据需要独显芯片的插帧、超分处理
如图5所示，独显芯片内部增加低功耗超分组件，可以对图像数据进行抗锯齿、锐化处理，提升图像清晰度。具体步骤与场景一相同，只是在开启插帧组件后再多 开启一个低功耗超分组件。
场景四、WQHD分辨率图像数据不需要独显芯片的插帧、超分处理
具体步骤与场景二相同，只是在关闭插帧组件后再多关闭一个低功耗超分组件。
需要说明的是，该数据处理系统可以用于手机显示屏，同样可适配与平板、笔记本电脑、车载、手表屏等。
本申请实施例提供的数据处理方法，执行主体可以为数据处理装置。本申请实施例中以数据处理装置执行数据处理方法为例，说明本申请实施例提供的数据处理装置。
如图6所示，本申请实施例的一种数据处理装置600，包括：
第一接收模块610，用于接收系统级芯片发送的第一开启指令；
第一处理模块620，用于根据所述第一开启指令，降低获取到的第一数据的分辨率，并对分辨率降低后的所述第一数据进行处理，得到第二数据；
第一发送模块630，用于将所述第二数据发送至显示驱动芯片；
其中，所述第一数据是所述系统级芯片发送的图像数据，所述第一数据的分辨率大于或等于第一阈值；所述第二数据的分辨率小于所述第一阈值。
可选地，所述第一处理模块还用于：
通过开启所述独立显示芯片内的下采样组件对所述第一数据进行下采样。
可选地，所述第一处理模块还用于：对分辨率降低后的所述第一数据进行以下至少一项处理：插帧；超分；降噪；色彩增强；色彩校准。
可选地，所述装置还包括：
第三处理模块，用于在接收所述第一开启指令之后，将所述独立显示芯片的输入端口与所述独立显示芯片的显示数据接收组件连通；其中，所述显示数据接收组件与所述下采样组件连接；
第三发送模块，用于向所述系统级芯片发送第一传输指令，所述第一传输指令用于通知所述系统级芯片发送所述第一数据。
可选地，所述装置还包括：
第三接收模块，用于在接收所述第一开启指令之后，接收所述系统级芯片发送的第一关闭指令；
第四处理模块，用于根据所述第一关闭指令，将所述独立显示芯片的输出端口与所述独立显示芯片的输入端口直接连通；
其中，所述独立显示芯片的输入端口与所述系统级芯片的输出端口连接，所述独立显示芯片的输出端口与显示驱动芯片的输入端口连接。
本申请实施例提供的数据处理装置能够实现图1的方法实施例实现的各个过程，为避免重复，这里不再赘述。
如图7所示，本申请实施例的一种数据处理装置700，包括：
第二接收模块710，用于接收系统级芯片发送的第二开启指令；
第二处理模块720，用于根据所述第二开启指令，在获取到独立显示芯片发送的第二数据的情况下，增大所述第二数据的分辨率，得到第三数据；
其中，所述第三数据的分辨率等于第一数据的分辨率，所述第一数据是所述系统级芯片发送的图像数据。
可选地，所述第二处理模块还用于：
通过开启所述显示驱动芯片内的上采样组件对所述第二数据进行上采样。
可选地，所述装置还包括：
第四接收模块，用于在接收所述第二开启指令之后，接收所述系统级芯片发送的第二关闭指令；
第五处理模块，用于根据所述第二关闭指令，关闭所述上采样组件并发送第二传输指令，所述第二传输指令用于通知所述系统级芯片发送所述第一数据；
第五接收模块，用于接收到经由所述独立显示芯片传输的所述第一数据。
本申请实施例提供的数据处理装置能够实现图2的方法实施例实现的各个过程，为避免重复，这里不再赘述。
如图8所示，本申请实施例的一种数据处理装置800，包括：
第二发送模块810，用于向显示驱动芯片发送第二开启指令，并在发送所述第二开启指令之后，向独立显示芯片发送第一开启指令；
其中，所述第一开启指令用于指示所述独立显示芯片降低所述系统级芯片发送的第一数据的分辨率后通过处理得到第二数据；所述第二开启指令用于指示所述显示驱动芯片增大所述第二数据的分辨率得到第三数据；
所述第一数据的分辨率大于或等于第一阈值；所述第二数据的分辨率小于所述第一阈值；所述第三数据的分辨率等于所述第一数据的分辨率。
可选地，所述装置还包括：
第四发送模块，用于向所述独立显示芯片发送第一关闭指令；
其中，所述第一关闭指令用于指示所述独立显示芯片将自身的输出端口与输入端口直接连通。
可选地，所述装置还包括：
第五发送模块，用于向所述显示驱动芯片发送第二关闭指令；
其中，所述第二关闭指令用于指示所述显示驱动芯片关闭上采样组件。
本申请实施例提供的数据处理装置能够实现图3的方法实施例实现的各个过程，为避免重复，这里不再赘述。
本申请实施例还提供一种电子设备，包括如上所述的数据处理系统。
需要说明的是，本申请实施例中的电子设备包括上述所述的移动电子设备和非移动电子设备。
图9为实现本申请实施例的一种电子设备的硬件结构示意图。
该电子设备900包括但不限于：射频单元901、网络模块902、音频输出单元903、输入单元904、传感器905、显示单元906、用户输入单元907、接口单元908、存储器909、以及处理器910等部件。
本领域技术人员可以理解，电子设备900还可以包括给各个部件供电的电源(比如电池)，电源可以通过电源管理系统与处理器910逻辑相连，从而通过电源管理系统实现管理充电、放电、以及功耗管理等功能。图9中示出的电子设备结构并不构成对电子设备的限定，电子设备可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置，在此不再赘述。
其中，电子设备900还包括如上所述的数据处理系统。
SoC会先向DDIC发送第二启动指令，指示DDIC在接收到第二数据后，增大第二数据的分辨率得到第三数据；然后向独显芯片发送第一启动指令，指示独显芯片在接收到第一数据后，先降低第一数据的分辨率，然后对分辨率降低的第一数据进行处理后得到第二数据发送给DDIC。DDIC在获取到第二数据的情况下，就能够增大所述第二数据的分辨率得到第三数据。
这样，对于SoC发送的分辨率大于或等于第一阈值的第一数据，由于独显芯片先降低了其分辨率，使得该独显芯片可以进一步实现图像数据的图像处理，保证了SoC和独显芯片的适配，提升了显示质量；而DDIC接收到第二数据后，会增大其分辨率恢复到原分辨率，在转换为panel驱动信号，完成显示驱动时，实现更高质量的显示。
应理解的是，本申请实施例中，输入单元904可以包括图形处理器(Graphics Processing Unit，GPU)9041和麦克风9042，图形处理器9041对在视频捕获模式或图像捕获模式中由图像捕获装置(如摄像头)获得的静态图片或视频的图像数据进行处理。显示单元906可包括显示面板9061，可以采用液晶显示器、有机发光二极管等形式来配置显示面板9061。用户输入单元907包括触控面板9071以及其他输入设备9072中的至少一种。触控面板9071，也称为触摸屏。触控面板9071可包括触摸检测装置和触摸控制器两个部分。其他输入设备9072可以包括但不限于物理键盘、功能键(比如音量控制按键、开关按键等)、轨迹球、鼠标、操作杆，在此不再赘述。
存储器909可用于存储软件程序以及各种数据。存储器909可主要包括存储程序或指令的第一存储区和存储数据的第二存储区，其中，第一存储区可存储操作系统、至少一个功能所需的应用程序或指令(比如声音播放功能、图像播放功能等)等。此外，存储器909可以包括易失性存储器或非易失性存储器，或者，存储器909可以包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(Read-Only Memory，ROM)、可编程只读存储器(Programmable ROM，PROM)、可擦除可编程只读存储器(Erasable PROM，EPROM)、电可擦除可编程只读存储器 (Electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(Random Access Memory，RAM)，静态随机存取存储器(Static RAM，SRAM)、动态随机存取存储器(Dynamic RAM，DRAM)、同步动态随机存取存储器(Synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(Double Data Rate SDRAM，DDRSDRAM)、增强型同步动态随机存取存储器(Enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(Synch link DRAM，SLDRAM)和直接内存总线随机存取存储器(Direct Rambus RAM，DRRAM)。本申请实施例中的存储器909包括但不限于这些和任意其它适合类型的存储器。
处理器910可包括一个或多个处理单元；可选的，处理器910集成应用处理器和调制解调处理器，其中，应用处理器主要处理涉及操作系统、用户界面和应用程序等的操作，调制解调处理器主要处理无线通信信号，如基带处理器。可以理解的是，上述调制解调处理器也可以不集成到处理器910中。
本申请实施例还提供一种可读存储介质，所述可读存储介质上存储有程序或指令，该程序或指令被处理器执行时实现上述数据处理方法实施例的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。
其中，所述处理器为上述实施例中所述的电子设备中的处理器。所述可读存储介质，包括计算机可读存储介质，如计算机只读存储器ROM、随机存取存储器RAM、磁碟或者光盘等。
各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。
应理解，本申请实施例提到的系统级芯片还可以称为系统芯片、芯片系统或片上系统芯片等。
本申请实施例提供一种计算机程序产品，该程序产品被存储在存储介质中，该程序产品被至少一个处理器执行以实现如上述数据处理方法实施例的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。此外，需要指出的是，本申请实施方式中的方法和装置的范围不限按示出或讨论的顺序来执行功能，还可包括根据所涉及的功能按基本同时的方式或按相反的顺序来执行功能，例如，可以按不同于所描述的次序来执行所描述的方法，并且还可以添加、省去、或组合各种步骤。另外，参照某些示例所描述的特征可在其他示例中被组合。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到上述实施例 方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分可以以计算机软件产品的形式体现出来，该计算机软件产品存储在一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端(可以是手机，计算机，服务器，或者网络设备等)执行本申请各个实施例所述的方法。
上面结合附图对本申请的实施例进行了描述，但是本申请并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本申请的启示下，在不脱离本申请宗旨和权利要求所保护的范围情况下，还可做出很多形式，均属于本申请的保护之内。

Claims (30)

  1. 一种数据处理方法，应用于独立显示芯片，所述方法包括：
    接收系统级芯片发送的第一开启指令；
    根据所述第一开启指令，降低获取到的第一数据的分辨率，并对分辨率降低后的所述第一数据进行处理，得到第二数据；
    将所述第二数据发送至显示驱动芯片；
    其中，所述第一数据是所述系统级芯片发送的图像数据，所述第一数据的分辨率大于或等于第一阈值；所述第二数据的分辨率小于所述第一阈值。
  2. 根据权利要求1所述的方法，其中，降低获取到的第一数据的分辨率包括：
    通过开启所述独立显示芯片内的下采样组件对所述第一数据进行下采样。
  3. 根据权利要求1所述的方法，其中，对分辨率降低后的所述第一数据进行以下至少一项处理：
    插帧；超分；降噪；色彩增强；色彩校准。
  4. 根据权利要求2所述的方法，其中，所述方法还包括：
    在接收所述第一开启指令之后，将所述独立显示芯片的输入端口与所述独立显示芯片的显示数据接收组件连通；其中，所述显示数据接收组件与所述下采样组件连接；
    向所述系统级芯片发送第一传输指令，所述第一传输指令用于通知所述系统级芯片发送所述第一数据。
  5. 根据权利要求1所述的方法，其中，所述方法还包括：
    在接收所述第一开启指令之后，接收所述系统级芯片发送的第一关闭指令；
    根据所述第一关闭指令，将所述独立显示芯片的输出端口与所述独立显示芯片的输入端口直接连通；
    其中，所述独立显示芯片的输入端口与所述系统级芯片的输出端口连接，所述独立显示芯片的输出端口与显示驱动芯片的输入端口连接。
  6. 一种数据处理方法，应用于显示驱动芯片，其中，所述方法包括：
    接收系统级芯片发送的第二开启指令；
    根据所述第二开启指令，在获取到独立显示芯片发送的第二数据的情况下，增大所述第二数据的分辨率，得到第三数据；
    其中，所述第三数据的分辨率等于第一数据的分辨率，所述第一数据是所述系统级芯片发送的图像数据。
  7. 根据权利要求6所述的方法，其中，增大所述第二数据的分辨率包括：
    通过开启所述显示驱动芯片内的上采样组件对所述第二数据进行上采样。
  8. 根据权利要求7所述的方法，其中，所述方法还包括：
    在接收所述第二开启指令之后，接收所述系统级芯片发送的第二关闭指令；
    根据所述第二关闭指令，关闭所述上采样组件并发送第二传输指令，所述第二传输指令用于通知所述系统级芯片发送所述第一数据；
    接收到经由所述独立显示芯片传输的所述第一数据。
  9. 一种数据处理方法，应用于系统级芯片，所述方法包括：
    向显示驱动芯片发送第二开启指令；
    在发送所述第二开启指令之后，向独立显示芯片发送第一开启指令；
    其中，所述第一开启指令用于指示所述独立显示芯片降低所述系统级芯片发送的第一数据的分辨率后通过处理得到第二数据；所述第二开启指令用于指示所述显示驱动芯片增大所述第二数据的分辨率得到第三数据；
    所述第一数据的分辨率大于或等于第一阈值；所述第二数据的分辨率小于所述第一阈值；所述第三数据的分辨率等于所述第一数据的分辨率。
  10. 根据权利要求9所述的方法，其中，所述方法还包括：
    向所述独立显示芯片发送第一关闭指令；
    其中，所述第一关闭指令用于指示所述独立显示芯片将自身的输出端口与输入端口直接连通。
  11. 根据权利要求9所述的方法，其中，所述方法还包括：
    向所述显示驱动芯片发送第二关闭指令；
    其中，所述第二关闭指令用于指示所述显示驱动芯片关闭上采样组件。
  12. 一种数据处理装置，包括：
    第一接收模块，用于接收系统级芯片发送的第一开启指令；
    第一处理模块，用于根据所述第一开启指令，降低获取到的第一数据的分辨率，并对分辨率降低后的所述第一数据进行处理，得到第二数据；
    第一发送模块，用于将所述第二数据发送至显示驱动芯片；
    其中，所述第一数据是所述系统级芯片发送的图像数据，所述第一数据的分辨率大于或等于第一阈值；所述第二数据的分辨率小于所述第一阈值。
  13. 根据权利要求12所述的装置，其中，所述第一处理模块还用于：
    通过开启所述独立显示芯片内的下采样组件对所述第一数据进行下采样。
  14. 根据权利要求12所述的装置，其中，所述第一处理模块还用于：
    对分辨率降低后的所述第一数据进行以下至少一项处理：插帧；超分；降噪；色彩增强；色彩校准。
  15. 根据权利要求13所述的装置，其中，所述装置还包括：
    第三处理模块，用于在接收所述第一开启指令之后，将所述独立显示芯片的输入端口与所述独立显示芯片的显示数据接收组件连通；其中，所述显示数据接收组件与所述下采样组件连接；
    第三发送模块，用于向所述系统级芯片发送第一传输指令，所述第一传输指令用于通知所述系统级芯片发送所述第一数据。
  16. 根据权利要求12所述的装置，其中，所述装置还包括：
    第三接收模块，用于在接收所述第一开启指令之后，接收所述系统级芯片发送的第一关闭指令；
    第四处理模块，用于根据所述第一关闭指令，将所述独立显示芯片的输出端口与所述独立显示芯片的输入端口直接连通；
    其中，所述独立显示芯片的输入端口与所述系统级芯片的输出端口连接，所述独立显示芯片的输出端口与显示驱动芯片的输入端口连接。
  17. 一种数据处理装置，包括：
    第二接收模块，用于接收系统级芯片发送的第二开启指令；
    第二处理模块，用于根据所述第二开启指令，在获取到独立显示芯片发送的第二数据的情况下，增大所述第二数据的分辨率，得到第三数据；
    其中，所述第三数据的分辨率等于第一数据的分辨率，所述第一数据是所述系统级芯片发送的图像数据。
  18. 根据权利要求17所述的装置，其中，所述第二处理模块还用于：
    通过开启所述显示驱动芯片内的上采样组件对所述第二数据进行上采样。
  19. 根据权利要求18所述的装置，其中，所述装置还包括：
    第四接收模块，用于在接收所述第二开启指令之后，接收所述系统级芯片发送的第二关闭指令；
    第五处理模块，用于根据所述第二关闭指令，关闭所述上采样组件并发送第二传输指令，所述第二传输指令用于通知所述系统级芯片发送所述第一数据；
    第五接收模块，用于接收到经由所述独立显示芯片传输的所述第一数据。
  20. 一种数据处理装置，包括：
    第二发送模块，用于向显示驱动芯片发送第二开启指令，并在发送所述第二开启指令之后，向独立显示芯片发送第一开启指令；
    其中，所述第一开启指令用于指示所述独立显示芯片降低系统级芯片发送的第一数据的分辨率后通过处理得到第二数据；所述第二开启指令用于指示所述显示驱动芯片增大所述第二数据的分辨率得到第三数据；
    所述第一数据的分辨率大于或等于第一阈值；所述第二数据的分辨率小于所述第一阈值；所述第三数据的分辨率等于所述第一数据的分辨率。
  21. 根据权利要求20所述的装置，其中，所述装置还包括：
    第四发送模块，用于向所述独立显示芯片发送第一关闭指令；
    其中，所述第一关闭指令用于指示所述独立显示芯片将自身的输出端口与输入端口直接连通。
  22. 根据权利要求20所述的装置，其中，所述装置还包括：
    第五发送模块，用于向所述显示驱动芯片发送第二关闭指令；
    其中，所述第二关闭指令用于指示所述显示驱动芯片关闭上采样组件。
  23. 一种数据处理系统，包括独立显示芯片、显示驱动芯片和系统级芯片；
    所述系统级芯片用于：向所述显示驱动芯片发送第二开启指令，并在发送所述第二开启指令之后，向所述独立显示芯片发送第一开启指令；
    所述独立显示芯片用于：接收所述第一开启指令之后，根据所述第一开启指令，降低获取到的第一数据的分辨率，以及对分辨率降低后的所述第一数据进行处理，得到第二数据，并向所述显示驱动芯片发送所述第二数据；
    所述显示驱动芯片用于：接收所述第二开启指令之后，根据所述第二开启指令，在获取到独立显示芯片发送的第二数据的情况下，增大所述第二数据的分辨率，得到第三数据；
    其中，所述第一数据是所述系统级芯片发送的图像数据，所述第一数据的分辨率大于或等于第一阈值；所述第二数据的分辨率小于所述第一阈值；所述第三数据的分辨率等于所述第一数据的分辨率。
  24. 根据权利要求23所述的系统，其中，
    所述显示驱动芯片还用于：根据接收到的、所述系统级芯片发送的第二关闭指令，关闭上采样组件并向系统级芯片发送第二传输指令，所述第二传输指令用于通知所述系统级芯片发送所述第一数据；
    所述独立显示芯片还用于：根据接收到的、所述系统级芯片发送的第一关闭指令，将自身的输出端口与输入端口直接连通，并在自身的输入端口接收到所述第一数据的情况下，直接通过自身的输出端口向所述显示驱动芯片发送所述第一数据。
  25. 根据权利要求23所述的系统，其中，所述独立显示芯片还用于：通过开启所述独立显示芯片内的下采样组件对所述第一数据进行下采样。
  26. 根据权利要求23所述的系统，其中，所述独立显示芯片还用于：对分辨率降低后的所述第一数据进行以下至少一项处理：
    插帧；超分；降噪；色彩增强；色彩校准。
  27. 根据权利要求23所述的系统，其中，所述显示驱动芯片还用于：通过开启所述显示驱动芯片内的上采样组件对所述第二数据进行上采样。
  28. 一种电子设备，包括如权利要求15至19任一项所述的数据处理系统。
  29. 一种可读存储介质，所述可读存储介质上存储程序或指令，所述程序或指令被处理器执行时实现如权利要求1至5任一项所述的数据处理方法的步骤，或者，实现如权利要求6至8任一项所述的数据处理方法的步骤，或者，实现如权利要求9至11任一项所述的数据处理方法的步骤。
  30. 一种计算机程序产品，所述程序产品被存储在存储介质中，所述程序产品被 至少一个处理器执行以实现如权利要求1至5任一项所述的数据处理方法的步骤，或者，实现如权利要求6至8任一项所述的数据处理方法的步骤，或者，实现如权利要求9至11任一项所述的数据处理方法的步骤。
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