WO2025001737A1 - 显示面板以及电子设备 - Google Patents

显示面板以及电子设备 Download PDF

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Publication number
WO2025001737A1
WO2025001737A1 PCT/CN2024/096430 CN2024096430W WO2025001737A1 WO 2025001737 A1 WO2025001737 A1 WO 2025001737A1 CN 2024096430 W CN2024096430 W CN 2024096430W WO 2025001737 A1 WO2025001737 A1 WO 2025001737A1
Authority
WO
WIPO (PCT)
Prior art keywords
interface
pad
pin
circuit board
display panel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2024/096430
Other languages
English (en)
French (fr)
Inventor
包征
陈功
方远�
王明强
贺雪英
张燚
向炼
杨鹏
毕丹炀
张家祥
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Publication of WO2025001737A1 publication Critical patent/WO2025001737A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
    • H01R12/70—Coupling devices
    • H01R12/71—Coupling devices for rigid printing circuits or like structures
    • H01R12/72—Coupling devices for rigid printing circuits or like structures coupling with the edge of the rigid printed circuits or like structures
    • H01R12/73—Coupling devices for rigid printing circuits or like structures coupling with the edge of the rigid printed circuits or like structures connecting to other rigid printed circuits or like structures
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits

Definitions

  • the present application relates to a display panel and an electronic device.
  • Wearable devices usually include a display panel.
  • the display panel includes a display substrate and a driver chip and a flexible circuit board bound to the display substrate.
  • the MIPI protocol is usually used to transmit signals between the driver chip, the flexible circuit board and the display substrate.
  • the MIPI protocol can transmit high-speed signals, has a large amount of data, low power consumption and good anti-interference performance. However, when in AOD (always on display) mode, high-speed signals do not need to be transmitted and the amount of data is also small. At this time, the use of the MIPI protocol will not be conducive to reducing the burden on the system and reducing power consumption.
  • a display panel comprising: a display substrate having a display area and a wiring area, the display area comprising a plurality of pixel units, the wiring area being provided with a plurality of pins, the plurality of pins comprising a first pin; a driving chip mounted on the wiring area of the display substrate, having a plurality of interfaces, the plurality of interfaces comprising an enable interface, the enable interface being configured to control the use of a communication protocol, the enable interface being electrically connected to the first pin; a circuit board having a plurality of gold fingers, the plurality of gold fingers comprising a first gold finger, the plurality of gold fingers of the circuit board being connected to the plurality of pins, the first gold finger being connected to the first pin; wherein the enable interface can be applied with a first potential signal and a second potential signal through the circuit board; when the first potential signal is applied to the enable interface, the communication protocol is not used; when the second potential signal is applied to the enable interface
  • the communication protocol comprises a QSPI protocol.
  • the MIPI communication protocol is used.
  • the plurality of gold fingers of the circuit board are connected to the plurality of pins by binding, and the first gold finger is connected to the first pin by binding.
  • the first potential signal is a high potential
  • the second potential signal is a low potential
  • the multiple interfaces also include a second interface and a third interface, one of the second interface and the third interface is used to provide a first potential signal, and the other is used to provide a second potential signal;
  • the multiple pins also include a second pin and a third pin, the second interface is electrically connected to the second pin, and the third interface is electrically connected to the third pin;
  • the multiple gold fingers also include a second gold finger and a third gold finger, the second gold finger is connected to the second pin, and the third gold finger is connected to the third pin;
  • the circuit board also has multiple pads, the multiple pads include a first pad, a second pad and a third pad, the first pad is electrically connected to the first gold finger, the second pad is electrically connected to the second gold finger, and the third pad is electrically connected to the third gold finger; the first pad is selectively connected to the second pad or the third pad.
  • the second golden finger is connected to the second pin by binding
  • the third golden finger is connected to the third pin by binding
  • the second pad and the third pad are both adjacent to the first pad, and the second pad and the third pad are disposed on different sides of the first pad.
  • the first pad and the second pad are connected via a conductive body disposed on the surface of the circuit board; or, the first pad and the third pad are connected via a conductive body disposed on the surface of the circuit board.
  • the circuit board also has a fifth solder pad and a board-to-board interface
  • the fifth solder pad has a first potential, which is used to provide a first potential signal to the first gold finger, and a resistor element is connected between the fifth solder pad and the first gold finger
  • the board-to-board interface is electrically connected to the first gold finger, and the board-to-board interface can switch between a first state and a second state, in the first state, the board-to-board interface is in a high-impedance state or a floating state
  • the board-to-board interface has a second potential, which provides a second potential signal to the enable interface.
  • the fifth pad is connected to ground.
  • the multiple interfaces also include a second interface, which is used to selectively provide a first potential signal or a second potential signal;
  • the multiple pins also include a second pin, and the second interface is electrically connected to the second pin;
  • the multiple gold fingers also include a second gold finger, the second gold finger is connected to the second pin, and the second gold finger is electrically connected to the first gold finger.
  • the second interface is a GPIO interface; the second interface switches to output the first potential signal or the second potential signal in a programmed manner.
  • an electronic device includes the display panel as described above.
  • FIG1 is a schematic diagram of a structure of a display panel applied to a wearable device
  • FIG2 is a schematic diagram of circuit connections of a portion of the structure of the display panel shown in FIG1 ;
  • FIG3 is a schematic diagram of the structure of a display panel according to an embodiment of the present application.
  • FIG4 is a schematic diagram of a use state of the display panel shown in FIG3 ;
  • FIG5 is a schematic diagram of the display panel shown in FIG3 in another use state
  • FIG6 is a schematic diagram of the structure of a display panel according to another embodiment of the present application.
  • FIG7 is a schematic diagram of a use state of the display panel shown in FIG6 ;
  • FIG8 is a schematic diagram of another use state of the display panel shown in FIG6 ;
  • FIG9 is a schematic structural diagram of a display panel according to another embodiment of the present application.
  • FIG10 is a schematic structural diagram of a display panel according to another embodiment of the present application.
  • 11 to 18 are schematic diagrams of a method for manufacturing a circuit board according to an embodiment of the present application.
  • Some power interfaces J1 on the driver chip 40 need to lead out signals to connect capacitors C to the circuit board 60.
  • One end (or one plate) B1 of the capacitor C is connected to the power interface J1 of the driver chip 40, and the other end (or another plate) B2 is grounded.
  • the external capacitor C plays a filtering role.
  • the capacitor C will lead out the clutter signal and import it into the ground, thereby filtering out the clutter.
  • components such as TVS (Transient Voltage Suppressors), diodes, Flash memories, ALS (Ambient Light Sensor), ZIF connectors, and magnetic beads will also be included.
  • Corresponding pads can be reserved on the circuit board 60, and these components can be installed on the surface of the circuit board 60 through SMT technology (Surface Mount Technology).
  • Wearable devices often use the MIPI (Mobile Industry Processor Interface) protocol to transmit signals, which can transmit high-speed signals, with large data volume, low power consumption and good anti-interference performance.
  • MIPI Mobile Industry Processor Interface
  • AOD Advanced Driver Assistance Device
  • QSPI Quadrature Serial peripheral interface
  • the driving chip 40 is installed in the wiring area 25 of the display substrate 20, and has multiple interfaces J, which include an enable interface J1 (i.e., EN interface or EN PIN).
  • the enable interface J1 is configured to control the use of a specific communication protocol, and the enable interface J1 is electrically connected to the first pin P3.
  • the enabling interface J1 can be applied with a first potential signal or a second potential signal through the circuit board 60.
  • the enabling interface J1 is applied with the first potential signal, the specific communication protocol is not used; when the enabling interface is applied with the second potential signal, the specific communication protocol is used.
  • the specific communication protocol can be selected for use or not. This is conducive to giving full play to the advantages of the communication protocol and avoiding its disadvantages. For example, when it is detected that it is at a time suitable for using the communication protocol, a second potential signal can be applied to the enabling interface to enable the specific communication protocol to be used. When it is detected that it is at a time not suitable for using the communication protocol, a first potential signal can be applied to the enabling interface to disable the specific communication protocol from being used.
  • the display area 23 is the main body of the display substrate 20, having a plurality of pixel units for displaying images; the wiring area 25 is located at an edge of the display substrate 20 to achieve electrical connection with external components. In some embodiments, the display area 23 is adjacent to the wiring area 25.
  • the plurality of pins P are located on a side of the wiring area 25 away from the display area 23 and are arranged along a straight line. In other embodiments, the plurality of pins P may also be arranged along multiple sides of the wiring area 25. For example, the plurality of pins P may be arranged along three outer sides of the wiring area 25 (excluding the side of the wiring area 25 adjacent to the display area 23).
  • the driver chip 40 is installed in the wiring area 25 by bonding. In some embodiments, the driver chip 40 is installed in the wiring area 25 by plugging. For example, the driver chip 40 is provided with a connector, and the wiring area 25 is provided with a matching connector. By plugging the connector into the matching connector, the driver chip 40 can be installed on the wiring area 25.
  • the enabling interface J1 can be electrically connected to the first pin P3 through a wire 28 in the wiring area 25.
  • the wire 28 is disposed inside the wiring area 25 of the display substrate 20.
  • the wire 28 is disposed on the surface of the wiring area 25 of the display substrate 20. For example, after the driver chip 40 is installed in the wiring area 25, a scattered wire is provided, one end of the wire is welded to the enabling interface J1, and the other end of the wire is welded to the first pin P3. The wire serves as the wire 28.
  • the communication protocol can be any communication protocol.
  • the communication protocol is a QSPI protocol.
  • the QSPI protocol is a (Queue Serial peripheral interface) communication protocol. It can be set that when the display panel is in AOD (Always on display) mode, the QSPI protocol is used. Because in AOD mode, the display panel does not need to transmit high-speed signals and the amount of data is also small, the use of the QSPI communication protocol is applicable and helps to reduce the workload of the driver chip. It can be further set that when the display panel is in other modes (for example, normal display), the QSPI protocol is not used, and other protocols are used.
  • the other protocols include the MIPI (Mobile Industry Processor Interface) protocol.
  • the MIPI protocol can transmit high-speed signals, has a large amount of data, low power consumption, and good anti-interference performance.
  • the plurality of gold fingers G of the circuit board 60 are connected to the plurality of pins P by bonding, and the first gold finger G3 is connected to the first pin P3 by bonding.
  • the plurality of gold fingers G are located on a side of the circuit board 60 adjacent to the wiring area 25 and are arranged along a straight line.
  • the circuit board 60 is a flexible printed circuit (FPC).
  • FPC flexible printed circuit
  • the first potential signal is a high potential
  • the second potential signal is a low potential, that is, when a high potential signal is applied to the enable interface J1, the specific communication protocol is not used; when a low potential signal is applied to the enable interface J1, the specific communication protocol is used.
  • the plurality of interfaces J further include a second interface J3 and a third interface J6, the second interface J3 is used to provide a first potential signal, and the third interface J6 is used to provide a second potential signal;
  • the plurality of pins P further include a second pin P5 and a third pin P8.
  • the second interface J3 is electrically connected to the second pin P5, and the third interface J6 is electrically connected to the third pin P8.
  • the plurality of gold fingers G further include a second gold finger G5 and a third gold finger G8, the second gold finger G5 is connected to the second pin P5, and the third gold finger G8 is connected to the third pin P8.
  • the circuit board 60 also has a plurality of pads, including a first pad S1, a second pad S2 and a third pad S3, the first pad S1 is electrically connected to the first gold finger G3, the second pad S2 is electrically connected to the second gold finger G5, and the third pad S3 is electrically connected to the third gold finger G8.
  • the above connection makes: the first pad S1 electrically connected to the enabling interface J1; the second pad S2 electrically connected to the second interface J3 and having a first potential; the third pad S3 electrically connected to the third interface J6 and having a second potential.
  • the first pad S1 and the second pad S2 can be connected, as shown in FIG4 , so that the enable interface J1 is connected to the first potential signal; at this time, the third interface J6 with the second potential and the third pad S3 are in a floating state.
  • the first pad S1 and the third pad S3 can be connected, as shown in Figure 5, so that the enable interface J1 is connected to the second potential signal; at this time, the second interface J3 with the first potential and the second pad S2 are in a floating state.
  • the second interface J3 can be electrically connected to the second pin P5 via a wiring 28 in the wiring area 25; the third interface J6 can be electrically connected to the third pin P8 via a wiring 28 in the wiring area 25.
  • the wiring 28 for connecting the second interface J3 to the second pin P5 and/or the wiring 28 for connecting the third interface J6 to the third pin P8 is disposed inside the wiring area 25 of the display substrate 20.
  • the wiring 28 for connecting the second interface J3 to the second pin P5 and/or the wiring 28 for connecting the third interface J6 to the third pin P8 is disposed inside the wiring area 25 of the display substrate 20. The surface of the wiring area 25.
  • two scattered wires are provided, so that: one end of the first wire is welded to the second interface J3, and the other end of the first wire is welded to the second pin P5; one end of the second wire is welded to the third interface J6, and the other end of the second wire is welded to the third pin P8.
  • the second gold finger G5 is connected to the second pin P5 by binding
  • the third gold finger G8 is connected to the third pin P8 by binding.
  • the first pad S1 can be electrically connected to the first gold finger G3 through a trace 68 in the circuit board 60.
  • the trace 68 is disposed inside the circuit board 60.
  • the trace 68 is disposed on the surface of the circuit board 60.
  • a scattered wire is provided, one end of the wire is welded to the first pad S1, and the other end of the wire is welded to the first gold finger G3.
  • the wire serves as the trace 68.
  • the second pad S2 can be electrically connected to the second gold finger G5 through a trace 68 in the circuit board 60.
  • the trace 68 is disposed inside the circuit board 60.
  • the trace 68 is disposed on the surface of the circuit board 60.
  • a scattered wire is provided, one end of the wire is welded to the second pad S2, and the other end of the wire is welded to the second gold finger G5. The wire serves as the trace 68.
  • the third pad S3 can be electrically connected to the third gold finger G8 through a trace 68 in the circuit board 60.
  • the trace 68 is disposed inside the circuit board 60.
  • the trace 68 is disposed on the surface of the circuit board 60.
  • a scattered wire is provided, one end of the wire is welded to the third pad S3, and the other end of the wire is welded to the third gold finger G8.
  • the wire serves as the trace 68.
  • the second pad S2 and the third pad S3 may be arranged adjacent to the first pad S1.
  • the second pad S2 and the third pad S3 may be arranged on different sides of the first pad S1.
  • the second pad S2 is arranged on the right side of the first pad S1
  • the third pad S3 is arranged on the lower side of the first pad S1.
  • the plurality of pads provided on the circuit board 60 may further include a fourth pad S4.
  • the fourth pad S4 may be a pad for grounding, used to provide a grounding path for the circuit board 60 or a component mounted on the circuit board 60. For example, when a capacitor component is mounted on the circuit board 60, one plate of the capacitor may be directly soldered to the fourth pad S4.
  • the first pad S1 and the second pad S2 can be connected by a conductive body 72 disposed on the surface of the circuit board 60.
  • the first pad S1 and the third pad S3 can be connected by a conductive body 74 disposed on the surface of the circuit board 60.
  • the conductive body 72 and the conductive body 74 are both good conductors, and their resistance values are small, which can be regarded as almost zero resistance.
  • the material of the conductive body 72 and the conductive body 74 can be copper, aluminum or silver.
  • the structure and manufacturing method of the conductive body 72 and the conductive body 74 can refer to the conductive body 51 in the subsequent Figure 18.
  • the display panel 200 may include a display substrate 20, a driving chip 40 and a circuit board 60.
  • the display substrate 20 has a display area 23 (AA area) and a wiring area 25 (Pad area).
  • the wiring area 25 is provided with a plurality of pins P, and the plurality of pins P include a first pin P3.
  • the circuit board 60 has a plurality of gold fingers G, the plurality of gold fingers G include a first gold finger G3, the plurality of gold fingers G of the circuit board 60 are connected to the plurality of pins P, and the first gold finger G3 is connected to the first pin P3.
  • the enabling interface J1 can be applied with a first potential signal or a second potential signal through the circuit board 60.
  • the enabling interface J1 is applied with the first potential signal, the specific communication protocol is not used; when the enabling interface is applied with the second potential signal, the specific communication protocol is used.
  • the specific communication protocol can be selected for use or not. This is conducive to giving full play to the advantages of the communication protocol and avoiding its disadvantages. For example, when it is detected that it is at a time suitable for using the communication protocol, a second potential signal can be applied to the enabling interface to enable the specific communication protocol to be used. When it is detected that it is at a time not suitable for using the communication protocol, a first potential signal can be applied to the enabling interface to disable the specific communication protocol from being used.
  • the display area 23 is the main body of the display substrate 20, having a plurality of pixel units for displaying images; the wiring area 25 is located at an edge of the display substrate 20 to achieve electrical connection with external components. In some embodiments, the display area 23 is adjacent to the wiring area 25.
  • the plurality of pins P are located on a side of the wiring area 25 away from the display area 23 and are arranged along a straight line. In other embodiments, the plurality of pins P may also be arranged along multiple sides of the wiring area 25. For example, the plurality of pins P may be arranged along three outer sides of the wiring area 25 (excluding the side of the wiring area 25 adjacent to the display area 23).
  • the driver chip 40 is installed in the wiring area 25 by bonding. In some embodiments, the driver chip 40 is installed in the wiring area 25 by plugging. For example, the driver chip 40 is provided with a connector, and the wiring area 25 is provided with a matching connector. By plugging the connector into the matching connector, the driver chip 40 can be installed on the wiring area 25.
  • the enabling interface J1 can be electrically connected to the first pin P3 through a wire 28 in the wiring area 25.
  • the wire 28 is disposed inside the wiring area 25 of the display substrate 20.
  • the wire 28 is disposed on the surface of the wiring area 25 of the display substrate 20. For example, after the driver chip 40 is installed in the wiring area 25, a scattered wire is provided, one end of the wire is welded to the enabling interface J1, and the other end of the wire is welded to the first pin P3. The wire serves as the wire 28.
  • the communication protocol can be any communication protocol.
  • the communication protocol is the QSPI protocol.
  • the QSPI protocol is a Queue Serial peripheral interface (Queue Serial Peripheral Interface) communication protocol. It can be set that when the display panel is in AOD (Always on display) mode, the QSPI protocol is used. Because in AOD mode, the display panel does not need to transmit high-speed signals and the amount of data is also small, the use of the QSPI communication protocol is suitable and helps to reduce the workload of the driver chip. It can be further set that when the display panel is in other modes (for example, normal display), the QSPI protocol is not used, and other protocols are used. Its protocols include MIPI (Mobile Industry Processor Interface) protocol. MIPI protocol can transmit high-speed signals, large data volume, low power consumption and good anti-interference performance.
  • MIPI Mobile Industry Processor Interface
  • the plurality of gold fingers G of the circuit board 60 are connected to the plurality of pins P by bonding, and the first gold finger G3 is connected to the first pin P3 by bonding.
  • the plurality of gold fingers G are located on a side of the circuit board 60 adjacent to the wiring area 25 and are arranged along a straight line.
  • the circuit board 60 is a flexible printed circuit (FPC).
  • FPC flexible printed circuit
  • the first potential signal is a high potential
  • the second potential signal is a low potential, that is, when a high potential signal is applied to the enable interface J1, the specific communication protocol is not used; when a low potential signal is applied to the enable interface J1, the specific communication protocol is used.
  • the plurality of interfaces J further include a second interface J3 and a third interface J6, the second interface J3 is used to provide a second potential signal, and the third interface J6 is used to provide a first potential signal;
  • the plurality of pins P further include a second pin P5 and a third pin P8.
  • the second interface J3 is electrically connected to the second pin P5, and the third interface J6 is electrically connected to the third pin P8.
  • the plurality of gold fingers G further include a second gold finger G5 and a third gold finger G8, the second gold finger G5 is connected to the second pin P5, and the third gold finger G8 is connected to the third pin P8.
  • the circuit board 60 also has a plurality of pads, including a first pad S1, a second pad S2 and a third pad S3, the first pad S1 is electrically connected to the first gold finger G3, the second pad S2 is electrically connected to the second gold finger G5, and the third pad S3 is electrically connected to the third gold finger G8.
  • the above connection makes: the first pad S1 electrically connected to the enabling interface J1; the second pad S2 electrically connected to the second interface J3 and having the second potential; the third pad S3 electrically connected to the third interface J6 and having the first potential.
  • the first pad S1 can be connected to the third pad S3, as shown in FIG7 , so that the enable interface J1 is connected to the first potential signal; at this time, the second interface J3 with the second potential and the second pad S2 are in a floating state.
  • the first pad S1 and the second pad S2 can be connected, as shown in Figure 8, so that the enable interface J1 is connected to the second potential signal; at this time, the third interface J6 with the first potential and the third pad S3 are in a floating state.
  • the second interface J3 can be electrically connected to the second pin P5 through a wiring 28 in the wiring area 25;
  • the third interface J6 can be electrically connected to the third pin P8 through a wiring 28 in the wiring area 25.
  • the wiring 28 for connecting the second interface J3 and the second pin P5 and/or the wiring 28 for connecting the third interface J6 and the third pin P8 are arranged inside the wiring area 25 of the display substrate 20.
  • the wiring 28 for connecting the second interface J3 and the second pin P5 and/or the wiring 28 for connecting the third interface J6 and the third pin P8 are arranged on the surface of the wiring area 25 of the display substrate 20.
  • two scattered wires are provided, so that: one end of the first wire is welded to the second interface J3, and the other end of the first wire is welded to the second pin P5; one end of the second wire is welded to the third interface J6, and the other end of the second wire is welded to the third pin P8.
  • the second gold finger G5 is connected to the second pin P5 by binding
  • the third gold finger G8 is connected to the third pin P8 by binding.
  • the first pad S1 can be electrically connected to the first gold finger G3 through a trace 68 in the circuit board 60.
  • the trace 68 is disposed inside the circuit board 60.
  • the trace 68 is disposed on the surface of the circuit board 60.
  • a scattered wire is provided, one end of the wire is welded to the first pad S1, and the other end of the wire is welded to the first gold finger G3.
  • the wire serves as the trace 68.
  • the second pad S2 can be electrically connected to the second gold finger G5 through a trace 68 in the circuit board 60.
  • the trace 68 is disposed inside the circuit board 60.
  • the trace 68 is disposed on the surface of the circuit board 60.
  • a scattered wire is provided, one end of the wire is welded to the second pad S2, and the other end of the wire is welded to the second gold finger G5. The wire serves as the trace 68.
  • the third pad S3 can be electrically connected to the third gold finger G8 through a trace 68 in the circuit board 60.
  • the trace 68 is disposed inside the circuit board 60.
  • the trace 68 is disposed on the surface of the circuit board 60.
  • a scattered wire is provided, one end of the wire is welded to the third pad S3, and the other end of the wire is welded to the third gold finger G8.
  • the wire serves as the trace 68.
  • the second pad S2 and the third pad S3 may be arranged adjacent to the first pad S1.
  • the second pad S2 and the third pad S3 may be arranged on different sides of the first pad S1.
  • the second pad S2 is arranged on the right side of the first pad S1
  • the third pad S3 is arranged on the lower side of the first pad S1.
  • the plurality of pads disposed on the circuit board 60 do not include a fourth pad for grounding.
  • the first pad S1 and the second pad S2 can be connected by a conductive body 85 disposed on the surface of the circuit board 60.
  • the first pad S1 and the third pad S3 can be connected by a conductive body 83 disposed on the surface of the circuit board 60.
  • the conductive body 85 and the conductive body 83 are both good conductors, and their resistance values are small, which can be almost regarded as zero resistance.
  • the material of the conductive body 85 and the conductive body 83 can be copper, aluminum or silver.
  • the structure and manufacturing method of the conductive body 85 and the conductive body 83 can refer to the conductive body 51 in the subsequent Figure 18.
  • FIG. 9 is a schematic structural diagram of a display panel 300 according to an embodiment of the present application.
  • the display panel 300 may include a display substrate 20, a driving chip 40 and a circuit board 60.
  • the display substrate 20 has a display area 23 (AA area) and a wiring area 25 (Pad area), and the wiring area 25 is provided with a plurality of pins P, and the plurality of pins P include a first pin P3.
  • the driving chip 40 is installed in the wiring area 25 of the display substrate 20, and has multiple interfaces J, which include an enable interface J1 (i.e., EN interface or EN PIN).
  • the enable interface J1 is configured to control the use of a specific communication protocol, and the enable interface J1 is electrically connected to the first pin P3.
  • the circuit board 60 has a plurality of gold fingers G, the plurality of gold fingers G include a first gold finger G3, the plurality of gold fingers G of the circuit board 60 are connected to the plurality of pins P, and the first gold finger G3 is connected to the first pin P3.
  • the enabling interface J1 can be applied with a first potential signal or a second potential signal through the circuit board 60.
  • the enabling interface J1 is applied with the first potential signal, the specific communication protocol is not used; when the enabling interface is applied with the second potential signal, the specific communication protocol is used.
  • the specific communication protocol can be selected for use or not. This is conducive to giving full play to the advantages of the communication protocol and avoiding its disadvantages. For example, when it is detected that it is at a time suitable for using the communication protocol, a second potential signal can be applied to the enabling interface to enable the specific communication protocol to be used. When it is detected that it is at a time not suitable for using the communication protocol, a first potential signal can be applied to the enabling interface to disable the specific communication protocol from being used.
  • the display area 23 is the main body of the display substrate 20, having a plurality of pixel units for displaying images; the wiring area 25 is located at an edge of the display substrate 20 to achieve electrical connection with external components. In some embodiments, the display area 23 is adjacent to the wiring area 25.
  • the plurality of pins P are located on a side of the wiring area 25 away from the display area 23 and are arranged along a straight line. In other embodiments, the plurality of pins P may also be arranged along multiple sides of the wiring area 25. For example, the plurality of pins P may be arranged along three outer sides of the wiring area 25 (excluding the side of the wiring area 25 adjacent to the display area 23).
  • the driver chip 40 is installed in the wiring area 25 by bonding. In some embodiments, the driver chip 40 is installed in the wiring area 25 by plugging. For example, the driver chip 40 is provided with a connector, and the wiring area 25 is provided with a matching connector. By plugging the connector into the matching connector, the driver chip 40 can be installed on the wiring area 25.
  • the enabling interface J1 can be electrically connected to the first pin P3 through a wire 28 in the wiring area 25.
  • the wire 28 is disposed inside the wiring area 25 of the display substrate 20.
  • the wire 28 is disposed on the surface of the wiring area 25 of the display substrate 20. For example, after the driver chip 40 is installed in the wiring area 25, a scattered wire is provided, one end of the wire is welded to the enabling interface J1, and the other end of the wire is welded to the first pin P3. The wire serves as the wire 28.
  • the communication protocol can be any communication protocol.
  • the communication protocol is the QSPI protocol.
  • the QSPI protocol is a Queue Serial peripheral interface (Queue Serial Peripheral Interface) communication protocol. It can be set that when the display panel is in AOD (Always on display) mode, the QSPI protocol is used. Because in AOD mode, the display panel does not need to transmit high-speed signals and the amount of data is also small, the use of the QSPI communication protocol is applicable and helps to reduce the workload of the driver chip. It can be further set that when the display panel is in other modes (for example, normal display), the QSPI protocol is not used, and other protocols are used.
  • the other protocols include the MIPI (Mobile Industry Processor Interface) protocol.
  • the MIPI protocol can transmit high-speed signals, has a large amount of data, low power consumption, and good anti-interference performance.
  • the plurality of gold fingers G of the circuit board 60 are connected to the plurality of pins P by bonding, and the first gold finger G3 is connected to the first pin P3 by bonding.
  • the plurality of gold fingers G are located on a side of the circuit board 60 adjacent to the wiring area 25 and are arranged along a straight line.
  • the circuit board 60 is a flexible printed circuit (FPC).
  • FPC flexible printed circuit
  • the first potential signal is a high potential
  • the second potential signal is a low potential, that is, when a high potential signal is applied to the enable interface J1, the specific communication protocol is not used; when a low potential signal is applied to the enable interface J1, the specific communication protocol is used.
  • the circuit board 60 also has a fifth pad SG and a board-to-board interface BP (i.e., B2BPIN).
  • the fifth pad SG has a first potential (i.e., a high potential) for providing a first potential signal to the first gold finger G3.
  • the fifth pad SG is a ground pad connected to the ground.
  • a resistor element R is also connected between the fifth pad SG and the first gold finger G3.
  • the board-to-board interface BP When the circuit board 60 is connected to other circuit boards, the board-to-board interface BP will be electrically connected to or in direct contact with the corresponding interface on the other circuit boards.
  • the other circuit boards can be connected to the controller of the electronic device to which the display panel 300 belongs, and provide signals to the board-to-board interface BP.
  • the board-to-board interface BP has two states, wherein the first state is to maintain a high impedance state (Hi-Z) or a floating state, and the second state is to be provided with a second potential signal and have a second potential (i.e., a low potential).
  • the board-to-board interface BP is electrically connected to the first gold finger G3.
  • another board-to-board interface is also included, and the other board-to-board interface is also used to be electrically connected to or in direct contact with the corresponding interface on the other circuit boards.
  • No resistor element may be inserted between the board-to-board interface BP and the first gold finger G3.
  • the board-to-board interface BP and the fifth pad SG may share a trace.
  • the first end of the resistor element R is connected to the fifth pad SG, and the second end of the resistor element R is connected to the first gold finger G3 via a trace 68;
  • the board-to-board interface BP is connected to the second end of the resistor element R or the trace 68 via a trace 69.
  • the trace 68 or a portion thereof is shared by the board-to-board interface BP and the fifth pad SG.
  • the resistance element R has a relatively large resistance value.
  • the resistance value of the resistance element R may be significantly greater than the resistance values of the trace 68 and the trace 69.
  • the resistance value of the resistance element R is 0.1 megaohms (M ⁇ ) to 1 megaohm, for example, 0.1 megaohms, 0.2 megaohms, 0.3 megaohms, 0.5 megaohms, 0.7 megaohms, 0.9 megaohms or 1 megaohm.
  • the board-to-board interface BP can be kept in a high impedance state (Hi-Z) or a floating state, and at this time, the enable interface J1 is provided with a first potential signal by the fifth pad SG.
  • the board-to-board interface BP can be kept at the second potential (low potential), at which time the fifth pad SG is equivalent to being short-circuited, and the enabling interface J1 is provided with a second potential signal by the board-to-board interface BP.
  • the trace 68 is disposed inside the circuit board 60. In some embodiments, the trace 68 is disposed on the surface of the circuit board 60. For example, a scattered wire is provided, one end of the wire is welded to the second end of the resistor R, and the other end of the wire is welded to the first gold finger G3. The wire is used as the trace 68.
  • the trace 69 is disposed inside the circuit board 60. In some embodiments, the trace 69 is disposed on the surface of the circuit board 60. For example, a scattered wire is provided, one end of the wire is welded to the second end of the resistor element R, and the other end of the wire is welded to the board-to-board interface BP. The wire is used as the trace 69.
  • FIG. 10 is a schematic structural diagram of a display panel 400 according to an embodiment of the present application.
  • the display panel 400 may include a display substrate 20, a driving chip 40 and a circuit board 60.
  • the display substrate 20 has a display area 23 (AA area) and a wiring area 25 (Pad area), and the wiring area 25 is provided with a plurality of pins P, and the plurality of pins P include a first pin P3.
  • the driving chip 40 is installed in the wiring area 25 of the display substrate 20, and has multiple interfaces J, which include an enable interface J1 (i.e., EN interface or EN PIN).
  • the enable interface J1 is configured to control the use of a specific communication protocol, and the enable interface J1 is electrically connected to the first pin P3.
  • the circuit board 60 has a plurality of gold fingers G, the plurality of gold fingers G include a first gold finger G3, the plurality of gold fingers G of the circuit board 60 are connected to the plurality of pins P, and the first gold finger G3 is connected to the first pin P3.
  • the enabling interface J1 can be applied with a first potential signal or a second potential signal through the circuit board 60.
  • the enabling interface J1 is applied with the first potential signal, the specific communication protocol is not used; when the enabling interface is applied with the second potential signal, the specific communication protocol is used.
  • the specific communication protocol can be selected for use or not. This is conducive to giving full play to the advantages of the communication protocol and avoiding its disadvantages. For example, when it is detected that it is at a time suitable for using the communication protocol, a second potential signal can be applied to the enabling interface to enable the specific communication protocol to be used. When it is detected that it is at a time not suitable for using the communication protocol, a first potential signal can be applied to the enabling interface to disable the specific communication protocol from being used.
  • the display area 23 is the main body of the display substrate 20, having a plurality of pixel units for displaying images; the wiring area 25 is located at an edge of the display substrate 20 to achieve electrical connection with external components. In some embodiments, the display area 23 is adjacent to the wiring area 25.
  • the plurality of pins P are located on a side of the wiring area 25 away from the display area 23 and are arranged along a straight line. In other embodiments, the plurality of pins P may also be arranged along multiple sides of the wiring area 25. For example, the plurality of pins P may be arranged along three outer sides of the wiring area 25 (excluding the side of the wiring area 25 adjacent to the display area 23).
  • the driver chip 40 is installed in the wiring area 25 by bonding. In some embodiments, the driver chip 40 is installed in the wiring area 25 by plugging. For example, the driver chip 40 is provided with a connector, and the wiring area 25 is provided with a mating connector. By plugging the connector into the mating connector, the driver chip 40 can be installed on the wiring area 25.
  • the enabling interface J1 can be electrically connected to the first pin P3 through a wire 28 in the wiring area 25.
  • the wire 28 is disposed inside the wiring area 25 of the display substrate 20.
  • the wire 28 is disposed on the surface of the wiring area 25 of the display substrate 20. For example, after the driver chip 40 is installed in the wiring area 25, a scattered wire is provided, one end of the wire is welded to the enabling interface J1, and the other end of the wire is welded to the first pin P3. The wire serves as the wire 28.
  • the communication protocol may be any communication protocol.
  • the communication protocol is a QSPI protocol.
  • the QSPI protocol is a Queue Serial Peripheral Interface (Queue Serial Peripheral Interface) communication protocol.
  • the QSPI protocol may be configured to be used when the display panel is in AOD (Always on Display) mode. Because in AOD mode, the display panel does not need to transmit high-speed signals and the amount of data is also small, the use of the QSPI communication protocol is suitable and is conducive to reducing the workload of the driver chip. It can be further set that when the display panel is in other modes (for example, normal display), the QSPI protocol is not used, and other protocols are used.
  • the other protocols include the MIPI (Mobile Industry Processor Interface) protocol.
  • the MIPI protocol can transmit high-speed signals, has a large amount of data, low power consumption, and good anti-interference performance.
  • the plurality of gold fingers G of the circuit board 60 are connected to the plurality of pins P by bonding, and the first gold finger G3 is connected to the first pin P3 by bonding.
  • the plurality of gold fingers G are located on a side of the circuit board 60 adjacent to the wiring area 25 and are arranged along a straight line.
  • the circuit board 60 is a flexible printed circuit (FPC).
  • FPC flexible printed circuit
  • the first potential signal is a high potential
  • the second potential signal is a low potential, that is, when a high potential signal is applied to the enable interface J1, the specific communication protocol is not used; when a low potential signal is applied to the enable interface J1, the specific communication protocol is used.
  • the plurality of interfaces J also include a second interface J4, and the second interface J4 is used to selectively provide a first potential signal (high potential signal) or a second potential signal (low potential signal).
  • the second interface J4 is a GPIO interface (General-purpose input/output). The second interface J4 can switch to output the first potential signal or the second potential signal by programming (Code).
  • the plurality of pins P further include a second pin P6.
  • the second interface J4 is electrically connected to the second pin P6.
  • the plurality of gold fingers G further include a second gold finger G6, which is connected to the second pin P6.
  • the second gold finger G6 is electrically connected to the first gold finger G3.
  • the second gold finger G6 is connected to the first gold finger G3 via a trace 68, a trace 67, and a trace 65.
  • the second interface J4 can be controlled to be at the first potential, and provide a first potential signal to the enabling interface J1.
  • the second interface J4 can be controlled to be at a second potential, and a second potential signal can be provided to the enabling interface J1.
  • the second interface J4 can be electrically connected to the second pin P6 through a wire 28 in the wiring area 25.
  • the wire 28 for connecting the second interface J4 and the second pin P6 is disposed inside the wiring area 25 of the display substrate 20.
  • the wire 28 for connecting the second interface J4 and the second pin P6 is disposed on the surface of the wiring area 25 of the display substrate 20. For example, after the driver chip 40 is installed in the wiring area 25, a scattered wire is provided, one end of the wire is welded to the second interface J4, and the other end of the wire is welded to the second pin P6.
  • the second gold finger G6 is connected to the second pin P6 by binding.
  • the traces 68, 67, 65 are disposed inside the circuit board 60. In this example, the traces 68 , 67 , and 65 are disposed on the surface of the circuit board 60 .
  • the display panel in the above embodiments may be a flexible display panel using OLED display technology.
  • the present application also provides an electronic device, which may include various display panels as described above.
  • the electronic device may be a wearable device.
  • the wearable device may be a watch.
  • the present application also provides a method for manufacturing a display panel, which can be used to manufacture the various display panels mentioned above.
  • the method for manufacturing a display panel may include:
  • the display substrate has a display area and a wiring area, the display area includes a plurality of pixel units, the wiring area is provided with a plurality of pins, and the plurality of pins includes a first pin;
  • the driver chip is mounted on the wiring area of the display substrate, wherein the driver chip has a plurality of interfaces, wherein the plurality of interfaces include an enable interface, wherein the enable interface is configured to control the use of a communication protocol, and the enable interface is electrically connected to the first pin;
  • the circuit board Connecting the circuit board to the display substrate, the circuit board having a plurality of gold fingers, the plurality of gold fingers including a first gold finger, the plurality of gold fingers of the circuit board being connected to the plurality of pins, the first gold finger being connected to the first pin;
  • the enabling interface can be applied with a first potential signal or a second potential signal through the circuit board; when the enabling interface is applied with the first potential signal, the communication protocol is not used; when the enabling interface is applied with the second potential signal, the communication protocol is used.
  • the step of providing or making a circuit board may include the following steps.
  • a double-layer board 53 is first provided, and the double-layer board 53 may include a first metal layer 536, a first insulating layer 534, and a second metal layer 532.
  • the first metal layer 536 and the second metal layer 532 may be made of copper.
  • the first insulating layer 534 may be made of a PI (polyimide) flexible material to make the double-layer board 53 flexible as a whole.
  • the second metal layer 532 may be etched with a chemical solution to form a desired circuit.
  • a hole 5320 may be formed in a portion of the second metal layer 532 that is etched away.
  • the double-layer board 53 and the single-layer board 55 are bonded together by a glue layer 57.
  • the material of the glue layer 57 may be AD glue.
  • the single-layer board 55 may include a second insulating layer 554 and a third metal layer 552.
  • the material of the second insulating layer 554 may be PI (polyimide) flexible material, so that the single-layer board 55 has flexibility as a whole.
  • the material of the third metal layer 552 may be copper.
  • a contact hole 530 may be formed in the double-layer board 53
  • a contact hole 550 may be formed in the single-layer board 55 by using a laser drilling process.
  • metal material is filled in the contact hole 530 to form a metal hole column 539
  • metal material is filled in the contact hole 550 to form a metal hole column 559.
  • the metal hole column 539 and the metal hole column 559 can be formed by electroplating process.
  • the material of the metal hole column 539 and the metal hole column 559 can be copper.
  • the first metal layer 536 and the third metal layer 552 can be etched with chemical solution to form the required circuit.
  • the etched away portion of the first metal layer 536 will form a hole 5363.
  • the etched away portion of the third metal layer 552 will form a hole 5523.
  • a first protective layer 59 (Coverlay) is covered on the surface of the first metal layer 536, and a third metal layer 536 is provided on the surface of the third metal layer 536.
  • the surface of the metal layer 552 is covered with a second protective layer 58 (Coverlay); and then a hole 592 is opened in the first protective layer 59.
  • the metal structure exposed by the hole 592 is used as a pad.
  • the pad can be the first pad, the second pad, and the third pad mentioned above.
  • the embodiment of the present application adopts a double-layer board + single-layer board structure, which can greatly reduce the overall thickness of the circuit board.
  • the double-layer board is used to route the signal line; most of the single-layer board is paved with metal to shield signal interference.
  • solder paste 513 is formed in the hole 592 .
  • the material of the solder paste 513 may be tin.
  • the solder paste 513 is electrically connected to the pad below the hole 592 .
  • a conductive body 51 is formed above the first protective layer 59 and the solder paste 513.
  • the conductive body 51 may be made of a metal material, such as copper. After the conductive body 51 is placed on the solder paste 513, an annealing process may be used to solidify and fix the connection between the conductive body 51 and the solder paste 513. The conductive body 51 is used to connect two different pads.
  • first and second are used for descriptive purposes only and should not be understood as indicating or implying relative importance.
  • plurality and “several” refer to two or more than two, unless otherwise clearly defined.

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Abstract

一种显示面板(100,200,300,400)以及电子设备，其中，显示面板(100,200,300,400)包括显示基板(20)、驱动芯片(40)与电路板(60)。显示基板(20)的接线区(25)设置有多个引脚(P)，多个引脚(P)包括第一引脚(P3)。驱动芯片(40)安装于显示基板(20)的接线区(25)，具有多个接口(J)，多个接口(J)包括使能接口(J1)。使能接口(J1)被配置为控制一通信协议的使用，与第一引脚(P3)电性相连。电路板(60)具有多个金手指(G)，多个金手指(G)包括第一金手指(G3)，电路板(60)的多个金手指(G)与多个引脚(P)连接，第一金手指(G3)与第一引脚(P3)连接。使能接口(J1)通过电路板(60)能够被施加第一电位信号，也能够被施加第二电位信号；使能接口(J1)被施加第一电位信号时，通信协议不被使用；使能接口(J1)被施加第二电位信号时，通信协议被使用。

Description

显示面板以及电子设备 技术领域
本申请涉及一种显示面板以及电子设备。
背景技术
可穿戴设备通常包括显示面板。所述显示面板包括显示基板以及绑定于所述显示基板上的驱动芯片与柔性电路板。所述驱动芯片与柔性电路板、显示基板之间通常采用MIPI协议来传输信号。MIPI协议可传输高速信号，数据量大，功耗低，抗干扰性能好。但是，当处于AOD(常亮显示)模式时，不需要传输高速信号，数据量也很小，此时仍采用MIPI协议将不利于降低系统的负担和减少功耗。
发明内容
根据本申请实施例的第一方面，提供一种显示面板，所述显示面板包括：显示基板，具有显示区与接线区，所述显示区包括多个像素单元，所述接线区设置有多个引脚，所述多个引脚包括第一引脚；驱动芯片，安装于所述显示基板的所述接线区，具有多个接口，所述多个接口包括使能接口，所述使能接口被配置为控制一通信协议的使用，所述使能接口与所述第一引脚电性相连；电路板，具有多个金手指，所述多个金手指包括第一金手指，所述电路板的多个金手指与所述多个引脚连接，所述第一金手指与所述第一引脚连接；其中，所述使能接口通过所述电路板能够被施加第一电位信号，也能够被施加第二电位信号；所述使能接口被施加第一电位信号时，所述通信协议不被使用；所述使能接口被施加第二电位信号时，所述通信协议被使用。
在一些实施例中，所述通信协议包括QSPI协议。
在一些实施例中，在所述QSPI协议不被使用时，MIPI通信协议被使用。
在一些实施例中，所述电路板的多个金手指通过绑定的方式与所述多个引脚连接，所述第一金手指通过绑定的方式与所述第一引脚连接。
在一些实施例中，所述第一电位信号为高电位，所述第二电位信号为低电位。
在一些实施例中，所述多个接口还包括第二接口和第三接口，所述第二接口和所述第三接口中的一个用于提供第一电位信号，另一个用于提供第二电位信号；所述多个引脚还包括第二引脚和第三引脚，所述第二接口与所述第二引脚电性相连，所述第三接口与所述第三引脚电性相连；所述多个金手指还包括第二金手指和第三金手指，所述第二金手指与所述第二引脚连接，所述第三金手指与所述第三引脚连接；所述电路板还具有多个焊盘，所述多个焊盘包括第一焊盘、第二焊盘与第三焊盘，所述第一焊盘与所述第一金手指电性相连，所述第二焊盘与所述第二金手指电性相连，所述第三焊盘与所述第三金手指电性相连；所述第一焊盘择一地与所述第二焊盘或所述第三焊盘连接。
在一些实施例中，所述第二金手指通过绑定的方式与所述第二引脚连接，所述第三金手指通过绑定的方式与所述第三引脚连接。
在一些实施例中，所述第一焊盘通过所述电路板内的一走线与所述第一金手指电性相连，所述第二焊盘通过所述电路板内的一走线与所述第二金手指电性相连，所 述第三焊盘通过所述电路板内的一走线与所述第三金手指电性相连。
在一些实施例中，所述第二焊盘、所述第三焊盘均与所述第一焊盘相邻，且所述第二焊盘与所述第三焊盘设置在所述第一焊盘的不同侧。
在一些实施例中，所述第一焊盘与所述第二焊盘通过设置在所述电路板表面上的一导通体实现连接；或，所述第一焊盘与所述第三焊盘通过设置在所述电路板表面上的一导通体实现连接。
在一些实施例中，所述电路板还具有第五焊盘与板对板接口，所述第五焊盘具有第一电位，用于向所述第一金手指提供第一电位信号，所述第五焊盘与所述第一金手指之间连接有电阻元件；所述板对板接口与所述第一金手指电性相连，并且所述板对板接口能够在第一状态和第二状态之间切换，在所述第一状态，所述板对板接口处于高阻态或浮接状态；在所述第二状态，所述板对板接口具有第二电位，向所述使能接口提供第二电位信号。
在一些实施例中，所述第五焊盘为与地相接。
在一些实施例中，所述多个接口还包括第二接口，所述第二接口用于选择性地提供第一电位信号或第二电位信号；所述多个引脚还包括第二引脚，所述第二接口与所述第二引脚电性相连；所述多个金手指还包括第二金手指，所述第二金手指与所述第二引脚连接，所述第二金手指与第一金手指电性相连。
在一些实施例中，所述第二接口为GPIO接口；所述第二接口通过编程的方式切换输出第一电位信号或第二电位信号。
根据本申请实施例的第二方面，提供一种电子设备，所述电子设备包括如前所述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本申请。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本申请的实施例，并与说明书一起用于解释本申请的原理。
图1是一种应用于可穿戴设备的显示面板的结构示意图；
图2是图1所示显示面板中部分结构的电路连接示意图；
图3是本申请一实施例显示面板的结构示意图；
图4是图3所示显示面板一种使用状态的示意图；
图5是图3所示显示面板另一种使用状态的示意图；
图6是本申请又一实施例显示面板的结构示意图；
图7是图6所示显示面板一种使用状态的示意图；
图8是图6所示显示面板另一种使用状态的示意图；
图9是本申请再一实施例显示面板的结构示意图；
图10是本申请另一实施例显示面板的结构示意图；
图11至图18是本申请一实施例电路板的制作方法的示意图。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本申请相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置和方法的例子。
在本申请使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本申请。除非另作定义，本申请使用的技术术语或者科学术语应当为本申请所属领域内具有一般技能的人士所理解的通常意义。本申请说明书以及权利要求书中使用的“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“多个”表示两个或两个以上。“包括”或者“包含”等类似词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而且可以包括电性的连接，不管是直接的还是间接的。“上”和/或“下”等类似词语只是为了便于说明，而并非限于一个位置或者一种空间定向。在本申请说明书和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
图1是一种应用于可穿戴设备的显示面板的结构示意图。所述显示面板可以是柔性OLED显示面板。为降低整个显示面板的尺寸和边界，通常会采用COP(Chip On Panel)技术，将驱动芯片40(Driver IC)直接绑定(bonding)在显示基板20上，驱动芯片40上的多个接口J与显示基板20上的多个引脚P连接。在组装电路板60时，电路板60上的多个金手指G与显示基板20上的多个引脚P直接绑定在一起。
请同时参照图1与图2，驱动芯片40上的一些电源接口J1需要引出信号以在电路板60上外接电容C，电容C的一端(或一个极板)B1连接驱动芯片40的电源接口J1，另一端(或另一个极板)B2接地。外接的所述电容C起到滤波作用。当驱动芯片40输出的电源信号混有杂波信号时，电容C会将杂波信号引出，导入大地，起到滤除杂波的功能。当然，在有些情况下，还会包括TVS(Transient Voltage Suppressors，瞬态电压抑制器)、二极管、Flash存储器、ALS(Ambient Light Sensor，环境光传感器)、ZIF连接器，以及磁珠等元器件。可以在电路板60上预留相应的焊盘，通过SMT技术(Surface Mount Technology，表面贴装技术)将这些元器件安装到电路板60的表面。
可穿戴设备常采用MIPI(Mobile Industry Processor Interface，移动行业处理器接口)协议来传输信号，可传输高速信号，数据量大，功耗低，抗干扰性能好。但是，当处于AOD(Always on display，常亮显示)模式时，不需要传输高速信号，数据量也很小，此时更佳的选择是：引入QSPI(Queue Serial peripheral interface，队列串行外设接口)通信协议，并在AOD模式下，利用QSPI协议来传输数据。但是，将QSPI协议用于AOD模式的技术还不成熟，因而本申请提供一种兼容使用QSPI协议和不使用QSPI协议两种方案。
图3是本申请一实施例显示面板100的结构示意图。图4是图3所示显示面板100一种使用状态的示意图。图5是图3所示显示面板100另一种使用状态的示意图。
请参照图3，所述显示面板100可以包括显示基板20、驱动芯片40与电路板60。其中，所述显示基板20具有显示区23(AA区)与接线区25(Pad区)，所述接线区25设置有多个引脚P，所述多个引脚P包括第一引脚P3。
所述驱动芯片40安装于所述显示基板20的所述接线区25，具有多个接口J，所述多个接口J包括一使能接口J1(即，EN接口或EN PIN)，所述使能接口J1被配置为控制一特定的通信协议的使用，所述使能接口J1与所述第一引脚P3电性相连。
所述电路板60具有多个金手指G，所述多个金手指G包括第一金手指G3，所述电路板60的多个金手指G与所述多个引脚P连接，所述第一金手指G3与所述第一引脚P3连接。
其中，所述使能接口J1通过所述电路板60能够被施加第一电位信号，也能够被施加第二电位信号。在所述使能接口J1被施加第一电位信号时，所述特定的通信协议不被使用；所述使能接口被施加第二电位信号时，所述特定的通信协议被使用。
上述实施例中，所述特定的通信协议既可被选择使用，也可不被选择使用。这有利于发挥该通信协议的优点，避免其缺点。比如，当检测到处于适合使用所述通信协议的时刻，可施加第二电位信号给所述使能接口，以使所述特定的通信协议被使用。当检测到处于不适合使用所述通信协议的时刻，可施加第一电位信号给所述使能接口，以使所述特定的通信协议不被使用。
所述显示区23与所述接线区25的位置关系有多种。在一些实施例中，所述显示区23为所述显示基板20的主体部分，具有多个像素单元，用于显示图像；所述接线区25位于所述显示基板20的一个边缘，实现与外部元件的电性连接。在一些实施例中，所述显示区23与所述接线区25相邻。
所述多个引脚P的排列方式有多种。在一些实施例中，所述多个引脚P位于所述接线区25远离所述显示区23的一侧，并沿一条直线排列。在其它实施例中，所述多个引脚P也可沿所述接线区25的多个侧边排列。比如，所述多个引脚P可以沿所述接线区25靠外的三条侧边(不含所述接线区25邻近所述显示区23的侧边)排列。
所述驱动芯片40的安装方式可以有多种。在一些实施例中，所述驱动芯片40通过绑定(bonding)的方式安装于所述接线区25。在一些实施例中，所述驱动芯片40通过插接的方式安装于所述接线区25。比如，所述驱动芯片40设置有一连接器，所述接线区25设置有一配对连接器，通过将所述连接器插接于所述配对连接器中，可实现所述驱动芯片40在所述接线区25上的安装。
所述使能接口J1可以通过所述接线区25内的一走线28与所述第一引脚P3电性相连。在一些实施例中，所述走线28设置于显示基板20接线区25的内部。在一些实施例中，所述走线28设置于显示基板20接线区25的表面。比如，待所述驱动芯片40安装于所述接线区25后，提供一零散的导线，使所述导线的一端焊接于所述使能接口J1，所述导线的另一端焊接于所述第一引脚P3。所述导线即作为所述走线28。
所述通信协议可以是任意的通信协议。在一些实施例中，所述通信协议为QSPI协议。QSPI协议即(Queue Serial peripheral interface，队列串行外设接口)通信协议。 可以被设定为，当显示面板处于AOD(Always on display，常亮显示)模式时，QSPI协议被使用。因为在AOD模式下，显示面板不需要传输高速信号，数据量也很小，使用QSPI通信协议正适用，有利于降低驱动芯片的工作负荷。进一步可被设定为，当显示面板处于其它模式(比如，正常显示)时，QSPI协议不被使用，同时其它协议被使用。所述其它协议包括MIPI(Mobile Industry Processor Interface，移动行业处理器接口)协议。MIPI协议可以传输高速信号，数据量大，功耗低，抗干扰性能好。
在一些实施例中，所述电路板60的多个金手指G通过绑定(bonding)的方式与所述多个引脚P连接，所述第一金手指G3通过绑定的方式与所述第一引脚P3连接。
所述多个金手指G的排列方式有多种。在一些实施例中，所述多个金手指G位于所述电路板60邻近所述接线区25的一侧，并沿一条直线排列。
在一些实施例中，所述电路板60为柔性电路板(FPC)。
在一些实施例中，所述第一电位信号为高电位，所述第二电位信号为低电位。即，当高电位信号被施加于所述使能接口J1，所述特定的通信协议不被使用；当低电位信号被施加于所述使能接口J1时，所述特定的通信协议被使用。
进一步地，所述多个接口J还包括第二接口J3和第三接口J6，所述第二接口J3用于提供第一电位信号，所述第三接口J6用于提供第二电位信号；所述多个引脚P还包括第二引脚P5和第三引脚P8。所述第二接口J3与所述第二引脚P5电性相连，所述第三接口J6与所述第三引脚P8电性相连。
所述多个金手指G还包括第二金手指G5和第三金手指G8，所述第二金手指G5与所述第二引脚P5连接，所述第三金手指G8与所述第三引脚P8连接。
所述电路板60还具有多个焊盘，所述多个焊盘包括第一焊盘S1、第二焊盘S2与第三焊盘S3，所述第一焊盘S1与第一金手指G3电性相连，所述第二焊盘S2与第二金手指G5电性相连，所述第三焊盘S3与第三金手指G8电性相连。
上述连接，使得：第一焊盘S1与使能接口J1电性相连；第二焊盘S2与第二接口J3电性相连，具有第一电位；第三焊盘S3与第三接口J6电性相连，具有第二电位。
当不需要使用所述特定的通信协议时，可将所述第一焊盘S1与所述第二焊盘S2连接，如图4所示，以使所述使能接口J1与第一电位信号相连；此时，具有第二电位的第三接口J6与第三焊盘S3处于浮接(Floating)状态。
当需要使用所述特定的通信协议时，可将所述第一焊盘S1与所述第三焊盘S3连接，如图5所示，以使所述使能接口J1与第二电位信号相连；此时，具有第一电位的第二接口J3与第二焊盘S2处于浮接(Floating)状态。
请参照图3至图5，所述第二接口J3可以通过所述接线区25内的一走线28与所述第二引脚P5电性相连；所述第三接口J6可以通过所述接线区25内的一走线28与所述第三引脚P8电性相连。在一些实施例中，用于连接第二接口J3与第二引脚P5的所述走线28和/或用于连接第三接口J6与第三引脚P8的所述走线28设置于显示基板20接线区25的内部。在一些实施例中，用于连接第二接口J3与第二引脚P5的所述走线28和/或用于连接第三接口J6与第三引脚P8的所述走线28设置于显示基板20 接线区25的表面。比如，待所述驱动芯片40安装于所述接线区25后，提供两个零散的导线，使：其中第一个导线的一端焊接于所述第二接口J3，所述第一个导线的另一端焊接于所述第二引脚P5；第二个导线的一端焊接于所述第三接口J6，所述第二个导线的另一端焊接于所述第三引脚P8。
在一些实施例中，所述第二金手指G5通过绑定的方式与所述第二引脚P5连接，所述第三金手指G8通过绑定的方式与所述第三引脚P8连接。
所述第一焊盘S1可以通过所述电路板60内的一走线68与所述第一金手指G3电性相连。在一些实施例中，所述走线68设置于电路板60的内部。在一些实施例中，所述走线68设置于电路板60的表面。比如，提供一个零散的导线，使所述导线的一端焊接于所述第一焊盘S1，所述导线的另一端焊接于所述第一金手指G3。所述导线即作为所述走线68。
类似的，所述第二焊盘S2可以通过所述电路板60内的一走线68与所述第二金手指G5电性相连。在一些实施例中，所述走线68设置于电路板60的内部。在一些实施例中，所述走线68设置于电路板60的表面。比如，提供一个零散的导线，使所述导线的一端焊接于所述第二焊盘S2，所述导线的另一端焊接于所述第二金手指G5。所述导线即作为所述走线68。
所述第三焊盘S3可以通过所述电路板60内的一走线68与所述第三金手指G8电性相连。在一些实施例中，所述走线68设置于电路板60的内部。在一些实施例中，所述走线68设置于电路板60的表面。比如，提供一个零散的导线，使所述导线的一端焊接于所述第三焊盘S3，所述导线的另一端焊接于所述第三金手指G8。所述导线即作为所述走线68。
为方便连接，可将所述第二焊盘S2、所述第三焊盘S3均设置得与所述第一焊盘S1相邻。比如，可将所述第二焊盘S2、所述第三焊盘S3设置在所述第一焊盘S1的不同侧。在一些实施例中，所述第二焊盘S2设置在所述第一焊盘S1的右侧，所述第三焊盘S3设置在所述第一焊盘S1的下侧。
设置在所述电路板60上的多个焊盘还可以包括第四焊盘S4。在一些实施例中，所述第四焊盘S4可以是用于接地的焊盘，用来为所述电路板60或安装在电路板60上的元件提供接地路径。比如，在将电容元件安装于电路板60上时，可将电容的一个极板直接焊接于所述第四焊盘S4。
所述第一焊盘S1与所述第二焊盘S2可以通过设置在所述电路板60表面上的导通体72实现连接。所述第一焊盘S1与所述第三焊盘S3可以通过设置在所述电路板60表面上的导通体74实现连接。所述导通体72与导通体74均为良好的导体，它们的电阻值较小，几乎可视为零电阻。所述导通体72与导通体74的材质可以是铜、铝或银等。其中的导通体72与导通体74的结构与制作方法可参后续图18中的导通体51。
图6是本申请一实施例显示面板200的结构示意图。图7是图6所示显示面板200一种使用状态的示意图。图8是图6所示显示面板100另一种使用状态的示意图。
请参照图6，所述显示面板200可以包括显示基板20、驱动芯片40与电路板60。其中，所述显示基板20具有显示区23(AA区)与接线区25(Pad区)，所述接 线区25设置有多个引脚P，所述多个引脚P包括第一引脚P3。
所述驱动芯片40安装于所述显示基板20的所述接线区25，具有多个接口J，所述多个接口J包括一使能接口J1(即，EN接口或EN PIN)，所述使能接口J1被配置为控制一特定的通信协议的使用，所述使能接口J1与所述第一引脚P3电性相连。
所述电路板60具有多个金手指G，所述多个金手指G包括第一金手指G3，所述电路板60的多个金手指G与所述多个引脚P连接，所述第一金手指G3与所述第一引脚P3连接。
其中，所述使能接口J1通过所述电路板60能够被施加第一电位信号，也能够被施加第二电位信号。在所述使能接口J1被施加第一电位信号时，所述特定的通信协议不被使用；所述使能接口被施加第二电位信号时，所述特定的通信协议被使用。
上述实施例中，所述特定的通信协议既可被选择使用，也可不被选择使用。这有利于发挥该通信协议的优点，避免其缺点。比如，当检测到处于适合使用所述通信协议的时刻，可施加第二电位信号给所述使能接口，以使所述特定的通信协议被使用。当检测到处于不适合使用所述通信协议的时刻，可施加第一电位信号给所述使能接口，以使所述特定的通信协议不被使用。
所述显示区23与所述接线区25的位置关系有多种。在一些实施例中，所述显示区23为所述显示基板20的主体部分，具有多个像素单元，用于显示图像；所述接线区25位于所述显示基板20的一个边缘，实现与外部元件的电性连接。在一些实施例中，所述显示区23与所述接线区25相邻。
所述多个引脚P的排列方式有多种。在一些实施例中，所述多个引脚P位于所述接线区25远离所述显示区23的一侧，并沿一条直线排列。在其它实施例中，所述多个引脚P也可沿所述接线区25的多个侧边排列。比如，所述多个引脚P可以沿所述接线区25靠外的三条侧边(不含所述接线区25邻近所述显示区23的侧边)排列。
所述驱动芯片40的安装方式可以有多种。在一些实施例中，所述驱动芯片40通过绑定(bonding)的方式安装于所述接线区25。在一些实施例中，所述驱动芯片40通过插接的方式安装于所述接线区25。比如，所述驱动芯片40设置有一连接器，所述接线区25设置有一配对连接器，通过将所述连接器插接于所述配对连接器中，可实现所述驱动芯片40在所述接线区25上的安装。
所述使能接口J1可以通过所述接线区25内的一走线28与所述第一引脚P3电性相连。在一些实施例中，所述走线28设置于显示基板20接线区25的内部。在一些实施例中，所述走线28设置于显示基板20接线区25的表面。比如，待所述驱动芯片40安装于所述接线区25后，提供一零散的导线，使所述导线的一端焊接于所述使能接口J1，所述导线的另一端焊接于所述第一引脚P3。所述导线即作为所述走线28。
所述通信协议可以是任意的通信协议。在一些实施例中，所述通信协议为QSPI协议。QSPI协议即(Queue Serial peripheral interface，队列串行外设接口)通信协议。可以被设定为，当显示面板处于AOD(Always on display)模式时，QSPI协议被使用。因为在AOD模式下，显示面板不需要传输高速信号，数据量也很小，使用QSPI通信协议正适用，有利于降低驱动芯片的工作负荷。进一步可被设定为，当显示面板处于其它模式(比如，正常显示)时，QSPI协议不被使用，同时其它协议被使用。所述其 它协议包括MIPI(Mobile Industry Processor Interface，移动行业处理器接口)协议。MIPI协议可以传输高速信号，数据量大，功耗低，抗干扰性能好。
在一些实施例中，所述电路板60的多个金手指G通过绑定(bonding)的方式与所述多个引脚P连接，所述第一金手指G3通过绑定的方式与所述第一引脚P3连接。
所述多个金手指G的排列方式有多种。在一些实施例中，所述多个金手指G位于所述电路板60邻近所述接线区25的一侧，并沿一条直线排列。
在一些实施例中，所述电路板60为柔性电路板(FPC)。
在一些实施例中，所述第一电位信号为高电位，所述第二电位信号为低电位。即，当高电位信号被施加于所述使能接口J1，所述特定的通信协议不被使用；当低电位信号被施加于所述使能接口J1时，所述特定的通信协议被使用。
进一步地，所述多个接口J还包括第二接口J3和第三接口J6，所述第二接口J3用于提供第二电位信号，所述第三接口J6用于提供第一电位信号；所述多个引脚P还包括第二引脚P5和第三引脚P8。所述第二接口J3与所述第二引脚P5电性相连，所述第三接口J6与所述第三引脚P8电性相连。
所述多个金手指G还包括第二金手指G5和第三金手指G8，所述第二金手指G5与所述第二引脚P5连接，所述第三金手指G8与所述第三引脚P8连接。
所述电路板60还具有多个焊盘，所述多个焊盘包括第一焊盘S1、第二焊盘S2与第三焊盘S3，所述第一焊盘S1与第一金手指G3电性相连，所述第二焊盘S2与第二金手指G5电性相连，所述第三焊盘S3与第三金手指G8电性相连。
上述连接，使得：第一焊盘S1与使能接口J1电性相连；第二焊盘S2与第二接口J3电性相连，具有第二电位；第三焊盘S3与第三接口J6电性相连，具有第一电位。
当不需要使用所述特定的通信协议时，可将所述第一焊盘S1与所述第三焊盘S3连接，如图7所示，以使所述使能接口J1与第一电位信号相连；此时，具有第二电位的第二接口J3与第二焊盘S2处于浮接(Floating)状态。
当需要使用所述特定的通信协议时，可将所述第一焊盘S1与所述第二焊盘S2连接，如图8所示，以使所述使能接口J1与第二电位信号相连；此时，具有第一电位的第三接口J6与第三焊盘S3处于浮接(Floating)状态。
请参照图6至图8，所述第二接口J3可以通过所述接线区25内的一走线28与所述第二引脚P5电性相连；所述第三接口J6可以通过所述接线区25内的一走线28与所述第三引脚P8电性相连。在一些实施例中，用于连接第二接口J3与第二引脚P5的所述走线28和/或用于连接第三接口J6与第三引脚P8的所述走线28设置于显示基板20接线区25的内部。在一些实施例中，用于连接第二接口J3与第二引脚P5的所述走线28和/或用于连接第三接口J6与第三引脚P8的所述走线28设置于显示基板20接线区25的表面。比如，待所述驱动芯片40安装于所述接线区25后，提供两个零散的导线，使：其中第一个导线的一端焊接于所述第二接口J3，所述第一个导线的另一端焊接于所述第二引脚P5；第二个导线的一端焊接于所述第三接口J6，所述第二个导线的另一端焊接于所述第三引脚P8。
在一些实施例中，所述第二金手指G5通过绑定的方式与所述第二引脚P5连接，所述第三金手指G8通过绑定的方式与所述第三引脚P8连接。
所述第一焊盘S1可以通过所述电路板60内的一走线68与所述第一金手指G3电性相连。在一些实施例中，所述走线68设置于电路板60的内部。在一些实施例中，所述走线68设置于电路板60的表面。比如，提供一个零散的导线，使所述导线的一端焊接于所述第一焊盘S1，所述导线的另一端焊接于所述第一金手指G3。所述导线即作为所述走线68。
类似的，所述第二焊盘S2可以通过所述电路板60内的一走线68与所述第二金手指G5电性相连。在一些实施例中，所述走线68设置于电路板60的内部。在一些实施例中，所述走线68设置于电路板60的表面。比如，提供一个零散的导线，使所述导线的一端焊接于所述第二焊盘S2，所述导线的另一端焊接于所述第二金手指G5。所述导线即作为所述走线68。
所述第三焊盘S3可以通过所述电路板60内的一走线68与所述第三金手指G8电性相连。在一些实施例中，所述走线68设置于电路板60的内部。在一些实施例中，所述走线68设置于电路板60的表面。比如，提供一个零散的导线，使所述导线的一端焊接于所述第三焊盘S3，所述导线的另一端焊接于所述第三金手指G8。所述导线即作为所述走线68。
为方便连接，可将所述第二焊盘S2、所述第三焊盘S3均设置得与所述第一焊盘S1相邻。比如，可将所述第二焊盘S2、所述第三焊盘S3设置在所述第一焊盘S1的不同侧。在一些实施例中，所述第二焊盘S2设置在所述第一焊盘S1的右侧，所述第三焊盘S3设置在所述第一焊盘S1的下侧。
与前面图3至图5所示实施例不同的是，设置在所述电路板60上的多个焊盘不包括用于接地的第四焊盘。
所述第一焊盘S1与所述第二焊盘S2可以通过设置在所述电路板60表面上的导通体85实现连接。所述第一焊盘S1与所述第三焊盘S3可以通过设置在所述电路板60表面上的导通体83实现连接。所述导通体85与导通体83均为良好的导体，它们的电阻值较小，几乎可视为零电阻。所述导通体85与导通体83的材质可以是铜、铝或银等。其中的导通体85与导通体83的结构与制作方法可参后续图18中的导通体51。
图9是本申请一实施例显示面板300的结构示意图。
请参照图9，所述显示面板300可以包括显示基板20、驱动芯片40与电路板60。其中，所述显示基板20具有显示区23(AA区)与接线区25(Pad区)，所述接线区25设置有多个引脚P，所述多个引脚P包括第一引脚P3。
所述驱动芯片40安装于所述显示基板20的所述接线区25，具有多个接口J，所述多个接口J包括一使能接口J1(即，EN接口或EN PIN)，所述使能接口J1被配置为控制一特定的通信协议的使用，所述使能接口J1与所述第一引脚P3电性相连。
所述电路板60具有多个金手指G，所述多个金手指G包括第一金手指G3，所述电路板60的多个金手指G与所述多个引脚P连接，所述第一金手指G3与所述第一引脚P3连接。
其中，所述使能接口J1通过所述电路板60能够被施加第一电位信号，也能够被施加第二电位信号。在所述使能接口J1被施加第一电位信号时，所述特定的通信协议不被使用；所述使能接口被施加第二电位信号时，所述特定的通信协议被使用。
上述实施例中，所述特定的通信协议既可被选择使用，也可不被选择使用。这有利于发挥该通信协议的优点，避免其缺点。比如，当检测到处于适合使用所述通信协议的时刻，可施加第二电位信号给所述使能接口，以使所述特定的通信协议被使用。当检测到处于不适合使用所述通信协议的时刻，可施加第一电位信号给所述使能接口，以使所述特定的通信协议不被使用。
所述显示区23与所述接线区25的位置关系有多种。在一些实施例中，所述显示区23为所述显示基板20的主体部分，具有多个像素单元，用于显示图像；所述接线区25位于所述显示基板20的一个边缘，实现与外部元件的电性连接。在一些实施例中，所述显示区23与所述接线区25相邻。
所述多个引脚P的排列方式有多种。在一些实施例中，所述多个引脚P位于所述接线区25远离所述显示区23的一侧，并沿一条直线排列。在其它实施例中，所述多个引脚P也可沿所述接线区25的多个侧边排列。比如，所述多个引脚P可以沿所述接线区25靠外的三条侧边(不含所述接线区25邻近所述显示区23的侧边)排列。
所述驱动芯片40的安装方式可以有多种。在一些实施例中，所述驱动芯片40通过绑定(bonding)的方式安装于所述接线区25。在一些实施例中，所述驱动芯片40通过插接的方式安装于所述接线区25。比如，所述驱动芯片40设置有一连接器，所述接线区25设置有一配对连接器，通过将所述连接器插接于所述配对连接器中，可实现所述驱动芯片40在所述接线区25上的安装。
所述使能接口J1可以通过所述接线区25内的一走线28与所述第一引脚P3电性相连。在一些实施例中，所述走线28设置于显示基板20接线区25的内部。在一些实施例中，所述走线28设置于显示基板20接线区25的表面。比如，待所述驱动芯片40安装于所述接线区25后，提供一零散的导线，使所述导线的一端焊接于所述使能接口J1，所述导线的另一端焊接于所述第一引脚P3。所述导线即作为所述走线28。
所述通信协议可以是任意的通信协议。在一些实施例中，所述通信协议为QSPI协议。QSPI协议即(Queue Serial peripheral interface，队列串行外设接口)通信协议。可以被设定为，当显示面板处于AOD(Always on display)模式时，QSPI协议被使用。因为在AOD模式下，显示面板不需要传输高速信号，数据量也很小，使用QSPI通信协议正适用，有利于降低驱动芯片的工作负荷。进一步可被设定为，当显示面板处于其它模式(比如，正常显示)时，QSPI协议不被使用，同时其它协议被使用。所述其它协议包括MIPI(Mobile Industry Processor Interface，移动行业处理器接口)协议。MIPI协议可以传输高速信号，数据量大，功耗低，抗干扰性能好。
在一些实施例中，所述电路板60的多个金手指G通过绑定(bonding)的方式与所述多个引脚P连接，所述第一金手指G3通过绑定的方式与所述第一引脚P3连接。
所述多个金手指G的排列方式有多种。在一些实施例中，所述多个金手指G位于所述电路板60邻近所述接线区25的一侧，并沿一条直线排列。
在一些实施例中，所述电路板60为柔性电路板(FPC)。
在一些实施例中，所述第一电位信号为高电位，所述第二电位信号为低电位。即，当高电位信号被施加于所述使能接口J1，所述特定的通信协议不被使用；当低电位信号被施加于所述使能接口J1时，所述特定的通信协议被使用。
进一步地，所述电路板60还具有第五焊盘SG与一个板对板接口BP(即B2BPIN)。所述第五焊盘SG具有第一电位(即，高电位)，用于向所述第一金手指G3提供第一电位信号。在一些实施例中，所述第五焊盘SG为接地焊盘，与地相接。所述第五焊盘SG与所述第一金手指G3之间还连接一电阻元件R。
在所述电路板60与其它电路板连接时，所述板对板接口BP会与所述其它电路板上的对应接口电性相连或直接接触。所述其它电路板可与所述显示面板300所属的电子设备的控制器相连，并向所述板对板接口BP提供信号。所述板对板接口BP存在两种状态，其中，第一种状态为保持高阻态(Hi-Z)或浮接(Floating)状态，第二种状态为被提供第二电位信号，具有第二电位(即，低电位)。所述板对板接口BP与所述第一金手指G3电性相连。在一些实施例中，除了一板对板接口BP外，还包括另外的板对板接口，所述另外的板对板接口同样用于与所述其它电路板上的对应接口电性相连或直接接触。
所述板对板接口BP与所述第一金手指G3之间可不插入电阻元件。所述板对板接口BP与所述第五焊盘SG可共用一段走线。在一个实施例中，所述电阻元件R的第一端与所述第五焊盘SG相连，所述电阻元件R的第二端通过一走线68连接于所述第一金手指G3；所述板对板接口BP通过一走线69连接于所述电阻元件R的第二端或者所述走线68。所述走线68或其一部分被所述板对板接口BP和所述第五焊盘SG所共用。
所述电阻元件R具有较大的电阻值。所述电阻元件R的电阻值可明显大于所述走线68和所述走线69的电阻值。在一些实施例中，所述电阻元件R的电阻值是0.1兆欧姆(MΩ)到1兆欧姆，比如，可以是0.1兆欧姆、0.2兆欧姆、0.3兆欧姆、0.5兆欧姆、0.7兆欧姆、0.9兆欧姆或1兆欧姆。
当不需要使用所述特定的通信协议时，可使所述板对板接口BP保持高阻态(Hi-Z)或浮接(Floating)状态，此时所述使能接口J1被所述第五焊盘SG提供第一电位信号。
当需要使用所述特定的通信协议时，可使所述板对板接口BP保持第二电位(低电位)，此时所述第五焊盘SG相当于被短路，所述使能接口J1被所述板对板接口BP提供第二电位信号。
在一些实施例中，所述走线68设置于电路板60的内部。在一些实施例中，所述走线68设置于电路板60的表面。比如，提供一个零散的导线，使所述导线的一端焊接于所述电阻元件R的第二端，所述导线的另一端焊接于所述第一金手指G3。所述导线即作为所述走线68。
在一些实施例中，所述走线69设置于电路板60的内部。在一些实施例中，所述走线69设置于电路板60的表面。比如，提供一个零散的导线，使所述导线的一端焊接于所述电阻元件R的第二端，所述导线的另一端焊接于所述板对板接口BP。所述导线即作为所述走线69。
图10是本申请一实施例显示面板400的结构示意图。
请参照图10，所述显示面板400可以包括显示基板20、驱动芯片40与电路板60。其中，所述显示基板20具有显示区23(AA区)与接线区25(Pad区)，所述接线区25设置有多个引脚P，所述多个引脚P包括第一引脚P3。
所述驱动芯片40安装于所述显示基板20的所述接线区25，具有多个接口J，所述多个接口J包括一使能接口J1(即，EN接口或EN PIN)，所述使能接口J1被配置为控制一特定的通信协议的使用，所述使能接口J1与所述第一引脚P3电性相连。
所述电路板60具有多个金手指G，所述多个金手指G包括第一金手指G3，所述电路板60的多个金手指G与所述多个引脚P连接，所述第一金手指G3与所述第一引脚P3连接。
其中，所述使能接口J1通过所述电路板60能够被施加第一电位信号，也能够被施加第二电位信号。在所述使能接口J1被施加第一电位信号时，所述特定的通信协议不被使用；所述使能接口被施加第二电位信号时，所述特定的通信协议被使用。
上述实施例中，所述特定的通信协议既可被选择使用，也可不被选择使用。这有利于发挥该通信协议的优点，避免其缺点。比如，当检测到处于适合使用所述通信协议的时刻，可施加第二电位信号给所述使能接口，以使所述特定的通信协议被使用。当检测到处于不适合使用所述通信协议的时刻，可施加第一电位信号给所述使能接口，以使所述特定的通信协议不被使用。
所述显示区23与所述接线区25的位置关系有多种。在一些实施例中，所述显示区23为所述显示基板20的主体部分，具有多个像素单元，用于显示图像；所述接线区25位于所述显示基板20的一个边缘，实现与外部元件的电性连接。在一些实施例中，所述显示区23与所述接线区25相邻。
所述多个引脚P的排列方式有多种。在一些实施例中，所述多个引脚P位于所述接线区25远离所述显示区23的一侧，并沿一条直线排列。在其它实施例中，所述多个引脚P也可沿所述接线区25的多个侧边排列。比如，所述多个引脚P可以沿所述接线区25靠外的三条侧边(不含所述接线区25邻近所述显示区23的侧边)排列。
所述驱动芯片40的安装方式可以有多种。在一些实施例中，所述驱动芯片40通过绑定(bonding)的方式安装于所述接线区25。在一些实施例中，所述驱动芯片40通过插接的方式安装于所述接线区25。比如，所述驱动芯片40设置有一连接器，所述接线区25设置有一配对连接器，通过将所述连接器插接于所述配对连接器中，可实现所述驱动芯片40在所述接线区25上的安装。
所述使能接口J1可以通过所述接线区25内的一走线28与所述第一引脚P3电性相连。在一些实施例中，所述走线28设置于显示基板20接线区25的内部。在一些实施例中，所述走线28设置于显示基板20接线区25的表面。比如，待所述驱动芯片40安装于所述接线区25后，提供一零散的导线，使所述导线的一端焊接于所述使能接口J1，所述导线的另一端焊接于所述第一引脚P3。所述导线即作为所述走线28。
所述通信协议可以是任意的通信协议。在一些实施例中，所述通信协议为QSPI协议。QSPI协议即(Queue Serial peripheral interface，队列串行外设接口)通信协议。可以被设定为，当显示面板处于AOD(Always on display)模式时，QSPI协议被使用。 因为在AOD模式下，显示面板不需要传输高速信号，数据量也很小，使用QSPI通信协议正适用，有利于降低驱动芯片的工作负荷。进一步可被设定为，当显示面板处于其它模式(比如，正常显示)时，QSPI协议不被使用，同时其它协议被使用。所述其它协议包括MIPI(Mobile Industry Processor Interface，移动行业处理器接口)协议。MIPI协议可以传输高速信号，数据量大，功耗低，抗干扰性能好。
在一些实施例中，所述电路板60的多个金手指G通过绑定(bonding)的方式与所述多个引脚P连接，所述第一金手指G3通过绑定的方式与所述第一引脚P3连接。
所述多个金手指G的排列方式有多种。在一些实施例中，所述多个金手指G位于所述电路板60邻近所述接线区25的一侧，并沿一条直线排列。
在一些实施例中，所述电路板60为柔性电路板(FPC)。
在一些实施例中，所述第一电位信号为高电位，所述第二电位信号为低电位。即，当高电位信号被施加于所述使能接口J1，所述特定的通信协议不被使用；当低电位信号被施加于所述使能接口J1时，所述特定的通信协议被使用。
进一步地，所述多个接口J还包括一第二接口J4，所述第二接口J4用于选择性地提供第一电位信号(高电位信号)或第二电位信号(低电位信号)。在一些实施例中，所述第二接口J4为GPIO接口(General-purpose input/output，通用输入输出端口)。所述第二接口J4可通过编程(Code)的方式切换输出第一电位信号或第二电位信号。
所述多个引脚P还包括第二引脚P6。所述第二接口J4与所述第二引脚P6电性相连。
所述多个金手指G还包括第二金手指G6，所述第二金手指G6与所述第二引脚P6连接。在所述电路板60内，所述第二金手指G6与第一金手指G3电性相连。在一些实施例中，所述第二金手指G6与第一金手指G3通过走线68、走线67和走线65相连通。
上述连接，使得：所述使能接口J1与所述第二接口J4电性相连，具有相同的电位。
当不需要使用所述特定的通信协议时，可控制所述第二接口J4处于第一电位，向所述使能接口J1提供第一电位信号。
当需要使用所述特定的通信协议时，可控制所述第二接口J4处于第二电位，向所述使能接口J1提供第二电位信号。
其中，所述第二接口J4可以通过所述接线区25内的一走线28与所述第二引脚P6电性相连。在一些实施例中，用于连接第二接口J4与第二引脚P6的所述走线28设置于显示基板20接线区25的内部。在一些实施例中，用于连接第二接口J4与第二引脚P6的所述走线28设置于显示基板20接线区25的表面。比如，待所述驱动芯片40安装于所述接线区25后，提供一个零散的导线，使所述导线的一端焊接于所述第二接口J4，所述导线的另一端焊接于所述第二引脚P6。
在一些实施例中，所述第二金手指G6通过绑定的方式与所述第二引脚P6连接。
在一些实施例中，所述走线68、67、65设置于电路板60的内部。在一些实施 例中，所述走线68、67、65设置于电路板60的表面。
上述各实施例中的显示面板可以是柔性显示面板，采用OLED显示技术。
本申请还提供一种电子设备，所述电子设备可以包括如前面所述的各种显示面板。在一些实施例中，所述电子设备可以是可穿戴设备。所述可穿戴设备可以是手表。
本申请还提供了一种显示面板的制作方法，所述制作方法可用于制作前面所述的各种显示面板。所述显示面板的制作方法可以包括：
提供一显示基板、一驱动芯片与一电路板；
其中，所述显示基板具有显示区与接线区，所述显示区包括多个像素单元，所述接线区设置有多个引脚，所述多个引脚包括第一引脚；
将所述驱动芯片安装于所述显示基板的所述接线区，所述驱动芯片具有多个接口，所述多个接口包括使能接口，所述使能接口被配置为控制一通信协议的使用，所述使能接口与所述第一引脚电性相连；
将所述电路板连接于所述显示基板，所述电路板具有多个金手指，所述多个金手指包括第一金手指，所述电路板的多个金手指与所述多个引脚连接，所述第一金手指与所述第一引脚连接；
其中，所述使能接口通过所述电路板能够被施加第一电位信号，也能够被施加第二电位信号；所述使能接口被施加第一电位信号时，所述通信协议不被使用；所述使能接口被施加第二电位信号时，所述通信协议被使用。
进一步地，其中提供或制作电路板的步骤可以包括以下步骤。
如图11，先提供一双层板53，所述双层板53可依此包括第一金属层536、第一绝缘层534与第二金属层532。其中，第一金属层536与第二金属层532的材质可以是铜。所述第一绝缘层534的材质可以是PI(聚酰亚胺)柔性材料，以使双层板53整体具有柔性。可利用化学药液刻蚀第二金属层532，以形成所需的线路。被刻蚀去除的第二金属层532部分区域会形成孔5320。
如图12，通过一胶层57将所述双层板53与一单层板55粘合为一体。其中，所述胶层57的材质可以是AD胶。所述单层板55可以依此包括第二绝缘层554和第三金属层552。第二绝缘层554的材质可以是PI(聚酰亚胺)柔性材料，以使单层板55整体具有柔性。所述第三金属层552的材质可以是铜。
如图13，可利用激光打孔工艺在所述双层板53内形成接触孔530，在所述单层板55内形成接触孔550。
如图14，在所述接触孔530填充金属材料以形成金属孔柱539，在所述接触孔550内填充金属材料形成金属孔柱559。可利用电镀工艺来形成所述金属孔柱539与金属孔柱559。所述金属孔柱539与金属孔柱559的材质可以是铜。
如图15，可利用化学药液对第一金属层536、第三金属层552进行刻蚀，以形成所需的线路。被刻蚀去除的第一金属层536部分区域会形成孔5363。被刻蚀去除的第三金属层552部分区域会形成孔5523。
如图16，在第一金属层536的表面覆盖第一保护层59(Coverlay)，在第三金 属层552的表面覆盖第二保护层58(Coverlay)；而后在第一保护层59内开设孔592。被所述孔592暴露的是金属结构作为焊盘。所述焊盘是可以是前述的第一焊盘、第二焊盘和第三焊盘。
常规的三层电路板(柔性电路板)厚度较厚，会挤压显示面板和电子设备的整机空间。本申请实施例采用双层板+单层板结构，可大幅减少电路板的整体厚度。其中，双层板用来走信号线；单层板的大部分区域铺实金属，用来屏蔽信号干扰。
如图17，在所述孔592内形成焊膏513。所述焊膏513的材质可以是锡。所述焊膏513与孔592下方的焊盘电连接。
如图18，在所述第一保护层59和焊膏513的上方形成导通体51。所述导通体51的材质可以是金属材料，比如铜。将导通体51放置于焊膏513上后，可通过退火工艺来固化导通体51与焊膏513之间的连接、固定。所述导通体51用于连接两个不同的焊盘。
在本申请中，不同实施例在不冲突的情况下，可以互为补充。
在本申请中，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性。术语“多个”、“若干”指两个或两个以上，除非另有明确的限定。
本领域技术人员在考虑说明书及实践这里公开的公开后，将容易想到本申请的其它实施方案。本申请旨在涵盖本申请的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本申请的一般性原理并包括本申请未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本申请的真正范围和精神由下面的权利要求指出。
应当理解的是，本申请并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本申请的范围仅由所附的权利要求来限制。

Claims (15)

  1. 一种显示面板，其特征在于，所述显示面板包括：
    显示基板，具有显示区与接线区，所述显示区包括多个像素单元，所述接线区设置有多个引脚，所述多个引脚包括第一引脚；
    驱动芯片，安装于所述显示基板的所述接线区，具有多个接口，所述多个接口包括使能接口，所述使能接口被配置为控制一通信协议的使用，所述使能接口与所述第一引脚电性相连；
    电路板，具有多个金手指，所述多个金手指包括第一金手指，所述电路板的多个金手指与所述多个引脚连接，所述第一金手指与所述第一引脚连接；
    其中，所述使能接口通过所述电路板能够被施加第一电位信号，也能够被施加第二电位信号；所述使能接口被施加第一电位信号时，所述通信协议不被使用；所述使能接口被施加第二电位信号时，所述通信协议被使用。
  2. 如权利要求1所述的显示面板，其特征在于，所述通信协议包括QSPI协议。
  3. 如权利要求2所述的显示面板，其特征在于，在所述QSPI协议不被使用时，MIPI通信协议被使用。
  4. 如权利要求1所述的显示面板，其特征在于，所述电路板的多个金手指通过绑定的方式与所述多个引脚连接，所述第一金手指通过绑定的方式与所述第一引脚连接。
  5. 如权利要求1所述的显示面板，其特征在于，所述第一电位信号为高电位，所述第二电位信号为低电位。
  6. 如权利要求1所述的显示面板，其特征在于，所述多个接口还包括第二接口和第三接口，所述第二接口和所述第三接口中的一个用于提供第一电位信号，另一个用于提供第二电位信号；
    所述多个引脚还包括第二引脚和第三引脚，所述第二接口与所述第二引脚电性相连，所述第三接口与所述第三引脚电性相连；
    所述多个金手指还包括第二金手指和第三金手指，所述第二金手指与所述第二引脚连接，所述第三金手指与所述第三引脚连接；
    所述电路板还具有多个焊盘，所述多个焊盘包括第一焊盘、第二焊盘与第三焊盘，所述第一焊盘与所述第一金手指电性相连，所述第二焊盘与所述第二金手指电性相连，所述第三焊盘与所述第三金手指电性相连；
    所述第一焊盘择一地与所述第二焊盘或所述第三焊盘连接。
  7. 如权利要求6所述的显示面板，其特征在于，所述第二金手指通过绑定的方式与所述第二引脚连接，所述第三金手指通过绑定的方式与所述第三引脚连接。
  8. 如权利要求6所述的显示面板，其特征在于，所述第一焊盘通过所述电路板内的一走线与所述第一金手指电性相连，所述第二焊盘通过所述电路板内的一走线与所述第二金手指电性相连，所述第三焊盘通过所述电路板内的一走线与所述第三金手指电性相连。
  9. 如权利要求6所述的显示面板，其特征在于，所述第二焊盘、所述第三焊盘均与所述第一焊盘相邻，且所述第二焊盘与所述第三焊盘设置在所述第一焊盘的不同侧。
  10. 如权利要求6所述的显示面板，其特征在于，所述第一焊盘与所述第二焊盘通过设置在所述电路板表面上的一导通体实现连接；
    或，所述第一焊盘与所述第三焊盘通过设置在所述电路板表面上的一导通体实现连接。
  11. 如权利要求1所述的显示面板，其特征在于，所述电路板还具有第五焊盘与板对板接口，所述第五焊盘具有第一电位，用于向所述第一金手指提供第一电位信号，所述第五焊盘与所述第一金手指之间连接有电阻元件；
    所述板对板接口与所述第一金手指电性相连，并且所述板对板接口能够在第一状态和第二状态之间切换，在所述第一状态，所述板对板接口处于高阻态或浮接状态；在所述第二状态，所述板对板接口具有第二电位，向所述使能接口提供第二电位信号。
  12. 如权利要求11所述的显示面板，其特征在于，所述第五焊盘为与地相接。
  13. 如权利要求1所述的显示面板，其特征在于，所述多个接口还包括第二接口，所述第二接口用于选择性地提供第一电位信号或第二电位信号；
    所述多个引脚还包括第二引脚，所述第二接口与所述第二引脚电性相连；所述多个金手指还包括第二金手指，所述第二金手指与所述第二引脚连接，所述第二金手指与第一金手指电性相连。
  14. 如权利要求13所述的显示面板，其特征在于，所述第二接口为GPIO接口；所述第二接口通过编程的方式切换输出第一电位信号或第二电位信号。
  15. 一种电子设备，其特征在于，所述电子设备包括如权利要求1至14任一项所述的显示面板。
PCT/CN2024/096430 2023-06-30 2024-05-30 显示面板以及电子设备 Ceased WO2025001737A1 (zh)

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