WO2024259767A1 - 一种相变材料及基于其的相变存储器和制备方法 - Google Patents

一种相变材料及基于其的相变存储器和制备方法 Download PDF

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WO2024259767A1
WO2024259767A1 PCT/CN2023/107806 CN2023107806W WO2024259767A1 WO 2024259767 A1 WO2024259767 A1 WO 2024259767A1 CN 2023107806 W CN2023107806 W CN 2023107806W WO 2024259767 A1 WO2024259767 A1 WO 2024259767A1
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phase change
change material
change memory
insulating layer
functional layer
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French (fr)
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程晓敏
靳杰
曾运韬
缪向水
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Huazhong University of Science and Technology
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/14—Thermal energy storage

Definitions

  • the present invention belongs to the technical field of memory in micro-nanoelectronics, and more specifically, relates to a phase change material and a phase change memory based on the phase change material and a preparation method thereof.
  • Phase Change Memory is considered to be one of the most likely storage-class memory (SCM) memories to fill the performance gap between dynamic random access memory and flash memory due to its advantages such as good miniaturization performance, non-volatility, fast erase and write speed, and long cycle life.
  • Phase change memory PCM uses the huge resistance difference between the crystalline and amorphous states of phase change materials to store data.
  • the phase change material When the phase change material is in the crystalline state, the material is in a low resistance state, indicating binary storage data "1"; when the phase change is in the amorphous state, the material is in a high resistance state, indicating binary storage data "0".
  • Applying current or voltage pulses to the storage device the temperature of the phase change material layer is changed by the local Joule heating effect, thereby realizing the reversible transformation between the crystalline and amorphous states of the phase change material.
  • phase change memory needs to have performance close to that of dynamic random access memory, which means that the write latency of phase change memory should be close to 10ns, and it should have high cycle endurance.
  • Phase change materials are the core of phase change memory.
  • the crystallization process of Sb-Te system phase change materials is a growth type.
  • the Sb-Te system is dominated by a fast phase change speed in a small size environment.
  • the material has a low melting point, and the power consumption of the device during the reset process based on this material system is correspondingly low.
  • the crystallization temperature of the Sb-Te system is low, and the amorphous thermal stability is poor, resulting in poor data retention ability of the device in the amorphous storage state "0".
  • researchers mainly improve the performance of the Sb-Te system by means of element doping.
  • the purpose of the present invention is to provide a phase change material and a phase change memory and a preparation method based thereon, aiming to solve the problems that the amorphous stability and Set speed of the existing Sb-Te system phase change memory are incompatible, and the reliability of the phase change storage is poor.
  • the present invention provides a phase change material having a general chemical formula of In x (Sb-Te) 1-x , which is obtained by doping the In element into a Sb-Te system phase change material, where x represents the atomic percentage of the In element; wherein 2% ⁇ x ⁇ 40%; and the phase change material is used as a phase change material functional layer of a phase change memory.
  • the Sb—Te system phase change material is one or more of SbTe, Sb 2 Te, Sb 4 Te and Sb 2 Te 3 .
  • the phase change material is in the form of a thin film, and the thickness of the thin film material is 5 nm to 300 nm.
  • the present invention provides a corresponding phase change memory, comprising: a bottom electrode, an insulating layer, a phase change material functional layer and an upper electrode; the insulating layer is disposed above the bottom electrode, and the insulating layer is disposed around the phase change material functional layer; the bottom electrode and the upper electrode are used to
  • the phase change material functional layer is conductive; the insulating layer is used to limit the spatial size of the phase change material functional layer; and the phase change material functional layer is used to realize the phase change storage function.
  • the phase change material functional layer is a confined structure, a mushroom structure or a nanowire structure.
  • the material of the top electrode and the bottom electrode is Al, Ag, Cu, Ti 3 W 7 , Pt, Au, W, Ti or TiN.
  • the material of the insulating layer is SiO 2 , SiC or (ZnS) y (SiO 2 ) 100-y , wherein y is an integer greater than 0 and less than 100.
  • the thickness of the bottom electrode and the upper electrode is 2nm-300nm
  • the thickness of the functional layer is 2nm-500nm
  • the thickness of the insulating layer is 2nm-500nm
  • the size of the through hole of the insulating layer is 10nm-500nm.
  • the present invention provides a corresponding preparation method, which adopts magnetron sputtering, electron beam evaporation, chemical vapor deposition or atomic layer deposition to prepare In x (Sb—Te) 1-x .
  • the present invention provides a phase change material, which is obtained by doping In elements into Sb-Te system phase change materials. Stronger chemical bonds are formed between doped In atoms and Te atoms, thereby improving the amorphous stability of the Sb-Te system phase change materials. Compared with an undoped Sb-Te system phase change film, the crystallization temperature of the phase change film is significantly increased, and the amorphous stability is significantly improved, thereby effectively solving the current situation of insufficient amorphous stability of the Sb-Te system.
  • the present invention provides a phase change memory based on phase change material, wherein the chemical formula of the phase change material is In x (Sb-Te) 1-x . Since the atomic radius of In atoms is slightly different from that of Sb and Te, In atoms form bonds with Te after being doped, which will not have a significant impact on the lattice of the Sb-Te material. At the same time, the grain size of the present invention is significantly reduced, shortening the time required for grain growth. Compared with undoped Sb-Te system phase change memory devices, the phase change memory of the present invention improves amorphous stability without sacrificing Set speed, and can even further improve Set speed.
  • the present invention provides a preparation method based on phase change material, wherein the chemical formula of the phase change material is In x (Sb-Te) 1-x , and the doping element In atoms are combined with the unbonded Te in the Sb-Te system material. After that, the lone pair electrons in the material are reduced, the void distribution in the material is reduced, and the density difference between the crystalline state and the amorphous state is reduced. Compared with the undoped Sb-Te system phase change memory device, the cycle characteristics of the phase change memory device of the present invention are significantly improved.
  • FIG2(a) is an X-ray diffraction pattern of the measured Sb 2 Te 3 , In 6.76 (Sb 2 Te 3 ) 93.24 , In 11.48 (Sb 2 Te 3 ) 88.52 , In 19.74 (Sb 2 Te 3 ) 80.26 phase change thin films provided in an embodiment of the present invention
  • FIG2( b ) is the grain size of the measured Sb 2 Te 3 , In 6.76 (Sb 2 Te 3 ) 93.24 , In 11.48 (Sb 2 Te 3 ) 88.52 , In 19.74 (Sb 2 Te 3 ) 80.26 phase change thin films provided in an embodiment of the present invention
  • FIG3 is an X-ray photoelectron spectrum of the measured Sb 2 Te 3 , In 6.76 (Sb 2 Te 3 ) 93.24 , In 11.48 (Sb 2 Te 3 ) 88.52 phase change films provided in an embodiment of the present invention
  • FIG4 is a schematic diagram of the phase change unit structure provided by an embodiment of the present invention.
  • FIG5 is a SET performance test diagram of the Sb 2 Te 3 and In 6.76 (Sb 2 Te 3 ) 93.24 phase change memory provided by an embodiment of the present invention
  • FIG6(a) is a test diagram of the cycle characteristics of the In 6.76 (Sb 2 Te 3 ) 93.24 phase change memory provided by an embodiment of the present invention; wherein the widths of the SET and RESET voltage pulses are both 5ns;
  • FIG6( b ) is a test diagram of the cycle characteristics of the Sb 2 Te 3 phase change memory in an embodiment of the present invention; wherein the widths of the SET and RESET voltage pulses are both 50 ns;
  • FIG. 7 shows the void concentrations of three amorphous materials, namely, Sb 2 Te 3 , In 5 (Sb 2 Te 3 ) 95 , and In 10 (Sb 2 Te 3 ) 90 in an embodiment of the present invention
  • 1 - substrate eg, single crystal silicon substrate with SiO 2 on the surface
  • 2 - bottom electrode eg, Pt
  • 3 - insulating layer eg, SiO 2
  • 4 - phase change material functional layer eg, Pt
  • the present invention provides a phase change material In x (Sb-Te) 1-x .
  • the In element is doped into the Sb-Te system phase change material, it forms a stronger chemical bond with the Te atom, thereby improving the amorphous thermal stability of the Sb-Te system phase change material.
  • the atomic radius of In is slightly different from that of Sb and Te, and the In atom Te will not destroy the lattice of the Sb-Te material after bonding.
  • the grain size of the phase change material provided by the present invention is significantly reduced, which shortens the time required for grain growth, improves the SET speed of the phase change memory device, and achieves a simultaneous improvement in amorphous stability and crystallization speed.
  • the In atom combines with the unbonded Te in the Sb-Te system phase change material, the lone pair electrons and void distribution in the material are reduced, the density difference between the crystalline and amorphous states of the material is reduced, and the cycle characteristics of the phase change memory device are improved.
  • the chemical formula of the phase change material is In x (Sb-Te) 1-x , which is obtained by doping the In element into the Sb-Te system phase change material, where x represents the atomic percentage of the In element; wherein 2% ⁇ x ⁇ 40%; the phase change material is used as a phase change material functional layer of a phase change memory.
  • the Sb—Te system phase change material is one or more of SbTe, Sb 2 Te, Sb 4 Te and Sb 2 Te 3 .
  • the phase change material is in the form of a thin film, and the thickness of the thin film material is 5 nm to 300 nm.
  • the present invention provides a corresponding phase change memory, including: a bottom electrode, an insulating layer, a phase change material functional layer and an upper electrode; the insulating layer is placed above the bottom electrode, and the insulating layer is arranged around the phase change material functional layer; the bottom electrode and the upper electrode are used to conduct electricity for the phase change material functional layer; the insulating layer is used to limit the spatial size of the phase change material functional layer; the phase change material functional layer is used to realize the phase change storage function.
  • the phase change material functional layer is a confined structure, a mushroom structure or a nanowire structure.
  • the material of the top electrode and the bottom electrode is Al, Ag, Cu, Ti 3 W 7 , Pt, Au, W, Ti or TiN.
  • the material of the insulating layer is SiO 2 , SiC or (ZnS) y (SiO 2 ) 100-y , wherein y is An integer greater than 0 and less than 100.
  • the thickness of the bottom electrode and the upper electrode is 2nm-300nm
  • the thickness of the functional layer is 2nm-500nm
  • the thickness of the insulating layer is 2nm-500nm
  • the size of the through hole of the insulating layer is 10nm-500nm.
  • the present invention provides a corresponding preparation method, which adopts magnetron sputtering, electron beam evaporation, chemical vapor deposition or atomic layer deposition to prepare In x (Sb—Te) 1-x .
  • phase change material phase change memory and preparation method of the present invention in detail, specific embodiments are described in detail below.
  • This embodiment provides a method for preparing an In-doped Sb-Te phase-change memory thin film material with high thermal stability, low delay and high reliability, wherein the general chemical formula is In x (Sb-Te) 1-x , and the value range of x is adjusted by the In target sputtering power;
  • the chemical formula of the In x (Sb—Te) 1-x phase change material is In x (Sb 2 Te 3 ) 1-x
  • the phase change memory thin film material is prepared by magnetron sputtering.
  • S1 Select a silicon wafer substrate with a crystal orientation of (100) and a SiO 2 layer of about 1 ⁇ m thick on the surface of the silicon wafer, and cut a substrate of 2 cm ⁇ 2 cm with a silicon wafer cutter;
  • the substrate is then transferred to an appropriate amount of anhydrous ethanol and cleaned for 3-5 minutes at the same power; the substrate is cleaned with deionized water, and then the deionized water is blown off with a nitrogen gun to obtain a dry and clean silicon wafer substrate;
  • the Sb 2 Te 3 phase change film was prepared by magnetron sputtering.
  • the preparation method of the Sb 2 Te 3 phase change film is the same as the steps in Example 1, except that the AC sputtering power of the Sb 2 Te 3 target is set to 30W, and the DC sputtering power of the In target is 0W.
  • D1 Use a silicon wafer cutter to cut a 8mm ⁇ 5mm sample from the film sample, place it on the temperature-controlled probe station, and insert two probes in the center of the sample with a spacing of about 5mm;
  • D2 Cover the temperature control detection platform with a lid and seal it with screws, then introduce high-purity nitrogen to prevent the phase change material from oxidizing during the heating process;
  • D3 Set up an automatic heating program.
  • the temperature-controlled detection platform rises from room temperature to 300°C at a rate of 12°C/min.
  • the 4200 semiconductor tester tracks and measures the resistance of the phase change material from 50°C.
  • the test voltage applied to the film is 0.1V, and the sampling interval is 0.1s.
  • the change of the resistance of the phase change film with temperature is obtained through the above steps, as shown in Figure 1.
  • the crystallization temperature of the pure ST phase change film is about 110°C.
  • the In doping concentration is 6.76at.%, 11.48at.%, 19.74at.%, and 26.46at.%
  • the corresponding crystallization temperatures of the phase change film are about 170.8°C, 194.7°C, 224.4°C, and 241.5°C, respectively.
  • the results show that after the incorporation of In atoms, the crystallization temperature of the phase change film is greatly improved, and the amorphous thermal stability is also greatly improved. Moreover, the crystallization temperature and amorphous thermal stability increase with the increase of doping concentration.
  • a 1 cm ⁇ 1 cm sample was cut from the film sample using a silicon wafer knife and placed in a vacuum annealing furnace;
  • the lid of the annealing furnace was closed to evacuate the air, and the sample was heated at a constant temperature of 300°C for 20 minutes;
  • the annealed sample was placed on the stage of the X-ray diffractometer, and the ray scanning range was set to 10-60°, with a collection time of 0.1 s per step.
  • the grain size in the Sb 2 Te 3 film is the largest, and as the In doping concentration increases, the grain size decreases.
  • the reduction of the grain size is conducive to shortening the growth time in the crystallization process and improving the Set speed of the phase change memory.
  • the interfaces in the material increase, and the interface effect will block atomic migration, which is beneficial to improving the cycle characteristics of phase change memory devices.
  • FIG3 shows the test results of Te atoms in three film samples: Sb 2 Te 3 , In 6.76 (Sb 2 Te 3 ) 93.24 , and In 11.48 (Sb 2 Te 3 ) 88.52 .
  • X-ray photoionization causes the inner electrons of atoms to be photoionized to generate vacancies.
  • the splitting spectrum of the Te element is mainly 3d 3/2 and 3d 5/2 of the d orbital.
  • Te mainly forms bonds with Sb, and the binding energies of Te 3d 3/2 and Te 3d 5/2 electron orbitals are 583.1eV and 572.7eV, respectively.
  • the binding energies of Te 3d 3/2 and Te 3d 5/2 electron orbitals decrease to 582.9eV and 572.5eV, respectively.
  • the present embodiment provides a method for preparing a phase change memory based on In-doped Sb-Te phase change memory material with high thermal stability, low delay and high reliability; the phase change memory is prepared on a substrate, including a bottom electrode and an upper electrode for applying an electrical signal, a functional layer for realizing phase change storage and an insulating layer for insulation isolation.
  • FIG4 is a schematic structural diagram of a phase change memory; wherein 1 is a substrate, 2 is a bottom electrode, 3 is an insulating layer, 4 is a phase change material functional layer, and 5 is an top electrode; in this embodiment, the substrate is made of silicon material, the top electrode and the bottom electrode are made of Pt material, the insulating layer is SiO 2 , and the phase change layer is In-doped Sb 2 Te 3 or pure Sb 2 Te 3 .
  • the chemical formula of the In-doped Sb 2 Te 3 phase change material functional layer is In 6.76 (Sb 2 Te 3 ) 93.24
  • the phase change storage material is prepared by magnetron sputtering.
  • Step 1 Select a silicon wafer substrate with a crystal orientation of (100) and a SiO 2 layer of about 1 ⁇ m thick on the surface of the silicon wafer; use a silicon wafer knife to cut out a substrate of size 3 cm ⁇ 3 cm; put the cut substrate into an acetone solution and ultrasonically clean it for 5 minutes to remove dust particles and stains on the surface of the substrate; then transfer the substrate to an appropriate amount of anhydrous ethanol and ultrasonically clean it for 3-5 minutes; wash the substrate with deionized water, and then blow off the deionized water with a nitrogen gun to obtain a dry and clean silicon wafer substrate.
  • Step 2 Use magnetron sputtering to deposit about 100 nm of Pt on the substrate to complete the preparation of the bottom electrode; wherein the background vacuum is 1 ⁇ 10 -4 Pa, the argon pressure is 0.5 Pa, the Pt target DC sputtering power is 40 W, and the sputtering time is 800 s;
  • Step 3 Use plasma enhanced chemical vapor deposition to deposit a SiO2 dielectric layer of about 100 nm on the bottom electrode at a reaction temperature of 300°C to complete the preparation of the insulating layer;
  • Step 4 Use a coating machine to evenly spin-coat a layer of electron beam photoresist on the SiO2 insulating layer, and use electron beam exposure and development processes to form a photoresist mask with small holes on the SiO2 insulating layer.
  • the small holes are circular and have a diameter of 250nm;
  • Step 5 Use plasma etching process to etch the SiO2 dielectric layer, and finally form a through hole with a diameter of 250nm and a depth of 100nm;
  • Step 6 Place the etched sample in the degumming solution and let it stand for 8 hours to ensure that the electron beam photoresist is completely removed;
  • Step 7 Use a coating machine to evenly spin-coat a layer of ultraviolet photoresist on the SiO2 insulating layer, and use ultraviolet exposure and development processes to form a photoresist mask with square holes on the SiO2 insulating layer; each square hole has a side length of 100 ⁇ m, and the center position is aligned with the center of the small hole;
  • Step 8 Deposit about 100nm of phase change material In 6.76 (Sb 2 Te 3 ) 93.24 by magnetron sputtering; wherein, the vacuum of the chamber is evacuated to 8 ⁇ 10 -5 Pa, the argon flow rate is set to 80sccm, and the argon pressure is 0.5Pa; the AC sputtering power of the Sb 2 Te 3 target is set to 30W, the DC sputtering power of the In target is 4W, the sputtering time is 500s, and the tray speed is 20r/min;
  • Step 9 Use magnetron sputtering to deposit about 100 nm of Pt on the substrate to complete the preparation of the upper electrode; wherein the background vacuum is 1 ⁇ 10 -4 Pa, the argon pressure is 0.5 Pa, the Pt target DC sputtering power is 40 W, and the sputtering time is 800 s;
  • Step 10 Place the sample in an appropriate amount of acetone solution to completely remove the UV photoresist and dissolve it completely to obtain the preparation of the phase change memory device.
  • phase change memory based on undoped Sb 2 Te 3 phase change memory material is prepared; in this comparative example, the preparation method of the phase change memory based on Sb 2 Te 3 phase change material is the same as the steps in Example 5, except that the AC sputtering power of the Sb 2 Te 3 target is set to 30W, and the DC sputtering power of the In target is 0W;
  • phase change memory based on In x (Sb 2 Te 3 ) 1-x phase change material of the present invention the phase change memory based on In 6.76 (Sb 2 Te 3 ) 93.24 phase change material of Example 5 and the phase change memory device based on Sb 2 Te 3 in Comparative Example 2 were tested for electrical characteristics, and the test results are shown in FIGS. 5 and 6 , respectively.
  • FIG5 is a SET speed performance test diagram of the phase change memory based on In 6.76 (Sb 2 Te 3 ) 93.24 phase change material in Example 5 of the present invention and the phase change memory based on undoped Sb 2 Te 3 phase change material in Comparative Example 2.
  • the device unit can complete the SET process, and the corresponding SET voltages are 0.55V, 0.72V, and 1.5V, respectively.
  • the pulse width is reduced to 40ns, the voltage amplitude continues to increase to 5V, and the device unit cannot complete the SET process.
  • the SET performance of the In 6.76 (Sb 2 Te 3 ) 93.24 device unit is greatly improved, and the SET process of 40ns, 16ns, 10ns, and 5ns can be realized, and the corresponding SET voltages are relatively small, which are 0.4V, 0.88V, 1.1V, and 1.55V, respectively. It can be seen that the SET speed of the In 6.76 (Sb 2 Te 3 ) 93.24 device is faster and the SET operation power consumption is lower.
  • FIG6(a) is a cycle performance test diagram of the phase change memory based on In 6.76 (Sb 2 Te 3 ) 93.24 phase change material in Example 5 of the present invention. Under the SET and RESET pulse widths of 5ns, the In 6.76 (Sb 2 Te 3 ) 93.24 device unit can achieve 3.6 ⁇ 10 8 cycles, with excellent cycle characteristics and reliability.
  • FIG6(b) is a cycle performance test diagram of the phase change memory based on Sb 2 Te 3 phase change material in Comparative Example 2 of the present invention. Under the SET and RESET pulse widths of 50ns, the Sb 2 Te 3 device unit can only achieve 1 ⁇ 10 4 cycles.
  • the cycle number of the In 6.76 (Sb 2 Te 3 ) 93.24 device unit is 4 orders of magnitude higher, and the SET and RESET pulse widths are only 5ns, and the performance is very close to DRAM.
  • the results show that In doping Sb 2 Te 3 can effectively improve the cycle characteristics of the device unit.
  • This embodiment provides a simulation calculation method based on the void distribution of In-doped Sb-Te phase change memory material.
  • Materials Studio software the In element doping concentrations are 0%, 5%, and 10%.
  • the Sb 2 Te 3 phase change memory material is modeled, and the first-principles molecular dynamics calculation is used to simulate the melting and quenching processes of the three models to obtain the amorphous material model.
  • the low electron density distribution in the amorphous materials of Sb 2 Te 3 , In 5 (Sb 2 Te 3 ) 95 , and In 10 (Sb 2 Te 3 ) 90 is calculated respectively, and the area with a low electron density value less than 0.22 is defined as the void distribution area.
  • the void distribution concentration in the amorphous model is statistically analyzed, and the results are shown in Figure 7.
  • the void concentrations of the three amorphous materials of Sb 2 Te 3 , In 5 (Sb 2 Te 3 ) 95 , and In 10 (Sb 2 Te 3 ) 90 are approximately 10.02%, 7.80%, and 5.23%, respectively.
  • the addition of In element effectively reduces the void concentration in Sb 2 Te 3 , which is beneficial to reduce the density difference between the crystalline and amorphous states of the phase change material, reduce the internal stress of the material, and increase the cycle life of the device.
  • the In x (Sb-Te) 1-x material prepared in the embodiment of the present invention is a phase change memory material with high thermal stability, low delay and high reliability.
  • the crystallization temperature test results of the In x (Sb-Te) 1-x phase change material and the Sb-Te phase change material show that the incorporation of In atoms can effectively increase the crystallization temperature of the Sb-Te phase change material and improve the amorphous thermal stability of the material
  • the electrical characteristics test results of the In x (Sb-Te) 1-x phase change memory and the Sb-Te phase change memory show that the incorporation of In atoms improves the amorphous thermal stability of the Sb-Te material while further improving the SET speed of the device.
  • the In x (Sb-Te) 1-x phase change memory device has excellent cycle characteristics and high reliability, and has great potential to become a storage-level memory.

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Abstract

本发明提供了一种相变材料及基于其的相变存储器和制备方法，属于微纳米电子中的存储器技术领域，相变材料为Inx(Sb-Te)1-x，2％<x<40％，采用磁控溅射法、电子束蒸发法、化学气相沉积法或原子层沉积法制备；相变存储器包括底电极、绝缘层、相变材料功能层和上电极。本发明与Sb-Te体系材料相比，该相变材料的结晶温度明显提高，结晶温度随着In元素含量的增加而升高，材料非晶热稳定性得到有效提升。将该材料应用于相变存储器，在提升非晶热稳定性的同时，进一步提升SET速度，降低器件写入时延，并且相变存储器件具有优异的循环特性。

Description

一种相变材料及基于其的相变存储器和制备方法 【技术领域】
本发明属于微纳米电子中的存储器技术领域，更具体地，涉及一种相变材料及基于其的相变存储器和制备方法。
【背景技术】
如今科学技术不断发展，个人电脑和智能手机等数码产品逐步普及，5G、物联网和大数据等通信技术深入生活，信息数据的爆炸式增长对传统存储设备提出了更快、更高可靠性等要求。相变存储器(Phase Change Memory，PCM)凭借其微缩性能好、非易失性、擦写速度快、循环寿命长等优点被认为是最有可能弥补动态随机存储器、闪存之间性能鸿沟的存储级内存(Storage Classic Memory，SCM)存储器之一。
相变存储器PCM利用相变材料在晶态和非晶态巨大的阻值差异以存储数据。当相变材料处于晶态时，材料为低阻态，表示二进制存储数据“1”；当相变处于非晶态时，材料为高阻态，表示二进制存储数据“0”。对存储器件施加电流或电压脉冲，利用局部焦耳热效应改变相变材料层的温度，从而实现相变材料晶态与非晶态之间的可逆转变。对初始态为晶态的相变材料施加幅度大、持续时间短的脉冲信号，使晶态相变材料温度高于熔化温度并快速冷却，从而变成非晶态；反之，对初始态为非晶态的相变材料施加幅度中等、持续时间长的脉冲信号，使相变材料温度介于结晶温度与熔化温度之间，并在充足的时间内冷却转化为晶态。作为存储级内存，相变存储器需要有接近动态随机存储器的性能，意味着相变存储器的写入时延要接近10ns，同时具备较高的循环耐久性。
相变材料是相变存储器的核心。Sb-Te体系相变材料的结晶过程以生长型 为主导，在小尺寸环境下具有很快的相变速度，同时材料熔点较低，基于该材料体系的器件Reset过程中功耗相应较低。但是Sb-Te体系结晶温度低，非晶热稳定性较差，导致器件在非晶存储态“0”的数据保持能力较差。目前研究者主要通过元素掺杂的手段对Sb-Te体系进行性能改良，研究表明不同种类的元素掺入后形成强键合，能够有效提高Sb-Te体系的非晶热稳定性，但其中大部分掺杂元素会牺牲Sb-Te体系的快速结晶优势，增加了器件的SET时延。同时现有Sb-Te体系相变存储材料在晶态和非晶态之间存在较大的密度差异，硫系材料Te元素的孤对电子会导致空位形成，多次擦写后最终在材料中形成空隙分布，Sb-Te体系相变存储器件的循环耐久性不理想。因此，开发一种具有高热稳定性、快速结晶、高可靠性的新型掺杂Sb-Te材料体系及其相变存储器具有重要意义。
【发明内容】
针对现有技术的缺陷，本发明的目的在于提供一种相变材料及基于其的相变存储器和制备方法，旨在解决现有的Sb-Te体系相变存储器非晶稳定性和Set速度不能兼容，而且相变存储的可靠性较差的问题。
为实现上述目的，第一方面，本发明提供了一种相变材料，化学通式为Inx(Sb-Te)1-x，将In元素掺入Sb-Te体系相变材料中得到，x代表In元素的原子百分比；其中，2％＜x＜40％；所述相变材料作为相变存储器的相变材料功能层。
进一步优选地，Sb-Te体系相变材料为SbTe、Sb2Te、Sb4Te和Sb2Te3的一种或者多种。
进一步优选地，相变材料为薄膜状，薄膜材料厚度为5nm～300nm。
第二方面，基于上述提供的相变材料，本发明提供了相应的相变存储器，包括：底电极、绝缘层、相变材料功能层和上电极；绝缘层置于底电极上方，且所述绝缘层设置于相变材料功能层的四周；底电极和上电极用于为相变材 料功能层导电；绝缘层用于限制相变材料功能层的空间尺寸；相变材料功能层用于实现相变存储功能。
进一步优选地，相变材料功能层为限制型结构、蘑菇型结构或纳米线结构。
进一步优选地，上电极和底电极的材料为Al、Ag、Cu、Ti3W7、Pt、Au、W、Ti或TiN。
进一步优选地，绝缘层的材料为SiO2、SiC或(ZnS)y(SiO2)100-y，其中，y为大于0小于100的整数。
进一步优选地，底电极和上电极的厚度为2nm～300nm，功能层的厚度为2nm～500nm，绝缘层的厚度为2nm～500nm，绝缘层通孔尺寸为10nm～500nm。
第三方面，基于提供的相变材料，本发明提供了相应的制备方法，采用磁控溅射法、电子束蒸发法、化学气相沉积法或原子层沉积法制备Inx(Sb-Te)1-x。
总体而言，通过本发明所构思的以上技术方案与现有技术相比，具有以下有益效果：
本发明提供了一种相变材料，将In元素掺入Sb-Te体系相变材料中得到，通过掺杂元素In原子与Te原子形成更强的化学键，提高Sb-Te体系相变材料的非晶稳定性，对比未掺杂Sb-Te体系相变薄膜，相变薄膜结晶温度明显提高，非晶稳定性明显提升，有效解决当前Sb-Te体系非晶稳定性不足的现状。
本发明提供了一种基于相变材料的相变存储器，其中，相变材料的化学通式为Inx(Sb-Te)1-x，由于In原子的原子半径与Sb和Te相差较小，In原子掺入后与Te成键，不会对Sb-Te材料的晶格产生大的影响，同时，本发明的晶粒尺寸明显减小，缩短了晶粒生长所需时间，对比未掺杂Sb-Te体系相变存储器件，本发明相变存储器在不牺牲Set速度的前提下提升了非晶稳定性，甚至能进一步提高Set速度。
本发明提供了一种基于相变材料的制备方法，其中，相变材料的化学通式为Inx(Sb-Te)1-x，通过掺杂元素In原子与Sb-Te体系材料中的未成键Te结合 后，材料中的孤对电子减少，材料中的空隙分布降低，晶态和非晶态间的密度差异减小，对比未掺杂Sb-Te体系相变存储器件，本发明相变存储器件的循环特性显著提升。
【附图说明】
图1是本发明实施例提供的所测Sb2Te3、In6.76(Sb2Te3)93.24、In11.48(Sb2Te3)88.52、In19.74(Sb2Te3)80.26和In26.46(Sb2Te3)73.54相变薄膜的R-T曲线；
图2(a)是本发明实施例提供的所测Sb2Te3、In6.76(Sb2Te3)93.24、In11.48(Sb2Te3)88.52、In19.74(Sb2Te3)80.26相变薄膜的X射线衍射图；
图2(b)是本发明实施例提供的所测Sb2Te3、In6.76(Sb2Te3)93.24、In11.48(Sb2Te3)88.52、In19.74(Sb2Te3)80.26相变薄膜的晶粒尺寸；
图3是本发明实施例提供的所测Sb2Te3、In6.76(Sb2Te3)93.24、In11.48(Sb2Te3)88.52相变薄膜的X射线光电子能谱图；
图4是本发明实施例提供的相变单元结构示意图；
图5是本发明实施例提供的Sb2Te3和In6.76(Sb2Te3)93.24相变存储器的SET性能测试图；
图6(a)是本发明实施例提供的In6.76(Sb2Te3)93.24相变存储器循环特性测试图；其中，SET、RESET电压脉冲宽度均为5ns；
图6(b)是本发明实施例中Sb2Te3相变存储器循环特性测试图；其中，SET、RESET电压脉冲宽度均为50ns；
图7是本发明实施例中Sb2Te3、In5(Sb2Te3)95、In10(Sb2Te3)90三种非晶材料的空隙浓度；
附图标记的含义如下：1-衬底(如表面有SiO2的单晶硅衬底)；2-底电极(如Pt)；3-绝缘层(如SiO2)；4-相变材料功能层；5-上电极(如Pt)。
【具体实施方式】
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实 施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
第一方面，本发明提供了一种相变材料Inx(Sb-Te)1-x，In元素掺入Sb-Te体系相变材料后，与Te原子形成更强的化学键，提高Sb-Te体系相变材料的非晶热稳定性；In的原子半径与Sb、Te相差较小，In原子Te成键后不会破坏Sb-Te材料的晶格；本发明提供的相变材料的晶粒尺寸明显减小，缩短了晶粒生长所需时间，提高相变存储器件的SET速度，实现非晶稳定性和结晶速度的同步提升；同时，In原子与Sb-Te体系相变材料中的未成键Te结合后，减少了材料中的孤对电子和空隙分布，减小了材料晶态和非晶态间的密度差异，提升了相变存储器件的循环特性。
更为具体地，相变材料的化学通式为Inx(Sb-Te)1-x，将In元素掺入Sb-Te体系相变材料中得到，x代表In元素的原子百分比；其中，2％＜x＜40％；所述相变材料作为相变存储器的相变材料功能层。
进一步优选地，Sb-Te体系相变材料为SbTe、Sb2Te、Sb4Te和Sb2Te3的一种或者多种。
进一步优选地，相变材料为薄膜状，薄膜材料厚度为5nm～300nm。
第二方面，基于上述提供的相变材料，本发明提供了相应的相变存储器，包括：底电极、绝缘层、相变材料功能层和上电极；绝缘层置于底电极上方，且所述绝缘层设置于相变材料功能层的四周；底电极和上电极用于为相变材料功能层导电；绝缘层用于限制相变材料功能层的空间尺寸；相变材料功能层用于实现相变存储功能。
进一步优选地，相变材料功能层为限制型结构、蘑菇型结构或纳米线结构。
进一步优选地，上电极和底电极的材料为Al、Ag、Cu、Ti3W7、Pt、Au、W、Ti或TiN。
进一步优选地，绝缘层的材料为SiO2、SiC或(ZnS)y(SiO2)100-y，其中，y为 大于0小于100的整数。
进一步优选地，底电极和上电极的厚度为2nm～300nm，功能层的厚度为2nm～500nm，绝缘层的厚度为2nm～500nm，绝缘层通孔尺寸为10nm～500nm。
第三方面，基于提供的相变材料，本发明提供了相应的制备方法，采用磁控溅射法、电子束蒸发法、化学气相沉积法或原子层沉积法制备Inx(Sb-Te)1-x。
为了进一步详细说明本发明相变材料、相变存储器以及制备方法，下面以具体的实施例予以详细说明。
实施例1
本实施例提供了一种In掺杂Sb-Te高热稳定性、低时延、高可靠性相变存储薄膜材料的制备方法，化学通式为Inx(Sb-Te)1-x，x的取值范围由In靶溅射功率进行调节；
更为具体地，在本实施例中，Inx(Sb-Te)1-x相变材料的化学通式为Inx(Sb2Te3)1-x，相变存储薄膜材料采用磁控溅射法制备，具体工艺流程如下：
S1：选取晶向为(100)的硅片衬底，硅片表面有约1μm厚的SiO2，用硅片刀切出尺寸2cm×2cm的衬底；
S2：将切好的衬底放入丙酮溶液中，超声清洗5-10分钟以去除衬底表面灰尘颗粒和污渍；
S3：再将衬底转移到适量无水乙醇中，同样功率下清洗3-5分钟；用去离子水清洗衬底，接着用氮气枪吹掉去离子水，得到干燥洁净的硅片衬底；
S4：将打磨好的Sb2Te3靶和In靶分别装入交流溅射靶位和直流溅射靶位，用高温双面胶将衬底固定在托盘上，并放入进样室；
S5：关闭腔体和进样室，打开机械泵和真空计，待腔体真空度到5×10-3Pa，开启分子泵，腔体真空度抽至8×10-5Pa；
S6：将气流量设置为80sccm，氩气压强为0.5Pa；将Sb2Te3靶材交流溅射功率设置为30W，In靶直流溅射功率为4W，溅射时间为500s，托盘转速 20r/min；
S7：溅射流程结束后，开进样室取片，重新放入一批衬底，更改In靶直流溅射功率，其余参数不变，重复上述流程得到掺杂浓度为6.76％、11.48％、19.74％和26.49％的相变薄膜样品。
对比例1
对比例采用磁控溅射法制备Sb2Te3相变薄膜，该对比例中，Sb2Te3相变薄膜的制备方法与实施例1中的步骤相同，不同之处在于，Sb2Te3靶材交流溅射功率设置为30W，In靶直流溅射功率为0W。
实施例2
为进一步说明本发明Inx(Sb2Te3)1-x相变材料，对实施例1和对比例1中的Inx(Sb2Te3)1-x和Sb2Te3相变薄膜进行结晶温度测试，具体流程如下：
D1：用硅片刀从薄膜样品中切出8mm×5mm的样片，放置在温控探针台上，将两个探针扎在样品中央，间距约5mm；
D2：盖上温控探测台的盖子，并用螺丝密封，之后通入高纯氮气，避免相变材料在加热过程中氧化；
D3：设置自动升温程序，温控探测台以12℃/min的速率从室温升至300℃，4200半导体测试仪从50℃开始跟踪测量相变材料阻值，对薄膜施加的测试电压为0.1V，采样间隔为0.1s。
通过上述步骤得到相变薄膜电阻随温度的变化，如图1所示。纯ST相变薄膜的结晶温度约为110℃，In掺杂浓度6.76at.％、11.48at.％、19.74at.％和26.46at.％时，相变薄膜对应的结晶温度分别约为170.8℃、194.7℃、224.4℃和241.5℃，结果说明In原子掺入后，相变薄膜的结晶温度得到大幅提升，非晶热稳定性也大幅提高，而且结晶温度和非晶热稳定性随着掺杂浓度的增加而提升。
实施例3
为进一步说明本发明Inx(Sb2Te3)1-x相变材料，对实施例1和对比例1中的中的Inx(Sb2Te3)1-x和Sb2Te3相变薄膜进行X射线衍射测试。具体流程如下：
用硅片刀从薄膜样品中切出1cm×1cm的样片，放置在真空退火炉中；
盖上退火炉的盖子抽真空，将样片在300℃下恒温加热20分钟；
退火完成的样品置于X射线衍射仪的载物台中，将射线扫描范围设置为10-60°，每步收集时长为0.1s。
通过上述步骤得到相变薄膜X射线衍射图谱，如图2(a)所示；从整体上看，在300℃温度下，随着In掺杂浓度增加，材料衍射图谱的衍射峰强度降低，分布变宽，说明材料薄膜的结晶程度降低，非晶热稳定性提高；图2(b)中，利用谢乐公式，计算得到Sb2Te3、In6.76(Sb2Te3)93.24、In11.48(Sb2Te3)88.52、In19.74(Sb2Te3)80.26相变薄膜的晶粒尺寸分别是31.7nm、24.7nm、18.5nm、13.5nm，Sb2Te3薄膜中晶粒尺寸最大，随着In掺杂浓度的增加，晶粒尺寸随之减小。晶粒尺寸的减小有利于缩短结晶过程中的生长时间，提高相变存储器的Set速度。同时，晶粒尺寸减小后，材料中的界面增加，界面效应会阻挡原子迁移，有利于提高相变存储器件的循环特性。
实施例4
为进一步说明本发明Inx(Sb2Te3)1-x相变材料，对上述实施例1中的Inx(Sb2Te3)1-x和对比例1中的Sb2Te3相变薄膜进行X射线光电子能谱测试。图3展示了Sb2Te3、In6.76(Sb2Te3)93.24、In11.48(Sb2Te3)88.52三种薄膜样品中Te原子的测试结果。X射线光致电离使原子内层电子光致电离产生空位，当Te原子的同价壳层有未成对的自旋电子时，内层空位将与之发生耦合，形成不同终态的离子，最终在XPS谱图上呈现出谱线分裂。Te元素的分裂谱主要是d轨道的3d3/2和3d5/2。在ST薄膜中，Te主要与Sb成键，Te 3d3/2和Te 3d5/2电子轨道的结合能分别是583.1eV、572.7eV。当In掺杂含量达到6.76at.％，Te 3d3/2和Te 3d5/2电子轨道的结合能减少到582.9eV、572.5eV，随着In掺杂含量增 加到11.48at.％，两者的结合能再次减少0.1eV。电子轨道的结合能发生变化，说明材料内部的成键情况也出现了变化。Te原子获得电子而带负电，随着In原子的掺入和含量的增加，外层Te 3d电子轨道的结合能降低说明Te原子周围聚集更多电子。同时In原子电负性(1.78)小于Sb(2.05)，X射线光电子能谱测试的结果表明In掺入后与Te结合成更高键能的In-Te键。
实施例5
本实施例提供一种基于In掺杂Sb-Te高热稳定性、低时延、高可靠性相变存储材料的相变存储器的制备方法；相变存储器制备于衬底，包括用于施加电信号的底电极和上电极，用于实现相变存储的功能层和用于绝缘隔离的绝缘层。
更为具体地，底电极和上电极相互分离，并与功能层相连，隔离层紧密包裹功能层，图4为相变存储器的结构示意图；其中，1为衬底，2为底电极，3为绝缘层，4为相变材料功能层，5为上电极；本实施例中，衬底采用硅材料，上电极和底电极采用Pt材料，绝缘层为SiO2，相变层为In掺杂Sb2Te3或纯Sb2Te3。
更为具体地，在本实施例中，In掺杂Sb2Te3相变材料功能层的化学式为In6.76(Sb2Te3)93.24，相变存储材料采用磁控溅射法制备，具体工艺流程如下：
步骤一：选取晶向为(100)的硅片衬底，硅片表面有约1μm厚的SiO2；用硅片刀切出尺寸3cm×3cm的衬底；将切好的衬底放入丙酮溶液，超声清洗5分钟以去除衬底表面灰尘颗粒和污渍；再将衬底转移到适量无水乙醇中，超声清洗3-5分钟；用去离子水清洗衬底，接着用氮气枪吹掉去离子水，得到干燥洁净的硅片衬底。
步骤二：使用磁控溅射在衬底上分别沉积约100nm的Pt，完成底电极的制备；其中，本底真空1×10-4Pa，氩气压力0.5Pa，Pt靶直流溅射功率40W，溅射时间800s；
步骤三：使用等离子体增强化学气相沉积法在底电极上沉积约100nm的SiO2介质层，反应温度为300℃，完成绝缘层的制备；
步骤四：用匀胶机在SiO2绝缘层上均匀旋涂一层电子束光刻胶，利用电子束曝光和显影工艺在SiO2绝缘层上形成带小孔的光刻胶掩膜，小孔为圆形，直径250nm；
步骤五：使用等离子刻蚀工艺对SiO2介质层进行刻蚀，最终形成直径250nm、深100nm的通孔；
步骤六：将刻蚀完成的样品置入去胶液中，静置8小时，确保电子束光刻胶完全去除；
步骤七：用匀胶机在SiO2绝缘层上均匀旋涂一层紫外光刻胶，利用紫外曝光和显影工艺在SiO2绝缘层上形成带正方形孔的光刻胶掩膜；每个正方形孔边长100μm，中心位置与小孔中心对齐；
步骤八：使用磁控溅射法沉积约100nm相变材料In6.76(Sb2Te3)93.24；其中，腔体真空度抽至8×10-5Pa，氩气流量设置为80sccm，氩气压强为0.5Pa；Sb2Te3靶材交流溅射功率设置为30W，In靶直流溅射功率为4W，溅射时间为500s，托盘转速20r/min；
步骤九：使用磁控溅射在衬底上分别沉积约100nm的Pt，完成上电极的制备；其中，本底真空1×10-4Pa，氩气压力0.5Pa，Pt靶直流溅射功率40W，溅射时间800s；
步骤十：将样品置于适量丙酮溶液，完全去除紫外光刻胶完全溶解后，得到相变存储器件的制备。
对比例2
本对比例制备基于未掺杂Sb2Te3相变存储材料的相变存储器；该对比例中，基于Sb2Te3相变材料的相变存储器的制备方法与实施例5中的步骤相同，不同之处在于，Sb2Te3靶材交流溅射功率设置为30W，In靶直流溅射功率为 0W；
实施例6
为进一步说明本发明所述基于Inx(Sb2Te3)1-x相变材料的相变存储器，将上述实施例5的基于In6.76(Sb2Te3)93.24相变材料的相变存储器和对比例2中的基于Sb2Te3相变存储器件进行电学特性测试，测试结果分别如图5和图6。
图5是本发明实施例5中基于In6.76(Sb2Te3)93.24相变材料的相变存储器和对比例2中的基于未掺杂Sb2Te3相变材料的相变存储器的SET速度性能测试图，从图5可知，对于未掺杂Sb2Te3相变存储器，脉宽为200ns、100ns、50ns时，器件单元能够完成SET过程，对应的SET电压分别是0.55V、0.72V、1.5V，当脉宽减少到40ns时，电压幅值持续增加到5V，器件单元也无法完成SET过程。In6.76(Sb2Te3)93.24器件单元的SET性能大幅提升，能够实现40ns、16ns、10ns、5ns的SET过程，且对应的SET电压较小，分别是0.4V、0.88V、1.1V和1.55V。由此可见，In6.76(Sb2Te3)93.24器件的SET速度更快，SET操作功耗更低。
图6(a)是本发明实施例5中基于In6.76(Sb2Te3)93.24相变材料的相变存储器循环性能测试图。在5ns的SET和RESET脉宽下，In6.76(Sb2Te3)93.24器件单元能够实现3.6×108次循环，具有优异的循环特性和可靠性。图6(b)是本发明对比例2中基于Sb2Te3相变材料的相变存储器循环性能测试图，在50ns的SET和RESET脉宽下，Sb2Te3器件单元只能够实现1×104次循环。相比于未掺杂Sb2Te3器件，In6.76(Sb2Te3)93.24器件单元的循环次数高出4个数量级，且SET、RESET的脉宽只有5ns，性能非常接近DRAM。结果说明In掺入Sb2Te3后能够有效提升器件单元的循环特性。
实施例7
本实施例提供一种基于In掺杂Sb-Te相变存储材料空隙分布的模拟计算方法。利用Materials Studio软件对In元素掺入浓度分别为0％、5％和10％ 的Sb2Te3相变存储材料进行建模，利用第一性原理分子动力学计算对三个模型进行熔化、淬火过程的模拟仿真得到非晶材料模型，并分别计算Sb2Te3、In5(Sb2Te3)95、In10(Sb2Te3)90非晶材料中的低电子密度分布，将低电子密度值小于0.22的区域定义为空隙分布区域。对非晶模型中空隙分布浓度进行统计，结果如图7所示，Sb2Te3、In5(Sb2Te3)95、In10(Sb2Te3)90三种非晶材料的空隙浓度分别约为10.02％、7.80％和5.23％。显然掺入In元素有效降低了Sb2Te3中的空隙浓度，有利于降低相变材料晶态和非晶态的密度差异，降低材料内部应力，增加器件的循环使用寿命。
综上所述，本发明实施例中制备的Inx(Sb-Te)1-x材料是一种高热稳定性、低时延、高可靠性相变存储材料。其中，Inx(Sb-Te)1-x相变材料和Sb-Te相变材料的结晶温度测试结果说明In原子的掺入可以有效提高Sb-Te相变材料的结晶温度，提升材料的非晶热稳定性；而且Inx(Sb-Te)1-x相变存储器和Sb-Te相变存储器的电学特性测试结果说明In原子的掺入在提高Sb-Te材料非晶热稳定性的同时，进一步提高器件的SET速度，与此同时Inx(Sb-Te)1-x相变存储器件具有优异的循环特性和高可靠性，具有成为存储级内存的巨大潜力。
本领域的技术人员容易理解，以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (9)

  1. 一种相变材料，其特征在于，化学通式为Inx(Sb-Te)1-x，将In元素掺入Sb-Te体系相变材料中得到，x代表In元素的原子百分比；其中，2％＜x＜40％；所述相变材料作为相变存储器的相变材料功能层。
  2. 根据权利要求1所述的相变材料，其特征在于，Sb-Te体系相变材料为SbTe、Sb2Te、Sb4Te和Sb2Te3的一种或者多种。
  3. 根据权利要求1所述的相变材料，其特征在于，相变材料为薄膜状，薄膜材料厚度为5nm～300nm。
  4. 一种基于权利要求1至3所述的相变材料的相变存储器，其特征在于，包括：底电极、绝缘层、相变材料功能层和上电极；所述绝缘层置于底电极上方，且所述绝缘层设置于所述相变材料功能层的四周；所述底电极和上电极用于为相变材料功能层导电；所述绝缘层用于限制相变材料功能层的空间尺寸；所述相变材料功能层用于实现相变存储功能。
  5. 根据权利要求4所述的相变存储器，其特征在于，所述相变材料功能层为限制型结构、蘑菇型结构或纳米线结构。
  6. 根据权利要求4所述的相变存储器，其特征在于，所述上电极和底电极的材料为Al、Ag、Cu、Ti3W7、Pt、Au、W、Ti或TiN。
  7. 根据权利要求4所述的相变存储器，其特征在于，所述绝缘层的材料为SiO2、SiC或(ZnS)y(SiO2)100-y，其中，y为大于0小于100的整数。
  8. 根据权利要求4所述的相变存储器，其特征在于，所述底电极和上电极的厚度为2nm～300nm，所述功能层的厚度为2nm～500nm，所述绝缘层的厚度为2nm～500nm，所述绝缘层通孔尺寸为10nm～500nm。
  9. 一种基于权利要求1至3任一所述的相变材料的制备方法，其特征在于，采用磁控溅射法、电子束蒸发法、化学气相沉积法或原子层沉积法制备Inx(Sb-Te)1-x。
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CN115084370A (zh) * 2022-06-30 2022-09-20 华中科技大学 一种相变薄膜、薄膜制备方法及相变存储器
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