WO2024255427A1 - 隔离结构及集成电路 - Google Patents

隔离结构及集成电路 Download PDF

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Publication number
WO2024255427A1
WO2024255427A1 PCT/CN2024/087925 CN2024087925W WO2024255427A1 WO 2024255427 A1 WO2024255427 A1 WO 2024255427A1 CN 2024087925 W CN2024087925 W CN 2024087925W WO 2024255427 A1 WO2024255427 A1 WO 2024255427A1
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WIPO (PCT)
Prior art keywords
field plate
floating field
region
ldmos
junction terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/CN2024/087925
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English (en)
French (fr)
Inventor
张龙
刘斯扬
张森
盘成务
何乃龙
顾力晖
孙伟锋
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Southeast University
CSMC Technologies Fab2 Co Ltd
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Southeast University
CSMC Technologies Fab2 Co Ltd
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Priority to JP2025538822A priority Critical patent/JP2026501401A/ja
Publication of WO2024255427A1 publication Critical patent/WO2024255427A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/051—Manufacture or treatment of isolation region based on field-effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/50—Isolation regions based on field-effect

Definitions

  • the present invention relates to the field of semiconductor manufacturing, in particular to an isolation structure and an integrated circuit.
  • High-voltage integrated circuits contain high-voltage semiconductor devices and low-voltage semiconductor devices, that is, there are high-voltage areas and low-voltage areas, so a high-low voltage isolation structure is needed to isolate the potential between the high-voltage area and the low-voltage area.
  • the isolation structure includes a junction terminal, an isolation ring, and a lateral double-diffused Metal-Oxide-Semiconductor Field Effect Transistor (LDMOS).
  • LDMOS is the gateway for transmitting electrical signals between the high-voltage area and the low-voltage area, and it is easy to become a weak point of breakdown when subjected to high voltage. By using technical means to make the internal potential distribution uniform and avoid the concentration of potential lines, the breakdown voltage of LDMOS can be increased.
  • an isolation structure is provided.
  • An isolation structure includes: a junction terminal, including a plurality of junction terminal floating field plates; a lateral double diffused metal oxide semiconductor field effect transistor, including a plurality of LDMOS floating field plates, each LDMOS floating field plate is electrically connected to at least one junction terminal floating field plate, and the length of each of the junction terminal floating field plates is greater than the length of the LDMOS floating field plate electrically connected thereto.
  • the junction terminal floating field plate and the LDMOS floating field plate are made of conductive material.
  • the above isolation structure can be applied in an integrated circuit, and when the device in the integrated circuit is working, the junction terminal floating field plate on the junction terminal can form an induced potential. Since the LDMOS floating field plate is electrically connected to the junction terminal floating field plate, the induced potential will affect the potential of the lateral double diffused metal oxide semiconductor field effect transistor through the LDMOS floating field plate.
  • each junction terminal floating field plate After each junction terminal floating field plate induces a certain potential on the junction terminal and transmits it to the lateral double diffused metal oxide semiconductor field effect transistor through the LDMOS floating field plate, for the lateral double diffused metal oxide semiconductor field effect transistor, each junction terminal floating field plate is equivalent to an external "voltage source", and the potential in the lateral double diffused metal oxide semiconductor field effect transistor will be controlled by the junction terminal floating field plate and the LDMOS floating field plate.
  • the spacing of each LDMOS floating field plate is controlled, the potential distribution inside the lateral double diffused metal oxide semiconductor field effect transistor can be indirectly controlled, and the spacing of the LDMOS floating field plate can be flexibly adjusted according to design requirements, that is, the free control of the internal potential of the lateral double diffused metal oxide semiconductor field effect transistor is realized, the internal potential distribution of the LDMOS can be uniform, and the breakdown voltage of the LDMOS can be improved.
  • the isolation structure further includes a lateral double diffused metal oxide semiconductor field effect An isolation ring of a transistor is used to isolate the LDMOS field effect transistor from the junction terminal.
  • the isolation ring also includes multiple isolation ring floating field plates, each LDMOS floating field plate is electrically connected to the corresponding junction terminal floating field plate through an isolation ring floating field plate, and one end of each isolation ring floating field plate extends to a corresponding junction terminal floating field plate, and the other end extends to a corresponding LDMOS floating field plate.
  • the lateral double diffused metal oxide semiconductor field effect transistor further includes a source region, a drain region, a gate, a drift region and a field region insulating layer, at least a portion of the drift region is located between the source region and the drain region, the field region insulating layer is located on the drift region, one side of the gate is close to the source region, and the other side is close to the drain region, the number of the LDMOS floating field plates is the same as the junction terminal floating field plates, and the multiple LDMOS floating field plates are electrically connected to the multiple junction terminal floating field plates one by one; the LDMOS floating The field plates include a first field plate arranged near the source region, a second field plate arranged near the drain region, and a third field plate located between the first field plate and the second field plate, the spacing between adjacent third field plates is less than a2, the spacing between one of the second field plates farthest from the drain region and an adjacent third field plate is greater than a3, and the spacing between adjacent second field plates is greater than a3,
  • the lateral double diffused metal oxide semiconductor field effect transistor includes NLDMOS and PLDMOS
  • the isolation ring includes a first isolation ring surrounding the NLDMOS and a second isolation ring surrounding the PLDMOS
  • the length of each of the junction terminal floating field plates is the sum of the lengths of the corresponding LDMOS floating field plate of the NLDMOS and the corresponding LDMOS floating field plate of the PLDMOS.
  • the junction terminal further includes a first insulating layer, and the plurality of junction terminal floating field plates are located on the first insulating layer.
  • the junction terminal also includes a cathode region and an anode region, the conductivity type of the cathode region and the anode region is the same as the conductivity type of the drain region of the NLDMOS, the cathode region is electrically connected to the potential of the source region of the NLDMOS through a metal connection, and the anode region is electrically connected to the potential of the drain region of the NLDMOS through a metal connection.
  • each junction terminal floating field plate is connected with the corresponding isolation ring floating field plate and the corresponding LDMOS floating field plate to form a closed loop.
  • the isolation ring also includes an isolation junction, a protection well and a second insulating layer, the multiple isolation ring floating field plates are located on the second insulating layer, the second insulating layer is located on the isolation junction and the protection well, the conductivity type of the isolation junction and the protection well is opposite to the conductivity type of the drain region of the NLDMOS, and the doping concentration of the protection well is greater than the doping concentration of the isolation junction.
  • each isolation ring floating field plate includes a junction terminal connection portion, an LDMOS connection portion and an intermediate portion, one end of the intermediate portion is connected to the junction terminal connection portion, and the angle between the intermediate portion and the extension line of the junction terminal connection portion on a plane is greater than zero and less than 80 degrees, and the other end of the intermediate portion is connected to the LDMOS connection portion, and the angle between the intermediate portion and the extension line of the LDMOS connection portion on a plane is greater than zero and less than 80 degrees;
  • the protection well is provided directly below at least a portion of the connection position between the junction terminal connection portion and the middle portion, and the protection well is provided directly below at least a portion of the connection position between the LDMOS connection portion and the middle portion.
  • the protection well includes a strip-shaped doped region arranged at the connection position between the multiple junction terminal connection parts and the middle part, and a strip-shaped doped region arranged at the connection position between the multiple LDMOS connection parts and the middle part; and/or the protection well includes a point-shaped doped region arranged in a column at the connection position between the multiple junction terminal connection parts and the middle part, and a point-shaped doped region arranged in a column at the connection position between the multiple LDMOS connection parts and the middle part.
  • the distance between the connection position of the junction terminal connection portion and the middle portion and the edge of the isolation ring is b1
  • the distance between the connection position of the LDMOS connection portion and the middle portion and the edge of the isolation ring is b2
  • b1 is 10% to 30% of the width of the isolation ring
  • b2 is 10% to 30% of the width of the isolation ring.
  • the junction terminal floating field plate, the isolation ring floating field plate and the LDMOS floating field plate are made of the same material and are manufactured in the same manufacturing step.
  • the gate is made of the same material as the junction terminal floating field plate, the isolation ring floating field plate and the LDMOS floating field plate, and are manufactured in the same manufacturing step.
  • the junction terminal floating field plate, the isolation ring floating field plate and the LDMOS floating field plate are made of doped polysilicon.
  • the spacings between adjacent junction terminal floating field plates are equal.
  • the spacing between adjacent junction terminal floating field plates is a1, a2 ⁇ a1 ⁇ a3, a2 ⁇ a1 ⁇ a4.
  • the spacing between adjacent junction terminal floating field plates is 1.0-3.2 ⁇ m
  • the spacing between adjacent third field plates is 0.5-3.0 ⁇ m
  • the spacing between adjacent first field plates and the spacing between the first field plate farthest from the source region and an adjacent third field plate is 1.2-4.0 ⁇ m
  • the spacing between adjacent second field plates and the spacing between the second field plate farthest from the drain region and an adjacent third field plate is 1.2-4.0 ⁇ m.
  • An integrated circuit comprises a first voltage region, a second voltage region and an isolation structure located between the first voltage region and the second voltage region, wherein the isolation structure is the isolation structure described in any of the above embodiments.
  • An operating voltage of the device in the second voltage region is greater than an operating voltage of the device in the first voltage region.
  • the junction terminal floating field plate on the junction terminal can form an induced potential. Since the LDMOS floating field plate is electrically connected to the junction terminal floating field plate, the induced potential will affect the potential of the lateral double diffused metal oxide semiconductor field effect transistor through the LDMOS floating field plate.
  • the spacing of the first field plate/the second field plate arranged near the source region/the drain region is set to be wider, and the spacing of the third field plate in the middle of the drift region is set to be narrower, so that the potential gradient of the lateral double diffused metal oxide semiconductor field effect transistor near the source region/the drain region can be reduced, and the potential gradient near the middle of the drift region can be increased, so that the potential distribution of the lateral double diffused metal oxide semiconductor field effect transistor is more uniform, and the breakdown voltage of the LDMOS is improved.
  • the drain of the NLDMOS is connected to the potential of the second voltage region, and the source of the NLDMOS is grounded.
  • FIG1 is a front view of an integrated circuit according to an embodiment
  • Fig. 2 is a cross-sectional view along line A-A' of Fig. 1;
  • Fig. 3 is a cross-sectional view along line B-B' of Fig. 1;
  • Fig. 4 is a cross-sectional view along line C-C' of Fig. 1;
  • Fig. 5 is a cross-sectional view along line D-D' in Fig. 1;
  • Fig. 6 is a cross-sectional view along line E-E' in Fig. 1;
  • FIG7 is a partial enlarged view of the first isolation ring in FIG1;
  • FIG8 is a partial enlarged view of the vicinity of the first isolation ring in one embodiment
  • Fig. 9 is a cross-sectional view along line D-D' in Fig. 1 in an embodiment with a protection well;
  • Fig. 10 is a cross-sectional view along line E-E' in Fig. 1 in an embodiment with a protection well;
  • FIG11 is a cross-sectional view along line D-D' in FIG1 in yet another embodiment with a protection well;
  • Fig. 12 is a cross-sectional view along line E-E' in Fig. 1 in yet another embodiment with a protection well;
  • FIG13 is a partial enlarged view of another embodiment near the first isolation ring
  • FIG. 14 is a partial enlarged view near the first isolation ring in yet another embodiment.
  • connection in this specification should be understood as “electrically connected” if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other. It should be understood that although the terms first, second, third, etc.
  • first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.
  • Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown due to, for example, manufacturing techniques and/or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the invention.
  • the semiconductor field vocabulary used in this article is technical vocabulary commonly used by technical personnel in this field.
  • P+ type represents P-type with heavy doping concentration
  • P-type represents P-type with medium doping concentration
  • P-type represents P-type with light doping concentration
  • N+ type represents N-type with heavy doping concentration
  • N-type represents N-type with medium doping concentration
  • N-type represents N-type with light doping concentration
  • a semiconductor high-low voltage isolation structure which controls the potential of the LDMOS in the isolation structure by means of a variable spacing field plate, and can regulate the potential distribution in the LDMOS drift region and the surface electric field distribution, thereby preventing the LDMOS from becoming a breakdown weak point of the isolation structure and obtaining a high-low voltage isolation structure with better isolation capability.
  • FIG1 is a schematic diagram of the structure of an integrated circuit in an embodiment, including a low voltage region 100, a high voltage region 300, and an isolation structure located between the low voltage region 100 and the high voltage region 300.
  • the operating voltage of the device in the high voltage region 300 is greater than that of the device in the low voltage region 100.
  • the isolation structure is used to isolate the potential between the high voltage area 300 and the low voltage area 100.
  • the isolation structure includes a junction termination 210 and a LDMOS field effect transistor.
  • the junction terminal 210 includes a plurality of junction terminal floating field plates 211.
  • the lateral double diffused metal oxide semiconductor field effect transistor includes a plurality of LDMOS floating field plates 251.
  • Each LDMOS floating field plate 251 is electrically connected to at least one junction terminal floating field plate 211.
  • the length of each junction terminal floating field plate 211 is greater than the length of the LDMOS floating field plate 251 electrically connected thereto.
  • Each junction terminal floating field plate 211 and the LDMOS floating field plate 251 are made of a conductive material.
  • a plurality of LDMOS floating field plates 251 are electrically connected to a plurality of junction terminal floating field plates 211 in a one-to-one correspondence, that is, one LDMOS floating field plate 251 is electrically connected to one junction terminal floating field plate 211.
  • one junction terminal floating field plate 211 may be connected to a plurality of LDMOS floating field plates 251, that is, an LDMOS floating field plate 251 electrically connected to a certain junction terminal floating field plate 211 is bifurcated into a plurality of LDMOS floating field plates in the LDMO region.
  • one LDMOS floating field plate 251 is connected to a plurality of junction terminal floating field plates 211, that is, a junction terminal floating field plate 211 electrically connected to a certain LDMOS floating field plate 251 is bifurcated into a plurality of LDMOS floating field plates in the junction terminal region.
  • the junction terminal floating field plate 211 on the junction terminal 210 can form an induced potential. Since the LDMOS floating field plate 251 is electrically connected to the junction terminal floating field plate 211, the induced potential will affect the potential of the lateral double diffused metal oxide semiconductor field effect transistor through the LDMOS floating field plate 251.
  • each junction terminal floating field plate 211 After each junction terminal floating field plate 211 induces a certain potential on the junction terminal 210 and transmits it to the lateral double diffused metal oxide semiconductor field effect transistor through the junction terminal floating field plate 211 and the LDMOS floating field plate 251, for the lateral double diffused metal oxide semiconductor field effect transistor, each junction terminal floating field plate 211 is equivalent to an external "voltage source", and the potential inside the lateral double diffused metal oxide semiconductor field effect transistor will be controlled by the junction terminal floating field plate 211 and the LDMOS floating field plate 251.
  • each LDMOS floating field plate 251 is controlled, the potential distribution inside the lateral double diffused metal oxide semiconductor field effect transistor can be indirectly controlled, and the spacing of the LDMOS floating field plate 251 can be flexibly adjusted according to design requirements, that is, the free control of the internal potential of the lateral double diffused metal oxide semiconductor field effect transistor is realized.
  • the isolation structure shown in FIG. 1 also includes an isolation ring surrounding the lateral double diffused metal oxide semiconductor field effect transistor, and the isolation ring is used to isolate the lateral double diffused metal oxide semiconductor field effect transistor from the junction terminal 210.
  • the isolation ring is connected to the lateral double diffused metal oxide semiconductor field effect transistor and the junction terminal 210.
  • the isolation ring includes a first isolation ring 230 and a second isolation ring 250
  • the lateral double diffused metal oxide semiconductor field effect transistor includes an NLDMOS 220 and a PLDMOS 240.
  • the first isolation ring 230 surrounds the NLDMOS 220
  • the second isolation ring 250 surrounds the PLDMOS 240.
  • the floating field plate refers to a field plate that is not connected to a potential.
  • the main structure of the first isolation ring 230 and the second isolation ring 250 is an isolation junction 233 (see FIG. 5).
  • the isolation junction is a P-type doped region.
  • FIG2 is a cross-sectional view along the line AA' of FIG1.
  • the NLDMOS 220 includes a source region 222, a drain region 224, a gate 226, a drift region 223, a field region insulating layer 32 and an LDMOS floating field plate 251. At least a portion of the drift region 223 is located between the source region 222 and the drain region 224.
  • the field region insulating layer 32 is disposed between the source region 222 and the drain region 224. 32 is located on the drift region 223.
  • One side of the gate 226 is close to the source region 222, and the other side is close to the drain region 224.
  • the source region 222 and the gate 226 are arranged close to the low voltage region 100, and the drain region 224 is arranged close to the high voltage region 300.
  • the number of LDMOS floating field plates 251 is the same as the number of junction terminal floating field plates 211, and the plurality of LDMOS floating field plates 251 are electrically connected to the plurality of junction terminal floating field plates 211 in a one-to-one correspondence.
  • Each LDMOS floating field plate 251 includes a first field plate arranged close to the source region 222, a second field plate arranged close to the drain region 224, and a third field plate arranged between the first field plate and the second field plate. In the embodiment shown in FIG. 1 and FIG. 2 , the number of LDMOS floating field plates 251 is N.
  • the 1st to p-1th are second field plates
  • the pth to Nmth are third field plates
  • the N-m+1th to Nth are first field plates.
  • the spacing between adjacent third field plates is less than a2.
  • the spacing between the one of the plurality of second field plates farthest from the drain region 224 (i.e., p-1) and an adjacent third field plate (i.e., p) is greater than a3, and the spacing between adjacent second field plates is greater than a3.
  • the spacing between the one of the plurality of first field plates farthest from the source region 222 (i.e., N-m+1) and an adjacent third field plate (i.e., Nm) is greater than a4, and the spacing between adjacent first field plates is greater than a4.
  • the relationship among a2, a3, and a4 is: a2 ⁇ a3, a2 ⁇ a4. That is, the interval between the first field plate disposed near the source region 222 and the second field plate disposed near the drain region 224 is set to be wider, and the interval between the third field plate located in the middle of the drift region 223 is set to be narrower.
  • FIG3 is a cross-sectional view along the line B-B' of FIG1 .
  • the PLDMOS 240 includes a source region 242, a drain region 244, a gate 246, a drift region 243, a field region insulating layer 34, and an LDMOS floating field plate 251. At least a portion of the drift region 243 is located between the source region 242 and the drain region 244, and the field region insulating layer 34 is located on the drift region 243.
  • One side of the gate 246 is close to the source region 242, and the other side is close to the drain region 244.
  • the source region 242 and the gate 246 are arranged close to the high voltage region 300, and the drain region 244 is arranged close to the low voltage region 100.
  • the number of the LDMOS floating field plates 251 is the same as the number of the junction terminal floating field plates 211, and the plurality of LDMOS floating field plates 251 are electrically connected to the plurality of junction terminal floating field plates 211 in a one-to-one correspondence.
  • Each LDMOS floating field plate 251 includes a first field plate disposed near the source region 242, a second field plate disposed near the drain region 244, and a third field plate disposed between the first field plate and the second field plate. In the embodiments shown in FIG. 1 and FIG.
  • the number of LDMOS floating field plates 251 is N, and starting from the LDMOS floating field plate 251 closest to the source region 244, the 1st to p-1th are first field plates, the pth to N-mth are third field plates, and the N-m+1th to Nth are second field plates.
  • the spacing between adjacent third field plates is less than a2, the spacing between a second field plate (i.e., the N-m+1th) farthest from the drain region 244 among the plurality of second field plates and the adjacent third field plate (i.e., the N-mth) is greater than a3, and the spacing between adjacent second field plates is greater than a3, the spacing between a first field plate (i.e., the p-1th) farthest from the source region 242 among the plurality of first field plates and the adjacent third field plate (i.e., the pth) is greater than a4, and the spacing between adjacent first field plates is greater than a4; then the relationship among a2, a3, and a4 is: a2 ⁇ a3, a2 ⁇ a4. That is, the spacing between the first field plate disposed near the source region 242 and the second field plate disposed near the drain region 244 is set wider, and the spacing between the third field plate located in the middle of the drift region 243 is set narrower.
  • each junction terminal floating field plate 211 is greater than the length of the corresponding LDMOS floating field plate to ensure that the potential of the junction terminal floating field plate 211 is dominant. Taking FIG. 1 as an example, the length of each junction terminal floating field plate 211 is greater than the sum of the lengths of the corresponding LDMOS floating field plate 251 in the NLDMOS 220 and the LDMOS floating field plate 251 in the PLDMOS 240.
  • the potential lines of the lateral double diffused metal oxide semiconductor field effect transistor at the source and drain are relatively concentrated, by setting the spacing between the first field plate/the second field plate arranged near the source region/the drain region to be wider and setting the spacing between the third field plate in the middle of the drift region to be narrower, the potential gradient of the lateral double diffused metal oxide semiconductor field effect transistor near the source region/the drain region can be reduced and the potential gradient near the middle of the drift region can be increased, thereby making the potential distribution of the lateral double diffused metal oxide semiconductor field effect transistor more uniform and improving the breakdown voltage of the LDMOS in the isolation structure.
  • the isolation ring further includes a plurality of isolation ring floating field plates 231, the same number as the junction terminal floating field plates 211.
  • Each junction terminal floating field plate 211 is electrically connected to a corresponding LDMOS floating field plate 251 through a corresponding isolation ring floating field plate 231.
  • One end of each isolation ring floating field plate 231 extends to a corresponding junction terminal floating field plate 211, and the other end extends to a corresponding LDMOS floating field plate 251.
  • the spacing between adjacent junction terminal floating field plates is a1, and a2 ⁇ a1 ⁇ a3, a2 ⁇ a1 ⁇ a4.
  • the spacing between adjacent junction terminal floating field plates 211 is 1.0-3.2 ⁇ m
  • the spacing between adjacent third field plates is 0.5-3.0 ⁇ m
  • the spacing between adjacent first field plates and the spacing between a first field plate farthest from the source region and an adjacent third field plate is 1.2-4.0 ⁇ m
  • the spacing between adjacent second field plates and the spacing between a second field plate farthest from the drain region and an adjacent third field plate is 1.2-4.0 ⁇ m.
  • adjacent junction terminal floating field plates 211 are equally spaced at a spacing of L 1.
  • the first to p-th LDMOS floating field plates 251 near the drain region 224 are equally spaced at a spacing of L 3
  • the Nm-th to N-th LDMOS floating field plates 251 near the source region 222 are equally spaced at a spacing of L 4
  • the remaining p-th to Nm-th LDMOS floating field plates 251 are equally spaced at a spacing of L 2.
  • the first to p-th LDMOS floating field plates 251 near the source region 242 are equally spaced at a spacing of L 6
  • the Nm-th to N-th LDMOS floating field plates 251 near the drain region 244 are equally spaced at a spacing of L 7
  • the remaining p-th to Nm-th LDMOS floating field plates 251 are equally spaced at a spacing of L 5 .
  • the total number N of the plurality of floating field plates ranges from 10 to 100, the values of p and m range from 2 to 15, and the value of N-p-m ranges from 1 to 96.
  • the source region 222 and the drain region 224 of the NLDMOS 220 are N+ regions, and the drift region 223 is an N-type drift region.
  • the source region 242 and the drain region 244 of the PLDMOS 240 are P+ regions, and the drift region 243 is a P-type drift region.
  • the NLDMOS 220 further includes a body region 221, a P-well 225, an N-well 227, a deep N-well 229, and a P-type buried layer 228.
  • the body region 221 and the source region 222 are short-circuited after being led out through contact holes.
  • the body region 221 and the source region 222 are located in the P-well 225.
  • the drain region 224 is located in the N-well 227.
  • the field region insulating layer 32 of the NLDMOS 220 is located between the source region 222 and the drain region 224.
  • the P-type buried layer 228 is located below the drift region 223 and the P-well 225.
  • the deep N-well 229 is located below the drift region 223 and the N-well 227.
  • the PLDMOS 240 further includes a body region 241, a P well 245, an N well 247, a deep N well 249, and a P-type buried layer 248.
  • the body region 241 and the source region 242 are short-circuited after being led out through contact holes.
  • the source region 242 is located in the N well 247.
  • the drain region 244 is located in the P well 245.
  • the field region insulating layer 34 of the PLDMOS 240 is located between the source region 242 and the drain region 244.
  • the deep N well 249 is located below the drift region 243 and the N well 247.
  • the P type buried layer 248 is located in the deep N well 249 and below the drift region 243 and the P well 245.
  • the drain of NLDMOS 220 is connected to the potential of high voltage region 300, and the source of NLDMOS 220 is grounded.
  • the source of PLDMOS 240 is connected to the potential of high voltage region 300, and the drain of PLDMOS 240 is grounded.
  • the isolation structure (including the junction terminal 210, the isolation ring and the lateral double diffused metal oxide semiconductor field effect transistor) also includes a substrate 10 at the bottom and a passivation layer 20 at the upper surface of the device.
  • the constituent material of the substrate 10 is P-type doped single crystal silicon.
  • the junction terminal floating field plate 211, the isolation ring floating field plate 231, and the LDMOS floating field plate 251 are made of the same material and are manufactured in the same step. In one embodiment, the junction terminal floating field plate 211, the isolation ring floating field plate 231, and the LDMOS floating field plate 251 are made of doped polysilicon. In one embodiment, the gate in the lateral double diffused metal oxide semiconductor field effect transistor (including NLDMOS 220 and PLDMOS 240) is made of doped polysilicon. In one embodiment, the junction terminal floating field plate 211, the isolation ring floating field plate 231, the LDMOS floating field plate 251, the gate 226, and the gate 246 can be manufactured in the same step.
  • FIG4 is a cross-sectional view along line C-C′ of FIG1 . Please refer to FIG1 and FIG4 together.
  • the junction terminal 210 further includes a first insulating layer 31 , and each junction terminal floating field plate 211 is located on the first insulating layer 31 .
  • the first insulating layer 31 , the field insulating layer 32 and the field insulating layer 34 may be made of silicon oxide, such as silicon dioxide.
  • the junction terminal 210 further includes a cathode region 212 and an anode region 214.
  • the conductivity type of the cathode region 212 and the anode region 214 is the same as the conductivity type of the drain region 224 of the NLDMOS 220, that is, both are N+ regions.
  • the cathode region 212 is electrically connected to the potential of the source region 222 of the NLDMOS 220 through a metal connection (not shown) led out through a contact hole
  • the anode region 214 is electrically connected to the potential of the drain region 224 of the NLDMOS 220 through a metal connection (not shown) led out through a contact hole.
  • Providing a structure similar to an NLDMOS without a gate in the junction terminal 210 is conducive to achieving isolation between the high voltage region 300 and the low voltage region 100.
  • the junction terminal 210 further includes an N-type region 213. At least a portion of the N-type region 213 is located between the cathode region 212 and the anode region 214, and the first insulating layer 31 is located on the N-type region 213.
  • the N-type region 213 functions similarly to a drift region.
  • the junction terminal 210 further includes a terminal isolation junction 271.
  • the terminal isolation junction 271 is located between the N-type region 213 and the low voltage region 100, and between the N-type region 213 and the high voltage region 300.
  • the terminal isolation junction 271 has the same conductivity type as the substrate 10. In the embodiment where the substrate 10 is a P-type substrate, the terminal isolation junction 271 is a P-type doped region.
  • the junction terminal 210 further includes a body region 216, a P well 215, an N well 217, a deep N well 219 and a P type buried layer 218.
  • the body region 216 and the cathode region 212 are short-circuited after being led out through a contact hole.
  • the body region 216 and the cathode region 212 are located in the P well 215.
  • the anode region 214 is located in the N well 217.
  • the first insulating layer 31 is located between the P well 215 and the N well 217.
  • the P-type buried layer 218 is located below the N-type region 213 and the P-well 215.
  • the deep N-well 219 is located below the N-type region 213 and the N-well 217.
  • each junction terminal floating field plate 211 is connected to a corresponding isolation ring floating field plate 231 and LDMOS floating field plate 251 on a plane to form a closed loop, i.e., a closed floating field plate. It can be understood that starting from the junction terminal 210, crossing the isolation ring, passing to the NLDMOS 220 and the PLDMOS 240, and connecting end to end.
  • the N floating field plates on the junction terminal 210 are distributed at equal intervals with a spacing of L1 .
  • the potential between the high voltage region 300 and the low voltage region 100 is separated by the isolation structure, and at this time, the drain end (i.e., the anode region 214) and the source end (i.e., the cathode region 212) of the junction terminal 210, the source end and the drain end of the PLDMOS 240, and the drain end and the source end of the NLDMOS 220 bear the voltage between the high voltage region 300 and the low voltage region 100, and the potential is reduced from the high voltage potential to the ground potential inside the junction terminal 210, the NLDMOS 220, and the PLDMOS 240.
  • the floating field plate Since the floating field plate is a highly doped polysilicon field plate, it has a large number of free electrons inside, so the floating field plate will have a certain induced potential in the electric field.
  • the N junction terminal floating field plates 211 on the junction terminal 210 will be affected by the potential distribution inside the junction terminal 210, and will induce potentials V 1 , V 2 , ..., V N , respectively.
  • the value of the induced potential of each floating field plate is determined by its location, and is almost equal to the potential of the junction terminal region below it. Therefore, the potential distribution inside the junction terminal 210 controls the induced potential of each junction terminal floating field plate 211.
  • the potential distribution inside the NLDMOS 220 and the PLDMOS 240 will also have a corresponding impact on the induced potential of the floating field plate.
  • the area occupied by the junction terminal 210 is much larger than the area occupied by the LDMOS. Accordingly, the junction terminal area passed by each closed floating field plate is also much larger than the area passed by the LDMOS (refer to FIG.
  • each closed floating field plate can only carry a certain induced potential, that is, each closed floating field plate is an equipotential body in the electric field, so the potential distribution in the junction terminal 210 has an absolute dominant position on the induced potential generated by the closed floating field plate, and it can be regarded that the induced potential carried by each closed floating field plate is determined by the junction terminal 210. Since the LDMOS is not enough to change the induced potential carried by each closed floating field plate, each field plate extending from the junction terminal 210 is equivalent to an external "voltage source" for the LDMOS, and the floating field plate forces the area of the LDMOS part below it to be close to the potential of the floating field plate.
  • the semiconductor high and low voltage isolation structure proposed in the above embodiment forms a potential control system with a floating field plate.
  • the potential distribution in the junction terminal 210 controls the induced potential of the closed floating field plate, and the induced potential of the closed floating field plate controls the potential distribution in the LDMOS.
  • the above embodiment realizes the potential control of LDMOS in the isolation structure based on the floating field plate with variable spacing.
  • the potential distribution in NLDMOS 220 and PLDMOS 240 is close to the junction terminal 210. If two adjacent field plates among the N floating field plates are transmitted to the LDMOS region with a spacing L1 that is equal everywhere, the potential distribution in LDMOS is clamped by the floating field plate at this time, so it is close to the potential distribution in the junction terminal 210.
  • the spacing of the LDMOS floating field plate 251 on the LDMOS the potential distribution in the LDMOS is further controlled according to the demand, and the electric field strength in different areas of the LDMOS is changed.
  • the present application adopts a variable spacing field plate, and the N junction terminal floating field plates 211 originally distributed at an equal spacing of L1 on the junction terminal 210 are "changed" in the form of an inclined field plate on the isolation ring. Subsequently, these N floating field plates will be distributed on the LDMOS at a spacing different from L1 . Each floating field plate has a certain potential before being transferred to the LDMOS region, so the potential difference between them is also certain. Changing the spacing between the field plates changes the potential between them. Correspondingly, the gradient of the electric potential in the LDMOS region covered by the variable-spacing LDMOS floating field plates 251 will also change, and the electric field strength is the gradient of the electric potential. Therefore, changing the spacing of the LDMOS floating field plates 251 in a certain area is to change the magnitude of the electric field strength in the corresponding area, thereby achieving control of the internal potential and surface electric field strength of the LDMOS.
  • variable spacing field plate is to control the potential distribution of LDMOS with the potential distribution of the junction terminal 210, so that the performance of LDMOS is improved, so the isolation capability of the entire isolation structure is also improved, and the closed floating field plate is an external control for its beneficiary device LDMOS.
  • the present application can eliminate the potential line concentration point, and the variable spacing field plate can control the gradient of the potential of each part in the drift region of LDMOS to be almost equal, which means that the change of potential is uniform and will not change sharply in some areas, so LDMOS will not become a weak point of breakdown of the isolation structure.
  • the present application has a comprehensive control over the internal potential of LDMOS, and the variable spacing field plate can realize the potential control of the entire drift region of LDMOS, rather than being limited to a part of it.
  • the solution will not lead to the complication of the process and structure, that is, it avoids increasing the manufacturing cost.
  • the closed floating field plate in the above embodiment can be a polysilicon field plate, and the polysilicon process is a common process for forming the gate of each type of device in the high and low voltage isolation structure manufacturing process, so the closed floating field plate can be formed in the same process as the polysilicon gate, and will not increase the manufacturing process.
  • the closed floating field plate controls the potential of the LDMOS, it is not necessary to change its internal structure, thereby avoiding the complexity of the LDMOS design and manufacturing.
  • FIG5 is a cross-sectional view along the D-D’ line in FIG1
  • FIG6 is a cross-sectional view along the E-E’ line in FIG1
  • FIG7 is a partial enlarged view of the first isolation ring 230 in FIG1 .
  • the isolation ring further includes a second insulating layer 33, each isolation ring floating field plate 231 is located on the second insulating layer 33, and the second insulating layer 33 is located on the isolation junction 233.
  • the material of the second insulating layer 33 can be silicon oxide, such as silicon dioxide.
  • the isolation junction 233 has the same conductivity type as the substrate 10. In an embodiment where the substrate 10 is a P-type substrate, the isolation junction 233 is a P-type doped region.
  • each isolation ring floating field plate 231 includes a junction terminal connection portion 231a, an LDMOS connection portion 231c, and an intermediate portion 231b.
  • One end of the intermediate portion 231b is connected to the junction terminal connection portion 231a, and the angle ⁇ between the intermediate portion 231b and the extension line of the junction terminal connection portion 231a on the plane is greater than zero and less than 80 degrees.
  • the other end of the intermediate portion 231b is connected to the LDMOS connection portion 231c, and the angle ⁇ between the intermediate portion 231b and the extension line of the LDMOS connection portion 231c on the plane is greater than zero and less than 80 degrees.
  • the spacing between adjacent LDMOS floating field plates 251 is inconsistent with the spacing between adjacent junction terminal floating field plates 211.
  • the spacing of the floating field plates is changed from the junction terminal floating field plate 211 to the spacing distribution of the LDMOS floating field plate 251 .
  • the distance between the connection position of the junction terminal connection portion 231a and the middle portion 231b and the edge of the isolation ring is b1
  • the distance between the connection position of the LDMOS connection portion 231c and the middle portion 231b and the edge of the isolation ring is b2
  • b1 is 10% to 30% of the width of the isolation ring
  • b2 is 10% to 30% of the width of the isolation ring. That is, the connection position of the middle portion 231b and the junction terminal connection portion 231a/LDMOS connection portion 231c should maintain a certain distance from the boundary of the isolation ring.
  • the corners of the inclined field plate i.e., at the positions of the angles ⁇ and ⁇
  • Setting the corners at a certain distance from the boundary of the isolation ring can improve the durability of the isolation ring compared to setting the corners at the boundary of the isolation ring.
  • the voltage is increased (ie, the breakdown voltage is increased) to avoid punch-through between the LDMOS field effect transistor and the junction terminal 210.
  • the corners of the inclined field plate are arranged at the positions of the DD' line and the EE' line.
  • the isolation ring further includes a protection well 235, and the second insulating layer 33 is located on the isolation junction 233 and the protection well 235.
  • the conductivity type of the protection well 235 is opposite to the conductivity type of the drain region 222 of the NLDMOS, and the doping concentration of the protection well 235 is greater than the doping concentration of the isolation junction 233.
  • the protection well 235 is a P+ doping region. The provision of the protection well 235 can further improve the withstand voltage of the isolation ring and avoid the concentration of the potential line causing the isolation ring to break through.
  • the protection well 235 is provided directly below the connection position of at least part of the junction terminal connection 231a and the middle part 231b, and the protection well 235 is provided directly below the connection position of at least part of the LDMOS connection 231c and the middle part 231b. This is because the corner of the inclined field plate will cause the electric lines to gather, so the protection well 235 is provided directly below the corner of the inclined field plate to obtain a better effect of improving the withstand voltage of the isolation ring.
  • FIG8 is a partial enlarged view of the isolation structure near the first isolation ring 230 in an embodiment, and the protection well 235 in the figure is semi-transparent.
  • the protection well 235 is a whole P+ structure.
  • the width of the implantation window of the protection well 235 should be 100%-110% of the distance between the two ends of the inclined field plate, and the length should be 100%-110% of the maximum distance between the first field plate and the Nth field plate, so as to be laid under the corners of all inclined field plates.
  • the region 100a in FIG8 has the same structure as the partial structure of the low-voltage region 100
  • the region 300a has the same structure as the partial structure of the high-voltage region 300.
  • FIG9 is a cross-sectional view along the D-D' line in FIG1 in an embodiment with the protection well 235
  • FIG10 is a cross-sectional view along the E-E' line in FIG1 in an embodiment with the protection well 235.
  • FIG9 is relative to the embodiment shown in FIG5, and FIG10 is relative to the embodiment shown in FIG6, in which the protection well 235 is added.
  • the protection well 235 may also act only on a portion of the isolation ring floating field plates 231, for example, only on the high-voltage side field plates, as shown in FIGS. 11 and 12.
  • the protection well 235 is disposed below a portion of the isolation ring floating field plates 231 close to the high-voltage region 300, and no protection well 235 is disposed below the remaining isolation ring floating field plates 231.
  • the protection well 235 is disposed below a plurality of isolation ring floating field plates 231 (i.e., the first to pth isolation ring floating field plates 231 close to the high-voltage region 300) with a spacing of L3 .
  • the length of the protection well 235 is 100%-110% of the maximum distance between the first to pth field plates.
  • the isolation ring floating field plates 231 acting on the protection well 235 are selected as several isolation ring floating field plates 231 close to the high-voltage area 300, which can obtain a better effect of improving the isolation ring's withstand voltage; in other embodiments, the isolation ring floating field plate 231 can also be arranged below other isolation ring floating field plates 231.
  • FIG13 is a partial enlarged view of another embodiment near the first isolation ring 230, in which the protection well 235 is semi-transparent.
  • the protection well 235 is a strip-shaped P+ type doping area set at the corner.
  • the width of the implantation window of the protection well 235 is 2%-5% of the isolation ring width C, and the length should be 100%-110% of the maximum distance between the first field plate and the Nth field plate, so as to be laid under the corners of all inclined field plates.
  • FIG. 14 is a partial enlarged view of another embodiment near the first isolation ring 230, in which the protection well 235 is The main difference between the embodiment shown in FIG8 and the embodiment shown in FIG8 is that the protection well 235 is a point-shaped P+ type doping area set at the corner, and these point-shaped P+ type doping areas are arranged in a row.
  • the width of the implantation window of the protection well 235 is 2%-5% of the width of the isolation ring.
  • the protection well 235 and the junction terminal 210 and the P+ injection in the lateral double diffused metal oxide semiconductor field effect transistor are the same injection, that is, the injection lithography before the ion injection of the protection well 235 and the body region 221 of the NLDMOS 220, the source region 242 and the drain region 244 of the PLDMOS 240, and the body region 216 of the junction terminal 210 use the same photolithography plate, and the lithography of the injection window is completed in the same photolithography step. Therefore, the formation of the protection well 235 will not increase the manufacturing process, which is conducive to cost saving.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明涉及一种隔离结构，包括：结终端，包括多个结终端浮空场板；横向双扩散金属氧化物半导体场效应晶体管，包括多个LDMOS浮空场板，每个LDMOS浮空场板与至少一结终端浮空场板电性连接，每个结终端浮空场板的长度大于与所述结终端浮空场板电性连接的所述LDMOS浮空场板的长度。

Description

隔离结构及集成电路
相关申请的交叉引用
本申请要求于2023年6月15日申请的，申请号为2023107143293、名称为“隔离结构及集成电路”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本发明涉及半导体制造领域，特别是涉及一种隔离结构，还涉及一种集成电路。
背景技术
高压集成电路中包含高压半导体器件和低压半导体器件，即存在高压区和低压区，因此需要用高低压隔离结构来隔离高压区和低压区之间的电位。该隔离结构包含结终端、隔离环、横向双扩散金属-氧化物-半导体场效应晶体管(Lateral double-diffused Metal-Oxide-Semiconductor Field Effect Transistor,简称LDMOS)，其中LDMOS是传递高压区和低压区之间电信号的门户，在承受高电压时易成为击穿薄弱点。通过技术手段使其内部电势分布均匀，避免电势线集中，可以提升LDMOS的击穿电压。
发明内容
根据一些实施例，提供一种隔离结构。
一种隔离结构，包括：结终端，包括多个结终端浮空场板；横向双扩散金属氧化物半导体场效应晶体管，包括多个LDMOS浮空场板，每个LDMOS浮空场板与至少一结终端浮空场板电性连接，每个所述结终端浮空场板的长度大于与其电性连接的所述LDMOS浮空场板的长度。所述结终端浮空场板和所述LDMOS浮空场板由导电材料构成。
上述隔离结构可以应用在集成电路中，当集成电路中的器件工作时，结终端上的结终端浮空场板能够形成感应电势。由于LDMOS浮空场板与结终端浮空场板电性连接，因此该感应电势会通过LDMOS浮空场板对横向双扩散金属氧化物半导体场效应晶体管的电势造成影响。每条结终端浮空场板在结终端上感应出确定的电势并通过LDMOS浮空场板传递到横向双扩散金属氧化物半导体场效应晶体管后，对于横向双扩散金属氧化物半导体场效应晶体管而言，每条结终端浮空场板相当于一个外置的“电压源”，横向双扩散金属氧化物半导体场效应晶体管内的电势将会被结终端浮空场板和LDMOS浮空场板控制，因此只要控制每条LDMOS浮空场板的间距就可以间接地控制横向双扩散金属氧化物半导体场效应晶体管内部的电势分布，并且可以根据设计需求对LDMOS浮空场板的间距灵活调整，即实现了对横向双扩散金属氧化物半导体场效应晶体管内部电势的自由控制，能够使LDMOS内部电势分布均匀，提升LDMOS的击穿电压。
在其中一个实施例中，隔离结构还包括包围所述横向双扩散金属氧化物半导体场效应 晶体管的隔离环，所述隔离环用于将所述横向双扩散金属氧化物半导体场效应晶体管与所述结终端隔离。
在其中一个实施例中，所述隔离环还包括多个隔离环浮空场板，每个LDMOS浮空场板通过一个隔离环浮空场板与相应的结终端浮空场板电性连接，每个隔离环浮空场板的一端延伸至对应的一结终端浮空场板、另一端延伸至对应的一LDMOS浮空场板。
在其中一个实施例中，所述横向双扩散金属氧化物半导体场效应晶体管还包括源极区、漏极区、栅极、漂移区及场区绝缘层，所述漂移区的至少部分区域位于所述源极区和漏极区之间，所述场区绝缘层位于所述漂移区上，所述栅极的一侧靠近所述源极区、另一侧靠近所述漏极区，所述LDMOS浮空场板的数量与所述结终端浮空场板相同，所述多个LDMOS浮空场板与所述多个结终端浮空场板一一对应电性连接；所述LDMOS浮空场板包括靠近所述源极区设置的第一场板、靠近所述漏极区设置的第二场板及位于所述第一场板和第二场板之间的第三场板，相邻的第三场板之间的间距小于a2，所述第二场板中离所述漏极区最远的一个与相邻的一第三场板之间的间距大于a3，且相邻的第二场板之间的间距大于a3，所述第一场板中离所述源极区最远的一个与相邻的一第三场板之间的间距大于a4，且相邻的第一场板之间的间距大于a4；a2<a3，a2<a4。
在其中一个实施例中，所述横向双扩散金属氧化物半导体场效应晶体管包括NLDMOS和PLDMOS，所述隔离环包括包围所述NLDMOS的第一隔离环和包围所述PLDMOS的第二隔离环，所述每个所述结终端浮空场板的长度是对应的所述NLDMOS的LDMOS浮空场板和对应的所述PLDMOS的LDMOS浮空场板的长度之和。
在其中一个实施例中，所述结终端还包括第一绝缘层，所述多个结终端浮空场板位于所述第一绝缘层上。
在其中一个实施例中，所述结终端还包括阴极区和阳极区，所述阴极区和所述阳极区的导电类型与所述NLDMOS的漏极区的导电类型相同，所述阴极区通过金属连线电性连接至所述NLDMOS的源极区的电位，所述阳极区通过金属连线电性连接至所述NLDMOS的漏极区的电位。
在其中一个实施例中，每个结终端浮空场板与对应的隔离环浮空场板及对应的LDMOS浮空场板连成闭合环。
在其中一个实施例中，所述隔离环还包括隔离结、保护阱及第二绝缘层，所述多个隔离环浮空场板位于所述第二绝缘层上，所述第二绝缘层位于所述隔离结和保护阱上，所述隔离结和保护阱的导电类型与所述NLDMOS的漏极区的导电类型相反，所述保护阱的掺杂浓度大于所述隔离结的掺杂浓度。
在其中一个实施例中，每个隔离环浮空场板均包括结终端连接部、LDMOS连接部及中间部，所述中间部的一端连接所述结终端连接部、且所述中间部在平面上与所述结终端连接部的延长线的夹角大于零度小于80度，所述中间部的另一端连接所述LDMOS连接部、且所述中间部在平面上与所述LDMOS连接部的延长线的夹角大于零度小于80度； 至少部分所述结终端连接部与所述中间部的连接位置的正下方设有所述保护阱，至少部分所述LDMOS连接部与所述中间部的连接位置的正下方设有所述保护阱。
所述保护阱包括设置在所述多个结终端连接部与所述中间部的连接位置处的条状掺杂区，以及设置在所述多个LDMOS连接部与所述中间部的连接位置处的条状掺杂区；和/或所述保护阱包括设置在所述多个结终端连接部与所述中间部的连接位置处呈列排布的点状掺杂区，以及设置在所述多个LDMOS连接部与所述中间部的连接位置处呈列排布的点状掺杂区。
在其中一个实施例中，所述结终端连接部与所述中间部的连接位置距所述隔离环的边缘的距离为b1，所述LDMOS连接部与所述中间部的连接位置距所述隔离环的边缘的距离为b2，b1为所述隔离环的宽度的10％至30％，b2为所述隔离环的宽度的10％至30％。
在其中一个实施例中，所述结终端浮空场板、隔离环浮空场板及LDMOS浮空场板的材质相同，且是在同一制造步骤中制造形成。
在其中一个实施例中，所述栅极的材质与所述结终端浮空场板、隔离环浮空场板及LDMOS浮空场板的材质相同，且是在同一制造步骤中制造形成。
在其中一个实施例中，所述结终端浮空场板、隔离环浮空场板及LDMOS浮空场板的材质为掺杂多晶硅。
在其中一个实施例中，相邻的结终端浮空场板的间距相等。
在其中一个实施例中，相邻的结终端浮空场板之间的间距为a1，a2<a1<a3，a2<a1<a4。
在其中一个实施例中，相邻的结终端浮空场板的间距为1.0-3.2μm，相邻的第三场板的间距为0.5-3.0μm，相邻的第一场板的间距及所述离所述源极区最远的一所述第一场板与相邻的一第三场板之间的间距为1.2-4.0μm，相邻的第二场板的间距及所述离所述漏极区最远的一所述第二场板与相邻的一第三场板之间的间距为1.2-4.0μm。
还有必要提供一种集成电路。
一种集成电路，包括第一电压区、第二电压区及位于所述第一电压区和第二电压区之间的隔离结构，所述隔离结构是前述任一实施例所述的隔离结构。
所述第二电压区中的器件的工作电压大于所述第一电压区中的器件的工作电压。
上述集成电路，当第一电压区和第二电压区中的器件工作时，结终端上的结终端浮空场板能够形成感应电势。由于LDMOS浮空场板与结终端浮空场板电性连接，因此该感应电势会通过LDMOS浮空场板对横向双扩散金属氧化物半导体场效应晶体管的电势造成影响。由于横向双扩散金属氧化物半导体场效应晶体管在源极和漏极处的电势线较为集中，因此通过将靠近源极区/漏极区设置的第一场板/第二场板的间距设置得较宽、将漂移区中间位置的第三场板的间距设置得较窄，可以使得横向双扩散金属氧化物半导体场效应晶体管在源极区/漏极区附近的电势梯度减小，在漂移区中间附近的电势梯度增大，从而使得横向双扩散金属氧化物半导体场效应晶体管的电势分布更加均匀，提升LDMOS的击穿电压。
在其中一个实施例中，所述NLDMOS的漏极接所述第二电压区的电位，所述NLDMOS的源极接地。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1是根据一实施例的集成电路的主视图；
图2是沿图1的A-A’线的剖视图；
图3是沿图1的B-B’线的剖视图；
图4是沿图1的C-C’线的剖视图；
图5是沿图1中的D-D’线的剖视图；
图6是沿图1中的E-E’线的剖视图；
图7是图1中第一隔离环的局部放大图；
图8是一实施例中在第一隔离环附近的局部放大图；
图9是一具有保护阱的实施例中沿图1中的D-D’线的剖视图；
图10是一具有保护阱的实施例中沿图1中的E-E’线的剖视图；
图11是再一具有保护阱的实施例中沿图1中的D-D’线的剖视图；
图12是再一具有保护阱的实施例中沿图1中的E-E’线的剖视图；
图13是另一实施例中在第一隔离环附近的局部放大图；
图14是又一实施例中在第一隔离环附近的局部放大图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。本说明书中的“连接”，如果被连接的电路、模块、单元等相互之间具有电信号或数据的传递，则应理解为“电性连 接”、“通信连接”等。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。可以理解，“至少一个”是指一个或多个，“多个”是指两个或两个以上。“元件的至少部分”是指元件的部分或全部。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例。这样，可以预期由于例如制造技术和/或容差导致的从所示形状的变化。因此，本发明的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本发明的范围。
本文所使用的半导体领域词汇为本领域技术人员常用的技术词汇，例如对于P型和N型杂质，为区分掺杂浓度，简易的将P+型代表重掺杂浓度的P型，P型代表中掺杂浓度的P型，P-型代表轻掺杂浓度的P型，N+型代表重掺杂浓度的N型，N型代表中掺杂浓度的N型，N-型代表轻掺杂浓度的N型。
根据一些实施例，提出的一种半导体高低压隔离结构，通过变间距场板对隔离结构内的LDMOS进行电势控制，能够对LDMOS漂移区内电势分布及表面电场分布进行调控，从而避免LDMOS成为隔离结构的击穿薄弱点、获得隔离能力更优秀的高低压隔离结构。图1是一实施例中集成电路的结构示意图，包括低压区100、高压区300及位于低压区100和高压区300之间的隔离结构。高压区300中的器件的工作电压大于低压区100中的器件 的工作电压，隔离结构用于隔离高压区300和低压区100之间的电位。
在一个实施例中，隔离结构包括结终端210和横向双扩散金属氧化物半导体场效应晶体管。
结终端210包括多个结终端浮空场板211。横向双扩散金属氧化物半导体场效应晶体管包括多个LDMOS浮空场板251。每个LDMOS浮空场板251与至少一结终端浮空场板211电性连接。每个结终端浮空场板211的长度大于与其电性连接的LDMOS浮空场板251的长度。每个结终端浮空场板211和LDMOS浮空场板251由导电材料构成。
本实施例中，多个LDMOS浮空场板251与多个结终端浮空场板211一一对应电性连接，即一个LDMOS浮空场板251电性连接一个结终端浮空场板211。在其他实施例中，也可以是一个结终端浮空场板211连接多个LDMOS浮空场板251，即与某一结终端浮空场板211电性连接的LDMOS浮空场板251在LDMO区域分叉为多个。或者一个LDMOS浮空场板251连接多个结终端浮空场板211，即与某一LDMOS浮空场板251电性连接的结终端浮空场板211在结终端区域分叉为多个。
当集成电路中的器件(即低压区100中的低压器件和高压区300中的高压器件)工作时，结终端210上的结终端浮空场板211能够形成感应电势。由于LDMOS浮空场板251与结终端浮空场板211电性连接，因此该感应电势会通过LDMOS浮空场板251对横向双扩散金属氧化物半导体场效应晶体管的电势造成影响。每个结终端浮空场板211在结终端210上感应出确定的电势并通过结终端浮空场板211和LDMOS浮空场板251传递到横向双扩散金属氧化物半导体场效应晶体管后，对于横向双扩散金属氧化物半导体场效应晶体管而言，每个结终端浮空场板211相当于一个外置的“电压源”，横向双扩散金属氧化物半导体场效应晶体管内的电势将会被结终端浮空场板211和LDMOS浮空场板251控制，因此只要控制每个LDMOS浮空场板251的间距就可以间接地控制横向双扩散金属氧化物半导体场效应晶体管内部的电势分布，并且可以根据设计需求对LDMOS浮空场板251的间距灵活调整，即实现了对横向双扩散金属氧化物半导体场效应晶体管内部电势的自由控制。
图1所示的隔离结构还包括包围横向双扩散金属氧化物半导体场效应晶体管的隔离环，隔离环用于将横向双扩散金属氧化物半导体场效应晶体管与结终端210隔离。隔离环与横向双扩散金属氧化物半导体场效应晶体管及结终端210连接。在图1所示的实施例中，隔离环包括第一隔离环230和第二隔离环250，横向双扩散金属氧化物半导体场效应晶体管包括NLDMOS 220和PLDMOS 240。第一隔离环230包围NLDMOS 220，第二隔离环250包围PLDMOS 240。浮空场板指场板未连接电位。第一隔离环230和第二隔离环250的主要结构为隔离结233(见图5)，在本申请的一个实施例中，隔离结为P型掺杂区。
图2是沿图1的A-A’线的剖视图。请一并参见图1和图2，在一个实施例中，NLDMOS 220包括源极区222、漏极区224、栅极226、漂移区223、场区绝缘层32及LDMOS浮空场板251。漂移区223的至少部分区域位于源极区222和漏极区224之间，场区绝缘层 32位于漂移区223上。栅极226的一侧靠近源极区222、另一侧靠近漏极区224。源极区222和栅极226靠近低压区100设置、漏极区224靠近高压区300设置。LDMOS浮空场板251的数量与结终端浮空场板211的数量相同，多个LDMOS浮空场板251与多个结终端浮空场板211一一对应电性连接。每个LDMOS浮空场板251包括靠近源极区222设置的第一场板、靠近漏极区224设置的第二场板及位于第一场板和第二场板之间的第三场板。在图1和图2所示的实施例中，LDMOS浮空场板251的数量为N，从最靠近漏极区224的一个LDMOS浮空场板251起算，第1至第p-1个为第二场板，第p至第N-m个为第三场板，第N-m+1个至第N个为第一场板。相邻的第三场板之间的间距小于a2。多个第二场板中离漏极区224最远的一个(即p-1)与相邻的一第三场板(即p)之间的间距大于a3，且相邻的第二场板之间的间距大于a3。多个第一场板中离源极区222最远的一个(即N-m+1)与相邻的一第三场板(即N-m)之间的间距大于a4，且相邻的第一场板之间的间距大于a4。a2、a3、a4的关系为：a2<a3，a2<a4。即靠近源极区222设置的第一场板和靠近漏极区224设置的第二场板的间距设置得较宽，位于漂移区223中间位置的第三场板的间距设置得较窄。
图3是沿图1的B-B’线的剖视图，请一并参见图1和图3，在一个实施例中，PLDMOS 240包括源极区242、漏极区244、栅极246、漂移区243、场区绝缘层34及LDMOS浮空场板251。漂移区243的至少部分区域位于源极区242和漏极区244之间，场区绝缘层34位于漂移区243上。栅极246的一侧靠近源极区242、另一侧靠近漏极区244。源极区242和栅极246靠近高压区300设置、漏极区244靠近低压区100设置。LDMOS浮空场板251的数量与结终端浮空场板211的数量相同，多个LDMOS浮空场板251与多个结终端浮空场板211一一对应电性连接。每个LDMOS浮空场板251包括靠近源极区242设置的第一场板、靠近漏极区244设置的第二场板及位于第一场板和第二场板之间的第三场板。在图1和图3所示的实施例中，LDMOS浮空场板251的数量为N，从最靠近源极区244的一个LDMOS浮空场板251起算，第1至第p-1个为第一场板，第p至第N-m个为第三场板，第N-m+1个至第N个为第二场板。相邻的第三场板之间的间距小于a2，多个第二场板中离漏极区244最远的一个第二场板(即第N-m+1个)与相邻的第三场板(即第N-m个)之间的间距大于a3，且相邻的第二场板之间的间距大于a3，多个第一场板中离源极区242最远的一个第一场板(即第p-1个)与相邻的第三场板(即第p个)之间的间距大于a4，且相邻的第一场板之间的间距大于a4；则a2、a3、a4的关系为：a2<a3，a2<a4。即靠近源极区242设置的第一场板和靠近漏极区244设置的第二场板的间距设置得较宽，位于漂移区243中间位置的第三场板的间距设置得较窄。
每个结终端浮空场板211的长度大于相应的LDMOS浮空场板的长度，以保证结终端浮空场板211的电势占主导地位。以图1为例，即每个结终端浮空场板211的长度大于相应的NLDMOS 220中的LDMOS浮空场板251与PLDMOS 240中的LDMOS浮空场板251的长度之和。
由于横向双扩散金属氧化物半导体场效应晶体管在源极和漏极处的电势线较为集中，因此通过将靠近源极区/漏极区设置的第一场板/第二场板的间距设置得较宽、将漂移区中间位置的第三场板的间距设置得较窄，可以将横向双扩散金属氧化物半导体场效应晶体管在源极区/漏极区附近的电势梯度减小、在漂移区中间附近的电势梯度增大，从而使得横向双扩散金属氧化物半导体场效应晶体管的电势分布更加均匀，提升隔离结构中的LDMOS的击穿电压。
在图1所示的实施例中，隔离环还包括数量与结终端浮空场板211相同的多个隔离环浮空场板231。每个结终端浮空场板211通过相应的隔离环浮空场板231与相应的LDMOS浮空场板251一一对应电性连接。每个隔离环浮空场板231的一端延伸至对应的一结终端浮空场板211，另一端延伸至对应的一LDMOS浮空场板251。
在一个实施例中，相邻的结终端浮空场板之间的间距为a1，且a2<a1<a3，a2<a1<a4。在满足前述条件a2<a1<a3，a2<a1<a4的基础上，相邻的结终端浮空场板211的间距为1.0-3.2μm，相邻的第三场板的间距为0.5-3.0μm，相邻的第一场板的间距及离源极区最远的一第一场板与相邻的一第三场板之间的间距为1.2-4.0μm，相邻的第二场板的间距及离漏极区最远的一第二场板与相邻的一第三场板之间的间距为1.2-4.0μm。
在本申请的一个实施例中，相邻的结终端浮空场板211以间距L1等间距分布。在NLDMOS 220中，靠近漏极区224的第一至第p个LDMOS浮空场板251以间距L3等间距分布，靠近源极区222的第N-m至第N个LDMOS浮空场板251以间距L4等间距分布，剩余的第p至第N-m个LDMOS浮空场板251以间距L2等间距分布。在PLDMOS 240中，靠近源极区242的第一至第p个LDMOS浮空场板251以间距L6等间距分布，靠近漏极区244的第N-m至第N个LDMOS浮空场板251以间距L7等间距分布，剩余的第p至第N-m个LDMOS浮空场板251以间距L5等间距分布。并且满足关系：L1>L2，L1>L5，L3>L1，L4>L1，L6>L1，L7>L1。
在一个实施例中，多个浮空场板的总数N的取值范围为10-100，p和m的取值范围为2-15，N-p-m的取值范围为1-96。
在一个实施例中，NLDMOS 220的源极区222和漏极区224为N+区，漂移区223为N型漂移区。PLDMOS 240的源极区242和漏极区244为P+区，漂移区243为P型漂移区。
在图2所示的实施例中，NLDMOS 220还包括体区221、P阱225、N阱227、深N阱229及P型埋层228。体区221与源极区222通过接触孔引出后短接。体区221和源极区222位于P阱225中。漏极区224位于N阱227中。NLDMOS 220的场区绝缘层32位于源极区222和漏极区224之间。P型埋层228位于漂移区223和P阱225的下方。深N阱229位于漂移区223和N阱227的下方。
在图3所示的实施例中，PLDMOS 240还包括体区241、P阱245、N阱247、深N阱249及P型埋层248。体区241与源极区242通过接触孔引出后短接。体区241和源极 区242位于N阱247中。漏极区244位于P阱245中。PLDMOS 240的场区绝缘层34位于源极区242和漏极区244之间。深N阱249位于漂移区243和N阱247的下方。P型埋层248位于深N阱249中，且位于漂移区243和P阱245的下方。
在一个实施例中，NLDMOS 220的漏极接高压区300的电位，NLDMOS 220的源极接地。在一个实施例中，PLDMOS 240的源极接高压区300的电位，PLDMOS 240的漏极接地。
在一个实施例中，隔离结构(包括结终端210、隔离环及横向双扩散金属氧化物半导体场效应晶体管)还包括位于底部的衬底10，以及位于器件上表面的钝化层20。在图1所示的实施例中，衬底10的构成材料选用P型掺杂的单晶硅。
在一个实施例中，结终端浮空场板211、隔离环浮空场板231及LDMOS浮空场板251的材质相同，且是在同一步骤中制造形成。在一个实施例中，结终端浮空场板211、隔离环浮空场板231及LDMOS浮空场板251的材质为掺杂多晶硅。在一个实施例中，横向双扩散金属氧化物半导体场效应晶体管(包括NLDMOS 220和PLDMOS 240)中的栅极的材质为掺杂多晶硅。在一个实施例中，结终端浮空场板211、隔离环浮空场板231、LDMOS浮空场板251、栅极226及栅极246可以在同一步骤中制造形成。
图4是沿图1的C-C’线的剖视图。请一并参见图1和图4，在一个实施例中，结终端210还包括第一绝缘层31，每个结终端浮空场板211位于第一绝缘层31上。
在一个实施例中，第一绝缘层31、场区绝缘层32和场区绝缘层34的材质可以为硅氧化物，例如二氧化硅。
在图4所示的实施例中，结终端210还包括阴极区212和阳极区214。阴极区212和阳极区214的导电类型与NLDMOS 220的漏极区224的导电类型相同，即均为N+区。阴极区212通过接触孔引出后的金属连线(图未示)电性连接至NLDMOS 220的源极区222的电位，阳极区214通过接触孔引出后的金属连线(图未示)电性连接至NLDMOS 220的漏极区224的电位。在结终端210中设置类似于没有栅极的NLDMOS结构，有利于实现对高压区300和低压区100之间的隔离。
在图4所示的实施例中，结终端210还包括N型区213。N型区213的至少部分区域位于阴极区212和阳极区214之间，第一绝缘层31位于N型区213上。N型区213的作用类似于漂移区。
在图4所示的实施例中，结终端210还包括终端隔离结271。终端隔离结271位于N型区213与低压区100之间，以及于N型区213与高压区300之间。终端隔离结271具有与衬底10相同的导电类型。在衬底10为P型衬底的实施例中，终端隔离结271为P型掺杂区。
在一个实施例中，结终端210还包括体区216、P阱215、N阱217、深N阱219及P型埋层218。体区216与阴极区212通过接触孔引出后短接。体区216和阴极区212位于P阱215中。阳极区214位于N阱217中。第一绝缘层31位于P阱215和N阱217之间。 P型埋层218位于N型区213和P阱215的下方。深N阱219位于N型区213和N阱217的下方。
参照图1，在一个实施例中，每个结终端浮空场板211与对应的隔离环浮空场板231及LDMOS浮空场板251在平面上连成闭合环，即闭合浮空场板。可以理解为，从结终端210出发，跨越隔离环，传递至NLDMOS 220和PLDMOS 240上，并首尾相接。结终端210上的N个浮空场板以间距L1等间距分布。当高压区300和低压区100中的器件开始工作时，高压区300与低压区100之间的电位被隔离结构隔开，此时结终端210的漏端(即阳极区214)和源端(即阴极区212)、PLDMOS 240的源端和漏端、NLDMOS 220的漏端和源端承受着高压区300与低压区100之间的电压，电势在结终端210、NLDMOS 220和PLDMOS 240内部从高压电位降低至地电位。由于浮空场板为高掺杂的多晶硅场板，其内部具有大量的自由电子，因此在电场中浮空场板将会带有一定的感应电势。在结终端210上的N个结终端浮空场板211将会受到结终端210内部电势分布的影响，分别感应出电势V1、V2、……、VN，每个浮空场板带有的感应电势的值由其所处位置决定，且与其下方处的结终端区域的电势几乎相等，因此结终端210内的电势分布控制着每个结终端浮空场板211带有的感应电势。当浮空场板传递至NLDMOS 220和PLDMOS 240后，NLDMOS 220和PLDMOS 240内的电势分布也会对浮空场板的感应电势造成相应的影响。而在隔离结构中，结终端210占用的面积远大于LDMOS占用的面积，相应的，每个闭合浮空场板经过的结终端区域也远多于经过的LDMOS的区域(参照图1)，并且每个闭合浮空场板只能带有一个确定的感应电势，即每个闭合浮空场板在电场中为等势体，因此结终端210内的电势分布对闭合浮空场板产生的感应电势占绝对的主导地位，可视为每个闭合浮空场板上带有的感应电势由结终端210决定。由于LDMOS不足以改变每个闭合浮空场板带有的感应电势，因此每个从结终端210延伸而来的场板对于LDMOS而言相当于一个外置的“电压源”，浮空场板迫使其下方的LDMOS部分的区域接近浮空场板的电势。
综上，上述实施例提出的半导体高低压隔离结构形成了具有浮空场板的电势控制系统。结终端210内的电势分布控制了闭合浮空场板带有的感应电势，闭合浮空场板带有的感应电势控制了LDMOS内的电势分布。
根据上述原理，上述实施例基于变间距的浮空场板实现了对隔离结构中LDMOS的电势控制。首先，使NLDMOS 220和PLDMOS 240内的电势分布接近结终端210。若N个浮空场板中相邻的两个场板以处处相等的间距L1传递至LDMOS区，此时LDMOS内的电势分布被浮空场板钳制，因此接近结终端210内的电势分布。再通过改变LDMOS浮空场板251在LDMOS上的间距，进一步按照需求控制LDMOS内的电势分布，改变LDMOS内不同区域的电场强度大小。本申请采用变间距场板，将原本在结终端210上以L1等间距分布的N个结终端浮空场板211在隔离环上以斜场板的形式“变轨”，随后，这N个浮空场板将在LDMOS上以区别于L1的间距分布。每个浮空场板在传递至LDMOS区前已具有确定的电势，因此它们之间的电势差也是确定的，改变场板间距即改变它们之间电势 的梯度，相应的，变间距的LDMOS浮空场板251覆盖的LDMOS区域的电势的梯度也会改变，而电场强度是电势的梯度，因此改变某个区域的LDMOS浮空场板251的间距即为改变对应区域电场强度的大小，由此实现了对LDMOS内部电势及表面电场强度的控制。
也即，变间距场板的目的是以结终端210的电势分布控制LDMOS的电势分布，从而使LDMOS的性能得到提升，因此整个隔离结构的隔离能力也得到了提升，闭合浮空场板对其受益器件LDMOS而言是外部控制。比传统场板技术更优秀的是：本申请可以消除电势线集中点，变间距场板可以控制LDMOS的漂移区内每一部分电势的梯度几乎相等，意味着电势的变化是均匀的、不会在部分区域内急剧变化，因此LDMOS也不会成为隔离结构的击穿薄弱点。本申请对LDMOS内部电势的控制是全面的，变间距场板可以实现对LDMOS整个漂移区的电势控制，而不仅局限在其中一部分区域。另一方面，方案不会导致工艺和结构复杂化，即避免了增加制造成本。上述实施例中的闭合浮空场板可以采用多晶硅场板，而多晶硅工艺为高低压隔离结构制造工艺中形成每个类器件栅极的常见工艺，因此闭合浮空场板可以与多晶硅栅极在同一道工艺中形成，并不会引起制造工艺的增加。除此之外，闭合浮空场板在对LDMOS进行电势控制时，不需要对其内部结构进行改变，因此也避免了LDMOS设计与制造的复杂化。
图5是沿图1中的D-D’线的剖视图，图6是沿图1中的E-E’线的剖视图，图7是图1中第一隔离环230的局部放大图。在一个实施例中，隔离环还包括第二绝缘层33，每个隔离环浮空场板231位于第二绝缘层33上，第二绝缘层33位于隔离结233上。在一个实施例中，第二绝缘层33的材质可以为硅氧化物，例如二氧化硅。隔离结233具有与衬底10相同的导电类型。在衬底10为P型衬底的实施例中，隔离结233为P型掺杂区。
参见图7，每个隔离环浮空场板231均包括结终端连接部231a、LDMOS连接部231c及中间部231b。中间部231b的一端连接结终端连接部231a、且中间部231b在平面上与结终端连接部231a的延长线的夹角β大于零度小于80度。中间部231b的另一端连接LDMOS连接部231c、且中间部231b在平面上与LDMOS连接部231c的延长线的夹角θ大于零度小于80度。对于闭合浮空场板，为了使隔离结构中的横向双扩散金属氧化物半导体场效应晶体管上的电势分布更加均匀，因此相邻LDMOS浮空场板251之间的间距与相邻结终端浮空场板211之间的间距不一致。通过在隔离环上采用前述斜场板的形式进行“变轨”，从而将浮空场板的间距从结终端浮空场板211变为LDMOS浮空场板251的间距分布。
在一个实施例中，结终端连接部231a与中间部231b的连接位置距隔离环的边缘的距离为b1，LDMOS连接部231c与中间部231b的连接位置距隔离环的边缘的距离为b2，b1为隔离环的宽度的10％至30％，b2为隔离环的宽度的10％至30％。即中间部231b与结终端连接部231a/LDMOS连接部231c的连接位置应与隔离环的边界保持一定的距离。这是因为斜场板的拐角(即在夹角β、夹角θ的位置)会导致电力线聚集，产生强电场。将拐角设置为离隔离环边界一定距离，相对于将拐角设置在隔离环边界，能够提高隔离环的耐 压(即提高击穿电压)，避免横向双扩散金属氧化物半导体场效应晶体管与结终端210之间发生穿通。在图7所示的实施例中，斜场板的拐角设置在D-D’线和E-E’线的位置。
在一个实施例中，隔离环还包括保护阱235，第二绝缘层33位于隔离结233和保护阱235上。保护阱235的导电类型与NLDMOS的漏极区222的导电类型相反，且保护阱235的掺杂浓度大于隔离结233的掺杂浓度。在一个实施例中，保护阱235为P+掺杂区。设置保护阱235可以进一步提高隔离环的耐压，避免电势线集中引起隔离环击穿。在一个实施例中，至少部分结终端连接部231a与中间部231b的连接位置的正下方设有保护阱235，至少部分LDMOS连接部231c与中间部231b的连接位置的正下方设有保护阱235。这是因为斜场板的拐角会导致电力线聚集，因此将保护阱235设置在斜场板的拐角的正下方能够获得较好的提高隔离环耐压的效果。
图8是一实施例中隔离结构在第一隔离环230附近的局部放大图，图中的保护阱235进行了半透明处理。在该实施例中，保护阱235为一整块的P+结构。对于采用离子注入工艺形成保护阱235的方案，在其中一个实施例中，保护阱235的注入窗口的宽度应为斜场板两端距离的100％-110％，长度应为第一个场板和第N个场板间最大距离的100％-110％，以敷设在所有斜场板的拐角下方。图8中的区域100a具有与低压区100的部分结构相同的结构，区域300a具有与高压区300的部分结构相同的结构。图9是具有保护阱235的实施例中沿图1中的D-D’线的剖视图，图10是具有保护阱235的实施例中沿图1中的E-E’线的剖视图。图9相对于图5所示的实施例、图10相对于图6所示的实施例增设了保护阱235。
在一些实施例中，保护阱235也可以只作用于一部分的隔离环浮空场板231，例如仅作用于高压侧场板，参照图11和图12。在图11和图12所示的实施例中，保护阱235设置于靠近高压区300的部分隔离环浮空场板231的下方，其余的隔离环浮空场板231的下方不设置保护阱235。在图12所示的实施例中，保护阱235是设置在间距为L3的多个隔离环浮空场板231(即靠近高压区300的第一个至第p个隔离环浮空场板231)的下方。在一些实施例中，保护阱235的长度为第一个至第p个场板最大距离的100％-110％。对于保护阱235只设置在部分隔离环浮空场板231的下方的实施例，将保护阱235作用的隔离环浮空场板231选为靠近高压区300的几个隔离环浮空场板231，能够获得较好的提高隔离环耐压的效果；在其他实施例中，隔离环浮空场板231也可以是设置于其他隔离环浮空场板231的下方。
图13是另一实施例中在第一隔离环230附近的局部放大图，图中的保护阱235进行了半透明处理。其与图8所示实施例的主要区别在于，保护阱235为设置在拐角处的条状P+型掺杂区。对于采用离子注入工艺形成保护阱235的方案，在其中一个实施例中，保护阱235的注入窗口的宽度为隔离环宽度C的2％-5％，长度应为第一个场板和第N个场板间最大距离的100％-110％，以敷设在所有斜场板的拐角下方。
图14是又一实施例中在第一隔离环230附近的局部放大图，图中的保护阱235进行 了半透明处理。其与图8所示实施例的主要区别在于，保护阱235为设置在拐角处的点状P+型掺杂区，这些点状的P+型掺杂区呈列排布。对于采用离子注入工艺形成保护阱235的方案，在其中一个实施例中，保护阱235的注入窗口的宽度为隔离环宽度的2％-5％。
在一个实施例中，保护阱235与结终端210及横向双扩散金属氧化物半导体场效应晶体管中的P+注入为同一道注入，即在保护阱235的离子注入前的注入光刻与NLDMOS 220的体区221、PLDMOS 240的源极区242和漏极区244、以及结终端210的体区216采用相同的光刻版，在同一步光刻步骤中完成注入窗口的光刻，因此保护阱235的形成不会额外增加制造工序，利于节约成本。
在本说明书的描述中，参考术语“有些实施例”、“其他实施例”、“理想实施例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特征包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性描述不一定指的是相同的实施例或示例。
以上所述实施例的每个技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的每个个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种隔离结构，包括：
    结终端，包括多个结终端浮空场板；
    横向双扩散金属氧化物半导体场效应晶体管，包括多个LDMOS浮空场板，每个LDMOS浮空场板与至少一结终端浮空场板电性连接，每个结终端浮空场板的长度大于与所述结终端浮空场板电性连接的所述LDMOS浮空场板的长度。
  2. 根据权利要求1所述的隔离结构，其特征在于，还包括包围所述横向双扩散金属氧化物半导体场效应晶体管的隔离环，所述隔离环用于将所述横向双扩散金属氧化物半导体场效应晶体管与所述结终端隔离。
  3. 根据权利要求2所述的隔离结构，其特征在于，所述隔离环还包括多个隔离环浮空场板，每个LDMOS浮空场板通过一个隔离环浮空场板与相应的结终端浮空场板电性连接，每个隔离环浮空场板的一端延伸至对应的结终端浮空场板，每个隔离环浮空场板的另一端延伸至对应的LDMOS浮空场板。
  4. 根据权利要求3所述的隔离结构，其特征在于，所述横向双扩散金属氧化物半导体场效应晶体管还包括源极区、漏极区、栅极、漂移区及场区绝缘层，所述漂移区的至少部分区域位于所述源极区和漏极区之间，所述场区绝缘层位于所述漂移区上，所述栅极的一侧靠近所述源极区、另一侧靠近所述漏极区，所述LDMOS浮空场板的数量与所述结终端浮空场板相同，所述多个LDMOS浮空场板与所述多个结终端浮空场板一一对应电性连接；所述LDMOS浮空场板包括靠近所述源极区设置的第一场板、靠近所述漏极区设置的第二场板及位于所述第一场板和第二场板之间的第三场板，相邻的第三场板之间的间距小于a2，多个第二场板中离所述漏极区最远的一个第二场板与相邻的第三场板之间的间距大于a3，且相邻的第二场板之间的间距大于a3，多个第一场板中离所述源极区最远的一个第一场板与相邻的第三场板之间的间距大于a4，且相邻的第一场板之间的间距大于a4；a2<a3，a2<a4。
  5. 根据权利要求4所述的隔离结构，其特征在于，所述横向双扩散金属氧化物半导体场效应晶体管包括NLDMOS和PLDMOS，所述隔离环包括包围所述NLDMOS的第一隔离环和包围所述PLDMOS的第二隔离环，所述每个所述结终端浮空场板的长度是对应的所述NLDMOS的LDMOS浮空场板和对应的所述PLDMOS的LDMOS浮空场板的长度之和。
  6. 根据权利要求5所述的隔离结构，其特征在于，所述结终端还包括第一绝缘层，所述多个结终端浮空场板位于所述第一绝缘层上。
  7. 根据权利要求6所述的隔离结构，其特征在于，所述结终端还包括阴极区和阳极区，所述阴极区和所述阳极区的为N型区，所述阴极区通过金属连线电性连接至所述NLDMOS的源极区的电位，所述阳极区通过金属连线电性连接至所述NLDMOS的漏极区的电位。
  8. 根据权利要求3所述的隔离结构，其特征在于，每个所述结终端浮空场板与对应的隔离环浮空场板及对应的LDMOS浮空场板连成闭合环。
  9. 根据权利要求7所述的隔离结构，其特征在于，所述隔离环还包括隔离结、保护阱及第二绝缘层，所述多个隔离环浮空场板位于所述第二绝缘层上，所述第二绝缘层位于所述隔离结和保护阱上，所述隔离结和保护阱为P型区，所述保护阱的掺杂浓度大于所述隔离结的掺杂浓度；
    每个隔离环浮空场板均包括结终端连接部、LDMOS连接部及中间部，所述中间部的一端连接所述结终端连接部，且所述中间部在平面上与所述结终端连接部的延长线的夹角大于零度小于80度，所述中间部的另一端连接所述LDMOS连接部，且所述中间部在平面上与所述LDMOS连接部的延长线的夹角大于零度小于80度；至少部分所述结终端连接部与所述中间部的连接位置的正下方设有所述保护阱，至少部分所述LDMOS连接部与所述中间部的连接位置的正下方设有所述保护阱。
  10. 根据权利要求9所述的隔离结构，其特征在于，所述保护阱包括设置在所述多个结终端连接部与所述中间部的连接位置处的条状掺杂区，以及设置在所述多个LDMOS连接部与所述中间部的连接位置处的条状掺杂区。
  11. 根据权利要求9所述的隔离结构，其特征在于，所述保护阱包括设置在所述多个结终端连接部与所述中间部的连接位置处呈列排布的点状掺杂区，以及设置在所述多个LDMOS连接部与所述中间部的连接位置处呈列排布的点状掺杂区。
  12. 根据权利要求9所述的隔离结构，其特征在于，所述结终端连接部与所述中间部的连接位置距所述隔离环的边缘的距离为b1，所述LDMOS连接部与所述中间部的连接位置距所述隔离环的边缘的距离为b2，b1为所述隔离环的宽度的10％至30％，b2为所述隔离环的宽度的10％至30％。
  13. 根据权利要求3所述的隔离结构，其特征在于，所述结终端浮空场板、隔离环浮空场板及LDMOS浮空场板的材质相同。
  14. 根据权利要求13所述的隔离结构，其特征在于，所述结终端浮空场板、隔离环浮空场板及LDMOS浮空场板的材质为掺杂多晶硅。
  15. 根据权利要求4所述的隔离结构，其特征在于，所述栅极的材质与所述结终端浮空场板、隔离环浮空场板及LDMOS浮空场板的材质相同。
  16. 根据权利要求4所述的隔离结构，其特征在于，相邻的结终端浮空场板之间的间距为a1，且a2<a1<a3，a2<a1<a4。
  17. 根据权利要求4所述的隔离结构，其特征在于，相邻的结终端浮空场板的间距相等。
  18. 根据权利要求4所述的隔离结构，其特征在于，相邻的结终端浮空场板的间距为1.0-3.2μm，相邻的第三场板的间距为0.5-3.0μm，相邻的第一场板的间距及所述离所述源极区最远的一所述第一场板与相邻的一第三场板之间的间距为1.2-4.0μm，相邻的第二场 板的间距及所述离所述漏极区最远的一所述第二场板与相邻的一第三场板之间的间距为1.2-4.0μm。
  19. 一种集成电路，包括第一电压区、第二电压区及位于所述第一电压区和第二电压区之间的如权利要求1-18中任一项所述的隔离结构。
  20. 根据权利要求19所述的集成电路，其特征在于，所述第二电压区中的器件的工作电压大于所述第一电压区中的器件的工作电压。
PCT/CN2024/087925 2023-06-15 2024-04-16 隔离结构及集成电路 Ceased WO2024255427A1 (zh)

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CN102184944A (zh) * 2011-04-29 2011-09-14 南京邮电大学 一种横向功率器件的结终端结构
CN109599394A (zh) * 2017-09-28 2019-04-09 台湾积体电路制造股份有限公司 集成电路及其制造方法
CN110518056A (zh) * 2019-08-02 2019-11-29 无锡华润上华科技有限公司 横向扩散金属氧化物半导体器件及其制造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102184944A (zh) * 2011-04-29 2011-09-14 南京邮电大学 一种横向功率器件的结终端结构
CN109599394A (zh) * 2017-09-28 2019-04-09 台湾积体电路制造股份有限公司 集成电路及其制造方法
CN110518056A (zh) * 2019-08-02 2019-11-29 无锡华润上华科技有限公司 横向扩散金属氧化物半导体器件及其制造方法

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