WO2024254940A1 - 显示背板及显示装置 - Google Patents

显示背板及显示装置 Download PDF

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Publication number
WO2024254940A1
WO2024254940A1 PCT/CN2023/108485 CN2023108485W WO2024254940A1 WO 2024254940 A1 WO2024254940 A1 WO 2024254940A1 CN 2023108485 W CN2023108485 W CN 2023108485W WO 2024254940 A1 WO2024254940 A1 WO 2024254940A1
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WO
WIPO (PCT)
Prior art keywords
transistor
sub
module
source
mirror current
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2023/108485
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English (en)
French (fr)
Inventor
曾勉
孙亮
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Application filed by Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US18/557,055 priority Critical patent/US20260087970A1/en
Priority to DE112023000107.3T priority patent/DE112023000107T5/de
Publication of WO2024254940A1 publication Critical patent/WO2024254940A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2003—Display of colours
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2074—Display of intermediate tones using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0242—Compensation of deficiencies in the appearance of colours

Definitions

  • the present application relates to the field of display technology, and in particular to a display backplane and a display device.
  • Micro light-emitting diodes such as Mini LED and Micro LED
  • Mini LED and Micro LED have significant advantages such as higher brightness, better luminous efficiency and lower power consumption, and have become the focus of research in the display panel industry.
  • the monochrome array display driver for micro-light emitting diodes usually uses a digital sub-field scanning method for monochrome display.
  • the 256 grayscales of each RGB sub-pixel make the existing clock frequency unable to meet the needs of full-color display.
  • the present application provides a display backplane and a display device to solve the technical problem that the existing display backplane cannot display in full color due to the limitation of clock frequency.
  • the present application provides a display backplane, which includes:
  • the pixel driving circuit comprises a signal receiving module, a signal storage module, a switch module and an adjustment module, wherein the signal receiving module receives a data signal from a data signal source and transmits the data signal to the signal storage module and the switch module, wherein the signal storage module is used to store the data signal, and the switch module is used to transmit an adjustment current from the adjustment module to the light-emitting device; and
  • a mirror current source module electrically connected to the regulating modules in the plurality of pixel driving circuits, the mirror current source module being used to regulate a regulating current input to the regulating module;
  • the multiple sub-pixel units include multiple first sub-pixel units, multiple second sub-pixel units, and multiple third sub-pixel units.
  • the luminous colors of the first sub-pixel units, the second sub-pixel units, and the third sub-pixel units are different, and the adjustment currents of the adjustment modules input by the mirror current source module to the first sub-pixel units, the second sub-pixel units, and the third sub-pixel units are different.
  • the present application also proposes a display device, wherein the display device includes a display backplane, and the display backplane includes:
  • the pixel driving circuit comprises a signal receiving module, a signal storage module, a switch module and an adjustment module, wherein the signal receiving module receives a data signal from a data signal source and transmits the data signal to the signal storage module and the switch module, wherein the signal storage module is used to store the data signal, and the switch module is used to transmit an adjustment current from the adjustment module to the light-emitting device; and
  • a mirror current source module electrically connected to the regulating modules in the plurality of pixel driving circuits, the mirror current source module being used to regulate a regulating current input to the regulating module;
  • the multiple sub-pixel units include multiple first sub-pixel units, multiple second sub-pixel units, and multiple third sub-pixel units.
  • the luminous colors of the first sub-pixel units, the second sub-pixel units, and the third sub-pixel units are different, and the adjustment currents of the adjustment modules input by the mirror current source module to the first sub-pixel units, the second sub-pixel units, and the third sub-pixel units are different.
  • FIG1 is a schematic structural diagram of a display backplane of the present application.
  • FIG2 is a sub-field segmentation diagram of a frame of display data in the display backplane of the present application.
  • FIG3 is a schematic diagram of a first mirror current source module and circuit connection of a display backplane of the present application
  • FIG4 is a connection diagram of a first pixel driving circuit and a mirror current unit of a display backplane of the present application
  • FIG5 is a connection diagram of a second pixel driving circuit and a mirror current unit of a display backplane of the present application
  • FIG6 is a schematic diagram of a color RGB display of a display backplane in one frame of the present application.
  • FIG7 is a schematic diagram of image data subfield processing in a display backplane of the present application.
  • FIG8 is a timing diagram of subfield scanning in the display backplane of the present application.
  • FIG9 is a simplified structural diagram of a column scanning circuit in a display backplane of the present application.
  • FIG10 is a schematic diagram of a second mirror current source module and circuit connection of a display backplane of the present application.
  • FIG. 11 is a schematic diagram showing a third mirror current source module and circuit connection of the display backplane of the present application.
  • the digital subfield scanning method is usually used for monochrome display in the display driver of the monochrome array of micro-LEDs.
  • the existing clock frequency cannot meet the requirements of full-color display. Therefore, a display backplane is urgently needed to solve the above technical problems.
  • the present application provides a display backplane 100 , which includes a plurality of sub-pixel units 10 and a mirror current source module 200 .
  • each sub-pixel unit 10 includes a pixel driving circuit 110 and a light-emitting device LED.
  • the pixel driving circuit 110 includes a signal receiving module 111, a signal storage module 112, a switch module 113 and an adjustment module 114.
  • the signal receiving module 111 receives a data signal from a data signal source Data, and transmits the data signal to the signal storage module 112 and the switch module 113.
  • the signal storage module 112 is used to store the data signal, and the switch module 113 is used to transmit the adjustment current from the adjustment module 114 to the light-emitting device LED.
  • the mirror current source module 200 is electrically connected to the regulating modules 114 in the plurality of pixel driving circuits 110 , and the mirror current source module 200 is used to regulate the regulating current input to the regulating module 114 .
  • the multiple sub-pixel units 10 include multiple first sub-pixel units 101 that emit a first color, multiple second sub-pixel units 102 that emit a second color, and multiple third sub-pixel units 103 that emit a third color.
  • the light-emitting colors of the first sub-pixel unit 101, the second sub-pixel unit 102, and the third sub-pixel unit 103 are different.
  • the first sub-pixel unit 101 is a red sub-pixel
  • the second sub-pixel unit 102 is a green sub-pixel
  • the third sub-pixel unit 103 is a blue sub-pixel.
  • the adjustment currents of the adjustment module 114 input by the mirror current source module 200 to the first sub-pixel unit 101, the second sub-pixel unit 102, and the third sub-pixel unit 103 are different.
  • the display backplane 100 may include a display area and a non-display area, and a plurality of scan lines and a plurality of data lines are arranged in the display area, and the plurality of scan lines and the plurality of data lines cross to enclose a plurality of sub-pixel units 10, and the pixel driving circuit 110 in each sub-pixel unit 10 is connected to the corresponding data line and scan line.
  • the mirror current source module 200 is arranged in the non-display area to adjust the working current of the light-emitting device LED by adjusting the current input to the adjustment module 114, so as to adjust the luminous flux of the light-emitting device LED of different colors.
  • the display backplane 100 can be used as a direct display device.
  • the light-emitting device LED of the display backplane 100 can be Mini LED or Micro LED, etc., or the display backplane 100 can also be used as a backlight source for a liquid crystal display panel.
  • the following description will take the display backplane 100 as an example of a direct display device.
  • the display backplane 100 may also include a timing controller 300, a data processor 400, a row scanning circuit 500 and a column scanning circuit 600, the row scanning circuit 500 is connected to the scanning line in the display backplane 100, and the column scanning circuit 600 is connected to the data line in the display backplane 100; the timing controller 300 transmits a scanning signal to the row scanning circuit 500, and the timing controller 300 controls the data processor 400 to transmit a data signal to the column scanning circuit 600.
  • the present application can realize grayscale display by subfield scanning, that is, the scanning time of each frame of the display picture is divided into subfields of different sizes, and the light emission of each subfield is controlled separately.
  • the total light emission time of each subfield is combined to achieve the control of the total light emission time in this frame, thereby controlling the lighting time of each display unit in the display panel, so as to achieve the effect of each display unit having different grayscales.
  • each sub-pixel unit 10 includes multiple frames of display data
  • each frame of display data includes multiple sub-frames
  • each sub-frame includes a data writing stage t1 and a light-emitting stage t2
  • the light-emitting duration of the light-emitting stage t2 in different sub-frames is different.
  • the weighted value of each sub-frame is different, that is, the duration of the light-emitting stage t2 in each sub-frame is different, and the lighting duration of the light-emitting device LED is different.
  • the weighted value can be set in a standard binary weighted value increment or a non-standard binary weighted value increment.
  • a frame of 1H display data includes 8 subframes, namely, subframe F1, subframe F2, subframe F3, subframe F4, subframe F5, subframe F6, subframe F7 and subframe F8.
  • the standard binary weight value increment method is adopted, and the weight value ratio of each subframe is 1 (2 0 ): 2 (2 1 ): 4 (2 2 ): 8 (2 3 ): 16 (2 4 ): 32 (2 5 ): 64 (2 6 ): 128 (2 7 ).
  • the display data of a frame of 1H is the gray scale superposition of each subframe, so as to realize 255 gray scale display.
  • each sub-pixel unit 10 of each row emit light after the addressing scanning time, and each sub-pixel unit 10 can continue to emit light during the driving time of the entire frame display picture.
  • the sub-pixel unit 10 when the data signal source Data received by the sub-pixel unit 10 in the writing stage t1 is a high level, the sub-pixel unit 10 continues to emit light in the corresponding light-emitting stage t2, and when the data signal source Data received by the sub-pixel unit 10 in the writing stage t1 is a low level, the sub-pixel unit 10 does not emit light in the corresponding light-emitting stage t2; or, when the data signal source Data received by the sub-pixel unit 10 in the writing stage t1 is a low level, the sub-pixel unit 10 continues to emit light in the corresponding light-emitting stage t2, and when the data signal source Data received by the sub-pixel unit 10 in the writing stage t1 is a high level, the sub-pixel unit 10 does not emit light in the corresponding light-emitting stage t2.
  • the grayscale calculation method can be:
  • Grayscale (Gray) 1*d1+2*d2+4*d3+8*d4+16*d5+32*d6+64*d7+128*d8.
  • white light is obtained by adding the three primary colors of red (R), green (G), and blue (B).
  • RGB red
  • B blue
  • their luminous flux ratio is also certain.
  • the present application separately regulates the luminous flux and grayscale of RGB.
  • the grayscale is regulated by sub-field scanning
  • the luminous flux is regulated by setting a mirror current source module 200 connected to the adjustment module 114 in the pixel driving circuit 110 in the display backplane 100 to adjust the current input to the light-emitting device LED in the pixel driving circuit 110 in different sub-pixel units 10, so that the sub-pixel units 10 of different colors drive the light-emitting device LED to emit light with a preset proportion of driving current, so that the light-emitting device LED of different colors has a preset luminous flux, and the display backplane 100 can achieve full-color display at the existing clock frequency.
  • the multiple sub-pixel units 10 include multiple first sub-pixel units 101 that emit a first color, multiple second sub-pixel units 102 that emit a second color, and multiple third sub-pixel units 103 that emit a third color.
  • the light-emitting colors of the first sub-pixel unit 101, the second sub-pixel unit 102 and the third sub-pixel unit 103 are different.
  • the first sub-pixel unit 101 is a red sub-pixel
  • the second sub-pixel unit 102 is a green sub-pixel
  • the third sub-pixel unit 103 is a blue sub-pixel.
  • the mirror current source module 200 may include a first mirror current unit 210, a second mirror current unit 220, and a third mirror current unit 230.
  • the first mirror current unit 210 is electrically connected to the adjustment module 114 of at least one column of the first sub-pixel unit 101
  • the second mirror current unit 220 is electrically connected to the adjustment module 114 of at least one column of the second sub-pixel unit 102
  • the third mirror current unit 230 is electrically connected to the adjustment module 114 of at least one column of the third sub-pixel unit 103.
  • the display backplane 100 may further include a plurality of first transmission lines 241, a plurality of second transmission lines 242, and a plurality of third transmission lines 243, and one transmission line corresponds to a column of sub-pixel units 10.
  • a first transmission line 241 is connected to the adjustment module 114 in a column of red sub-pixels
  • a second transmission line 242 is connected to the adjustment module 114 in a column of green sub-pixels
  • a third transmission line 243 is connected to the adjustment module 114 in a column of blue sub-pixels.
  • the number of columns of red sub-pixels is the same as the number of first transmission lines 241
  • the number of columns of green sub-pixels is the same as the number of second transmission lines 242
  • the number of columns of blue sub-pixels is the same as the number of third transmission lines 243.
  • multiple first transmission lines 241 are connected in parallel
  • multiple second transmission lines 242 are connected in parallel
  • multiple third transmission lines 243 are connected in parallel
  • the first mirror current unit 210 is connected to the multiple first transmission lines 241
  • the second mirror current unit 220 is connected to the multiple second transmission lines 242
  • the third mirror current unit 230 is connected to the multiple third transmission lines 243; that is, the current of the adjustment module 114 in all the red sub-pixels in the display backplane 100 is regulated by the first mirror current unit 210, the current of the adjustment module 114 in all the green sub-pixels is regulated by the second mirror current unit 220, and the current of the adjustment module 114 in all the blue sub-pixels is regulated by the second mirror current unit 220.
  • the first transmission line 241, the second transmission line 242 and the third transmission line 243 may be arranged in different layers.
  • multiple source and drain layers may be arranged, and multiple first transmission lines 241, multiple second transmission lines 242 and multiple third transmission lines 243 may be arranged in different source and drain layers, or arranged in the same source and drain layer, and connected by metal bridges at the positions where the transmission lines cross.
  • the extension direction of the first transmission line 241, the second transmission line 242 and the third transmission line 243 can be the same as the extension direction of the data line and the constant voltage high level line, and the voltage transmitted in the transmission line and the constant voltage high level line is a constant voltage, the transmission line and the constant voltage high level line can be set on both sides of the data line, so that the coupling capacitance generated by the data line and the transmission line and the constant voltage high level line on both sides is offset.
  • the first end of the signal receiving module 111 is connected to the scanning signal source Gate, the second end of the signal receiving module 111 is connected to the data signal source Data, the third end of the signal receiving module 111, the first end of the signal storage module 112, and the first end of the switch module 113 are connected to the first node Q, the second end of the switch module 113 is connected to the adjustment module 114, the third end of the switch module 113 is connected to the light-emitting device LED, and the second end of the signal storage module 112 and the adjustment module 114 are connected to the constant voltage high level source VDD.
  • the switch module 113 may include a first transistor T1
  • the signal receiving module 111 may include a second transistor T2
  • the regulating module 114 may include a third transistor T3
  • the signal storage module 112 may include a storage capacitor Cst.
  • the gate of the second transistor T2 is connected to the scan signal source
  • the source of the second transistor T2 is connected to the data signal source Data
  • the drain of the second transistor T2 is connected to the first plate of the storage capacitor Cst and the gate of the first transistor T1
  • the source of the first transistor T1 is connected to the drain of the third transistor T3
  • the drain of the first transistor T1 is connected to the anode of the light-emitting device LED
  • the source of the third transistor T3 is connected to the constant voltage high level source VDD and the second plate of the storage capacitor Cst
  • the gate of the third transistor T3 is connected to the mirror current source module 200.
  • the mirror current unit in the mirror current source module 200 includes a current source 240, a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6; the first end of the current source 240 is connected to the digital-to-analog converter, the second end of the current source 240 is connected to the gates of the fifth transistor T5 and the sixth transistor T6, and the source of the sixth transistor T6, the drains of the fifth transistor T5 and the sixth transistor T6 are connected to the constant voltage low level source VSS, the source of the fifth transistor T5 is connected to the gates of the third transistor T3 and the fourth transistor T4, and the drain of the fourth transistor T4, and the source of the fourth transistor T4 is connected to the constant voltage high level source VDD.
  • the analog-to-digital converter 700 is a current-type DAC
  • different mirror current units have different analog-to-digital converters 700, and different color sub-pixels are individually controlled by different current-type DACs; for example, the first mirror current unit 210 is controlled by a current-type DAC corresponding to the red sub-pixel, the second mirror current unit 220 is controlled by a current-type DAC corresponding to the green sub-pixel, and the third mirror current unit 230 is controlled by a current-type DAC corresponding to the blue sub-pixel.
  • the pixel driving circuit 100 also includes a reference current line Iref, which is electrically connected to the gates of the third transistor T3 and the fourth transistor T4; at the same time, a reference current line Iref is provided in each column of sub-pixel units 10, and the reference current line Iref transmits the reference current output from the mirror current unit to the gate terminal of the third transistor T3 in the sub-pixel unit 10 in the same column.
  • a reference current line Iref is electrically connected to the gates of the third transistor T3 and the fourth transistor T4; at the same time, a reference current line Iref is provided in each column of sub-pixel units 10, and the reference current line Iref transmits the reference current output from the mirror current unit to the gate terminal of the third transistor T3 in the sub-pixel unit 10 in the same column.
  • the first transistor T1 , the second transistor T2 , and the third transistor T3 are P-type transistors
  • the fourth transistor T4 is a P-type transistor
  • the fifth transistor T5 and the sixth transistor T6 are N-type transistors.
  • the low level transmitted by the data signal source Data turns on the second transistor T2, and the data signal source transmits a low level to the first node Q through the source terminal of the second transistor T2, so that the first transistor T1 is turned on, and the storage capacitor Cst starts to charge; at the same time, the analog-to-digital converter 700 receives data from the register and transmits a current signal to the current source 240, so that the current source 240 outputs an initial reference current Iref 0 ;
  • the mirror current unit in this embodiment can accurately replicate the required current according to the W/L ratio in the corresponding transistor.
  • the fifth transistor T5 and the sixth transistor T6 constitute a first-stage mirror current circuit.
  • the current flowing through the third transistor T3 is transferred to the light emitting device LED through the source and drain of the first transistor T1 to make the light emitting device LED emit light.
  • the driving current of the light emitting device LED is positively correlated with the initial reference current Iref 0 output by the current source 240 .
  • the storage capacitor Cst is discharged to maintain the potential of the first node Q, so that the first transistor T1 is turned on and the light emitting device LED continues to emit light.
  • the present application can control the luminous brightness of the light-emitting device LED in the corresponding sub-pixel unit 10 by adjusting the reference current output from the mirror current unit; and for sub-pixel units 10 of different colors, different reference currents can be set for sub-pixel units 10 of different colors.
  • the present application can adjust the different reference currents output in the mirror current unit so that the light-emitting devices of different colors have different luminous fluxes, so that the luminous flux of the RGB sub-pixel unit meets the ratio of white light in a preset ratio.
  • the signal receiving module 111 includes a first receiving module and a second receiving module, the first ends of the first receiving module and the second receiving module are connected to the scanning signal source Gate, the second end of the first receiving module is connected to the first data signal source Data1, the second end of the second receiving module is connected to the second data signal source Data2, the third end of the second receiving module, the first end of the signal storage module 112, and the first end of the switch module 113 are connected to the second node M, the third end of the first receiving module and the second end of the signal storage module 112 are connected to the third node N, the second end of the switch module 113 is connected to the adjustment module 114, the third end of the switch module 113 is connected to the light-emitting device LED, and the third end of the signal storage module 112 and the adjustment module 114 are connected to the constant voltage high level source VDD.
  • the switch module 113 includes a first transistor T1
  • the first signal receiving module includes a first receiving transistor T21
  • the second signal receiving module includes a second receiving transistor T22
  • the regulating module 114 includes a third transistor T3
  • the signal storage module 112 includes a seventh transistor T7 , an eighth transistor T8 , a ninth transistor T9 and a tenth transistor T10 .
  • the gate of the first receiving transistor T21 is connected to the scanning signal source, the source of the first receiving transistor T21 is connected to the first data signal source Data1, the drain of the first receiving transistor T21 is connected to the gates of the seventh transistor T7 and the ninth transistor T9, the source of the eighth transistor T8, and the drain of the tenth transistor T10; the gate of the second receiving transistor T22 is connected to the scanning signal source, the source of the second receiving transistor T22 is connected to the second data signal source Data2, the drain of the second receiving transistor T22 is connected to the eighth transistor T8 and the tenth transistor T10.
  • the gate of the first transistor T10 is connected to the gate of the seventh transistor T7, the source of the seventh transistor T7, the drain of the ninth transistor T9, and the gate of the first transistor T1; the drains of the seventh transistor T7 and the eighth transistor T8 are connected to the constant voltage low level source VSS, the sources of the ninth transistor T9 and the tenth transistor T10 are connected to the constant voltage high level source VDD, the source of the first transistor T1 is connected to the drain of the third transistor T3, the drain of the first transistor T1 is connected to the anode of the light emitting device LED, the source of the third transistor T3 is connected to the constant voltage high level source VDD, and the gate of the third transistor T3 is connected to the mirror current source module 200.
  • the pixel driving circuit 110 further includes a reference current line Iref, and the reference current line Iref is electrically connected to the gates of the third transistor T3 and the fourth transistor T4.
  • the first receiving transistor T21, the second receiving transistor T22, the seventh transistor T7 and the eighth transistor T8 are N-type transistors
  • the first transistor T1, the third transistor T3, the ninth transistor T9 and the tenth transistor T10 are P-type transistors
  • the fourth transistor T4 is a P-type transistor
  • the fifth transistor T5 and the sixth transistor T6 are N-type transistors.
  • the signal storage module 112 is in the writing stage, the first data signal source Data1 is written at a low level, the second data signal source Data2 is written at a high level, the high level output by the scanning signal source Scan turns on the second receiving transistor T22, the gate of the first transistor T1 is turned on by the low level output by the second data signal source Data2, and the current output by the third transistor T3 is transmitted to the light emitting device LED through the first transistor T1;
  • the high level output by the scanning signal source Scan turns on the first receiving transistor T1
  • the gate of the seventh transistor T7 is turned on by the high level output by the first data signal source Data1
  • the second node M between the seventh transistor T7 and the ninth transistor T9 is connected to the constant voltage low level source VSS, and the second node M maintains a low level
  • the gate of the tenth transistor T10 is turned on by the low level output by the second data signal source Data2
  • the third node N between the eighth transistor T8 and the tenth transistor T10 is connected to the constant voltage high level source VDD, and the third node N maintains a high level.
  • the signal storage module 112 is in the reading stage, and the low level of the second node M maintains the first transistor T1 turned on, so that the light emitting device LED continues to emit light.
  • this embodiment utilizes the seventh transistor T7, the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 to form two inverters, and the data signals transmitted by the first data signal source Data1 and the second data signal source Data2 are stored in the two inverters via the corresponding data signals output by the first receiving transistor T21 and the second receiving transistor T22 to replace the storage capacitor Cst in FIG4 ; since the capacitance in the storage capacitor Cst changes over time, the stored capacitance is unstable, and in the second stage, the voltage data output by the storage capacitor Cst may be different from the voltage data input in the first stage, while the inverter in FIG5 outputs a digital signal that does not change over time and is more stable than the storage capacitor.
  • the working principle of the mirror current unit in FIG. 5 is the same as that of the mirror current source in FIG. 4 .
  • the specific working principle can refer to the contents recorded in FIG. 4 .
  • pixel driving circuit 110 in FIG. 4 and FIG. 5 is only an example of the present application, and other pixel driving circuits 110 in the art are also applicable to the present application.
  • Figure 6 is a schematic diagram of the color RGB display of the display backplane 100 of the present application in 1 frame
  • the horizontal width is the luminous duration of the sub-pixel units 10 of different colors, that is, the displayed grayscale
  • the vertical height is the luminous brightness of the sub-pixels of different colors, that is, the luminous flux.
  • the luminous duration is achieved by sub-field scanning.
  • the binary number corresponding to grayscale L200 is 00010011
  • the digital signal corresponding to grayscale L128 is 00000001
  • the binary number corresponding to grayscale L64 is 00000010
  • the binary number corresponding to grayscale L0 is 00000000
  • the binary number of each grayscale is converted from parallel to serial.
  • the binary number of the first subframe SF is 0000
  • the binary number of the second subframe SF is 0000
  • the binary number of the third subframe SF is 0000
  • the binary number of the fourth subframe SF is 0001
  • the binary number of the fifth subframe SF is 0000
  • the binary number of the sixth subframe SF is 0000
  • the binary number of the seventh subframe SF is 0101
  • the binary number of the eighth subframe SF is 1001.
  • the data of the eight subfields in the above-mentioned one frame are written into the column scanning circuit 600 according to the subfield scanning timing in FIG. 8 .
  • the column scanning circuit 600 may include modules such as a shift register (Shift), a latch (Latch), and a level converter (Level Shift).
  • the shift register and the latch module are turned on under the action of the corresponding signal line, and the shift register and the latch module perform serial-to-parallel conversion on the received binary data, and the level converter converts the potential corresponding to the "0" or "1" state into two potentials of turning off the pixel circuit drive tube and turning on the pixel circuit drive tube, and outputs them from different output ports.
  • the present application separately regulates the luminous flux and grayscale of RGB.
  • the grayscale is achieved by sub-field scanning, while the luminous flux is regulated by setting a mirror current source module 200 in the display backplane 100 connected to the adjustment module 114 in the pixel driving circuit 110 to adjust the current input to the light-emitting device LED in the pixel driving circuit 110 in different sub-pixel units 10, so as to achieve different luminous fluxes of light-emitting devices LED of different colors, so that the display backplane 100 can achieve full-color display at the existing clock frequency.
  • the number of sub-pixel units 10 on the display backplane 100 is relatively large, resulting in differences in the potential received by the gate of the third transistor T3 of the sub-pixel unit 10 that is farther away from the current source.
  • the reference currents transmitted from the mirror current source module 200 to the sub-pixel units 10 in different columns are different, resulting in an uneven display problem.
  • the mirror current source module 200 may include a plurality of cascaded first mirror current units 210, a plurality of cascaded second mirror current units 220, and a plurality of cascaded third mirror current units 230, the plurality of cascaded first mirror current units 210 constitute a first mirror current group 211, the plurality of cascaded second mirror current units 220 constitute a second mirror current group 221, and the plurality of cascaded third mirror current units 230 constitute a third mirror current group 231; a first mirror current unit 210 is electrically connected to the adjustment module 114 of a column of first sub-pixel units 101, a second mirror current unit 220 is electrically connected to the adjustment module 114 of a column of second sub-pixel units 102, and a third mirror current unit 230 is electrically connected to the adjustment module 114 of a column of third sub-pixel units 103.
  • the present embodiment provides the same number of mirror current units as the number of transmission lines, one transmission line is connected to one mirror current unit, and the number of first transmission lines 241 is the same as the number of first mirror current units 210, the number of second transmission lines 242 is the same as the number of second mirror current units 220, and the number of third transmission lines 243 is the same as the number of third mirror current units 230.
  • any two first transmission lines 241 are separately arranged, any two second transmission lines 242 are separately arranged, and any two third transmission lines 243 are separately arranged.
  • each column of sub-pixel units 10 since a plurality of mirror current units are cascaded, the current source 240 and the sixth transistor T6 in each mirror current unit are shared, and the fourth transistor T4 and the fifth transistor T5 in each mirror current unit copy the reference current output by the current source 240 and transmit it to the corresponding third transistor T3.
  • the cascaded mirror current units enable each column of sub-pixel units 10 to have an independent reference current, thereby improving the technical problem that the potential received by the gate of the third transistor T3 is different due to the transmission distance; at the same time, each column of sub-pixel units 10 has an independent reference current, thereby increasing the stability of the pixel driving circuit 110.
  • the multiple sub-pixel units 10 include a first sub-pixel group 121 and a second sub-pixel group 122 arranged along the column direction; the display backplane 100 includes a first mirror current source module 131 and a second mirror current source module 132 mirrored on both sides of the multiple sub-pixel units 10, the first mirror current source module 131 is electrically connected to the adjustment module 114 in the first sub-pixel group 121, and the second mirror current source module 132 is electrically connected to the adjustment module 114 in the second sub-pixel group 122.
  • the sub-pixels in the display backplane 100 are divided into upper and lower partitions, the first mirror current source module 131 is connected to the gate of the third transistor T3 in the first sub-pixel group 121, and the second mirror current source module 132 is connected to the gate of the third transistor T3 in the second sub-pixel group 122, so that the number of sub-pixel units 10 connected to each mirror current unit is reduced.
  • the number of sub-pixel units 10 connected to one mirror current unit in FIG11 is reduced by one half, that is, the length of the corresponding transmission line will be reduced by one half, thereby improving the technical problem that the potential received by the gate of the third transistor T3 is different due to the transmission line impedance.
  • the pixel driving circuit 110 and the mirror current source module 200 in FIG. 10 and FIG. 11 may be the same as the pixel driving circuit 110 and the mirror current source module 200 in FIG. 4 and FIG. 5 .
  • the present application also proposes a display device, which includes a terminal body and the above-mentioned display backplane, and the terminal body and the display panel are combined into one.
  • the terminal body when the display backplane is a backlight source, the terminal body can be a liquid crystal display panel, and the display backplane and the liquid crystal display panel are combined into a display device; when the display backplane is a direct display device, the terminal body can be a circuit board or other device bound to the display panel and a cover plate covering the display panel.
  • the display device can include electronic devices such as mobile phones, televisions, and laptops.

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Abstract

公开了一种显示背板及显示装置。显示背板包括子像素单元（10）和镜像电流源模块（200），每一子像素单元（10）包括具有调节模块（114）的像素驱动电路（110）和发光器件（LED），镜像电流源模块（200）与多个像素驱动电路（110）中调节模块（114）电连接，镜像电流源模块（200）用于调节输入至调节模块（114）的调节电流，镜像电流源模块（200）输入至不同颜色子像素单元（10）的调节电流相异。

Description

显示背板及显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种显示背板及显示装置。
 背景技术
微型发光二极管，例如Mini LED、Micro LED，其具有亮度更高、发光效率更好、功耗更低的显著优势，已成为显示面板行业研究的重点。
目前针对微型发光二极管的单色阵列显示驱动，通常利用数字子场扫描法进行单色显示，而随着对显示面板的分辨率、刷帧率和显示灰阶要求的提高，以及为了实现RGB全彩色显示，RGB子像素的各256个灰阶，使得现有的时钟频率无法满足全彩显示的需求。
因此，亟需一种显示背板以解决上述技术问题。
 发明概述
本申请提供一种显示背板及显示装置，以解决现有显示背板因时钟频率的限制无法全彩显示的技术问题。
为解决上述方案，本申请提供的技术方案如下：
本申请提供一种显示背板，其包括：
多个子像素单元，每一所述子像素单元包括像素驱动电路和发光器件，所述像素驱动电路包括信号接收模块、信号存储模块、开关模块及调节模块，所述信号接收模块接收来自数据信号源的数据信号，并将所述数据信号传输至所述信号存储模块和所述开关模块，所述信号存储模块用于存储所述数据信号，所述开关模块用于将来自所述调节模块的调节电流传输至所述发光器件；以及
镜像电流源模块，与多个所述像素驱动电路中所述调节模块电连接，所述镜像电流源模块用于调节输入至所述调节模块的调节电流；
其中，多个所述子像素单元包括多个第一子像素单元、多个第二子像素单元、多个第三子像素单元，所述第一子像素单元、所述第二子像素单元及所述第三子像素单元的发光颜色相异，所述镜像电流源模块输入至所述第一子像素单元、所述第二子像素单元及所述第三子像素单元中的所述调节模块的调节电流相异。
本申请还提出了一种显示装置，其中，所述显示装置包括显示背板，所述显示背板包括：
多个子像素单元，每一所述子像素单元包括像素驱动电路和发光器件，所述像素驱动电路包括信号接收模块、信号存储模块、开关模块及调节模块，所述信号接收模块接收来自数据信号源的数据信号，并将所述数据信号传输至所述信号存储模块和所述开关模块，所述信号存储模块用于存储所述数据信号，所述开关模块用于将来自所述调节模块的调节电流传输至所述发光器件；以及
镜像电流源模块，与多个所述像素驱动电路中所述调节模块电连接，所述镜像电流源模块用于调节输入至所述调节模块的调节电流；
其中，多个所述子像素单元包括多个第一子像素单元、多个第二子像素单元、多个第三子像素单元，所述第一子像素单元、所述第二子像素单元及所述第三子像素单元的发光颜色相异，所述镜像电流源模块输入至所述第一子像素单元、所述第二子像素单元及所述第三子像素单元中的所述调节模块的调节电流相异。
 附图说明
图1为本申请显示背板的结构简图；
图2为本申请显示背板中一帧显示数据的子场切分图；
图3为本申请显示背板的第一种镜像电流源模块及电路连接示意图；
图4为本申请显示背板的第一种像素驱动电路和镜像电流单元连接图；
图5为本申请显示背板的第二种像素驱动电路和镜像电流单元连接图；
图6为本申请显示背板在一帧中彩色RGB显示的示意图；
图7为本申请显示背板中图像数据子场处理示意图；
图8为本申请显示背板中子场扫描时序图；
图9为本申请显示背板中列扫描电路的结构简图；
图10为本申请显示背板的第二种镜像电流源模块及电路连接示意图；
图11为本申请显示背板的第三种镜像电流源模块及电路连接示意图。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
目前针对微型发光二极管的单色阵列显示驱动，通常利用数字子场扫描法进行单色显示，而随着对显示面板的分辨率、刷帧率和显示灰阶要求的提高，以及为了实现RGB全彩色显示，RGB子像素的各256个灰阶，使得现有的时钟频率无法满足全彩显示的需求。因此亟需一种显示背板以解决上述技术问题。
请参阅图1至图11，本申请提供一种显示背板100，其包括多个子像素单元10和镜像电流源模块200。
在本实施例中，每一子像素单元10包括像素驱动电路110和发光器件LED，像素驱动电路110包括信号接收模块111、信号存储模块112、开关模块113及调节模块114，信号接收模块111接收来自数据信号源Data的数据信号，并将数据信号传输至信号存储模块112和开关模块113，信号存储模块112用于存储数据信号，开关模块113用于将来自调节模块114的调节电流传输至发光器件LED。
在本实施例中，镜像电流源模块200与多个像素驱动电路110中调节模块114电连接，镜像电流源模块200用于调节输入至调节模块114的调节电流。
在本实施例中，多个子像素单元10包括发第一颜色的多个第一子像素单元101、发第二颜色的多个第二子像素单元102、发第三颜色的多个第三子像素单元103，第一子像素单元101、第二子像素单元102及第三子像素单元103的发光颜色相异，例如第一子像素单元101为红色子像素，第二子像素单元102为绿色子像素，第三子像素单元103为蓝色子像素，镜像电流源模块200输入至第一子像素单元101、第二子像素单元102及第三子像素单元103中的调节模块114的调节电流相异。
需要说明的是，显示背板100可以包括显示区和非显示区，显示区内设置有多条扫描线和多条数据线，多条扫描线和多条数据线交叉围合成多个子像素单元10，每一子像素单元10内的像素驱动电路110和对应的数据线和扫描线连接。镜像电流源模块200设置于非显示区，以通过调节输入至调节模块114的电流调节发光器件LED的工作电流，以调节不同颜色的发光器件LED的发光通量。
需要说明的是，显示背板100可以作为直接显示设备，例如显示背板100的发光器件LED可以为Mini LED或Micro LED等，或者显示背板100也可以作为液晶显示面板的背光源，下面以显示背板100为直接显示设备为例进行说明。
需要说明的是，请参阅图1，显示背板100还可以包括时序控制器300、数据处理器400、行扫描电路500和列扫描电路600，行扫描电路500和显示背板100中的扫描线连接，列扫描电路600和显示背板100中的数据线连接；时序控制器300向行扫描电路500传输扫描信号，时序控制器300控制数据处理器400向列扫描电路600传输数据信号。
需要说明的是，本申请可以利用子场扫描的方式实现灰度显示，即将每一帧显示画面的扫描时间划分为大小不同的子场，对每一子场分别进行发光控制，各个子场发光总时间组合以达到对这帧内发光总时间的控制，从而对显示面板中的每个显示单元的点亮时间进行控制，达到每一个显示单元具有不同灰阶的效果。
需要说明的是，每一子像素单元10包括多帧显示数据，每帧显示数据包括多个子帧，每个子帧包括数据写入阶段t1和发光阶段t2，不同子帧内的发光阶段t2的发光时长相异。其中，每个子帧的加权值大小不同，即每个子帧内发光阶段t2的时长不同，发光器件LED的点亮时长不同。加权值的设置方式可以是标准的二进制加权值递增或者非标准的二进制加权值递增。
在图2的结构中，一帧1H显示数据包括8个子帧，分别为子帧F1、子帧F2、子帧F3、子帧F4、子帧F5、子帧F6、子帧F7和子帧F8，采用标准的二进制加权值递增的方式，每个子帧的加权值之比为1(2 0)：2(2 1)：4(2 2)：8(2 3)：16(2 4)：32(2 5)：64(2 6)：128(2 7)，一帧1H的显示数据为每个子帧的灰阶叠加，从而实现255灰阶显示。为了提高子像素单元10的L255灰阶的发光亮度，在扫描信号对每一行子像素单元10进行扫描时，每一行的子像素单元10在经过寻址扫描时间后发光，每个子像素单元10可以在整帧显示画面的驱动时间内持续发光。
即，当子像素单元10在写入阶段t1接收的数据信号源Data为高电平时，子像素单元10在对应的发光阶段t2持续发光，当子像素单元10在写入阶段t1接收的数据信号源Data为低电平时，子像素单元10在对应的发光阶段t2不发光；或者，当子像素单元10在写入阶段t1接收的数据信号源Data为低电平时，子像素单元10在对应的发光阶段t2持续发光，当子像素单元10在写入阶段t1接收的数据信号源Data为高电平时，子像素单元10在对应的发光阶段t2不发光。
例如，以实现显示频率60Hz，分辨率为1280x1024的单绿色Micro‑LED阵列的256级灰度调节为例，8个子场(记为子场1~8)组成1帧画面，将8个子场的发光阶段t2比设为1:2:4:8:16:32:64:128，将输入至8个子场的Data数据记为d1~d8。则灰度计算方式可以为：
灰度(Gray)＝1*d1+2*d2+4*d3+8*d4+16*d5+32*d6+64*d7+128*d8。
例如，当输入至第m个子场的Data数据为高电平时，dm＝1；当输入至第m个子场的Data数据为低电平时，dm＝0。当输入至所有子场的Data数据均为高电平时，d1~d8全为1，则Gray＝256；当输入至所有子场的Data数据均为低电平时，d1~d8全为0，则Gray＝0。
需要说明的是，全彩显示中白光(W)是由红(R)、绿(G)、蓝(B)三基色相加而得，在固定的色坐标规格下，它们的光通量比例也是一定的。例如，在W(0.300，0.315)、R(0.682，0.317)、G(0.250，0.710)、B(0.138，0.051)的色坐标规格下，RGB的光通量比例ΦR:ΦG:ΦB=3.18:9.27:1。
而本申请将RGB的光通量和灰阶分开调控，灰阶利用子场扫描的方式，而光通量通过在显示背板100中设置与像素驱动电路110中的调节模块114连接的镜像电流源模块200，以调节不同子像素单元10中像素驱动电路110中输入至发光器件LED的电流，以使不同颜色的子像素单元10以预设比例的驱动电流驱动发光器件LED发光，以使不同颜色的发光器件LED具有预设的发光通量，使显示背板100在现有的时钟频率下实现全彩显示。
需要说明的是，本申请中多个子像素单元10的排列方式不作具体限定，下面以标准的RGB为例进行说明。
现结合具体实施例对本申请的技术方案进行描述。
请参阅图3，多个子像素单元10包括发第一颜色的多个第一子像素单元101、发第二颜色的多个第二子像素单元102、发第三颜色的多个第三子像素单元103，第一子像素单元101、第二子像素单元102及第三子像素单元103的发光颜色相异，例如第一子像素单元101为红色子像素，第二子像素单元102为绿色子像素，第三子像素单元103为蓝色子像素。
在本实施例中，镜像电流源模块200可以包括第一镜像电流单元210、第二镜像电流单元220、第三镜像电流单元230，第一镜像电流单元210与至少一列第一子像素单元101的调节模块114电连接，第二镜像电流单元220与至少一列第二子像素单元102的调节模块114电连接，第三镜像电流单元230与至少一列第三子像素单元103的调节模块114电连接。
在本实施例中，显示背板100还可以包括多条第一传输线241、多条第二传输线242及多条第三传输线243，一条传输线对应一列子像素单元10。例如图3的结构中，一条第一传输线241和一列红色子像素中的调节模块114连接，一条第二传输线242和一列绿色子像素中的调节模块114连接，一条第三传输线243和一列蓝色子像素中的调节模块114连接，红色子像素的列数和第一传输线241的数量相同，绿色子像素的列数和第二传输线242的数量相同，蓝色子像素的列数和第三传输线243的数量相同。
在本实施例中，多条第一传输线241并联连接，多条第二传输线242并联连接，多条第三传输线243并联连接，第一镜像电流单元210和多条第一传输线241连接，第二镜像电流单元220和多条第二传输线242连接，第三镜像电流单元230和多条第三传输线243连接；即显示背板100中所有的红色子像素中的调节模块114的电流由第一镜像电流单元210调控，所有的绿色子像素中的调节模块114的电流由第二镜像电流单元220调控，所有的蓝色子像素中的调节模块114的电流由第二镜像电流单元220调控。
在本实施例中，第一传输线241、第二传输线242及第三传输线243可以异层设置。例如，可以设置多层源漏极层，将多条第一传输线241、多条第二传输线242及多条第三传输线243设置在不同的源漏极层中，或者设置在同一层源漏极层，在传输线交叉的位置利用金属过桥进行连接。
在本实施例中，由于第一传输线241、第二传输线242及第三传输线243的延伸方向可以和数据线及恒压高电平线的延伸方向相同，而传输线和恒压高电平线中传输的电压为恒定电压，因此可以将传输线和恒压高电平线设置在数据线的两侧，使得数据线和两侧的传输线和恒压高电平线产生的耦合电容抵消。
在本申请的显示背板100中，信号接收模块111的第一端连接扫描信号源Gate，信号接收模块111的第二端连接数据信号源Data，信号接收模块111的第三端、信号存储模块112的第一端、开关模块113的第一端连接于第一节点Q，开关模块113的第二端和调节模块114连接，开关模块113的第三端和发光器件LED连接，信号存储模块112的第二端和调节模块114连接恒压高电平源VDD。
请参阅图4，开关模块113可以包括第一晶体管T1，信号接收模块111包括第二晶体管T2，调节模块114包括第三晶体管T3，信号存储模块112包括存储电容Cst。
在本实施例中，请参阅图4，第二晶体管T2的栅极连接扫描信号源，第二晶体管T2的源极连接数据信号源Data，第二晶体管T2的漏极连接存储电容Cst的第一极板和第一晶体管T1的栅极，第一晶体管T1的源极连接第三晶体管T3的漏极，第一晶体管T1的漏极连接发光器件LED的阳极，第三晶体管T3的源极连接恒压高电平源VDD和存储电容Cst的第二极板，第三晶体管T3的栅极连接镜像电流源模块200。
在本实施例中，请参阅图4，镜像电流源模块200中的镜像电流单元包括电流源240、第四晶体管T4、第五晶体管T5及第六晶体管T6；电流源240的第一端连接数模转换器，电流源240的第二端连接第五晶体管T5和第六晶体管T6的栅极、及第六晶体管T6的源极，第五晶体管T5和第六晶体管T6的漏极连接恒压低电平源VSS，第五晶体管T5的源极连接第三晶体管T3和第四晶体管T4的栅极、及第四晶体管T4的漏极，第四晶体管T4的源极连接恒压高电平源VDD。
在本实施例中，模数转换器700为电流型DAC，且不同的镜像电流单元具备不同的模数转换器700，不同颜色子像素由不同的电流型DAC单独控制；例如，第一镜像电流单元210由与红色子像素对应的电流型DAC，第二镜像电流单元220由与绿色子像素对应的电流型DAC，第三镜像电流单元230由与蓝色子像素对应的电流型DAC。
在本实施例中，像素驱动电路100还包括参考电流线Iref，参考电流线Iref与第三晶体管T3和第四晶体管T4的栅极电连接；同时，每一列子像素单元10中设置有一条参考电流线Iref，该参考电流线Iref将从镜像电流单元中输出的参考电流传输至同一列的子像素单元10中的第三晶体管T3的栅极端。
在本实施例中，第一晶体管T1、第二晶体管T2及第三晶体管T3为P型晶体管，第四晶体管T4为P型晶体管，第五晶体管T5和第六晶体管T6为N型晶体管。
下面对图4中的电路图的工作原理进行描述。
在第一阶段，数据信号源Data传输的低电平将第二晶体管T2打开，数据信号源通过第二晶体管T2的源极端向第一节点Q传输低电平，以使第一晶体管T1被打开，同时存储电容Cst开始充电；同时，模数转换器700接收来自寄存器的数据，并向电流源240传递电流信号，以使电流源240输出初始参考电流Iref 0；
本实施例中的镜像电流单元可以根据对应晶体管中W/L的比例精确复制所需要的电流，例如第五晶体管T5和第六晶体管T6构成第一级镜像电流电路，根据镜像电流电路的特点，调整第五晶体管T5和第六晶体管T6的W/L参数，则流经第五晶体管T5的电流可以为k 1*Iref 0，其中，k 1=(W5/L5)/(W6/L6)；
同时第三晶体管T3和第四晶体管T4形成第二级镜像电流电路，调整第三晶体管T3和第四晶体管T4的W/L参数，使流经第三晶体管T3的电流为k 1*k 2*Iref 0，其中，k 2=(W3/L4)/(W4/L4)。
因此，由于第一晶体管T1被打开，流经第三晶体管T3的电流通过第一晶体管T1的源极和漏极传递至发光器件LED，以使发光器件LED发光，发光器件LED的驱动电流与电流源240输出初始参考电流Iref 0呈正相关。
在第二阶段，存储电容Cst放电以维持第一节点Q的电位，以使第一晶体管T1打开，发光器件LED持续发光。
在本实施例中，本申请可以通过调控从镜像电流单元输出的参考电流，以控制对应子像素单元10中发光器件LED的发光亮度；而对于不同颜色的子像素单元10，其可以针对不同颜色的子像素单元10设置不同的参考电流，例如在W(0.300，0.315)、R(0.682，0.317)、G(0.250，0.710)、B(0.138，0.051)的色坐标规格下，RGB的光通量比例ΦR:ΦG:ΦB=3.18:9.27:1，具体参与附图6中的结构，横向宽度为不同颜色子像素单元10的发光时长，即显示灰阶，纵向高度为不同颜色子像素的发光亮度，即不同颜色子像素的光通量，而不同的光通量对应发光器件LED不同的驱动电流，本申请可以通过调控镜像电流单元中输出的不同的参考电流，以使不同颜色的发光器件具有不同的光通量，以使RGB子像素单元的光通量以预设比例满足白光的配比。
在本申请的显示背板100中，信号接收模块111包括第一接收模块和第二接收模块，第一接收模块和第二接收模块的第一端连接扫描信号源Gate，第一接收模块的第二端连接第一数据信号源Data1，第二接收模块的第二端连接第二数据信号源Data2，第二接收模块的第三端、信号存储模块112的第一端、开关模块113的第一端连接于第二节点M，第一接收模块的第三端、信号存储模块112的第二端连接于第三节点N，开关模块113的第二端和调节模块114连接，开关模块113的第三端和发光器件LED连接，信号存储模块112的第三端和调节模块114连接于恒压高电平源VDD。
请参阅图5，开关模块113包括第一晶体管T1，第一信号接收模块包括第一接收晶体管T21，第二信号接收模块包括第二接收晶体管T22，调节模块114包括第三晶体管T3，信号存储模块112包括第七晶体管T7、第八晶体管T8、第九晶体管T9及第十晶体管T10。
请参阅图5，第一接收晶体管T21的栅极连接扫描信号源，第一接收晶体管T21的源极连接第一数据信号源Data1，第一接收晶体管T21的漏极连接第七晶体管T7和第九晶体管T9的栅极、第八晶体管T8的源极、第十晶体管T10的漏极；第二接收晶体管T22的栅极连接扫描信号源，第二接收晶体管T22的源极连接第二数据信号源Data2，第二接收晶体管T22的漏极连接第八晶体管T8和第十晶体管T10的栅极、第七晶体管T7的源极、第九晶体管T9的漏极、第一晶体管T1的栅极；第七晶体管T7和第八晶体管T8的漏极连接恒压低电平源VSS，第九晶体管T9和第十晶体管T10的源极连接恒压高电平源VDD，第一晶体管T1的源极连接第三晶体管T3的漏极，第一晶体管T1的漏极连接发光器件LED的阳极，第三晶体管T3的源极连接恒压高电平源VDD，第三晶体管T3的栅极连接镜像电流源模块200。
在本实施例中，像素驱动电路110还包括参考电流线Iref，参考电流线Iref与第三晶体管T3和第四晶体管T4的栅极电连接。
在本实施例中，第一接收晶体管T21、第二接收晶体管T22、第七晶体管T7及第八晶体管T8为N型晶体管，第一晶体管T1、第三晶体管T3、第九晶体管T9及第十晶体管T10为P型晶体管，第四晶体管T4为P型晶体管，第五晶体管T5和第六晶体管T6为N型晶体管。
下面对图5中的电路图的工作原理进行描述。
在第一阶段，信号存储模块112为写入阶段，第一数据信号源Data1写入低电平，第二数据信号源Data2写入高电平，扫描信号源Scan输出的高电平将第二接收晶体管T22打开，第一晶体管T1的栅极被第二数据信号源Data2输出的低电平打开，第三晶体管T3输出的电流通过第一晶体管T1传递至发光器件LED中；
同时，扫描信号源Scan输出的高电平将第一接收晶体管T1打开，第七晶体管T7的栅极被第一数据信号源Data1输出的高电平打开，第七晶体管T7和第九晶体管T9之间的第二节点M与恒压低电平源VSS连接，第二节点M维持低电平；同理，第十晶体管T10的栅极被第二数据信号源Data2输出的低电平打开，第八晶体管T8和第十晶体管T10之间的第三节点N与恒压高电平源VDD连接，第三节点N维持高电平。
在第二阶段，信号存储模块112为读取阶段，第二节点M的低电平维持第一晶体管T1的打开，使得发光器件LED持续发光。
与图4的结构相比，本实施例利用第七晶体管T7、第八晶体管T8、第九晶体管T9及第十晶体管T10构成2个反相器，第一数据信号源Data1和第二数据信号源Data2传输的数据信号经对应的第一接收晶体管T21和第二接收晶体管T22输出的数据信号存储在2个反相器中，以替换图4中的存储电容Cst；由于存储电容Cst中的电容量随时间会发生变化，所存储的电容量不稳定，在第二阶段中，存储电容Cst所输出的电压数据与第一阶段输入的电压数据可能存在差异，而图5中的反相器输出数字信号，不随时间发生变化，与存储电容相比更加稳定。
其次，图5中的镜像电流单元的工作原理与图4中的镜像电流源相同，具体工作原理可以参阅图4所记载的内容。
需要说明的是，图4和图5中的像素驱动电路110仅为本申请的示例，本领域中其他像素驱动电路110也适用本申请。
请参阅图6，图6为本申请的显示背板100在1帧中彩色RGB显示的示意图，横向宽度为不同颜色子像素单元10的发光时长，即显示灰阶，纵向高度为不同颜色子像素的发光亮度，即光通量。
在本实施例中，发光时长通过子场扫描的方式实现，例如图7中的结构，灰阶L200对应的二进制为00010011，灰阶L128对应数字信号为00000001，灰阶L64对应的二进制为00000010，灰阶L0对应的二进制为00000000，并将每一灰阶的二进制进行并串转换，例如第1子帧SF的二进制为0000，第2子帧SF的二进制为0000，第3子帧SF的二进制为0000，第4子帧SF的二进制为0001，第5子帧SF的二进制为0000，第6子帧SF的二进制为0000，第7子帧SF的二进制为0101，第8子帧SF的二进制为1001；其次，将上述1帧中8个子场的数据以图8中的子场扫描时序写入列扫描电路600中。
请参阅图9，图9为本申请的显示背板100中列扫描电路600的结构图。列扫描电路600可以包括移位寄存器(Shift)、锁存器(Latch)、电平转换器(Level Shift)等模块。其中，移位寄存器和锁存器模块在对应的信号线的作用下开启，以及移位寄存器和锁存器模块将接收的二进制数据进行串并转换，电平转换器将对应“0”或“1”状态的电位分别转换成关闭像素电路驱动管和开启像素电路驱动管的两种电位，并从不同的输出端口输出。
本申请将RGB的光通量和灰阶分开调控，灰阶利用子场扫描的方式，而光通量通过在显示背板100中设置与像素驱动电路110中的调节模块114连接的镜像电流源模块200，以调节不同子像素单元10中像素驱动电路110中输入至发光器件LED的电流，以实现不同颜色的发光器件LED的不同发光通量，使显示背板100在现有的时钟频率下实现全彩显示。
随着显示设备分辨率的增加，显示背板100上的子像素单元10的数量较多，使得距离电流源越远的子像素单元10的第三晶体管T3的栅极接收的电位具有差异，例如图3的结构中，从镜像电流源模块200传输至不同列的子像素单元10中的参考电流不相同，进而出现显示不均问题。
请参阅图10，镜像电流源模块200可以包括级联的多个第一镜像电流单元210、级联的多个第二镜像电流单元220、及级联的多个第三镜像电流单元230，级联的多个第一镜像电流单元210构成第一镜像电流组211，级联的多个第二镜像电流单元220构成第二镜像电流组221，级联的多个第三镜像电流单元230构成第三镜像电流组231；一第一镜像电流单元210与一列第一子像素单元101的调节模块114电连接，一第二镜像电流单元220与一列第二子像素单元102的调节模块114电连接，一第三镜像电流单元230与一列第三子像素单元103的调节模块114电连接。
与图3的结构相比，本实施例设置了与传输线的数量相同的镜像电流单元，一条传输线与一个镜像电流单元连接，且第一传输线241的数量和第一镜像电流单元210的数量相同，第二传输线242的数量和第二镜像电流单元220的数量相同，第三传输线243的数量和第三镜像电流单元230的数量相同。
在本实施例中，任意两条第一传输线241分离设置，任意两条第二传输线242分离设置，任意两条第三传输线243分离设置。
在本实施例中，由于多个镜像电流单元级联设置，则每一镜像电流单元中的电流源240和第六晶体管T6共用，每一镜像电流单元中的第四晶体管T4和第五晶体管T5将电流源240输出的参考电流复制，并传输至对应的第三晶体管T3中。级联的镜像电流单元使得每一列子像素单元10具有独立的参考电流，改善了因传输距离远近而导致第三晶体管T3的栅极接收的电位具有差异的技术问题；同时，每一列子像素单元10具备独立的参考电流，增加了像素驱动电路110的稳定性。
在本申请的显示背板100中，请参阅图11，多个子像素单元10包括沿列方向排布的第一子像素组121和第二子像素组122；显示背板100包括镜像设置于多个子像素单元10两侧的第一镜像电流源模块131和第二镜像电流源模块132，第一镜像电流源模块131与第一子像素组121中的调节模块114电连接，第二镜像电流源模块132与第二子像素组122中的调节模块114电连接。
在图10的基础上，由于显示背板100在列方向上的子像素单元10的数量较多，而由于金属线阻抗的作用，使得同一列中距离镜像电流单元较远的子像素中第三晶体管T3的栅极接收的电位具有差异；而本实施例将显示背板100中的子像素进行上下分区，第一镜像电流源模块131和第一子像素组121中的第三晶体管T3的栅极连接，第二镜像电流源模块132和第二子像素组122中的第三晶体管T3的栅极连接，使得每一个镜像电流单元连接的子像素单元10的数量减少，与图10相比，图11中一个镜像电流单元连接的子像素单元10减少了二分之一，即对应的传输线的长度将减少二分之一，改善了因传输线阻抗而导致第三晶体管T3的栅极接收的电位具有差异的技术问题。
在本实施例中，图10与图11中像素驱动电路110和镜像电流源模块200可以与图4和图5中的像素驱动电路110和镜像电流源模块200相同。
本申请还提出了一种显示装置，其包括终端主体和上述显示背板，终端主体和显示面板组合为一体。例如，当显示背板为背光源时，则终端主体可以为液晶显示面板，显示背板和液晶显示面板组合成显示装置；当显示背板为直接显示设备时，终端主体可以为绑定于显示面板的电路板等器件以及覆盖在显示面板上的盖板等。显示装置可以包括手机、电视机、笔记本电脑等电子设备。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种显示背板，其中，包括：
    多个子像素单元，每一所述子像素单元包括像素驱动电路和发光器件，所述像素驱动电路包括信号接收模块、信号存储模块、开关模块及调节模块，所述信号接收模块接收来自数据信号源的数据信号，并将所述数据信号传输至所述信号存储模块和所述开关模块，所述信号存储模块用于存储所述数据信号，所述开关模块用于将来自所述调节模块的调节电流传输至所述发光器件；以及
    镜像电流源模块，与多个所述像素驱动电路中所述调节模块电连接，所述镜像电流源模块用于调节输入至所述调节模块的调节电流；
    其中，多个所述子像素单元包括多个第一子像素单元、多个第二子像素单元、多个第三子像素单元，所述第一子像素单元、所述第二子像素单元及所述第三子像素单元的发光颜色相异，所述镜像电流源模块输入至所述第一子像素单元、所述第二子像素单元及所述第三子像素单元中的所述调节模块的调节电流相异。
  2. 根据权利要求1所述的显示背板，其中，所述镜像电流源模块包括第一镜像电流单元、第二镜像电流单元、第三镜像电流单元，所述第一镜像电流单元与至少一列所述第一子像素单元的所述调节模块电连接，所述第二镜像电流单元与至少一列所述第二子像素单元的所述调节模块电连接，所述第三镜像电流单元与至少一列所述第三子像素单元的所述调节模块电连接。
  3. 根据权利要求2所述的显示背板，其中，所述镜像电流源模块包括级联的多个第一镜像电流单元、级联的多个第二镜像电流单元、及级联的多个第三镜像电流单元；
    其中，一所述第一镜像电流单元与一列所述第一子像素单元的所述调节模块电连接，一所述第二镜像电流单元与一列所述第二子像素单元的所述调节模块电连接，一所述第二镜像电流单元与一列所述第二子像素单元的所述调节模块电连接。
  4. 根据权利要求2所述的显示背板，其中，多个所述子像素单元包括沿列方向排布的第一子像素组和第二子像素组；
    其中，所述显示背板包括镜像设置于多个所述子像素单元两侧的第一镜像电流源模块和第二镜像电流源模块，所述第一镜像电流源模块与所述第一子像素组中的所述调节模块电连接，所述第二镜像电流源模块与所述第二子像素组中的所述调节模块电连接。
  5. 根据权利要求2所述的显示背板，其中，所述显示背板还包括多条第一传输线、多条第二传输线及多条第三传输线；
    所述第一镜像电流单元通过多条所述第一传输线与对应的所述调节模块电连接，所述第二镜像电流单元通过多条所述第二传输线与对应的所述调节模块电连接，所述第三镜像电流单元通过多条所述第三传输线与对应的所述调节模块电连接；
    其中，所述第一传输线、所述第二传输线及所述第三传输线异层设置。
  6. 根据权利要求5所述的显示背板，其中，所述信号接收模块的第一端连接扫描信号源，所述信号接收模块的第二端连接数据信号源，所述信号接收模块的第三端、所述信号存储模块的第一端、所述开关模块的第一端连接于第一节点，所述开关模块的第二端和所述调节模块连接，所述开关模块的第三端和所述发光器件连接，所述信号存储模块的第二端和所述调节模块连接于所述恒压高电平源。
  7. 根据权利要求6所述的显示背板，其中，所述开关模块包括第一晶体管，所述信号接收模块包括第二晶体管，所述调节模块包括第三晶体管，所述信号存储模块包括存储电容；
    其中，所述第二晶体管的栅极连接扫描信号源，所述第二晶体管的源极连接第一数据信号源，所述第二晶体管的漏极连接所述存储电容的第一极板和所述第一晶体管的栅极，所述第一晶体管的源极连接所述第三晶体管的漏极，所述第一晶体管的漏极连接所述发光器件的阳极，所述第三晶体管的源极连接恒压高电平源和所述存储电容的第二极板，所述第三晶体管的栅极连接所述镜像电流源模块。
  8. 根据权利要求7所述的显示背板，其中，所述第一晶体管、所述第二晶体管及所述第三晶体管为P型晶体管。
  9. 根据权利要求7所述的显示背板，其中，所述镜像电流源模块中的镜像电流单元包括电流源、第四晶体管、第五晶体管及第六晶体管；
    其中，所述电流源的第一端连接数模转换器，所述电流源的第二端连接所述第五晶体管和所述第六晶体管的栅极、及所述第六晶体管的源极，所述第五晶体管和所述第六晶体管的漏极连接恒压低电平源，所述第五晶体管的源极连接所述第三晶体管和所述第四晶体管的栅极、及所述第四晶体管的漏极，所述第四晶体管的源极连接恒压高电平源。
  10. 根据权利要求5所述的显示背板，其中，所述信号接收模块包括第一接收模块和第二接收模块，所述第一接收模块和所述第二接收模块的第一端连接扫描信号源，所述第一接收模块的第二端连接第一数据信号源，所述第二接收模块的第二端连接第二数据信号源，所述第二接收模块的第三端、所述信号存储模块的第一端、所述开关模块的第一端连接于第二节点，所述第一接收模块的第三端、所述信号存储模块的第二端连接于第三节点，所述开关模块的第二端和所述调节模块连接，所述开关模块的第三端和所述发光器件连接，所述信号存储模块的第三端和所述调节模块连接于所述恒压高电平源。
  11. 根据权利要求10所述的显示背板，其中，所述开关模块包括第一晶体管，所述第一接收模块包括第一接收晶体管，所述第二接收模块包括第二接收晶体管，所述调节模块包括第三晶体管，所述信号存储模块包括第七晶体管、第八晶体管、第九晶体管及第十晶体管；
    其中，所述第一接收晶体管的栅极连接扫描信号源，所述第一接收晶体管的源极连接第一数据信号源，所述第一接收晶体管的漏极连接所述第七晶体管和所述第九晶体管的栅极、所述第八晶体管的源极、所述第十晶体管的漏极；
    所述第二接收晶体管的栅极连接扫描信号源，所述第二接收晶体管的源极连接第二数据信号源，所述第二接收晶体管的漏极连接所述第八晶体管和所述第十晶体管的栅极、所述第七晶体管的源极、所述第九晶体管的漏极、第一晶体管的栅极；
    第七晶体管和第八晶体管的漏极连接恒压低电平源，第九晶体管和第十晶体管的源极连接恒压高电平源，所述第一晶体管的源极连接所述第三晶体管的漏极，所述第一晶体管的漏极连接所述发光器件的阳极，所述第三晶体管的源极连接恒压高电平源，所述第三晶体管的栅极连接所述镜像电流源模块。
  12. 根据权利要求11所述的显示背板，其中，所述第一接收晶体管、所述第二接收晶体管、所述第七晶体管及所述第八晶体管为N型晶体管，所述第一晶体管、所述第三晶体管、所述第九晶体管及所述第十晶体管为P型晶体管。
  13. 根据权利要求11所述的显示背板，其中，所述镜像电流源模块中的镜像电流单元包括电流源、第四晶体管、第五晶体管及第六晶体管；
    其中，所述电流源的第一端连接数模转换器，所述电流源的第二端连接所述第五晶体管和所述第六晶体管的栅极、及所述第六晶体管的源极，所述第五晶体管和所述第六晶体管的漏极连接恒压低电平源，所述第五晶体管的源极连接所述第三晶体管和所述第四晶体管的栅极、及所述第四晶体管的漏极，所述第四晶体管的源极连接恒压高电平源。
  14. 根据权利要求13所述的显示背板，其中，所述第四晶体管为P型晶体管，所述第五晶体管和所述第六晶体管为N型晶体管。
  15. 根据权利要求13所述的显示背板，其中，所述像素驱动电路还包括参考电流线，所述参考电流线与所述第三晶体管和所述第四晶体管的栅极电连接。
  16. 根据权利要求1所述的显示背板，其中，所述显示背板还包括时序控制器、数据处理器、行扫描电路和列扫描电路，所述行扫描电路和所述显示背板中的扫描线连接，所述列扫描电路和所述显示背板中的数据线连接；
    其中，所述时序控制器向所述行扫描电路传输扫描信号，所述时序控制器控制所述数据处理器向所述列扫描电路传输数据信号。
  17. 根据权利要求1所述的显示背板，其中，多个所述子像素单元包括沿列方向排布的第一子像素组和第二子像素组；
    其中，所述显示背板包括镜像设置于多个所述子像素单元两侧的第一镜像电流源模块和第二镜像电流源模块，所述第一镜像电流源模块与所述第一子像素组中的所述调节模块电连接，所述第二镜像电流源模块与所述第二子像素组中的所述调节模块电连接。
  18. 根据权利要求1所述的显示背板，其中，每一所述子像素单元包括多帧显示数据，每帧所述显示数据包括多个子帧，每个所述子帧包括数据写入阶段和发光阶段，不同所述子帧内的发光阶段的发光时长相异；
    其中，当所述子像素单元在所述写入阶段接收的数据信号源为高电平时，所述子像素单元在对应的所述发光阶段持续发光，当所述子像素单元在所述写入阶段接收的数据信号源为低电平时，所述子像素单元在对应的所述发光阶段不发光。
  19. 根据权利要求1所述的显示背板，其中，每一所述子像素单元包括多帧显示数据，每帧所述显示数据包括多个子帧，每个所述子帧包括数据写入阶段和发光阶段，不同所述子帧内的发光阶段的发光时长相异；
    当所述子像素单元在所述写入阶段接收的数据信号源为低电平时，所述子像素单元在对应的所述发光阶段持续发光，当所述子像素单元在所述写入阶段接收的数据信号源为高电平时，所述子像素单元在对应的所述发光阶段不发光。
  20. 一种显示装置，其中，所述显示装置包括显示背板，所述显示背板包括：
    多个子像素单元，每一所述子像素单元包括像素驱动电路和发光器件，所述像素驱动电路包括信号接收模块、信号存储模块、开关模块及调节模块，所述信号接收模块接收来自数据信号源的数据信号，并将所述数据信号传输至所述信号存储模块和所述开关模块，所述信号存储模块用于存储所述数据信号，所述开关模块用于将来自所述调节模块的调节电流传输至所述发光器件；以及
    镜像电流源模块，与多个所述像素驱动电路中所述调节模块电连接，所述镜像电流源模块用于调节输入至所述调节模块的调节电流；
    其中，多个所述子像素单元包括多个第一子像素单元、多个第二子像素单元、多个第三子像素单元，所述第一子像素单元、所述第二子像素单元及所述第三子像素单元的发光颜色相异，所述镜像电流源模块输入至所述第一子像素单元、所述第二子像素单元及所述第三子像素单元中的所述调节模块的调节电流相异。
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