WO2024204491A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2024204491A1
WO2024204491A1 PCT/JP2024/012558 JP2024012558W WO2024204491A1 WO 2024204491 A1 WO2024204491 A1 WO 2024204491A1 JP 2024012558 W JP2024012558 W JP 2024012558W WO 2024204491 A1 WO2024204491 A1 WO 2024204491A1
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Prior art keywords
region
concentration region
film
electrode
high concentration
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PCT/JP2024/012558
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English (en)
French (fr)
Japanese (ja)
Inventor
誠悟 森
佑紀 中野
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to CN202480020659.5A priority Critical patent/CN120937525A/zh
Priority to DE112024001515.8T priority patent/DE112024001515T5/de
Priority to JP2025511112A priority patent/JPWO2024204491A1/ja
Publication of WO2024204491A1 publication Critical patent/WO2024204491A1/ja
Priority to US19/342,681 priority patent/US20260032990A1/en
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156—Drain regions of DMOS transistors
    • H10D62/157—Impurity concentrations or distributions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H10D62/405—Orientations of crystalline planes
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/50—Physical imperfections
    • H10D62/53—Physical imperfections the imperfections being within the semiconductor body 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/60—Schottky-barrier diodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
    • H10D84/141—VDMOS having built-in components
    • H10D84/143—VDMOS having built-in components the built-in components being PN junction diodes
    • H10D84/144—VDMOS having built-in components the built-in components being PN junction diodes in antiparallel diode configurations

Definitions

  • Patent document 1 discloses a semiconductor device having a termination structure in the peripheral region of the drift layer.
  • the present disclosure provides a semiconductor device having a novel configuration.
  • the present disclosure provides a semiconductor device including a chip having a main surface, a high concentration region of a first conductivity type formed on a surface layer of the main surface on the inner side of the chip, and a low concentration region of the first conductivity type formed on a surface layer of the main surface on the peripheral side of the chip, the low concentration region having an impurity concentration lower than the impurity concentration of the high concentration region.
  • the present disclosure provides a semiconductor device including a chip having a main surface, an active region provided in an inner portion of the main surface, an outer peripheral region provided on the periphery of the main surface, a high concentration region of a first conductivity type formed in a surface layer portion of the main surface in the active region, and a low concentration region of the first conductivity type formed in the surface layer portion of the main surface in the outer peripheral region and having an impurity concentration lower than the impurity concentration of the high concentration region.
  • FIG. 1 is a plan view showing a semiconductor device according to a first embodiment.
  • FIG. 2 is a cross-sectional view taken along the line II-II shown in FIG.
  • FIG. 3 is a cross-sectional view in which structures outside the chip are removed from the cross-sectional view shown in FIG.
  • FIG. 4 is a plan view showing an example of the layout of the first main surface.
  • FIG. 5 is a plan view showing an example of the layout of high concentration regions and low concentration regions.
  • FIG. 6 is an enlarged plan view showing a main portion of the first main surface.
  • FIG. 7 is an enlarged plan view showing further essential parts of the first main surface.
  • FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. FIG.
  • FIG. 9 is an enlarged cross-sectional view showing a main part of FIG.
  • FIG. 10 is a cross-sectional view taken along line X-X shown in FIG.
  • FIG. 11 is an enlarged cross-sectional view showing a main part of FIG.
  • FIG. 12 is a cross-sectional view showing a main part of a semiconductor device according to the second embodiment.
  • FIG. 13 is a cross-sectional view showing a main part of a semiconductor device according to the third embodiment.
  • FIG. 14 is a cross-sectional view showing a modification of the semiconductor device shown in FIG.
  • FIG. 15 is a cross-sectional view showing a main part of a semiconductor device according to the fourth embodiment.
  • FIG. 16 is an enlarged plan view showing a main part of a semiconductor device according to a fifth embodiment.
  • FIG. 17 is a cross-sectional view taken along line XVII-XVII shown in FIG.
  • FIG. 18 is a plan view showing a semiconductor device according to the sixth embodiment.
  • FIG. 19 is a cross-sectional view taken along line XIX-XIX shown in FIG.
  • FIG. 20 is a cross-sectional view showing a semiconductor device according to the seventh embodiment.
  • FIG. 21 is a cross-sectional view showing a semiconductor device according to an eighth embodiment.
  • FIG. 22 is a cross-sectional view showing a semiconductor device according to a ninth embodiment.
  • FIG. 23 is a cross-sectional view showing a modified example of the outer body region.
  • FIG. 24 is a cross-sectional view showing a modified example of the field region.
  • FIG. 25 is a cross-sectional view showing a first modified example of the source pad electrode.
  • FIG. 26 is a cross-sectional view showing a second modified example of the source pad electrode.
  • this term includes a numerical value (shape) that is equal to the numerical value (shape) of the comparison target, as well as a numerical error (shape error) within a range of ⁇ 10% based on the numerical value (shape) of the comparison target.
  • shape a numerical value that is equal to the numerical value (shape) of the comparison target
  • error a numerical error within a range of ⁇ 10% based on the numerical value (shape) of the comparison target.
  • the conductivity type of a semiconductor is indicated using “p-type” or “n-type”, but “p-type” may also be referred to as the “first conductivity type” and “n-type” as the “second conductivity type”. Of course, “n-type” may also be referred to as the "first conductivity type” and “p-type” as the “second conductivity type”.
  • P-type is a conductivity type resulting from a trivalent element
  • n-type is a conductivity type resulting from a pentavalent element.
  • the trivalent element is at least one of boron, aluminum, gallium, and indium.
  • the pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.
  • FIG. 1 is a plan view showing a semiconductor device 1A according to the first embodiment.
  • FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. 1.
  • FIG. 3 is a cross-sectional view obtained by removing structures outside the chip 2 from the cross-sectional view shown in FIG. 2.
  • FIG. 4 is a plan view showing an example layout of the first main surface 3.
  • FIG. 5 is a plan view showing an example layout of the high concentration region 10 and the low concentration region 11.
  • Figure 6 is an enlarged plan view showing a main portion of the first main surface 3.
  • Figure 7 is an enlarged plan view showing further main portions of the first main surface 3.
  • Figure 8 is a cross-sectional view taken along line VIII-VIII shown in Figure 7.
  • Figure 9 is an enlarged cross-sectional view showing the main portions of Figure 8.
  • Figure 10 is a cross-sectional view taken along line X-X shown in Figure 7.
  • Figure 11 is an enlarged cross-sectional view showing the main portions of Figure 10.
  • semiconductor device 1A is a semiconductor switching device having an insulated gate type transistor structure Tr as an example of a device structure.
  • the transistor structure Tr has a vertical structure.
  • Semiconductor device 1A is a SiC semiconductor device having a chip 2 including a SiC single crystal. Chip 2 may be referred to as a "SiC chip” or a "semiconductor chip.”
  • the chip 2 is made of hexagonal SiC single crystal and is formed into a rectangular parallelepiped shape.
  • the hexagonal SiC single crystal has a number of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc.
  • the chip 2 is made of 4H-SiC single crystal, but the chip 2 may be made of other polytypes.
  • the chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4.
  • the first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed in a plan view from the vertical direction Z (hereinafter simply referred to as "plan view").
  • the vertical direction Z is also the thickness direction of the chip 2 and the normal direction of the first main surface 3 (second main surface 4).
  • the first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape when viewed in a plan view.
  • the first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal.
  • the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal
  • the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.
  • the first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X.
  • the third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.
  • the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal
  • the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal.
  • the first direction X may be the a-axis direction of the SiC single crystal
  • the second direction Y may be the m-axis direction of the SiC single crystal.
  • the chip 2 (first main surface 3 and second main surface 4) has an off angle that is inclined at a predetermined angle in a predetermined off direction relative to the c-plane of the SiC single crystal.
  • the c-axis ((0001) axis) of the SiC single crystal is inclined from the vertical axis toward the off direction by the off angle.
  • the c-plane of the SiC single crystal is inclined by the off angle relative to the horizontal plane.
  • the off-direction is preferably the a-axis direction of the SiC single crystal (i.e., the second direction Y).
  • the off-angle may be greater than 0° and less than or equal to 10°.
  • the off-angle may have a value that falls within at least one of the following ranges: greater than 0° and less than or equal to 1°, 1° or more and less than or equal to 2.5°, 2.5° or more and less than or equal to 5°, 5° or more and less than or equal to 7.5°, and 7.5° or more and less than or equal to 10°.
  • the off angle is preferably 5° or less. It is particularly preferable that the off angle be 2° or more and 4.5° or less.
  • the off angle is typically set in the range of 4° ⁇ 0.1°. This specification does not exclude a configuration in which the off angle is 0° (i.e., a configuration in which the first main surface 3 is a just plane relative to the c-plane).
  • the chip 2 has a layered structure including a first semiconductor layer 6 and a second semiconductor layer 7.
  • the first semiconductor layer 6 is made of a substrate (SiC substrate) including a SiC single crystal (semiconductor single crystal) and has the off direction and off angle described above.
  • the first semiconductor layer 6 forms the second main surface 4 and forms part of the first to fourth side surfaces 5A to 5D.
  • the first semiconductor layer 6 may have a thickness of 10 ⁇ m or more and 500 ⁇ m or less.
  • the thickness of the first semiconductor layer 6 may have a value that belongs to at least one of the following ranges: 10 ⁇ m or more and 50 ⁇ m or less, 50 ⁇ m or more and 100 ⁇ m or less, 100 ⁇ m or more and 150 ⁇ m or less, 150 ⁇ m or more and 200 ⁇ m or less, 200 ⁇ m or more and 300 ⁇ m or less, 300 ⁇ m or more and 400 ⁇ m or less, and 400 ⁇ m or more and 500 ⁇ m or less.
  • the second semiconductor layer 7 is made of an epitaxial layer (SiC epitaxial layer) containing a SiC single crystal (semiconductor single crystal) and is laminated on the first semiconductor layer 6.
  • the second semiconductor layer 7 has the off direction and off angle described above.
  • the second semiconductor layer 7 forms the first main surface 3 and forms parts of the first to fourth side surfaces 5A to 5D. It is preferable that the second semiconductor layer 7 has a thickness less than that of the first semiconductor layer 6. Of course, the thickness of the second semiconductor layer 7 may be greater than the thickness of the first semiconductor layer 6.
  • the thickness of the second semiconductor layer 7 may be 5 ⁇ m or more and 50 ⁇ m or less.
  • the thickness of the second semiconductor layer 7 may have a value that belongs to at least one of the following ranges: 5 ⁇ m or more and 10 ⁇ m or less, 10 ⁇ m or more and 15 ⁇ m or less, 15 ⁇ m or more and 20 ⁇ m or less, 20 ⁇ m or more and 25 ⁇ m or less, 25 ⁇ m or more and 30 ⁇ m or less, 30 ⁇ m or more and 35 ⁇ m or less, 35 ⁇ m or more and 40 ⁇ m or less, 40 ⁇ m or more and 45 ⁇ m, and 45 ⁇ m or more and 50 ⁇ m or less.
  • the semiconductor device 1A includes an active region 8 set on the chip 2 (first main surface 3).
  • the active region 8 is set on the inner part of the chip 2 (first main surface 3).
  • the active region 8 includes a device structure (transistor structure Tr) and is a region where an output current (drain current) is generated.
  • the active region 8 is set in the inner part of the chip 2 at a distance from the periphery of the chip 2 (first to fourth side faces 5A to 5D) in a plan view.
  • the active region 8 is set in a polygonal shape (a square shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view.
  • the planar area of the active region 8 is preferably 50% to 90% of the planar area of the first main surface 3.
  • the semiconductor device 1A includes a peripheral region 9 that is set outside the active region 8 in the chip 2.
  • the peripheral region 9 is a region that does not include a device structure (transistor structure Tr).
  • the peripheral region 9 is set on the periphery of the chip 2 (first main surface 3). In other words, the peripheral region 9 is provided in the region between the periphery of the chip 2 and the active region 8 in a planar view.
  • the peripheral region 9 extends in a band shape along the active region 8 in a planar view, and is set in a polygonal ring shape (a square ring in this embodiment) that surrounds the active region 8.
  • the semiconductor device 1A has a relatively high first impurity concentration and includes an n-type high concentration region 10 formed in a surface layer portion of the first main surface 3.
  • a drain potential as a high potential (first potential) is applied to the high concentration region 10.
  • the high concentration region 10 may be referred to as a "first region,” a “first drift region,” a “first high concentration drift region,” or the like.
  • the first impurity concentration may be 1 ⁇ 10 16 cm -3 or more and 5 ⁇ 10 17 cm -3 or less.
  • the high concentration region 10 is formed on the inner side of the chip 2. Specifically, the high concentration region 10 is formed in the surface layer of the first main surface 3 in the active region 8, and extends in a layer along the first main surface 3. The high concentration region 10 is formed as a low resistance region (first low resistance region) having a relatively low resistance value in the active region 8. The high concentration region 10 is preferably formed throughout the entire active region 8. The high concentration region 10 may extend approximately perpendicular to the first main surface 3 in a cross-sectional view.
  • the high concentration region 10 extends from the active region 8 to the peripheral region 9, and has a portion located in the surface layer of the first main surface 3 in the peripheral region 9.
  • the high concentration region 10 extends from the active region 8 to the peripheral region 9 all around, and is formed at a distance inward from the periphery of the first main surface 3.
  • the high concentration region 10 is preferably formed at a distance inward from at least one of the first to fourth side surfaces 5A to 5D.
  • the high concentration region 10 is formed at a distance inward from the entire circumference of the first to fourth side surfaces 5A to 5D, and has a peripheral portion that surrounds the active region 8.
  • the high concentration region 10 is formed in the second semiconductor layer 7.
  • the high concentration region 10 may be formed by introducing an n-type impurity into a surface layer of the second semiconductor layer 7 (e.g., an n-type second semiconductor layer 7).
  • the high concentration region 10 is formed at a distance from the bottom of the second semiconductor layer 7 toward the first main surface 3, and faces the first semiconductor layer 6 with a part of the second semiconductor layer 7 in between.
  • the high concentration region 10 is preferably formed at a distance from the depth position of the middle part of the second semiconductor layer 7 toward the first main surface.
  • the thickness of the high concentration region 10 is preferably less than 1/2 the thickness of the second semiconductor layer 7.
  • the high concentration region 10 may cross the depth position of the middle part of the second semiconductor layer 7 in the thickness direction.
  • the thickness of the high concentration region 10 may be greater than 1/2 the thickness of the second semiconductor layer 7.
  • the high concentration region 10 may have a thickness of 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the thickness of the high concentration region 10 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the semiconductor device 1A includes an n-type low concentration region 11 having a second impurity concentration less than the first impurity concentration of the high concentration region 10 and formed in a surface layer portion of the first main surface 3.
  • the low concentration region 11 may be referred to as a "second region,” a “second drift region,” a “first low concentration drift region,” or the like.
  • the second impurity concentration may be 1 ⁇ 10 15 cm -3 or more and 5 ⁇ 10 16 cm -3 or less.
  • the low concentration region 11 is formed on the peripheral side of the chip 2 relative to the high concentration region 10. Specifically, the low concentration region 11 is formed in the surface layer of the first main surface 3 in the outer peripheral region 9, and extends in a layer along the first main surface 3. The low concentration region 11 is located in the region between the periphery of the first main surface 3 and the high concentration region 10. The low concentration region 11 is formed in the outer peripheral region 9 as a high resistance region (first high resistance region) having a higher resistance value than the high concentration region 10.
  • the low concentration region 11 extends in a band shape along the high concentration region 10 (active region 8) in a planar view.
  • the low concentration region 11 has a portion that extends in a band shape in the first direction X and a portion that extends in a band shape in the second direction Y in a planar view, and divides the high concentration region 10 (active region 8) from multiple directions.
  • the low concentration region 11 is formed in a ring shape (specifically, a square ring shape) that surrounds the high concentration region 10 (active region 8) in a planar view.
  • the low concentration region 11 has an inner edge on the inside side of the first main surface 3 and an outer edge on the peripheral side of the first main surface 3.
  • the inner edge of the low concentration region 11 is connected to the peripheral edge of the high concentration region 10. This allows the low concentration region 11 to be electrically connected to the high concentration region 10.
  • the low concentration region 11 is connected to the high concentration region 10 at the outer peripheral region 9. It is preferable that the outer edge of the low concentration region 11 is exposed from at least one of the first to fourth side surfaces 5A to 5D. In this embodiment, the outer edge of the low concentration region 11 is exposed from all of the first to fourth side surfaces 5A to 5D.
  • the low concentration region 11 crosses the depth position of the bottom of the high concentration region 10 in the thickness direction and is formed deeper than the high concentration region 10.
  • the low concentration region 11 has a bottom located lower (towards the second main surface 4) than the bottom of the high concentration region 10.
  • the low concentration region 11 forms a region boundary portion 12 with the high concentration region 10 that extends in the thickness direction of the chip 2 (see Figure 10).
  • the region boundary portion 12 is formed with a gap from the bottom of the low concentration region 11 towards the first main surface 3.
  • the region boundary 12 is formed approximately perpendicular to the first main surface 3. Specifically, the region boundary 12 has an upper end, a lower end, and an extension. The upper end is located on the first main surface 3 side. The lower end is located on the second main surface 4 side, and is located approximately on the same straight line as the upper end in the thickness direction. The extension extends approximately perpendicular to the first main surface 3 between the upper end and the lower end.
  • the low concentration region 11 is formed in the second semiconductor layer 7.
  • the low concentration region 11 preferably crosses the middle depth position of the second semiconductor layer 7 in the thickness direction.
  • the thickness of the low concentration region 11 is preferably at least half the thickness of the second semiconductor layer 7.
  • the low concentration region 11 is formed in the second semiconductor layer 7 throughout the entire thickness range between the first main surface 3 and the bottom of the second semiconductor layer 7 (first semiconductor layer 6), and is connected to the first semiconductor layer 6.
  • the high concentration region 10 may be formed by introducing an n-type impurity into a surface layer of the second semiconductor layer 7 (e.g., an n-type second semiconductor layer 7).
  • the low concentration region 11 is formed using the n-type second semiconductor layer 7, and has a thickness corresponding to the thickness of the second semiconductor layer 7.
  • the semiconductor device 1A has a single layer structure consisting of the low concentration region 11 in the peripheral portion (peripheral region 9) of the second semiconductor layer 7.
  • the semiconductor device 1A includes an n-type inner low concentration region 13 formed in a region below the high concentration region 10 in the surface layer portion of the first main surface 3.
  • the inner low concentration region 13 may be referred to as a "third region,” a “third drift region,” a “second low concentration drift region,” or the like.
  • the third impurity concentration may be 1 ⁇ 10 15 cm -3 or more and 5 ⁇ 10 16 cm -3 or less.
  • the inner low concentration region 13 is formed on the inner side of the chip 2 relative to the low concentration region 11. Specifically, the inner low concentration region 13 is formed in a region below the high concentration region 10 in the active region 8. The inner low concentration region 13 is formed as a high resistance region (second high resistance region) in the active region 8 that has a higher resistance value than the high concentration region 10. The inner low concentration region 13 extends in a layer shape along the high concentration region 10 and is connected to the high concentration region 10 in the thickness direction. As a result, the inner low concentration region 13 is electrically connected to the high concentration region 10.
  • the inner low concentration region 13 is preferably formed over the entire region below the high concentration region 10 and connected to the entire high concentration region 10 in the thickness direction. In this embodiment, the inner low concentration region 13 is formed over the entire active region 8. The inner low concentration region 13 is further extended from the active region 8 to the peripheral region 9, where it is connected to the region on the bottom side of the low concentration region 11.
  • the inner low concentration region 13 is electrically connected to the low concentration region 11.
  • the inner low concentration region 13 is pulled out from the active region 8 to the outer peripheral region 9 along the entire periphery, and is connected to the inner edge of the low concentration region 11 along the entire periphery.
  • the third impurity concentration of the inner low concentration region 13 is approximately equal to the second impurity concentration of the region on the bottom side of the low concentration region 11.
  • the inner low concentration region 13 is formed in the second semiconductor layer 7.
  • the inner low concentration region 13 is formed in the second semiconductor layer 7 throughout the entire thickness range between the high concentration region 10 and the bottom of the second semiconductor layer 7 (the first semiconductor layer 6), and is connected to the first semiconductor layer 6.
  • the inner low concentration region 13 may be formed by introducing an n-type impurity into a surface layer of the second semiconductor layer 7 (e.g., an n-type second semiconductor layer 7).
  • the inner low concentration region 13 is formed by utilizing a part (a region on the bottom side) of the n-type second semiconductor layer 7.
  • the semiconductor device 1A has a multilayer structure including a high concentration region 10 and an inner low concentration region 13 in the inner part (active region 8) of the second semiconductor layer 7.
  • the semiconductor device 1A includes an n-type base region 14 formed in a region (surface layer portion) on the second main surface 4 side in the chip 2.
  • the base region 14 may be referred to as a "fourth region,” a “drain region,” or the like.
  • the base region 14 has a fourth impurity concentration higher than the first impurity concentration of the high concentration region 10.
  • the fourth impurity concentration may be not less than 5 ⁇ 10 17 cm -3 and not more than 3 ⁇ 10 19 cm -3 .
  • the base region 14 is formed in the region below the high concentration region 10 on the inner side of the chip 2 and is electrically connected to the high concentration region 10.
  • the base region 14 is extended from the region below the high concentration region 10 to the peripheral side of the chip 2 and has a portion located in the region below the low concentration region 11.
  • the base region 14 is electrically connected to the low concentration region 11 on the peripheral side of the chip 2.
  • the base region 14 has a portion that is electrically connected to the high concentration region 10 in the active region 8.
  • the base region 14 is connected to the inner low concentration region 13 in the active region 8, and is electrically connected to the high concentration region 10 via the inner low concentration region 13.
  • the base region 14 also has a portion that is drawn out from the active region 8 to the peripheral region 9, and is electrically connected to the low concentration region 11 in the peripheral region 9.
  • the base region 14 is formed as a low resistance region that has a relatively low resistance value in both the active region 8 and the peripheral region 9.
  • the base region 14 extends in a layer shape along the second main surface 4, is exposed from the second main surface 4 of the chip 2, and is exposed from a portion of the first side surfaces 5A to 5D of the chip 2.
  • the base region 14 has a thickness greater than the thickness of the high concentration region 10, the thickness of the low concentration region 11, and the thickness of the inner low concentration region 13.
  • the base region 14 is formed in the first semiconductor layer 6.
  • the base region 14 is formed throughout the thickness range between the lower end (second main surface 4) of the first semiconductor layer 6 and the upper end (second semiconductor layer 7) of the first semiconductor layer 6, and is connected to the second semiconductor layer 7.
  • the base region 14 is formed using the n-type first semiconductor layer 6, and has a thickness corresponding to the thickness of the first semiconductor layer 6.
  • the semiconductor device 1A includes a plurality of p-type body regions 20 formed in the surface layer of the first main surface 3 in the active region 8.
  • the plurality of body regions 20 are formed in the surface layer of the high concentration region 10.
  • a source potential is applied to the plurality of body regions 20 as a low potential (second potential) different from a high potential (first potential).
  • the multiple body regions 20 are arranged at intervals in the first direction X, and are each formed in a band shape extending in the second direction Y. In other words, the multiple body regions 20 are arranged in stripes extending in the second direction Y. Furthermore, the extension direction of the multiple body regions 20 coincides with the off-direction of the SiC single crystal.
  • the multiple body regions 20 are formed at intervals from the bottom of the high concentration region 10 toward the first main surface 3, and face the inner low concentration region 13 (base region 14) across a portion of the high concentration region 10. It is preferable that the multiple body regions 20 are formed at intervals from the middle of the high concentration region 10 toward the first main surface 3. Of course, the multiple body regions 20 may cross the depth position of the middle of the high concentration region 10 in the thickness direction. The multiple body regions 20 are exposed from the first main surface 3.
  • the body regions 20 may each have a width of 1 ⁇ m or more and 10 ⁇ m or less.
  • the width of the body regions 20 may have a value that belongs to at least one of the following ranges: 1 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 5 ⁇ m or less, 5 ⁇ m or more and 6 ⁇ m or less, 6 ⁇ m or more and 7 ⁇ m or less, 7 ⁇ m or more and 8 ⁇ m or less, 8 ⁇ m or more and 9 ⁇ m or less, and 9 ⁇ m or more and 10 ⁇ m or less.
  • the width of the body regions 20 is preferably 2 ⁇ m or more and 5 ⁇ m or less.
  • the body regions 20 may each have a thickness (depth) of 0.1 ⁇ m or more and 2.5 ⁇ m or less.
  • the thickness of the body regions 20 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, and 2 ⁇ m or more and 2.5 ⁇ m or less.
  • the thickness of the body regions 20 is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • the multiple body regions 20 each form a pn junction (pn junction diode: body diode) with the high concentration region 10.
  • the multiple body regions 20 spread a depletion layer into the high concentration region 10 when a reverse bias voltage is applied to the pn junction.
  • the depletion layer spreads from the high concentration region 10 side toward the low concentration region 11 side in the horizontal direction along the first main surface 3.
  • the range of the depletion layer is expanded toward the peripheral side of the chip 2 by the low concentration region 11.
  • a lateral breakdown voltage is required on the peripheral side (outer peripheral region 9 side) of the chip 2.
  • the low concentration region 11 increases the breakdown voltage on the peripheral side (outer peripheral region 9 side) of the chip 2, improving the breakdown voltage.
  • the depletion layer extends from the high concentration region 10 to the inner low concentration region 13 in the thickness direction of the chip 2.
  • the range of the depletion layer is expanded by the inner low concentration region 13.
  • a vertical breakdown voltage is required on the inner side (active region 8) of the chip 2.
  • the inner low concentration region 13 increases the breakdown voltage on the inner side (active region 8 side) of the chip 2, improving the breakdown voltage.
  • the semiconductor device 1A includes a p-type outer body region 21 formed in the surface layer of the first main surface 3 in the peripheral region 9.
  • the outer body region 21 is formed in either or both of the surface layer of the high concentration region 10 and the surface layer of the low concentration region 11. In this embodiment, the outer body region 21 is formed in the surface layer of the high concentration region 10.
  • the outer body region 21 preferably has a p-type impurity concentration that is approximately equal to the p-type impurity concentration of the body region 20.
  • the p-type impurity concentration of the outer body region 21 may be less than the p-type impurity concentration of the body region 20, or may be higher than the p-type impurity concentration of the body region 20.
  • the outer body region 21 is formed on the surface layer of the high concentration region 10 at a distance from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D) toward the active region 8, and extends in a band shape along the active region 8.
  • the outer body region 21 has a portion that extends in a band shape in the first direction X and a portion that extends in a band shape in the second direction Y in a plan view, and divides the active region 8 from multiple directions.
  • the outer body region 21 surrounds the active region 8 in a plan view and is partitioned into a polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3.
  • the outer body region 21 forms the boundary between the active region 8 and the peripheral region 9.
  • the outer body region 21 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quadrant arc shape) in a plan view (see FIG. 6).
  • the outer body region 21 has an inner edge on the active region 8 side and an outer edge on the peripheral side of the first main surface 3.
  • the inner edge of the outer body region 21 is connected to the multiple body regions 20 in a portion extending in the first direction X.
  • the outer body region 21 is electrically connected to the multiple body regions 20 in the surface portion of the high concentration region 10.
  • the outer edge of the outer body region 21 is formed at a distance from the periphery of the high concentration region 10 toward the active region 8. In other words, the outer edge of the outer body region 21 is formed at a distance from the low concentration region 11. The entire outer body region 21 is located within the high concentration region 10. The edge of the outer body region 21 is located in the surface layer of the high concentration region 10.
  • the outer body region 21 preferably has a width greater than the width of the body region 20.
  • the width of the body region 20 is the width in a direction perpendicular to the extension direction (i.e., the first direction X).
  • the width of the outer body region 21 is the width in a direction perpendicular to the extension direction.
  • the width of the outer body region 21 may be approximately equal to the width of the body region 20, or may be less than the thickness of the body region 20.
  • the ratio of the width of the outer body region 21 to the width of the body region 20 may be 1 or more and 50 or less.
  • the width ratio may have a value that belongs to at least one of the following ranges: 1 or more and 10 or less, 10 or more and 20 or less, 20 or more and 30 or less, 30 or more and 40 or less, and 40 or more and 50 or less. It is preferable that the width ratio is 10 or more. It is preferable that the width ratio is 20 or more and 40 or less.
  • the outer body region 21 is formed at a distance from the bottom of the high concentration region 10 toward the first main surface 3, and faces the inner low concentration region 13 (base region 14) across a portion of the high concentration region 10. It is preferable that the outer body region 21 is formed at a distance from the middle of the high concentration region 10 toward the first main surface 3. Of course, the outer body region 21 may cross the depth position of the middle of the high concentration region 10 in the thickness direction. The outer body region 21 is exposed from the first main surface 3.
  • the outer body region 21 has a thickness (depth) that is approximately equal to the thickness (depth) of the body region 20.
  • the thickness of the outer body region 21 may be less than the thickness of the body region 20, or may be greater than the thickness of the body region 20.
  • the outer body region 21 forms a pn junction (pn junction diode: body diode) with the high concentration region 10.
  • the outer body region 21 expands a depletion layer into the high concentration region 10 when a reverse bias voltage is applied to the pn junction.
  • the depletion layer of the outer body region 21 is integrated with the depletion layers of the multiple body regions 20 and expands in the horizontal and thickness directions.
  • the range of the depletion layer of the outer body region 21 is expanded toward the peripheral side of the chip 2 by the low concentration region 11. This improves the breakdown voltage on the peripheral side (outer peripheral region 9) of the chip 2.
  • the depletion layer of the outer body region 21 extends from the high concentration region 10 to the inner low concentration region 13 in the thickness direction of the chip 2.
  • the range of the depletion layer of the outer body region 21 is expanded by the inner low concentration region 13. This improves the breakdown voltage on the inner side (active region 8 side) of the chip 2.
  • the semiconductor device 1A includes a plurality of n-type surface drift regions 22 formed in a surface portion of the first main surface 3.
  • the surface drift regions 22 are each partitioned into regions between a plurality of body regions 20 adjacent in the first direction X in the surface portion of the high concentration region 10.
  • the surface drift regions 22 are each partitioned by a plurality of body regions 20 and an outer body region 21 in the surface portion of the high concentration region 10.
  • each of the multiple surface drift regions 22 is made up of a portion of the high concentration region 10.
  • the multiple surface drift regions 22 may have an n-type impurity concentration higher than the n-type impurity concentration of the high concentration region 10, or may have an n-type impurity concentration lower than the n-type impurity concentration of the high concentration region 10.
  • the multiple surface drift regions 22 are arranged at intervals in the first direction X, and are each formed in a band shape extending in the second direction Y. In other words, the multiple surface drift regions 22 are formed in stripes extending in the second direction Y.
  • the multiple surface drift regions 22 form an n-type (pnp-type) JFET structure together with the multiple body regions 20 located on both sides.
  • the JFET resistance component of the JFET structure is reduced by the high concentration region 10.
  • the multiple surface drift regions 22 may have a width of 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the width of the surface drift regions 22 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the semiconductor device 1A includes a plurality of n-type source regions 23, 24 formed in the surface layer of each of the body regions 20.
  • the source regions 23, 24 have an n-type impurity concentration higher than the n-type impurity concentration of the high concentration region 10.
  • a source potential is applied to the source regions 23, 24.
  • the multiple source regions 23, 24 include a first source region 23 located on one side (third side surface 5C side) in the first direction X and a second source region 24 located on the other side (fourth side surface 5D side) in the first direction X in the surface layer portion of each body region 20.
  • one first source region 23 is formed on one end side of the body region 20 and one second source region 24 is formed on the other end side of the body region 20 in the first direction X.
  • the first source region 23 is formed at a distance from one end of the body region 20 to the other end, and extends in a band shape along the extension direction of the body region 20.
  • the first source region 23 is formed at a distance from the outer body region 21 in the second direction Y. In other words, the first source region 23 is not formed in the outer body region 21.
  • the first source region 23 is formed at a distance from the bottom of the body region 20 toward the first main surface 3, and faces the high concentration region 10 with a part of the body region 20 in between.
  • the second source region 24 is formed at a distance from the first source region 23 to the other end side of the body region 20.
  • the second source region 24 is formed at a distance from the other end of the body region 20 to one end side, and extends in a band shape along the extension direction of the body region 20.
  • the second source region 24 is formed at a distance from the outer body region 21 in the second direction Y. In other words, the second source region 24 is not formed in the outer body region 21.
  • the second source region 24 is formed at a distance from the bottom of the body region 20 to the first main surface 3 side, and faces the high concentration region 10 across a part of the body region 20.
  • each first source region 23 may be formed at intervals in the extension direction of the body region 20. In this case, each first source region 23 may be formed in a strip extending in the second direction Y.
  • the multiple second source regions 24 may be formed at intervals in the extension direction of the body region 20. In this case, each second source region 24 may be formed in a strip extending in the second direction Y.
  • the semiconductor device 1A includes a plurality of p-type contact regions 25 formed in the surface layer of each of the body regions 20 in the active region 8.
  • the contact regions 25 may be referred to as "backgate regions.”
  • a source potential is applied to the contact regions 25.
  • the contact regions 25 have a p-type impurity concentration higher than the p-type impurity concentration of the body regions 20.
  • one contact region 25 is interposed in the region between the first source region 23 and the second source region 24 in the surface portion of the corresponding body region 20.
  • the contact region 25 extends in a strip shape along the extension direction of the body region 20 (source regions 23, 24).
  • the contact region 25 is formed at a distance from the outer body region 21 in the second direction Y. In other words, the contact region 25 is not formed in the outer body region 21.
  • the contact region 25 is formed at a distance from the bottom of the body region 20 toward the first main surface 3, and faces the high concentration region 10 across a portion of the body region 20.
  • each contact region 25 may be formed at intervals in the extension direction of the body region 20.
  • each contact region 25 may be formed in a strip shape extending in the second direction Y.
  • the semiconductor device 1A includes a plurality of p-type channel regions 26, 27 formed in a surface layer portion of the first main surface 3.
  • the plurality of channel regions 26, 27 are partitioned in the surface layer portions of the plurality of body regions 20 between the ends of the plurality of body regions 20 (the plurality of surface drift regions 22) and the peripheries of the plurality of source regions 23, 24.
  • the plurality of channel regions 26, 27 are arranged at intervals in the first direction X and are each formed in a band shape extending in the second direction Y.
  • the plurality of channel regions 26, 27 are arranged in stripes extending in the second direction Y.
  • the multiple channel regions 26, 27 include multiple first channel regions 26 and multiple second channel regions 27.
  • the multiple first channel regions 26 are each partitioned into a region between one end of the multiple body regions 20 (surface drift region 22) and the multiple first source regions 23, forming a current path that extends horizontally.
  • the multiple second channel regions 27 are each partitioned into a region between the other end of the multiple body regions 20 (surface drift region 22) and the multiple second source regions 24, forming a current path that extends horizontally.
  • the semiconductor device 1A includes a plurality of planar electrode type gate structures 30 arranged on the first main surface 3 in the active region 8.
  • the plurality of gate structures 30 are arranged at intervals in the first direction X, and are each formed in a band shape extending in the second direction Y. In other words, the plurality of gate structures 30 are arranged in stripes extending in the second direction Y. Furthermore, the extension direction of the plurality of gate structures 30 coincides with the off-direction of the SiC single crystal.
  • Each gate structure 30 is disposed over at least one channel region 26, 27. In this embodiment, each gate structure 30 is disposed across one surface drift region 22 and across two adjacent body regions 20, covering multiple channel regions 26, 27.
  • each gate structure 30 is disposed so as to straddle the first source region 23 on one body region 20 side and the second source region 24 on the other body region 20 side, and covers the surface drift region 22, the first source region 23, the second source region 24, the first channel region 26, and the second channel region 27.
  • the gate structure 30 has a laminated structure including an insulating film 31 and a gate electrode 32.
  • the insulating film 31 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the insulating film 31 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the insulating film 31 includes a silicon oxide film made of an oxide of the chip 2.
  • the insulating film 31 covers the first main surface 3 in a film-like shape and is disposed on at least one of the channel regions 26, 27. In this embodiment, the insulating film 31 is disposed so as to cross one surface drift region 22 and straddle two adjacent body regions 20, covering the multiple channel regions 26, 27.
  • the insulating film 31 is disposed so as to straddle the first source region 23 on one body region 20 side and the second source region 24 on the other body region 20 side, and covers the surface drift region 22, the first source region 23, the second source region 24, the first channel region 26, and the second channel region 27.
  • the insulating film 31 partially covers the first source region 23 at a distance from the contact region 25, and exposes a part of the first source region 23 and the contact region 25 from the first main surface 3.
  • the insulating film 31 partially covers the second source region 24 at a distance from the contact region 25, and exposes a part of the second source region 24 and the contact region 25 from the first main surface 3.
  • the insulating film 31 may have a thickness of 10 nm or more and 150 nm or less.
  • the thickness of the insulating film 31 may have a value that belongs to at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less.
  • the thickness of the insulating film 31 is preferably 25 nm or more and 75 nm or less.
  • the gate electrode 32 is disposed on the insulating film 31 and faces at least one of the channel regions 26, 27 across the insulating film 31.
  • a gate potential is applied to the gate electrode 32 as a control potential.
  • the gate electrode 32 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon.
  • the conductivity type of the gate electrode 32 is adjusted according to the gate threshold voltage to be achieved.
  • the gate electrode 32 is formed in a strip shape extending in the second direction Y. In this embodiment, the gate electrode 32 is formed spaced inward from both ends of the insulating film 31 in the first direction X, exposing both ends of the insulating film 31.
  • the gate electrode 32 is disposed on the insulating film 31 so as to cross one surface drift region 22 and straddle two adjacent body regions 20, and faces the multiple channel regions 26, 27 across the insulating film 31.
  • the gate electrode 32 is disposed so as to straddle the first source region 23 on one body region 20 side and the second source region 24 on the other body region 20 side, and faces the surface drift region 22, the first source region 23, the second source region 24, the first channel region 26, and the second channel region 27 across the insulating film 31.
  • the gate electrode 32 controls the inversion and non-inversion of the channel regions 26, 27 in response to the gate potential.
  • a gate potential is applied to the gate electrode 32, the channel regions 26, 27 are turned on, and a drain current flows between the high concentration region 10 and the source regions 23, 24 via the channel regions 26, 27 (body region 20).
  • a planar gate type transistor structure Tr including the high concentration region 10 is formed in the inner part (active region 8) of the chip 2.
  • the semiconductor device 1A includes a p-type termination region 40 formed on the first main surface 3 in the peripheral region 9.
  • the termination region 40 may also be referred to as a "well region", a “termination well region”, etc.
  • the termination region 40 is formed in either or both of the surface layer portion of the high concentration region 10 and the surface layer portion of the low concentration region 11 in the peripheral region 9. In this embodiment, the termination region 40 is formed in the surface layer portion of the high concentration region 10 in the peripheral region 9.
  • the termination region 40 may have a p-type impurity concentration different from the p-type impurity concentration of the body region 20.
  • the p-type impurity concentration of the termination region 40 may be higher than the p-type impurity concentration of the body region 20.
  • the p-type impurity concentration of the termination region 40 may be lower than the p-type impurity concentration of the body region 20.
  • the p-type impurity concentration of the termination region 40 may be approximately equal to the p-type impurity concentration of the body region 20.
  • the termination region 40 may have a p-type impurity concentration different from the p-type impurity concentration of the outer body region 21.
  • the p-type impurity concentration of the termination region 40 may be higher than the p-type impurity concentration of the outer body region 21.
  • the p-type impurity concentration of the termination region 40 may be lower than the p-type impurity concentration of the outer body region 21.
  • the p-type impurity concentration of the termination region 40 may be approximately equal to the p-type impurity concentration of the outer body region 21.
  • the termination region 40 is spaced inward from the periphery of the first main surface 3 and is formed in the region between the periphery of the first main surface 3 and the outer body region 21.
  • the termination region 40 extends in a band shape along the outer body region 21 in a plan view.
  • the termination region 40 has a portion that extends in a band shape in the first direction X and a portion that extends in a band shape in the second direction Y in a plan view, and divides the active region 8 from multiple directions.
  • the termination region 40 surrounds the outer body region 21 in a plan view and is partitioned into a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3.
  • the termination region 40 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quadrant arc shape) in a plan view (see FIG. 6).
  • the termination region 40 is formed at a distance from the bottom of the high concentration region 10 toward the first main surface 3, and faces the inner low concentration region 13 across a part of the high concentration region 10.
  • the termination region 40 is preferably formed at a distance from the middle of the high concentration region 10 toward the first main surface 3. Of course, the termination region 40 may cross the depth position of the middle of the high concentration region 10 in the thickness direction.
  • the termination region 40 may have a thickness (depth) approximately equal to the thickness (depth) of the outer body region 21.
  • the thickness of the termination region 40 may be greater than the thickness of the outer body region 21, or may be less than the thickness of the outer body region 21.
  • the termination region 40 has an inner edge on the active region 8 side and an outer edge on the peripheral side of the first main surface 3.
  • the inner edge of the termination region 40 is connected to the outer edge of the outer body region 21 at the surface layer of the high concentration region 10. This means that the termination region 40 is electrically connected to the outer body region 21.
  • the termination region 40 is electrically connected to multiple body regions 20 via the outer body region 21.
  • the inner edge of the termination region 40 is connected to the outer edge of the outer body region 21 around the entire periphery.
  • the termination region 40 may be considered as part of the outer body region 21 (the pull-out portion).
  • the termination region 40 (inner edge) has an overlap region 41 that overlaps the outer edge of the outer body region 21 at the surface portion of the high concentration region 10.
  • the overlap region 41 is a high concentration region that includes the outer edge of the outer body region 21 and the inner edge of the termination region 40.
  • the overlap region 41 includes both the p-type impurities of the outer body region 21 and the p-type impurities of the termination region 40, and has a p-type impurity concentration that is higher than both the p-type impurity concentration of the outer body region 21 and the p-type impurity concentration of the termination region 40.
  • the p-type impurity concentration of the overlap region 41 is higher than the p-type impurity concentration of the body region 20.
  • the p-type impurity concentration of the overlap region 41 may be lower than the p-type impurity concentration of the contact region 25.
  • the p-type impurity concentration of the overlap region 41 may be higher than the p-type impurity concentration of the contact region 25.
  • the overlap region 41 extends in a band shape along the outer body region 21 in a plan view.
  • the overlap region 41 has a portion that extends in a band shape in the first direction X and a portion that extends in a band shape in the second direction Y in a plan view, and defines the active region 8 from multiple directions.
  • the overlap region 41 is defined in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3.
  • the overlap region 41 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a planar view in an arc shape (preferably a quarter arc shape) (see FIG. 6). It is preferable that the width of the overlap region 41 is greater than the width of the body region 20. Of course, the width of the overlap region 41 may be less than the width of the body region 20.
  • the termination region 40 forms a pn junction (pn junction diode: body diode) with the high concentration region 10.
  • the termination region 40 expands a depletion layer into the high concentration region 10 when a reverse bias voltage is applied to the pn junction.
  • the depletion layer in the termination region 40 is integrated with the depletion layers in the multiple body regions 20 and the depletion layer in the outer body region 21, and expands in the horizontal and thickness directions.
  • the range of the depletion layer in the termination region 40 is expanded toward the peripheral side of the chip 2 by the low concentration region 11. This improves the breakdown voltage on the peripheral side (outer peripheral region 9) of the chip 2.
  • the depletion layer in the termination region 40 extends from the high concentration region 10 to the inner low concentration region 13 in the thickness direction of the chip 2.
  • the range of the depletion layer in the termination region 40 is also extended by the inner low concentration region 13 in the peripheral region 9. This improves the breakdown voltage on the peripheral edge (peripheral region 9) side of the chip 2.
  • the outer edge of the termination region 40 preferably crosses the periphery of the high concentration region 10 and is located in the low concentration region 11.
  • the termination region 40 is preferably located in the surface layer of the low concentration region 11 in the peripheral region 9 and has a portion (outer edge) that forms a pn junction with the low concentration region 11 (see FIG. 10).
  • the edge of the outer edge of the termination region 40 is located in the surface layer of the low concentration region 11.
  • the depletion layer extends directly from the termination region 40 to the low concentration region 11. Therefore, the range of the depletion layer is appropriately expanded in the peripheral portion (outer peripheral region 9) of the chip 2.
  • the outer edge of the termination region 40 may be formed at a distance from the peripheral portion of the high concentration region 10 toward the active region 8, and may be located within the high concentration region 10.
  • the semiconductor device 1A may have a relatively high-concentration p-type well region (46) instead of the overlap region 41.
  • the well region (46) has a p-type impurity concentration higher than both the p-type impurity concentration of the outer body region 21 and the p-type impurity concentration of the termination region 40.
  • the p-type impurity concentration of the well region (46) is higher than the p-type impurity concentration of the body region 20.
  • the p-type impurity concentration of the well region (46) may be approximately equal to the p-type impurity concentration of the contact region 25.
  • the p-type impurity concentration of the well region (46) may be less than the p-type impurity concentration of the contact region 25, or may be higher than the p-type impurity concentration of the contact region 25.
  • the well region (46) may be formed in either or both of the surface layer of the outer body region 21 and the surface layer of the termination region 40. Such a configuration is effective when the termination region 40 has a p-type impurity concentration approximately equal to the p-type impurity concentration of the outer body region 21 and is formed as part of the outer body region 21 (the pull-out portion).
  • the semiconductor device 1A includes at least one p-type field region 42 formed in the surface layer of the first main surface 3 in the peripheral region 9.
  • the multiple field regions 42 may be formed in an electrically floating state.
  • the multiple field regions 42 may be fixed to the source potential.
  • the number of field regions 42 is arbitrary.
  • the number of field regions 42 may be 1 or more and 20 or less.
  • the number of field regions 42 may have a value that belongs to at least one of the following ranges: 1 or more and 5 or less, 5 or more and 10 or less, 10 or more and 15 or less, and 15 or more and 20 or less.
  • the number of field regions 42 is typically 1 or more and 8 or less.
  • semiconductor device 1A includes three field regions 42.
  • the multiple field regions 42 are formed in the surface layer of the low concentration region 11.
  • the multiple field regions 42 are formed in the region between the periphery of the first main surface 3 and the active region 8, spaced inward from the periphery of the first main surface 3.
  • the multiple field regions 42 are formed in the region between the periphery of the first main surface 3 and the outer body region 21.
  • the multiple field regions 42 are arranged in the region between the periphery of the first main surface 3 and the high concentration region 10, with a gap between them on the periphery side of the first main surface 3 from the high concentration region 10. More specifically, the multiple field regions 42 are arranged in the region between the periphery of the first main surface 3 and the termination region 40, with a gap between them on the periphery side of the first main surface 3 from the termination region 40. In other words, the multiple field regions 42 are not formed in the high concentration region 10.
  • the multiple field regions 42 are formed in a band shape extending along the active region 8 (termination region 40) in a planar view.
  • the multiple field regions 42 each have a portion extending in a band shape in the first direction X and a portion extending in a band shape in the second direction Y.
  • the multiple field regions 42 are formed in a polygonal ring shape (a square ring shape in this embodiment) surrounding the active region 8 (termination region 40) in a planar view.
  • the field regions 42 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape) (see FIG. 6).
  • the edge portions of the field regions 42 are located in the surface layer portion of the low concentration region 11.
  • the field regions 42 are formed at intervals from the bottom of the low concentration region 11 toward the first main surface 3, and face the base region 14 with a portion of the low concentration region 11 in between.
  • the multiple field regions 42 are formed at intervals from the depth position of the bottom of the high concentration region 10 toward the first main surface 3. It is preferable that the multiple field regions 42 are formed at intervals from the depth position of the middle of the high concentration region 10 toward the first main surface 3. Of course, the multiple field regions 42 may cross the depth position of the middle of the high concentration region 10 in the thickness direction.
  • the multiple field regions 42 each form a pn junction (pn junction diode) with the low concentration region 11.
  • the multiple field regions 42 expand the depletion layer toward the low concentration region 11 when a reverse bias voltage is applied.
  • the depletion layer of the multiple field regions 42 merges with the depletion layer of the termination region 40 and expands in the horizontal and thickness directions.
  • the range of the depletion layer of the multiple field regions 42 is expanded by the low concentration region 11. This improves the breakdown voltage on the peripheral side (outer peripheral region 9) of the chip 2.
  • the low concentration region 11 expands the range of the depletion layer, so the number of field regions 42 can be reduced. This reduces the area occupied by the peripheral region 9 on the chip 2, and increases the area occupied by the active region 8 on the chip 2. This improves the electrical characteristics of the transistor structure Tr (device structure) formed in the active region 8. This configuration is also effective in achieving a smaller chip 2.
  • the width, depth, spacing, p-type impurity concentration, etc. of the multiple field regions 42 are arbitrary and can take various values depending on the electric field to be relaxed.
  • the width of the multiple field regions 42 may be approximately constant or may be non-uniform.
  • the width of the multiple field regions 42 may gradually increase toward the peripheral edge side of the first main surface 3.
  • the width of the multiple field regions 42 may gradually decrease toward the peripheral edge side of the first main surface 3.
  • the depth of the multiple field regions 42 may be approximately constant or may be non-uniform.
  • the depth of the multiple field regions 42 may gradually increase toward the peripheral edge side of the first main surface 3.
  • the depth of the multiple field regions 42 may gradually decrease toward the peripheral edge side of the first main surface 3.
  • the multiple field regions 42 may have a relatively shallow portion and a deep portion that is deeper than the shallow portion.
  • the shallow portion may be formed on the inner side, and the deep portion may be formed on the peripheral edge side.
  • the shallow portion may be formed on the peripheral edge side, and the deep portion may be formed on the inner side.
  • the spacing between the multiple field regions 42 may be approximately constant or may be non-uniform.
  • the spacing between the multiple field regions 42 may gradually increase toward the peripheral edge of the first main surface 3.
  • the spacing between the multiple field regions 42 may gradually decrease toward the peripheral edge of the first main surface 3.
  • the p-type impurity concentration of the multiple field regions 42 may be approximately constant or may be non-uniform.
  • the p-type impurity concentration of the multiple field regions 42 may gradually increase toward the peripheral edge side of the first main surface 3.
  • the p-type impurity concentration of the multiple field regions 42 may gradually decrease toward the peripheral edge side of the first main surface 3.
  • the p-type impurity concentration of the multiple field regions 42 may be approximately equal to the p-type impurity concentration of the body region 20 (outer body region 21).
  • the p-type impurity concentration of the multiple field regions 42 may be higher than the p-type impurity concentration of the body region 20 (outer body region 21), or may be lower than the p-type impurity concentration of the body region 20 (outer body region 21).
  • the p-type impurity concentration of the multiple field regions 42 may be approximately equal to the p-type impurity concentration of the termination region 40.
  • the p-type impurity concentration of the multiple field regions 42 may be higher than the p-type impurity concentration of the termination region 40, or may be lower than the p-type impurity concentration of the termination region 40.
  • the semiconductor device 1A includes a peripheral insulating film 43 that covers the first main surface 3 in the peripheral region 9.
  • the peripheral insulating film 43 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the peripheral insulating film 43 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the peripheral insulating film 43 includes a silicon oxide film made of an oxide of the chip 2.
  • the peripheral insulating film 43 is preferably made of the same type of insulating material as the insulating film 31.
  • the peripheral insulating film 43 preferably has a thickness approximately equal to that of the insulating film 31.
  • the peripheral insulating film 43 covers the first main surface 3 in the peripheral region 9 in the form of a film.
  • the peripheral insulating film 43 collectively covers the high concentration region 10, the low concentration region 11, the outer body region 21, the termination region 40, and the multiple field regions 42.
  • the peripheral insulating film 43 is connected to the multiple insulating films 31 on the active region 8 side. Specifically, the peripheral insulating film 43 is formed integrally with the multiple insulating films 31, and forms a single insulating film together with the multiple insulating films 31.
  • the semiconductor device 1A includes a gate wiring 44 arranged on the first main surface 3 in the peripheral region 9.
  • the gate wiring 44 is selectively routed on the first main surface 3 and has a portion that extends in a different direction from the multiple gate electrodes 32.
  • the gate wiring 44 is connected to the multiple gate electrodes 32 and applies a gate signal to the multiple gate electrodes 32.
  • the gate wiring 44 may be referred to as a "second gate electrode" or the like.
  • the gate wiring 44 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. It is preferable that the gate wiring 44 has the same conductivity type as the gate electrode 32.
  • the gate wiring 44 is arranged on the peripheral insulating film 43 at a distance from the periphery of the first main surface 3 toward the active region 8 in the peripheral region 9. Specifically, the gate wiring 44 is arranged at a distance from the low concentration region 11 toward the active region 8 in a plan view. In this embodiment, the gate wiring 44 is arranged at a distance from the termination region 40 toward the active region 8, and is arranged on the portion of the peripheral insulating film 43 that covers the outer body region 21.
  • the gate wiring 44 faces the outer body region 21 across the peripheral insulating film 43.
  • the gate wiring 44 also faces the high concentration region 10 (inner low concentration region 13) in the stacking direction, and does not face the low concentration region 11 in the stacking direction.
  • the gate wiring 44 may also partially face the termination region 40 in the stacking direction.
  • the gate wiring 44 extends in a band shape along the active region 8 in a plan view.
  • the gate wiring 44 has a portion that extends in a band shape in the first direction X and a portion that extends in a band shape in the second direction Y in a plan view, and divides the active region 8 from multiple directions.
  • the gate wiring 44 surrounds the active region 8 in a plan view and is divided into a polygonal ring shape (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3.
  • the gate wiring 44 may be either ended or endless.
  • the gate wiring 44 extends in a strip shape (ring shape in this embodiment) along the outer body region 21 in a plan view, and faces the outer body region 21 across the outer insulating film 43 in the stacking direction over the entire extension direction.
  • the gate wiring 44 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quarter arc shape) in a plan view (see FIG. 6).
  • the gate wiring 44 is formed narrower than the outer body region 21 in a plan view, and is disposed above the outer body region 21 at a distance from the inner and outer edges of the outer body region 21.
  • the multiple gate electrodes 32 are extended up to above the outer body region 21, and the gate wiring 44 is connected to the multiple gate electrodes 32 above the outer body region 21.
  • the thickness of the gate wiring 44 is preferably approximately equal to the thickness of the gate electrode 32.
  • the width of the gate wiring 44 is preferably greater than the width of the gate electrode 32.
  • the width of the gate wiring 44 is the width in a direction perpendicular to the extension direction.
  • the ratio of the width of the gate wiring 44 to the width of the gate electrode 32 may be 1 or more and 50 or less.
  • the width ratio may have a value belonging to at least one of the ranges of 1 to 10, 10 to 20, 20 to 30, 30 to 40, and 40 to 50.
  • the width ratio may be 5 or more.
  • the width ratio may be 20 to 40.
  • the width of the gate wiring 44 may be less than or equal to the width of the gate electrode 32.
  • the width of the gate wiring 44 may be greater than the width of the outer body region 21.
  • the semiconductor device 1A includes an insulating interlayer film 50 that covers the first main surface 3.
  • the interlayer film 50 may also be called an "interlayer insulating film,” “intermediate insulating film,” or the like.
  • the interlayer film 50 has an insulating surface 51 that extends along the first main surface 3.
  • the interlayer film 50 collectively covers the active region 8 and the peripheral region 9 on the first main surface 3.
  • the interlayer film 50 covers the multiple gate structures 30 in the active region 8. In the peripheral region 9, the interlayer film 50 collectively covers the high concentration region 10, low concentration region 11, outer body region 21, termination region 40, and multiple field regions 42, sandwiching the peripheral insulating film 43 therebetween.
  • the interlayer film 50 covers the gate wiring 44 in the peripheral region 9.
  • the interlayer film 50 is continuous with the first to fourth side surfaces 5A to 5D.
  • the interlayer film 50 is formed at a distance inward from the first to fourth side surfaces 5A to 5D, and may expose the peripheral portion (low concentration region 11) of the first main surface 3.
  • the interlayer film 50 has a layered structure including a first oxide film 52 (first insulating film) and a second oxide film 53 (second insulating film) that are layered in this order from the first main surface 3 side. That is, the interlayer film 50 has an insulating surface 51 formed by the second oxide film 53.
  • the first oxide film 52 has a single layer structure made of a silicon oxide film with no added impurities.
  • the first oxide film 52 may be referred to as an NSG film (Nondoped Silicate Glass film).
  • the first oxide film 52 has a thickness less than the thickness of the gate electrode 32. Of course, the thickness of the first oxide film 52 may be greater than the thickness of the gate electrode 32.
  • the first oxide film 52 collectively covers the active region 8 and the peripheral region 9.
  • the first oxide film 52 collectively covers the multiple gate structures 30 in the active region 8.
  • the first oxide film 52 covers both the insulating film 31 and the gate electrode 32 of each gate structure 30 in a film-like manner.
  • the first oxide film 52 has a portion that covers the insulating film 31 (first main surface 3) in a film-like manner along the horizontal direction.
  • the first oxide film 52 covers the insulating film 31 with a gap from the height position of the electrode surface (upper end) of the gate electrode 32 toward the insulating film 31.
  • the first oxide film 52 has a portion that extends in a film-like manner in the stacking direction along the sidewall of the gate electrode 32.
  • the first oxide film 52 has a portion that covers the electrode surface of the gate electrode 32 in a film-like manner along the horizontal direction.
  • the first oxide film 52 preferably has an arc corner portion that is curved in an arc shape in the portion that covers the corner portion of the gate electrode 32.
  • the arc corner portion may have a center of curvature on the gate electrode 32 side.
  • the first oxide film 52 collectively covers the high concentration region 10, low concentration region 11, outer body region 21, termination region 40, and multiple field regions 42 in the peripheral region 9, sandwiching the peripheral insulating film 43 therebetween.
  • the first oxide film 52 covers the gate wiring 44 in the peripheral region 9.
  • the first oxide film 52 has a portion that covers the peripheral insulating film 43 (first main surface 3) in a film-like manner along the horizontal direction.
  • the first oxide film 52 covers the peripheral insulating film 43 with a gap from the height position of the wiring surface (upper end) of the gate wiring 44 toward the peripheral insulating film 43.
  • the first oxide film 52 has a portion that extends in a film-like manner in the stacking direction along the sidewall of the gate wiring 44.
  • the first oxide film 52 has a portion that covers the wiring surface of the gate wiring 44 in a film-like manner along the horizontal direction.
  • the first oxide film 52 preferably has an arc corner portion that is curved in an arc shape in the portion that covers the corner portion of the gate wiring 44.
  • the arc corner portion may have a center of curvature on the gate wiring 44 side.
  • the second oxide film 53 may have a single layer structure made of a silicon oxide film containing phosphorus, or a multilayer structure including a silicon oxide film containing phosphorus.
  • the silicon oxide film containing phosphorus may contain boron.
  • the silicon oxide film containing phosphorus may be called a PSG film (Phosphorus Silicon Glass film).
  • the silicon oxide film containing both phosphorus and boron may be called a BPSG film (Boron Phosphorus Silicon Glass film).
  • the second oxide film 53 may have a single layer structure made of a PSG film or a BPSG film stacked on the first oxide film 52.
  • the second oxide film 53 may have a layered structure including a PSG film stacked on the first oxide film 52 and a BPSG film stacked on the PSG film.
  • the second oxide film 53 may have a layered structure including a BPSG film stacked on the first oxide film 52 and a PSG film stacked on the BPSG film.
  • the second oxide film 53 has a single-layer structure made of a PSG film, for example.
  • the thickness of the second oxide film 53 may be greater than the thickness of the first oxide film 52.
  • the second oxide film 53 may have a thickness less than the thickness of the first oxide film 52.
  • the thickness of the second oxide film 53 may be greater than the thickness of the gate electrode 32.
  • the second oxide film 53 may have a thickness less than the thickness of the gate electrode 32.
  • the second oxide film 53 covers the first oxide film 52 in a film-like manner, and collectively covers the active region 8 and the peripheral region 9 with the first oxide film 52 in between.
  • the second oxide film 53 collectively covers the multiple gate structures 30 in the active region 8 with the first oxide film 52 in between.
  • the second oxide film 53 covers both the insulating film 31 and the gate electrode 32 in a film-like manner with the first oxide film 52 in between.
  • the second oxide film 53 has a portion that covers the insulating film 31 with the first oxide film 52 sandwiched between them.
  • the second oxide film 53 extends in the lamination direction along the sidewall of the gate electrode 32 in a film shape, and has a portion that covers the sidewall of the gate electrode 32 with the first oxide film 52 sandwiched between them.
  • the second oxide film 53 extends in the horizontal direction along the electrode surface of the gate electrode 32 in a film shape, and has a portion that covers the electrode surface of the gate electrode 32 with the first oxide film 52 sandwiched between them.
  • the second oxide film 53 preferably has an arc corner portion that is curved in an arc shape in the portion that covers the corner of the gate electrode 32.
  • the arc corner portion may have a center of curvature on the gate electrode 32 side.
  • the second oxide film 53 collectively covers the high concentration region 10, low concentration region 11, outer body region 21, termination region 40, and multiple field regions 42 in the peripheral region 9, sandwiching the peripheral insulating film 43 and the first oxide film 52 between them.
  • the second oxide film 53 covers the gate wiring 44 in the peripheral region 9, sandwiching the first oxide film 52 between them.
  • the second oxide film 53 has a portion that covers the outer insulating film 43 with the first oxide film 52 sandwiched between them.
  • the second oxide film 53 extends in the lamination direction along the sidewall of the gate wiring 44 in the form of a film, and has a portion that covers the sidewall of the gate wiring 44 with the first oxide film 52 sandwiched between them.
  • the second oxide film 53 extends in the horizontal direction along the wiring surface of the gate wiring 44 in the form of a film, and has a portion that covers the wiring surface of the gate wiring 44 with the first oxide film 52 sandwiched between them.
  • the second oxide film 53 preferably has an arc corner portion that is curved in an arc shape in the portion that covers the corner of the gate wiring 44.
  • the arc corner portion may have a center of curvature on the gate wiring 44 side.
  • the semiconductor device 1A includes a plurality of source openings 54 formed in the interlayer film 50 in the active region 8.
  • the plurality of source openings 54 are formed in regions to the sides of the plurality of gate electrodes 32 at intervals from the plurality of gate electrodes 32, respectively, and expose the first main surface 3 (chip 2). Specifically, the plurality of source openings 54 penetrate the insulating film 31 and the interlayer film 50 in the regions between the plurality of gate electrodes 32.
  • the multiple source openings 54 penetrate both the first oxide film 52 and the second oxide film 53, and have wall surfaces defined by both the first oxide film 52 and the second oxide film 53.
  • the multiple source openings 54 each have an opening end defined by an arc corner portion of the interlayer film 50.
  • the multiple source openings 54 each expose a corresponding multiple source region 23, 24 and contact region 25.
  • the multiple source openings 54 are formed at intervals in the first direction X, and are each formed in a band shape extending in the second direction Y. That is, the multiple source openings 54 are formed in a stripe shape extending in the second direction Y.
  • the multiple source openings 54 are formed at intervals in the second direction Y from the gate wiring 44. That is, the multiple source openings 54 are formed in a region surrounded by the multiple gate electrodes 32 and the gate wiring 44.
  • the multiple source openings 54 may be formed in a region between two gate structures 30 adjacent in the first direction X. In this case, the multiple source openings 54 may be formed in a line spaced apart in the second direction Y. Furthermore, in this case, each source opening 54 may be formed in a quadrilateral shape (square shape) in a plan view, a rectangular shape extending in the first direction X, a rectangular shape extending in the second direction Y, a hexagonal shape, a circular shape, or the like.
  • the source opening 54 may have a width W of 0.1 ⁇ m or more and 3 ⁇ m or less.
  • the width W of the source opening 54 may have a value belonging to at least one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.25 ⁇ m or less, 1.25 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 1.75 ⁇ m or less, 1.75 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.25 ⁇ m or less, 2.25 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 2.75 ⁇ m or less, and 2.75 ⁇ m or more and 3 ⁇ m or less.
  • the width W of the source opening 54 is preferably 0.2 ⁇ m
  • the source opening 54 may have a depth D of 0.1 ⁇ m or more and 2 ⁇ m or less.
  • the depth D of the source opening 54 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.25 ⁇ m or less, 1.25 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 1.75 ⁇ m or less, and 1.75 ⁇ m or more and 2 ⁇ m or less.
  • the depth D of the source opening 54 is preferably 0.5 ⁇ m or more and 1 ⁇ m or less.
  • the source opening 54 preferably has an aspect ratio D/W of 0.5 to 3.
  • the aspect ratio D/W is defined by the ratio of the depth D of the source opening 54 to the width W of the source opening 54.
  • the aspect ratio D/W may have a value that falls within at least one of the following ranges: 0.5 to 0.75, 0.75 to 1, 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 3.
  • the aspect ratio D/W is preferably greater than 1.
  • the source openings 54 preferably have a depth D greater than their width W, and are each formed in a vertically elongated shape in cross-sectional view. With this configuration, the gate structures 30 are arranged at a narrow pitch.
  • the aspect ratio D/W of the vertically elongated source openings 54 is preferably greater than 1 and equal to or less than 2.
  • the semiconductor device 1A includes a plurality of source recesses 55 formed in the first main surface 3 in the portions exposed from the plurality of source openings 54.
  • the semiconductor device 1A does not necessarily have to have the source recesses 55. Therefore, a configuration that does not have the source recesses 55 may be adopted.
  • the multiple source recesses 55 each have a planar shape that matches the planar shape of the corresponding source opening 54, and are recessed from the first main surface 3 toward the second main surface 4.
  • the multiple source recesses 55 are formed at intervals from the bottoms of the corresponding body regions 20 toward the first main surface 3, exposing the corresponding multiple source regions 23, 24 and contact regions 25.
  • the multiple source recesses 55 are formed at intervals from the bottoms of the corresponding multiple source regions 23, 24 (contact regions 25) toward the first main surface 3.
  • the semiconductor device 1A includes at least one (in this embodiment, multiple) outer openings 56 formed in the interlayer film 50 in the peripheral region 9.
  • the multiple outer openings 56 are formed in a portion of the interlayer film 50 that covers the termination region 40.
  • the multiple outer openings 56 penetrate the interlayer film 50 and expose the termination region 40.
  • the multiple outer openings 56 are formed in a portion of the interlayer film 50 that covers the overlap region 41 of the termination region 40 and expose the overlap region 41.
  • the outer openings 56 may expose the outer body region 21 instead of or in addition to the termination region 40 (overlapping region 41).
  • the outer openings 56 penetrate both the first oxide film 52 and the second oxide film 53, and have wall surfaces defined by both the first oxide film 52 and the second oxide film 53.
  • the outer openings 56 each have an opening end defined by an arc corner portion of the interlayer film 50.
  • the multiple outer openings 56 are formed at intervals along the termination region 40 (overlap region 41) (see Figures 6 and 7).
  • the multiple outer openings 56 may be formed in a quadrangular (square), rectangular, hexagonal, circular, or other shape in a plan view.
  • the multiple outer openings 56 may be formed in a band shape extending along the termination region 40 (overlap region 41) in a plan view.
  • the semiconductor device 1A may have a single outer opening 56.
  • the single outer opening 56 may be formed in a band shape extending along the termination region 40 (overlapping region 41).
  • the single outer opening 56 may have a portion extending in a band shape in the first direction X and a portion extending in a band shape in the second direction Y in a plan view.
  • the single outer opening 56 may be formed in a polygonal ring shape (a square ring in this embodiment) with or without ends, having four sides parallel to the periphery of the first main surface 3.
  • the single outer opening 56 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape) following the termination region 40 (overlapping region 41) in a plan view (see FIG. 6).
  • the semiconductor device 1A includes a plurality of outer recesses 57 formed in the portions of the first main surface 3 exposed from the plurality of outer openings 56.
  • the semiconductor device 1A does not necessarily have to have the outer recesses 57. Therefore, a configuration that does not have the outer recesses 57 may be adopted.
  • the multiple outer recesses 57 each have a planar shape that matches the planar shape of the corresponding outer opening 56, and are recessed from the first main surface 3 toward the second main surface 4.
  • the multiple outer recesses 57 are formed at intervals from the bottom of the termination region 40 (overlap region 41) toward the first main surface 3, and each exposes the termination region 40 (overlap region 41).
  • the outer recesses 57 may have a depth approximately equal to the depth of the source recess 55.
  • the semiconductor device 1A includes at least one (in this embodiment, multiple) gate openings 58 formed in the interlayer film 50 in the peripheral region 9.
  • the multiple gate openings 58 are formed in a portion of the interlayer film 50 that covers the gate wiring 44.
  • the multiple gate openings 58 penetrate the interlayer film 50 and expose the gate wiring 44.
  • the multiple gate openings 58 penetrate both the first oxide film 52 and the second oxide film 53, and have wall surfaces that are defined by both the first oxide film 52 and the second oxide film 53.
  • Each of the multiple gate openings 58 has an opening end that is defined by an arc corner portion of the interlayer film 50.
  • the multiple gate openings 58 are formed at intervals along the gate wiring 44 (see Figures 6 and 7).
  • the multiple gate openings 58 may be formed in a quadrangular (square), rectangular, hexagonal, circular, or other shape in a plan view.
  • the multiple gate openings 58 may be formed in a strip shape extending along the gate wiring 44 in a plan view.
  • the semiconductor device 1A may have a single gate opening 58.
  • the single gate opening 58 may be formed in a strip shape extending along the gate wiring 44.
  • the single gate opening 58 may have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in a plan view.
  • the single gate opening 58 may be formed in a polygonal ring shape (a square ring in this embodiment) with four sides parallel to the periphery of the first main surface 3, either with or without ends.
  • the single gate opening 58 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape) following the gate wiring 44 in a plan view (see FIG. 6).
  • the semiconductor device 1A includes a source pad electrode 60 disposed on the interlayer film 50.
  • the source pad electrode 60 is a terminal electrode to which a source potential is applied from the outside.
  • the source pad electrode 60 may also be referred to as a "first pad electrode,” a “first main surface electrode,” a “first terminal electrode,” etc.
  • the source pad electrode 60 is disposed on a portion of the interlayer film 50 that covers the active region 8.
  • the source pad electrode 60 covers the multiple gate electrodes 32 with the interlayer film 50 in between, and is electrically isolated from the multiple gate electrodes 32 by the interlayer film 50.
  • the source pad electrode 60 is electrically connected to the multiple body regions 20, the outer body region 21, the multiple source regions 23, 24, the contact region 25, etc. via the multiple source openings 54.
  • the source pad electrode 60 has a first pad portion 60a, a second pad portion 60b, and a third pad portion 60c.
  • the first pad portion 60a has a relatively large planar area and forms the main body of the source pad electrode 60.
  • the first pad portion 60a is formed in a polygonal shape (a square shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and is biased toward the fourth side surface 5D with respect to the center of the active region 8.
  • the first pad portion 60a covers the multiple gate electrodes 32 with the interlayer film 50 in between, and is electrically connected to the multiple body regions 20, etc. via the multiple source openings 54.
  • the second pad portion 60b has a planar area less than that of the first pad portion 60a, and is pulled out in a strip shape (rectangular shape) from one end of the first pad portion 60a in the second direction Y (the end on the first side surface 5A side) toward the third side surface 5C.
  • the second pad portion 60b covers the multiple gate electrodes 32 with the interlayer film 50 in between, and is electrically connected to the multiple body regions 20, etc. via the multiple source openings 54.
  • the third pad portion 60c has a planar area less than that of the first pad portion 60a, and is pulled out in a strip shape (rectangular shape) from the other end of the first pad portion 60a in the second direction Y (the end on the second side surface 5B side) toward the third side surface 5C, and faces the second pad portion 60b in the second direction Y.
  • the third pad portion 60c covers the multiple gate electrodes 32 with the interlayer film 50 in between, and is electrically connected to the multiple body regions 20, etc. via the multiple source openings 54.
  • the plane area of the third pad portion 60c may be approximately equal to the plane area of the second pad portion 60b. Of course, the plane area of the third pad portion 60c may be greater than the plane area of the second pad portion 60b, or may be less than the plane area of the second pad portion 60b. Either or both of the second pad portion 60b and the third pad portion 60c may be used as a terminal portion for monitoring a current.
  • the source pad electrode 60 does not necessarily have to have both the second pad portion 60b and the third pad portion 60c at the same time.
  • the source pad electrode 60 may have only one of the second pad portion 60b and the third pad portion 60c.
  • the source pad electrode 60 may be composed of only the first pad portion 60a, and may not have the second pad portion 60b and the third pad portion 60c.
  • the source pad electrode 60 includes a first underlying electrode film 61, a plurality of first buried electrodes 62, and a first main electrode film 63.
  • the first underlying electrode film 61 may be referred to as a "source underlying electrode film”
  • the first buried electrodes 62 may be referred to as a “source buried electrode”
  • the first main electrode film 63 may be referred to as a "source main electrode film”.
  • the first underlying electrode film 61 forms the lower layer of the source pad electrode 60 (first pad portion 60a, second pad portion 60b, and third pad portion 60c) and covers the interlayer film 50 in the active region 8.
  • the first underlying electrode film 61 collectively covers the region of the interlayer film 50 in which the multiple source openings 54 are formed, and penetrates into the multiple source openings 54 from above the insulating surface 51.
  • the first base electrode film 61 has a portion that covers the insulating surface 51 in a film-like manner, and a portion that covers the wall surfaces of the multiple source openings 54 in a film-like manner.
  • the first base electrode film 61 may have a portion that covers the gate wiring 44 with the interlayer film 50 in between.
  • the first base electrode film 61 may be formed spaced inward from the gate wiring 44 in a plan view.
  • the first underlying electrode film 61 has a layered structure including a first electrode film 64 layered on the interlayer film 50, and a second electrode film 65 layered on the first electrode film 64.
  • the first electrode film 64 includes a Ti film
  • the second electrode film 65 includes a TiN film.
  • the first underlying electrode film 61 does not necessarily have to have a layered structure, and may have a single layer structure consisting of either the first electrode film 64 (Ti film) or the second electrode film 65 (TiN film).
  • the thickness of the first electrode film 64 may be 10 nm or more and 100 nm or less.
  • the thickness of the first electrode film 64 may have a value that belongs to at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, and 75 nm or more and 100 nm or less.
  • the thickness of the second electrode film 65 may be 50 nm or more and 200 nm or less.
  • the thickness of the second electrode film 65 may have a value belonging to at least one of the following ranges: 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less. It is preferable that the thickness of the second electrode film 65 is greater than the thickness of the first electrode film 64.
  • the first electrode film 64 collectively covers the region of the interlayer film 50 where the multiple source openings 54 are formed, and penetrates into the multiple source openings 54 from above the insulating surface 51.
  • the first electrode film 64 has a portion that covers the insulating surface 51 in a film-like manner, and a portion that covers the wall surfaces of the multiple source openings 54 in a film-like manner.
  • the first electrode film 64 directly covers the insulating surface 51 (second oxide film 53), and faces the multiple gate electrodes 32 across the interlayer film 50.
  • the first electrode film 64 covers the arc corner of the interlayer film 50 (second oxide film 53) in a film-like manner, following the arc corner of the interlayer film 50 (second oxide film 53), and penetrates into the source opening 54.
  • the first electrode film 64 has a portion that extends in an arc shape at the arc corner. This improves the film-forming property of the first electrode film 64 on the interlayer film 50 (the wall surface of the source opening 54).
  • the first electrode film 64 extends along the wall surface of the source opening 54 and covers the insulating film 31, the first oxide film 52 and the second oxide film 53.
  • the first electrode film 64 faces the side wall of the gate electrode 32 across the interlayer film 50.
  • the first electrode film 64 covers the first main surface 3 in a film-like manner at the bottom of each source opening 54 and is electrically connected to the first main surface 3.
  • the first electrode film 64 has a portion that covers the source recess 55 in a film-like manner at the bottom of each source opening 54 and is electrically connected to the multiple source regions 23, 24 and the contact region 25.
  • the first electrode film 64 may cover the source recess 55 in a film-like manner with a gap from the height position of the first main surface 3 to the bottom side of the source recess 55.
  • the first electrode film 64 may have a portion located on the bottom side of the source recess 55 with respect to the height position of the first main surface 3, and a portion located on the insulating film 31 side with respect to the height position of the first main surface 3.
  • the second electrode film 65 covers the area of the interlayer film 50 where the multiple source openings 54 are formed on the first electrode film 64 in a film-like manner.
  • the second electrode film 65 has a portion that covers the insulating surface 51 in a film-like manner with the first electrode film 64 in between, and a portion that covers the wall surfaces of the multiple source openings 54 in a film-like manner with the first electrode film 64 in between.
  • the second electrode film 65 faces the multiple gate electrodes 32 across the first electrode film 64 and the interlayer film 50 in the portion covering the insulating surface 51.
  • the second electrode film 65 covers the arc corner portion of the interlayer film 50 (second oxide film 53) in a film-like manner, following the first electrode film 64, and extends into the source opening 54.
  • the second electrode film 65 has a portion that extends in an arc shape at the arc corner portion of the interlayer film 50. This improves the film formability of the second electrode film 65 on the interlayer film 50 (the wall surface of the source opening 54).
  • the second electrode film 65 extends along the wall surface of the source opening 54, and covers the insulating film 31, the first oxide film 52, and the second oxide film 53 with the first electrode film 64 in between.
  • the second electrode film 65 faces the side wall of the gate electrode 32 with the first electrode film 64 and the interlayer film 50 in between.
  • the second electrode film 65 has a portion that covers the source recess 55 in a film-like manner at the bottom of each source opening 54 with the first electrode film 64 in between, and is electrically connected to the multiple source regions 23, 24 and the contact region 25 via the first electrode film 64.
  • the second electrode film 65 may have a portion located within the source recess 55.
  • the entire second electrode film 65 is located above the source recess 55.
  • the multiple first buried electrodes 62 form a middle layer of the source pad electrode 60 (first pad portion 60a, second pad portion 60b, and third pad portion 60c), and are buried in the multiple source openings 54, respectively.
  • the first buried electrodes 62 include a conductive material different from the conductive material of the first base electrode film 61.
  • the first buried electrodes 62 include at least one of tungsten, molybdenum, a tungsten alloy, and a molybdenum alloy. In this embodiment, the first buried electrodes 62 include tungsten.
  • the multiple first buried electrodes 62 are buried in a one-to-one correspondence with the multiple source openings 54 via a single first base electrode film 61.
  • the multiple first buried electrodes 62 are electrically connected to the first main surface 3 (chip 2) within the multiple source openings 54.
  • the first buried electrode 62 is electrically connected to the multiple source regions 23, 24 and contact region 25 via the first base electrode film 61.
  • the configuration of one first buried electrode 62 is described below.
  • the first buried electrode 62 has a first buried electrode surface 66 exposed from the source opening 54, exposing the insulating surface 51.
  • the first buried electrode surface 66 may be referred to as a "source buried electrode film.”
  • the first buried electrode 62 is embedded in the source opening 54 at a distance from the insulating surface 51 toward the first main surface 3, exposing a portion of the first base electrode film 61 (second electrode film 65) that covers the insulating surface 51.
  • the first buried electrode 62 covers the first oxide film 52 and the second oxide film 53 with the first underlying electrode film 61 in between.
  • the first buried electrode 62 faces the sidewall of the gate electrode 32 in the horizontal direction.
  • the first buried electrode 62 may have a portion located within the source recess 55.
  • the entire first buried electrode 62 is located above the source recess 55.
  • the first buried electrode surface 66 is located closer to the first main surface 3 than the insulating surface 51, and does not have a portion that faces the electrode surface of the gate electrode 32 across the interlayer film 50 in the stacking direction (vertical direction Z). In this embodiment, the first buried electrode surface 66 has a portion that covers the arc corner portion of the interlayer film 50 across the first base electrode film 61.
  • the first buried electrode surface 66 may be located below the arc corner of the interlayer film 50.
  • the first buried electrode surface 66 is located closer to the insulating surface 51 than the height position of the first oxide film 52.
  • the first buried electrode surface 66 is preferably located above the electrode surface of the gate electrode 32.
  • the first buried electrode surface 66 has a recess in the center that is recessed toward the first main surface 3 (chip 2).
  • the bottom of the recess is preferably located on the insulating surface 51 side relative to the height position of the electrode surface of the gate electrode 32.
  • a part (e.g., the recess) or the entire first buried electrode surface 66 may be located below the electrode surface of the gate electrode 32.
  • a part (e.g., the recess) or the entire first buried electrode surface 66 may be located on the insulating surface 51 side relative to the height position of the first oxide film 52.
  • the first main electrode film 63 forms the upper layer of the source pad electrode 60 (the first pad portion 60a, the second pad portion 60b, and the third pad portion 60c) and covers the first base electrode film 61 and the multiple first buried electrodes 62 in a film-like manner.
  • the first main electrode film 63 contains a conductive material different from the conductive material of the first base electrode film 61 and the conductive material of the first buried electrodes 62.
  • the first main electrode film 63 may include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film.
  • the Al alloy film may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film.
  • the first main electrode film 63 has a thickness greater than the thickness (total thickness) of the first underlying electrode film 61.
  • the first main electrode film 63 has a thickness greater than the thickness of the first buried electrode 62.
  • the thickness of the first main electrode film 63 may be 0.5 ⁇ m or more and 5 ⁇ m or less.
  • the thickness of the first main electrode film 63 may have a value that belongs to at least one of the following ranges: 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the first main electrode film 63 is mechanically and electrically connected to the first underlying electrode film 61 in the portion covering the insulating surface 51, and faces the multiple gate electrodes 32 across the first underlying electrode film 61 and the interlayer film 50.
  • the first main electrode film 63 is mechanically and electrically connected to the multiple first buried electrodes 62 in the portion covering the multiple source openings 54.
  • the first main electrode film 63 is electrically connected to the multiple body regions 20, the outer body region 21, the multiple source regions 23, 24, the contact region 25, etc. via both the first underlying electrode film 61 and the multiple first buried electrodes 62.
  • the first main electrode film 63 is connected to the first buried electrode surface 66 at a height position on the first main surface 3 side relative to the height position of the insulating surface 51.
  • the first main electrode film 63 has a portion that covers the recess of the first buried electrode surface 66.
  • the first main electrode film 63 may have a portion that covers the circular arc corner portion of the interlayer film 50 with the first base electrode film 61 in between.
  • the first main electrode film 63 is connected to the first buried electrode surface 66 above the height position of the first oxide film 52.
  • the first main electrode film 63 is connected to the first buried electrode surface 66 above the electrode surface of the gate electrode 32.
  • the first main electrode film 63 does not have a portion that faces the gate electrode 32 in the horizontal direction. If the first buried electrode surface 66 is located below the height position of the electrode surface of the gate electrode 32 and the height position of the first oxide film 52, the first main electrode film 63 may have a portion that faces the gate electrode 32 in the horizontal direction.
  • the film formation of the first main electrode film 63 for the multiple source openings 54 is improved by the multiple first buried electrodes 62. This ensures an appropriate current path between the first main surface 3 and the first main electrode film 63. This configuration is effective in suppressing film formation defects caused by the multiple source openings 54 and reducing wiring resistance.
  • the semiconductor device 1A includes a plurality of first silicide portions 67 formed on the surface portions of the first main surface 3 exposed from the plurality of source openings 54.
  • the plurality of first silicide portions 67 are formed in a film shape along the wall surfaces (side walls and bottom walls) of the plurality of source recesses 55, and are mechanically and electrically connected to the first base electrode film 61.
  • the plurality of first silicide portions 67 are formed on the surface layers of the plurality of body regions 20, and electrically connect the plurality of first buried electrodes 62 to the plurality of body regions 20 via the first base electrode film 61.
  • the first silicide portion 67 may include at least one of Ti silicide, Ni silicide, Co silicide, Mo silicide, and W silicide.
  • the first silicide portion 67 is preferably made of Ti silicide, Ni silicide, or Co silicide.
  • the semiconductor device 1A includes a source finger electrode 68 that is extended from the source pad electrode 60 onto the peripheral region 9.
  • the source finger electrode 68 transmits the source potential applied to the source pad electrode 60 to the peripheral region 9.
  • the source finger electrode 68 is extended from the portion of the source pad electrode 60 (first pad portion 60a) on the fourth side surface 5D side onto the portion of the interlayer film 50 that covers the peripheral region 9.
  • the source finger electrode 68 is extended up to above the termination region 40.
  • the source finger electrode 68 is formed at a distance from the low concentration region 11 toward the active region 8 in a plan view, and faces the high concentration region 10 (inner low concentration region 13) in the stacking direction.
  • the source finger electrode 68 does not face the low concentration region 11 in the stacking direction.
  • the source finger electrode 68 may be extended from the region above the high concentration region 10 to the region above the low concentration region 11, and may have a portion facing the low concentration region 11 in the stacking direction.
  • the source finger electrode 68 is electrically connected to the termination region 40 via a plurality of outer openings 56. Specifically, the source finger electrode 68 is electrically connected to the overlap region 41 of the termination region 40 via a plurality of outer openings 56. The source finger electrode 68 extends in a band shape along the termination region 40 (overlap region 41). The source finger electrode 68 has a portion that extends in a band shape in the first direction X and a portion that extends in a band shape in the second direction Y in a plan view.
  • the source finger electrode 68 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3, and surrounds the source pad electrode 60.
  • the source finger electrode 68 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quadrant arc shape) in a plan view (see FIG. 6).
  • the source finger electrode 68 like the source pad electrode 60, includes a first underlying electrode film 61, a plurality of first buried electrodes 62, and a first main electrode film 63.
  • the first underlying electrode film 61 forms a lower layer of the source finger electrode 68, and covers the interlayer film 50 in the peripheral region 9.
  • the first underlying electrode film 61 collectively covers the region of the interlayer film 50 in which the plurality of outer openings 56 are formed, and extends into the plurality of outer openings 56 from above the insulating surface 51.
  • the first underlying electrode film 61 has a portion that covers the insulating surface 51 in a film-like manner, and a portion that covers the wall surfaces of the plurality of outer openings 56 in a film-like manner.
  • the first base electrode film 61 like the source pad electrode 60, has a layered structure including a first electrode film 64 and a second electrode film 65.
  • the first electrode film 64 collectively covers the area of the interlayer film 50 in which the multiple outer openings 56 are formed, and penetrates into the multiple outer openings 56 from above the insulating surface 51.
  • the first electrode film 64 has a portion that covers the insulating surface 51 in a film-like manner, and a portion that covers the wall surfaces of the multiple outer openings 56 in a film-like manner.
  • the first electrode film 64 covers the arc corner of the interlayer film 50 (second oxide film 53) in a film-like manner, following the arc corner of the interlayer film 50 (second oxide film 53), and enters the outer opening 56.
  • the first electrode film 64 has a portion that extends in an arc shape at the arc corner. This improves the film-forming ability of the first electrode film 64 on the interlayer film 50 (wall surface of the outer opening 56).
  • the first electrode film 64 extends along the wall surface of the outer opening 56, and covers the peripheral insulating film 43, the first oxide film 52, and the second oxide film 53.
  • the first electrode film 64 covers the first main surface 3 in a film-like manner at the bottom of each outer opening 56, and is electrically connected to the first main surface 3 (chip 2). Specifically, the first electrode film 64 has a portion that covers the outer recess 57 in a film-like manner at the bottom of each outer opening 56, and is electrically connected to the termination region 40 (overlap region 41) within the outer recess 57.
  • the first electrode film 64 may cover the outer recess 57 in a film-like manner with a gap from the height position of the first main surface 3 to the bottom side of the outer recess 57.
  • the first electrode film 64 may have a portion located on the bottom side of the outer recess 57 relative to the height position of the first main surface 3, and a portion located on the peripheral insulating film 43 side relative to the height position of the first main surface 3.
  • the second electrode film 65 is disposed on the first electrode film 64 and covers the area of the interlayer film 50 in which the multiple outer openings 56 are formed.
  • the second electrode film 65 has a portion that covers the insulating surface 51 in a film-like manner with the first electrode film 64 in between, and a portion that covers the wall surfaces of the multiple outer openings 56 in a film-like manner with the first electrode film 64 in between.
  • the second electrode film 65 covers the arc corners of the interlayer film 50 (second oxide film 53) in a film-like manner and extends into the outer opening 56.
  • the second electrode film 65 has a portion that extends in an arc shape at the arc corners of the interlayer film 50 (second oxide film 53). This improves the film-forming properties of the second electrode film 65 on the interlayer film 50 (wall surface of the outer opening 56).
  • the second electrode film 65 extends along the wall surface of the outer opening 56 and covers the peripheral insulating film 43, first oxide film 52, and second oxide film 53 with the first electrode film 64 in between.
  • the second electrode film 65 has a portion that covers the outer recess 57 in a film-like manner at the bottom of each outer opening 56, sandwiching the first electrode film 64 therebetween, and is electrically connected to the termination region 40 (overlapping region 41) via the first electrode film 64.
  • the second electrode film 65 may have a portion that is located within the outer recess 57.
  • the entire second electrode film 65 is located above the outer recess 57.
  • the multiple first buried electrodes 62 form a middle layer of the source finger electrode 68, and are buried in the multiple outer openings 56, respectively.
  • the multiple first buried electrodes 62 are buried in a one-to-one correspondence with the multiple outer openings 56 via a single first base electrode film 61.
  • the multiple first buried electrodes 62 are electrically connected to the termination region 40 (overlap region 41) via the first base electrode film 61.
  • the first buried electrode 62 has a first buried electrode surface 66 exposed from the outer opening 56, exposing the insulating surface 51. Specifically, the first buried electrode 62 is buried in the outer opening 56 at a distance from the insulating surface 51 toward the first principal surface 3, exposing the portion of the first base electrode film 61 (second electrode film 65) that covers the insulating surface 51. In other words, the first buried electrode surface 66 is located closer to the first principal surface 3 than the insulating surface 51.
  • the first buried electrode 62 covers the first oxide film 52 and the second oxide film 53 with the first base electrode film 61 in between.
  • the first buried electrode 62 has a portion that covers the arc corner portion of the interlayer film 50 with the first base electrode film 61 in between.
  • the first buried electrode 62 is buried at a distance from the arc corner portion of the interlayer film 50 toward the outer insulating film 43, and the entire arc corner portion may be exposed.
  • the first buried electrode surface 66 is located on the insulating surface 51 side of the height position of the first oxide film 52 in the outer opening 56. Of course, the first buried electrode surface 66 may be located on the outer insulating film 43 side of the height position of the first oxide film 52.
  • the first buried electrode 62 may have a portion positioned within the outer recess 57.
  • the entire first buried electrode 62 is positioned above the outer recess 57.
  • the first main electrode film 63 forms the upper layer of the source finger electrode 68, and covers the first underlying electrode film 61 and the multiple first buried electrodes 62 in a film-like manner.
  • the first main electrode film 63 is mechanically and electrically connected to the first underlying electrode film 61 in the portion covering the insulating surface 51, and is mechanically and electrically connected to the multiple first buried electrodes 62 in the portion covering the multiple outer openings 56.
  • the first main electrode film 63 is electrically connected to the termination region 40 (overlap region 41) via the first underlying electrode film 61 and the multiple first buried electrodes 62.
  • the first main electrode film 63 is connected to the first buried electrode surface 66 at a height position on the first main surface 3 side relative to the height position of the insulating surface 51.
  • the first main electrode film 63 is connected to the first buried electrode surface 66 above the height position of the first oxide film 52.
  • the first main electrode film 63 has a portion that covers the recess of the first buried electrode surface 66.
  • the first main electrode film 63 may have a portion that covers the arc corner portion of the interlayer film 50, sandwiching the first base electrode film 61.
  • the first main electrode film 63 may be connected to the first buried electrode 62 in a region below the first oxide film 52.
  • the deposition properties of the first main electrode film 63 on the multiple outer openings 56 are improved by the multiple first buried electrodes 62. This ensures an appropriate current path between the termination region 40 (overlap region 41) and the first main electrode film 63. This configuration is effective in suppressing deposition defects caused by the multiple outer openings 56 and reducing wiring resistance.
  • the semiconductor device 1A includes a plurality of second silicide portions 69 formed on the surface portions of the first main surface 3 exposed from the plurality of outer openings 56.
  • the plurality of second silicide portions 69 are formed in a film shape along the wall surfaces (side walls and bottom walls) of the plurality of outer recesses 57, and are mechanically and electrically connected to the first base electrode film 61.
  • the plurality of second silicide portions 69 are formed in the surface layer portion of the termination region 40 (overlap region 41), and electrically connect the plurality of first buried electrodes 62 to the termination region 40 (overlap region 41) via the first base electrode film 61.
  • the second silicide portion 69 may include at least one of Ti silicide, Ni silicide, Co silicide, Mo silicide, and W silicide.
  • the second silicide portion 69 is preferably made of Ti silicide, Ni silicide, or Co silicide. It is particularly preferable that the second silicide portion 69 is made of the same type of silicide as the first silicide portion 67.
  • the semiconductor device 1A includes a gate finger electrode 70 selectively routed over the interlayer film 50.
  • the gate finger electrode 70 transmits a gate potential to the gate wiring 44.
  • the gate finger electrode 70 is routed over a portion of the interlayer film 50 that covers the gate wiring 44 (i.e., over the outer peripheral region 9), and is electrically connected to the gate wiring 44 via a plurality of gate openings 58.
  • the gate finger electrode 70 is disposed in the region between the source pad electrode 60 and the source finger electrode 68 and spaced apart from the source pad electrode 60 and the source finger electrode 68.
  • the gate finger electrode 70 extends in a strip shape along the gate wiring 44.
  • the gate finger electrode 70 has a portion that extends in a strip shape in the first direction X and a portion that extends in a strip shape in the second direction Y in a plan view.
  • the gate finger electrode 70 is formed in a band shape with four sides parallel to the periphery of the first main surface 3, and surrounds the source pad electrode 60.
  • the gate finger electrode 70 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quadrant arc shape) in a plan view (see FIG. 6).
  • the gate finger electrode 70 has a pair of open ends on the fourth side surface 5D side through which the source finger electrode 68 passes.
  • the gate finger electrode 70 includes a second underlying electrode film 71, at least one (in this embodiment, multiple) second buried electrodes 72, and a second main electrode film 73.
  • the second underlying electrode film 71 may be referred to as the "gate underlying electrode film”
  • the second buried electrode 72 may be referred to as the “gate buried electrode”
  • the second main electrode film 73 may be referred to as the "gate main electrode film”.
  • the second underlying electrode film 71 forms the lower layer of the gate finger electrode 70, and covers the interlayer film 50 in the peripheral region 9.
  • the second underlying electrode film 71 collectively covers the region of the interlayer film 50 in which the multiple gate openings 58 are formed, and penetrates into the multiple gate openings 58 from above the insulating surface 51.
  • the second underlying electrode film 71 has a portion that covers the insulating surface 51 in a film-like manner, and a portion that covers the wall surfaces of the multiple gate openings 58 in a film-like manner.
  • the second base electrode film 71 has a layered structure including a first electrode film 74 layered on the interlayer film 50, and a second electrode film 75 layered on the first electrode film 74. It is preferable that the first electrode film 74 includes the same type of conductive material as the first electrode film 64 on the source side, and the second electrode film 75 includes the same type of conductive material as the second electrode film 65 on the source side. In this embodiment, the first electrode film 74 includes a Ti film, and the second electrode film 75 includes a TiN film.
  • the second base electrode film 71 does not necessarily have to have a laminated structure, and may have a single-layer structure consisting of either the first electrode film 74 (Ti film) or the second electrode film 75 (TiN film).
  • the first electrode film 74 may have a thickness approximately equal to the thickness of the first electrode film 64 on the source side.
  • the second electrode film 75 may have a thickness approximately equal to the thickness of the second electrode film 65 on the source side.
  • the first electrode film 74 collectively covers the region of the interlayer film 50 in which the multiple gate openings 58 are formed, and penetrates into the multiple gate openings 58 from above the insulating surface 51.
  • the first electrode film 74 has a portion that covers the insulating surface 51 in a film-like manner, and a portion that covers the wall surfaces of the multiple gate openings 58 in a film-like manner.
  • the first electrode film 74 covers the arc corner portion of the interlayer film 50 (second oxide film 53) in a film-like manner, following the arc corner portion, and extends into the gate opening 58.
  • the first electrode film 74 has a portion that extends in an arc shape at the arc corner portion. This improves the film-forming property of the first electrode film 74 on the interlayer film 50 (the wall surface of the gate opening 58).
  • the first electrode film 74 extends along the wall surface of the gate opening 58 and covers the first oxide film 52 and the second oxide film 53.
  • the first electrode film 74 covers the gate wiring 44 at the bottom of each gate opening 58 in a film-like manner and is electrically connected to the gate wiring 44.
  • the second electrode film 75 covers the area of the interlayer film 50 on the first electrode film 74 where the multiple gate openings 58 are formed.
  • the second electrode film 75 has a portion that covers the insulating surface 51 in a film-like manner with the first electrode film 74 in between, and a portion that covers the wall surfaces of the multiple gate openings 58 in a film-like manner with the first electrode film 74 in between.
  • the second electrode film 75 covers the arc corners of the interlayer film 50 (second oxide film 53) in a film-like manner and penetrates into the gate opening 58.
  • the second electrode film 75 has a portion that extends in an arc shape at the arc corners of the interlayer film 50 (second oxide film 53). This improves the film-forming properties of the second electrode film 75 on the interlayer film 50 (the wall surface of the gate opening 58).
  • the second electrode film 75 extends along the wall surface of the gate opening 58, and covers the first oxide film 52 and the second oxide film 53 with the first electrode film 74 in between.
  • the second electrode film 75 has a portion that covers the gate wiring 44 in a film-like manner at the bottom of each gate opening 58 with the first electrode film 74 in between, and is electrically connected to the gate wiring 44 via the first electrode film 74.
  • the multiple second buried electrodes 72 form a middle layer of the gate finger electrode 70 and are buried in the multiple gate openings 58, respectively.
  • the second buried electrodes 72 include a conductive material different from the conductive material of the second base electrode film 71.
  • the second buried electrodes 72 include at least one of tungsten, molybdenum, a tungsten alloy, and a molybdenum alloy.
  • the second buried electrodes 72 preferably include the same type of conductive material as the conductive material of the first buried electrodes 62. In this embodiment, the second buried electrodes 72 include tungsten.
  • the multiple second buried electrodes 72 are buried in a one-to-one correspondence with the multiple gate openings 58 via a single second base electrode film 71.
  • the multiple second buried electrodes 72 are electrically connected to the gate wiring 44 via the second base electrode film 71 within the multiple gate openings 58.
  • the second buried electrode 72 has a second buried electrode surface 76 exposed from the gate opening 58, exposing the insulating surface 51.
  • the second buried electrode surface 76 may be referred to as a "gate buried electrode surface.”
  • the second buried electrode 72 is buried in the gate opening 58 at a distance from the insulating surface 51 toward the first principal surface 3, exposing a portion of the second base electrode film 71 (second electrode film 75) that covers the insulating surface 51. In other words, the second buried electrode surface 76 is located closer to the first principal surface 3 than the insulating surface 51.
  • the second buried electrode 72 covers the first oxide film 52 and the second oxide film 53 with the second base electrode film 71 in between.
  • the second buried electrode 72 has a portion that covers the arc corner portion of the interlayer film 50 with the second base electrode film 71 in between.
  • the second buried electrode 72 is buried at a distance from the arc corner portion of the interlayer film 50 toward the gate wiring 44 side, and the entire arc corner portion may be exposed.
  • the second buried electrode surface 76 is located closer to the insulating surface 51 than the height position of the first oxide film 52. Of course, the second buried electrode surface 76 may be located closer to the gate wiring 44 than the height position of the first oxide film 52.
  • the second main electrode film 73 forms the upper layer of the gate finger electrode 70, and covers the second base electrode film 71 and the multiple second buried electrodes 72 in a film-like manner.
  • the second main electrode film 73 contains a conductive material different from the conductive material of the second base electrode film 71 and the conductive material of the second buried electrodes 72.
  • the second main electrode film 73 may include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film.
  • the Al alloy film may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film.
  • the second main electrode film 73 preferably includes the same type of conductive material as the conductive material of the first main electrode film 63.
  • the second main electrode film 73 may have a thickness approximately equal to that of the first main electrode film 63.
  • the second main electrode film 73 is mechanically and electrically connected to the second base electrode film 71 in the portion covering the insulating surface 51, and is mechanically and electrically connected to the multiple second buried electrodes 72 in the portion covering the multiple gate openings 58. As a result, the second main electrode film 73 is electrically connected to the gate wiring 44 via the second base electrode film 71 and the multiple second buried electrodes 72.
  • the second main electrode film 73 is connected to the second buried electrode 72 at a height position on the first main surface 3 side relative to the height position of the insulating surface 51.
  • the second main electrode film 73 is connected to the second buried electrode surface 76 above the height position of the first oxide film 52.
  • the second main electrode film 73 has a portion that covers the recess of the second buried electrode surface 76.
  • the second main electrode film 73 may have a portion that covers the arc corner portion of the interlayer film 50, sandwiching the second base electrode film 71.
  • the second main electrode film 73 may be connected to the second buried electrode 72 in a region below the first oxide film 52.
  • the film formation of the second main electrode film 73 for the multiple gate openings 58 is improved by the multiple second buried electrodes 72. This ensures an appropriate current path between the gate wiring 44 and the second main electrode film 73. This configuration is effective in suppressing film formation defects caused by the multiple gate openings 58 and reducing wiring resistance.
  • the semiconductor device 1A includes a gate pad electrode 80 disposed on the interlayer film 50.
  • the gate pad electrode 80 is a terminal electrode to which a gate potential is applied from the outside.
  • the gate pad electrode 80 may also be referred to as a "second pad electrode,” a “second main surface electrode,” a “second terminal electrode,” etc.
  • the gate pad electrode 80 is disposed in the region between the source pad electrode 60 and the source finger electrodes 68 and spaced apart from the source pad electrode 60 and the source finger electrodes 68.
  • the gate pad electrode 80 is disposed in a region on the third side surface 5C side relative to the first pad portion 60a, and is sandwiched between the second pad portion 60b and the third pad portion 60c. In other words, the gate pad electrode 80 faces the first pad portion 60a in the first direction X, and faces the second pad portion 60b and the third pad portion 60c in the second direction Y.
  • the gate pad electrode 80 is formed in a polygonal shape (a square shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view.
  • the gate pad electrode 80 has a planar area less than that of the source pad electrode 60 (first pad portion 60a).
  • the gate pad electrode 80 may have a planar area less than that of the second pad portion 60b (third pad portion 60c).
  • the gate pad electrode 80 is disposed on the portion covering the active region 8 and the peripheral region 9, and is connected to the gate finger electrode 70.
  • the gate pad electrode 80 may cover multiple gate electrodes 32 with the interlayer film 50 in between, or may cover the gate wiring 44 with the interlayer film 50 in between.
  • the gate pad electrode 80 like the gate finger electrode 70, includes a second base electrode film 71 and a second main electrode film 73.
  • the second base electrode film 71 forms a lower layer of the gate pad electrode 80 and covers the interlayer film 50 in a film-like manner.
  • the second base electrode film 71 like the gate finger electrode 70, has a layered structure including a first electrode film 74 and a second electrode film 75.
  • the first electrode film 74 covers the interlayer film 50 in a film-like manner
  • the second electrode film 75 covers the first electrode film 74 in a film-like manner.
  • the second main electrode film 73 forms an upper layer of the gate pad electrode 80 and covers the second base electrode film 71 in a film-like manner.
  • the gate pad electrode 80 may have a plurality of second buried electrodes 72, similar to the gate finger electrode 70.
  • the gate pad electrode 80 may be electrically connected to the gate wiring 44 via the plurality of second buried electrodes 72, similar to the gate finger electrode 70.
  • the gate pad electrode 80 may be electrically connected to the multiple gate electrodes 32 via multiple second buried electrodes 72.
  • the gate pad electrode 80 does not have to have multiple second buried electrodes 72.
  • the gate pad electrode 80 does not have to have electrical connection parts to the multiple gate electrodes 32 and to the gate wiring 44 in the area directly below.
  • the gate potential applied to the gate pad electrode 80 is applied to the gate wiring 44 via the gate finger electrode 70.
  • the gate potential is transmitted to the multiple gate electrodes 32 via a wiring path (current path) along the gate wiring 44. This causes the multiple gate electrodes 32 to be turned on, controlling the on/off of the multiple channel regions 26, 27.
  • the semiconductor device 1A includes a drain pad electrode 85 covering the second main surface 4.
  • the drain pad electrode 85 is a terminal electrode to which a drain potential is applied from the outside.
  • the drain pad electrode 85 may also be referred to as a "third pad electrode,” a “third main surface electrode,” a “third terminal electrode,” etc.
  • the drain pad electrode 85 is electrically connected to the base region 14.
  • the drain pad electrode 85 has a portion facing the high concentration region 10 (inner low concentration region 13) across the base region 14, and a portion facing the low concentration region 11 across the base region 14.
  • the drain pad electrode 85 may cover the entire second main surface 4 so as to be continuous with the periphery of the second main surface 4 (first to fourth side surfaces 5A to 5D).
  • the drain pad electrode 85 may partially cover the second main surface 4 so as to expose the periphery of the second main surface 4.
  • the breakdown voltage that can be applied between the source pad electrode 60 and the drain pad electrode 85 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less.
  • the breakdown voltage may have a value that belongs to at least one of the following ranges: 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.
  • the semiconductor device 1A includes a chip 2, an n-type high concentration region 10, and an n-type low concentration region 11.
  • the chip 2 has a first main surface 3.
  • the high concentration region 10 has a relatively high first impurity concentration, and is formed in a surface layer of the first main surface 3 on the inner side of the chip 2.
  • the low concentration region 11 has a second impurity concentration lower than the first impurity concentration of the high concentration region 10, and is formed in a surface layer of the first main surface 3 on the peripheral side of the chip 2.
  • This configuration makes it possible to provide a semiconductor device 1A with a novel configuration.
  • the resistance value on the inner side of the chip 2 can be reduced by utilizing the high concentration region 10, and the voltage resistance of the peripheral portion of the chip 2 can be improved by utilizing the low concentration region 11.
  • the chip 2 preferably contains SiC as an example of a wide band gap semiconductor.
  • SiC due to its characteristics (physical properties), an extremely high voltage is applied, and the breakdown voltage can decrease due to an electric field at the periphery of the chip 2.
  • the breakdown voltage on the periphery side of the chip 2 containing SiC is improved by utilizing the low concentration region 11.
  • the chip 2 may have first to fourth side surfaces 5A to 5D.
  • the high concentration region 10 may be formed with a space from at least one of the first to fourth side surfaces 5A to 5D.
  • the low concentration region 11 may be exposed from at least one of the first to fourth side surfaces 5A to 5D. With this configuration, the formation region of the low concentration region 11 is expanded to a range exposed from at least one of the first to fourth side surfaces 5A to 5D. This appropriately improves the breakdown voltage of the peripheral portion of the chip 2.
  • the low concentration region 11 preferably extends in a band shape along the high concentration region 10 in a plan view. With this configuration, the withstand voltage on the peripheral side of the chip 2 is improved by utilizing the low concentration region 11 extending in a band shape.
  • the low concentration region 11 preferably surrounds the high concentration region 10 in a plan view. With this configuration, the withstand voltage on the peripheral side of the chip 2 is improved all around the high concentration region 10.
  • the low concentration region 11 is preferably connected to the high concentration region 10. This configuration ensures electrical continuity between the high concentration region 10 and the low concentration region 11. This suppresses discontinuity in the electric field between the high concentration region 10 and the low concentration region 11, and appropriately improves the breakdown voltage of the peripheral portion of the chip 2.
  • the low concentration region 11 forms a region boundary portion 12 that extends in the thickness direction of the chip 2 with the high concentration region 10.
  • the region boundary portion 12 may extend approximately perpendicular to the first main surface 3.
  • the semiconductor device 1A may include an n-type inner low-concentration region 13.
  • the inner low-concentration region 13 may have a third impurity concentration lower than the first impurity concentration of the high-concentration region 10, and may be formed in a region below the high-concentration region 10 in the inner part of the chip 2. With this configuration, the resistance value on the inner side of the chip 2 can be reduced by utilizing the high-concentration region 10, and the withstand voltage on the inner side of the chip 2 can be improved by utilizing the inner low-concentration region 13.
  • the inner low concentration region 13 is connected to the low concentration region 11 at the periphery of the chip 2. This configuration ensures electrical continuity between the low concentration region 11 and the inner low concentration region 13. This suppresses discontinuity in the electric field between the low concentration region 11 and the inner low concentration region 13, and appropriately improves the withstand voltage of the periphery of the chip 2.
  • the semiconductor device 1A may include a p-type body region 20 (first impurity region) formed in a surface layer of the high concentration region 10 in a region on the inner side of the high concentration region 10.
  • the body region 20 forms a pn junction with the high concentration region 10, and expands a depletion layer into the high concentration region 10 when a reverse bias voltage is applied. With this configuration, the range of the depletion layer is expanded toward the peripheral side of the chip 2 by the low concentration region 11. This appropriately improves the breakdown voltage on the peripheral side of the chip 2.
  • the semiconductor device 1A may include a p-type outer body region 21 (second impurity region) formed in either or both of the surface layer of the high concentration region 10 and the surface layer of the low concentration region 11 in the peripheral region of the chip 2.
  • the outer body region 21 may be formed in the surface layer of the high concentration region 10 and form a pn junction with the high concentration region 10.
  • the outer body region 21 expands the depletion layer into the high concentration region 10 when a reverse bias voltage is applied.
  • the range of the depletion layer is expanded toward the peripheral side of the chip 2 by the low concentration region 11. This appropriately improves the breakdown voltage on the peripheral side of the chip 2.
  • the outer body region 21 may be formed to extend the depletion layer that is integrated with the depletion layer of the body region 20.
  • the outer body region 21 may be connected to the body region 20.
  • the outer body region 21 may have a p-type impurity concentration that is approximately equal to the p-type impurity concentration of the body region 20.
  • the semiconductor device 1A may include a p-type termination region 40 (third impurity region) formed in either or both of the surface layer of the high concentration region 10 and the surface layer of the low concentration region 11.
  • the termination region 40 may be formed in the high concentration region 10 and form a pn junction with the high concentration region 10. In this case, the termination region 40 expands the depletion layer into the high concentration region 10 when a reverse bias voltage is applied. With this configuration, the range of the depletion layer is expanded toward the peripheral edge side of the chip 2 by the low concentration region 11. This appropriately improves the breakdown voltage on the peripheral edge side of the chip 2.
  • the termination region 40 may be formed to expand the depletion layer that is integrated with the depletion layer of the body region 20.
  • the termination region 40 may be formed to expand the depletion layer that is integrated with the depletion layer of the outer body region 21.
  • the termination region 40 may be connected to the outer body region 21.
  • the termination region 40 may have a p-type impurity concentration different from the p-type impurity concentration of the body region 20.
  • the termination region 40 may have an extension portion that is extended from the high concentration region 10 to the low concentration region 11.
  • the extension portion of the termination region 40 forms a pn junction with the low concentration region 11, and spreads the depletion layer into the low concentration region 11 when a reverse bias voltage is applied. With this configuration, the depletion layer spreads appropriately from the termination region 40 to the low concentration region 11. This appropriately improves the breakdown voltage on the peripheral side of the chip 2.
  • the semiconductor device 1A may include a p-type field region 42 (fourth impurity region) formed in the surface layer of the low concentration region 11.
  • the field region 42 forms a pn junction with the low concentration region 11, and expands a depletion layer into the low concentration region 11 when a reverse bias voltage is applied.
  • the range of the depletion layer in the field region 42 is expanded by the low concentration region 11. This appropriately improves the breakdown voltage on the peripheral side of the chip 2.
  • the field region 42 is preferably formed at a distance from the high concentration region 10 to the peripheral side of the chip 2.
  • the field region 42 is preferably formed at a distance from the body region 20 to the peripheral side of the chip 2.
  • the field region 42 is preferably formed at a distance from the outer body region 21 to the peripheral side of the chip 2.
  • the field region 42 is preferably formed at a distance from the termination region 40 to the peripheral side of the chip 2.
  • the semiconductor device 1A may include an n-type base region 14.
  • the base region 14 may have a fourth impurity concentration lower than the first impurity concentration of the high concentration region 10, and may be formed in a region below the high concentration region 10 on the inner side of the chip 2.
  • the base region 14 may have a portion that is pulled out from the inner part of the chip 2 toward the periphery and is located in a region below the low concentration region 11.
  • the semiconductor device 1A includes a chip 2, an active region 8, a peripheral region 9, a high concentration region 10, and a low concentration region 11.
  • the chip 2 has a first main surface 3.
  • the active region 8 is provided in an inner portion of the first main surface 3.
  • the peripheral region 9 is provided in a peripheral portion of the first main surface 3.
  • the high concentration region 10 has a first impurity concentration and is formed in the surface layer of the first main surface 3 in the active region 8.
  • the low concentration region 11 has a second impurity concentration lower than the first impurity concentration of the high concentration region 10 and is formed in the surface layer of the first main surface 3 in the peripheral region 9.
  • the chip 2 preferably contains SiC as an example of a wide band gap semiconductor.
  • SiC due to its characteristics (physical properties), an extremely high voltage is applied, and the breakdown voltage may decrease due to an electric field at the periphery of the chip 2.
  • the breakdown voltage on the peripheral region 9 side of the chip 2 containing SiC is improved by utilizing the low concentration region 11.
  • the chip 2 may have first to fourth side surfaces 5A to 5D.
  • the high concentration region 10 may be formed with a space from at least one of the first to fourth side surfaces 5A to 5D.
  • the low concentration region 11 may be exposed from at least one of the first to fourth side surfaces 5A to 5D. With this configuration, the formation region of the low concentration region 11 is expanded to a range exposed from at least one of the first to fourth side surfaces 5A to 5D. This appropriately improves the breakdown voltage on the outer periphery region 9 side.
  • the low concentration region 11 preferably extends in a band shape along the high concentration region 10 in a plan view. With this configuration, the withstand voltage on the outer peripheral region 9 side is improved by utilizing the low concentration region 11 extending in a band shape.
  • the low concentration region 11 preferably surrounds the high concentration region 10 in a plan view. With this configuration, the withstand voltage on the outer peripheral region 9 side is improved all around the high concentration region 10.
  • the low concentration region 11 is preferably connected to the high concentration region 10. This configuration ensures electrical continuity between the high concentration region 10 and the low concentration region 11. This suppresses discontinuity in the electric field between the high concentration region 10 and the low concentration region 11, and appropriately improves the breakdown voltage on the outer periphery region 9 side.
  • the low concentration region 11 forms a region boundary 12 with the high concentration region 10 that extends in the thickness direction of the chip 2.
  • the region boundary 12 may extend approximately perpendicular to the first main surface 3.
  • the semiconductor device 1A may include an n-type inner low concentration region 13.
  • the inner low concentration region 13 may have a third impurity concentration lower than the first impurity concentration of the high concentration region 10, and may be formed in a region below the high concentration region 10 on the active region 8 side. With this configuration, the resistance value on the active region 8 side can be reduced by utilizing the high concentration region 10, and the breakdown voltage on the active region 8 side can be improved by utilizing the inner low concentration region 13.
  • the inner low concentration region 13 is connected to the low concentration region 11 on the outer peripheral region 9 side.
  • This configuration ensures electrical continuity between the low concentration region 11 and the inner low concentration region 13. This suppresses discontinuity of the electric field between the low concentration region 11 and the inner low concentration region 13, and appropriately improves the breakdown voltage on the outer peripheral region 9 side.
  • the semiconductor device 1A may include a p-type body region 20 (first impurity region) formed in the surface layer of the high concentration region 10 on the active region 8 side.
  • the body region 20 forms a pn junction with the high concentration region 10, and expands a depletion layer into the high concentration region 10 when a reverse bias voltage is applied. With this configuration, the range of the depletion layer is expanded toward the peripheral region 9 side by the low concentration region 11. This appropriately improves the breakdown voltage on the peripheral region 9 side.
  • the semiconductor device 1A may include a p-type outer body region 21 (second impurity region) formed in one or both of the surface layer of the high concentration region 10 and the surface layer of the low concentration region 11 in the region on the peripheral region 9 side.
  • the outer body region 21 may be formed in the surface layer of the high concentration region 10 and form a pn junction with the high concentration region 10.
  • the outer body region 21 expands the depletion layer into the high concentration region 10 when a reverse bias voltage is applied.
  • the range of the depletion layer is expanded toward the outer peripheral region 9 by the low concentration region 11. This appropriately improves the breakdown voltage on the outer peripheral region 9 side.
  • the outer body region 21 may be formed to extend the depletion layer that is integrated with the depletion layer of the body region 20.
  • the outer body region 21 may be connected to the body region 20.
  • the outer body region 21 may have a p-type impurity concentration that is approximately equal to the p-type impurity concentration of the body region 20.
  • the semiconductor device 1A may include a p-type termination region 40 (third impurity region) formed in either or both of the surface layer of the high concentration region 10 and the surface layer of the low concentration region 11 in the region on the peripheral region 9 side.
  • the termination region 40 may be formed in the high concentration region 10 and form a pn junction with the high concentration region 10.
  • the termination region 40 expands the depletion layer into the high concentration region 10 when a reverse bias voltage is applied.
  • the range of the depletion layer is expanded toward the outer peripheral region 9 by the low concentration region 11. This appropriately improves the breakdown voltage on the outer peripheral region 9 side.
  • the termination region 40 may be formed to expand the depletion layer that is integrated with the depletion layer of the body region 20.
  • the termination region 40 may be formed to expand the depletion layer that is integrated with the depletion layer of the outer body region 21.
  • the termination region 40 may be connected to the outer body region 21.
  • the termination region 40 may have a p-type impurity concentration different from the p-type impurity concentration of the body region 20.
  • the termination region 40 may have an extension portion that is extended from the high concentration region 10 to the low concentration region 11.
  • the extension portion of the termination region 40 forms a pn junction with the low concentration region 11, and spreads the depletion layer into the low concentration region 11 when a reverse bias voltage is applied. With this configuration, the depletion layer spreads appropriately from the termination region 40 to the low concentration region 11. This appropriately improves the breakdown voltage on the outer periphery region 9 side.
  • the semiconductor device 1A may include a p-type field region 42 (fourth impurity region) formed in the surface layer of the low concentration region 11 in the peripheral region 9.
  • the field region 42 forms a pn junction with the low concentration region 11, and expands the depletion layer into the low concentration region 11 when a reverse bias voltage is applied.
  • the range of the depletion layer in the field region 42 is expanded by the low concentration region 11. This appropriately improves the breakdown voltage on the peripheral region 9 side.
  • the field region 42 is preferably formed at a distance from the high concentration region 10 to the peripheral side of the chip 2.
  • the field region 42 is preferably formed at a distance from the body region 20 to the peripheral side of the chip 2.
  • the field region 42 is preferably formed at a distance from the outer body region 21 to the peripheral side of the chip 2.
  • the field region 42 is preferably formed at a distance from the termination region 40 to the peripheral side of the chip 2.
  • the field region 42 preferably extends in a band shape along the high concentration region 10 in a planar view. With this configuration, the depletion layer spreads in a band shape from the field region 42 toward the low concentration region 11. This appropriately improves the breakdown voltage on the outer periphery region 9 side.
  • the field region 42 preferably surrounds the high concentration region 10 in a planar view. With this configuration, the depletion layer spreads from the field region 42 toward the low concentration region 11 so as to surround the high concentration region 10. This appropriately improves the breakdown voltage on the outer periphery region 9 side.
  • Multiple field regions 42 may be formed at intervals in the surface layer of the low concentration region 11. With this configuration, multiple depletion layers spread from the multiple field regions 42 toward the low concentration region 11. This appropriately improves the breakdown voltage on the outer periphery region 9 side.
  • the semiconductor device 1A may include an n-type base region 14.
  • the base region 14 may have a fourth impurity concentration lower than the first impurity concentration of the high concentration region 10, and may be formed in a region below the high concentration region 10 in the active region 8.
  • the base region 14 may have a portion extending from the active region 8 toward the peripheral region 9 and located in a region below the low concentration region 11.
  • the semiconductor device 1A may include a transistor structure Tr as an example of a device structure formed in the active region 8.
  • the transistor structure Tr may include a high concentration region 10.
  • FIG. 12 is a cross-sectional view showing a semiconductor device 1B according to the second embodiment.
  • Semiconductor device 1B has a layout that is a modification of the high concentration region 10 of semiconductor device 1A. Specifically, the high concentration region 10 is formed in the second semiconductor layer 7 throughout the entire thickness range between the first main surface 3 and the bottom of the second semiconductor layer 7 (first semiconductor layer 6), and is connected to the first semiconductor layer 6. That is, in this embodiment, semiconductor device 1B does not have an inner low concentration region 13.
  • the high concentration region 10 is formed substantially perpendicular to the first main surface 3 in a cross-sectional view.
  • the high concentration region 10 may be formed by introducing n-type impurities into the entire thickness range of the n-type second semiconductor layer 7.
  • the low concentration region 11 is formed in the same layout as in the semiconductor device 1A.
  • the inner edge of the low concentration region 11 is connected to the periphery of the high concentration region 10 throughout the entire thickness range of the high concentration region 10.
  • the region boundary 12 crosses the depth position of the middle part of the second semiconductor layer 7 in the thickness direction.
  • the lower end of the region boundary 12 is connected to the first semiconductor layer 6.
  • FIG. 13 is a cross-sectional view showing a semiconductor device 1C according to the third embodiment.
  • FIG. 14 is a cross-sectional view showing a modified example of the semiconductor device 1C shown in FIG. 13.
  • the semiconductor device 1C has a layout in which the high concentration region 10 according to the semiconductor device 1B is modified.
  • the high concentration region 10 is formed in a tapered shape in which the horizontal width gradually increases from the first main surface 3 in the thickness direction in a cross-sectional view.
  • the peripheral portion of the high concentration region 10 slopes obliquely downward from the inner portion (active region 8) of the chip 2 toward the peripheral portion (outer peripheral region 9) of the chip 2.
  • the peripheral portion (sloping peripheral portion) of the high concentration region 10 is located in the outer peripheral region 9.
  • the inclined part of the high concentration region 10 may be formed by introducing n-type impurities in a direction inclined with respect to the first main surface 3 by oblique ion implantation.
  • the low concentration region 11 has an inner edge that slopes downward following the edge (inclined edge) of the high concentration region 10.
  • the low concentration region 11 is formed in a tapered shape in which the horizontal width gradually decreases from the first main surface 3 toward the thickness direction in a cross-sectional view. This configuration is effective in reducing the resistance value of the current spreading path while increasing the breakdown voltage on the edge side of the chip 2.
  • the low concentration region 11 and the high concentration region 10 form a region boundary 12 that slopes obliquely downward.
  • the region boundary 12 has an upper end on the first main surface 3 side, a lower end on the second main surface 4 side, and a sloped portion between the upper end and the lower end.
  • the upper end is located on the inner side of the chip 2 in the outer peripheral region 9.
  • the lower end is located on the peripheral edge side of the chip 2 in the outer peripheral region 9.
  • the sloped portion slopes obliquely downward from the upper end to the lower end in the outer peripheral region 9.
  • the inclination angle ⁇ (absolute value) of the inclined portion may be greater than 0° and less than or equal to 75°.
  • the inclination angle ⁇ is the angle that the inclined portion forms with a virtual vertical line L (virtual perpendicular line) that is perpendicular to the first main surface 3 in a cross-sectional view when the virtual perpendicular line L is set to pass through the upper end of the area boundary portion 12.
  • the inclination angle ⁇ may have a value that belongs to at least one of the following ranges: greater than 0° and less than 15°, greater than 15° and less than 30°, greater than 30° and less than 45°, greater than 45° and less than 60°, and greater than 60° and less than 75°. It is preferable that the inclination angle ⁇ is greater than 20° and less than 60°. It is particularly preferable that the inclination angle ⁇ is greater than 30° and less than 50°.
  • At least the innermost field region 42 of the multiple field regions 42 is preferably formed on the surface layer of the low concentration region 11 at a distance from the upper end of the high concentration region 10 (the upper end of the region boundary 12) toward the peripheral edge of the chip 2.
  • the innermost field region 42 may face the inclined portion of the high concentration region 10 (the inclined portion of the region boundary 12) in the thickness direction, sandwiching a part of the low concentration region 11 therebetween.
  • the multiple field regions 42 are formed in the surface layer of the low concentration region 11 at intervals from the lower end of the high concentration region 10 (the lower end of the region boundary 12) toward the peripheral edge of the chip 2. In other words, it is particularly preferred that the multiple field regions 42 do not face the high concentration region 10 in the thickness direction.
  • the semiconductor device 1C may have an inner low concentration region 13. That is, the high concentration region 10 may be formed at a distance from the bottom of the second semiconductor layer 7 toward the first main surface, as in the case of the semiconductor device 1A, and may face the first semiconductor layer 6 across a part of the second semiconductor layer 7. In this case, the inner low concentration region 13 passes below the lower end of the high concentration region 10 (the lower end of the region boundary portion 12) and is connected to the region on the bottom side of the low concentration region 11 in the peripheral region 9.
  • FIG. 15 is a cross-sectional view showing a semiconductor device 1D according to a fourth embodiment.
  • the semiconductor device 1D has a layout that is a modification of the layout within the chip 2 according to the semiconductor device 1C.
  • the low concentration region 11 is formed at a distance from the bottom of the second semiconductor layer 7 toward the first main surface 3, and has a bottom located within the second semiconductor layer 7.
  • the low concentration region 11 may cross the depth position of the middle part of the second semiconductor layer 7 in the thickness direction.
  • the thickness of the low concentration region 11 may be 1/2 or more of the thickness of the second semiconductor layer 7.
  • the low concentration region 11 may be formed with a gap from the depth position of the middle part of the second semiconductor layer 7 toward the first main surface 3. In other words, the thickness of the low concentration region 11 may be less than 1/2 of the thickness of the second semiconductor layer 7.
  • the semiconductor device 1D includes an n-type outer high concentration region 15 formed in a region below the low concentration region 11 in the surface layer portion of the first main surface 3.
  • the outer high concentration region 15 may be referred to as a "fifth region,” a “fourth drift region,” a “second high concentration drift region,” or the like.
  • the outer high concentration region 15 has a fifth impurity concentration higher than the second impurity concentration of the low concentration region 11.
  • the fifth impurity concentration may be 1 ⁇ 10 15 cm -3 or more and 5 ⁇ 10 16 cm -3 or less.
  • the outer high concentration region 15 is formed on the peripheral edge side of the chip 2 relative to the high concentration region 10.
  • the outer high concentration region 15 extends in a layer shape along the low concentration region 11 in the outer peripheral region 9, and is connected to the low concentration region 11 in the thickness direction. As a result, the outer high concentration region 15 is electrically connected to the low concentration region 11.
  • the outer high concentration region 15 is formed as a low resistance region (second low resistance region) in the outer peripheral region 9 that has a lower resistance value than the low concentration region 11.
  • This configuration is effective in reducing the resistance value of the current spreading path when considering the current flowing diagonally between the inner part of the chip 2 and the peripheral part of the chip 2 (i.e., current spreading).
  • the outer high concentration region 15 is formed in the region between the periphery of the first main surface 3 and the high concentration region 10 in the outer peripheral region 9, and extends in a band shape along the high concentration region 10 (active region 8) in a planar view.
  • the outer high concentration region 15 has a portion extending in a band shape in the first direction X and a portion extending in a band shape in the second direction Y in a planar view, and divides the high concentration region 10 (active region 8) from multiple directions.
  • the outer high concentration region 15 is formed in a ring shape (a square ring shape in this embodiment) surrounding the high concentration region 10 (active region 8) in a planar view. It is preferable that the outer high concentration region 15 is formed in the entire region below the low concentration region 11.
  • the outer high concentration region 15 has an outer edge portion on the peripheral side of the first main surface 3 and an inner edge portion on the inward side of the first main surface 3.
  • the inner edge portion of the outer high concentration region 15 is connected to the peripheral portion of the high concentration region 10.
  • the outer high concentration region 15 is connected to the high concentration region 10 in the outer peripheral region 9.
  • the outer high concentration region 15 is electrically connected to the high concentration region 10.
  • the fifth impurity concentration of the outer high concentration region 15 is preferably approximately equal to the first impurity concentration of the region on the bottom side of the high concentration region 10.
  • the outer edge of the outer high concentration region 15 is preferably exposed from at least one of the first to fourth side faces 5A to 5D. In this embodiment, the outer edge of the outer high concentration region 15 is exposed from all of the first to fourth side faces 5A to 5D.
  • the outer high concentration region 15 is formed in the second semiconductor layer 7.
  • the semiconductor device 1D has a multi-layer structure including a low concentration region 11 and an outer high concentration region 15 in the peripheral portion (peripheral region 9) of the second semiconductor layer 7.
  • the outer high concentration region 15 may be formed by introducing n-type impurities into a portion (region on the bottom side) of the n-type second semiconductor layer 7.
  • the outer high concentration region 15 is formed in the second semiconductor layer 7 throughout the entire thickness range between the bottom of the second semiconductor layer 7 (first semiconductor layer 6) and the bottom of the low concentration region 11, and is connected to the first semiconductor layer 6.
  • the thickness of the outer high concentration region 15 is less than 1/2 the thickness of the second semiconductor layer 7.
  • the thickness of the outer high concentration region 15 is greater than 1/2 the thickness of the second semiconductor layer 7.
  • the multiple field regions 42 are formed in the surface layer of the low concentration region 11, as in the case of the semiconductor device 1A.
  • the multiple field regions 42 are formed at intervals from the bottom of the low concentration region 11 toward the first main surface 3, and face the outer high concentration region 15 with a portion of the low concentration region 11 in between.
  • the multiple field regions 42 are preferably formed at intervals from the middle of the low concentration region 11 toward the first main surface 3.
  • the thickness of the multiple field regions 42 may be less than 1/2 the thickness of the low concentration region 11.
  • the multiple field regions 42 may cross the middle of the low concentration region 11 in the thickness direction.
  • the thickness of the multiple field regions 42 may be 1/2 or more the thickness of the low concentration region 11.
  • the drain pad electrode 85 has a portion facing the high concentration region 10 across the base region 14, and a portion facing the low concentration region 11 (outer high concentration region 15) across the base region 14.
  • FIG. 16 is an enlarged plan view showing a main portion of the active region 8 of a semiconductor device 1E according to the fifth embodiment.
  • FIG. 17 is a cross-sectional view taken along line XVII-XVII shown in FIG. 16.
  • FIG. 17 shows an example in which the configuration of semiconductor device 1A (high concentration region 10, low concentration region 11, etc.) is applied to semiconductor device 1E.
  • the configurations of semiconductor devices 1B to 1D may also be applied to semiconductor device 1E.
  • the semiconductor device 1E is a semiconductor switching device that has a trench-gate type transistor structure Tr as an example of a device structure in the active region 8 instead of a planar-gate type transistor structure Tr.
  • the semiconductor device 1E has a single body region 20 instead of multiple body regions 20.
  • the single body region 20 is formed in the surface layer of the first main surface 3 throughout the active region 8.
  • the single body region 20 is formed in the surface layer of the high concentration region 10.
  • the single body region 20 is formed at a distance from the bottom of the high concentration region 10 toward the first main surface 3, and faces the inner low concentration region 13 (base region 14) with a portion of the high concentration region 10 in between.
  • the single body region 20 is preferably formed at a distance from the middle of the high concentration region 10 toward the first main surface 3. Of course, the single body region 20 may cross the depth position of the middle of the high concentration region 10 in the thickness direction. The single body region 20 is exposed from the first main surface 3.
  • the single body region 20 forms a pn junction (pn junction diode: body diode) with the high concentration region 10.
  • the single body region 20 spreads a depletion layer into the high concentration region 10 when a reverse bias voltage is applied.
  • the depletion layer spreads from the high concentration region 10 toward the low concentration region 11 in the horizontal direction along the first main surface 3.
  • the aforementioned outer body region 21 is formed in the surface layer of the first main surface 3 (high concentration region 10) in the peripheral region 9, as in the case of the semiconductor device 1A.
  • the outer body region 21 is connected to a single body region 20 around the entire periphery of the active region 8.
  • the outer body region 21 can be considered to be formed by the peripheral portion of the single body region 20.
  • the semiconductor device 1E has a plurality of trench electrode type gate structures 35 instead of the plurality of planar electrode type gate structures 30.
  • the plurality of gate structures 35 are arranged at intervals in the first direction X, and are each formed in a band shape extending in the second direction Y. In other words, the plurality of gate structures 35 are arranged in stripes extending in the second direction Y. Furthermore, the extension direction of the plurality of gate structures 35 coincides with the off-direction of the SiC single crystal.
  • the multiple gate structures 35 are formed at intervals from the bottom of the high concentration region 10 toward the first main surface 3, and face the inner low concentration region 13 (base region 14) across a portion of the high concentration region 10. In other words, the multiple gate structures 35 are formed shallower than the high concentration region 10, and face the low concentration region 11 in the horizontal direction.
  • Each of the multiple gate structures 35 includes a trench 36, an insulating film 31, and a gate electrode 32.
  • the trench 36 is formed on the first main surface 3 and defines the walls (side walls and bottom wall) of the gate structure 35.
  • the insulating film 31 covers the walls of the trench 36 in a film-like manner.
  • the gate electrode 32 is embedded in the trench 36 with the insulating film 31 in between.
  • the aforementioned multiple source regions 23, 24 are formed on both sides of multiple gate structures 35 in the surface layer portion of the single body region 20.
  • the first source region 23 is formed along one sidewall of the corresponding gate structure 35 and faces the gate electrode 32 with the insulating film 31 between them.
  • the second source region 24 is formed along the other sidewall of the corresponding gate structure 35 and faces the gate electrode 32 with the insulating film 31 between them.
  • the multiple source regions 23, 24 each extend in a strip shape along the extension direction of the multiple gate structures 35.
  • the multiple source regions 23, 24 are formed at intervals from the bottom of the single body region 20 toward the first main surface 3, and face the high concentration region 10 with a portion of the single body region 20 in between.
  • the aforementioned multiple contact regions 25 are formed in the surface layer of the single body region 20 in the regions between the multiple source regions 23, 24.
  • the multiple contact regions 25 each extend in a strip shape along the extension direction of the multiple gate structures 35.
  • the multiple contact regions 25 are formed at intervals from the bottom of the single body region 20 toward the first main surface 3, and face the high concentration region 10 across a portion of the single body region 20.
  • the aforementioned multiple channel regions 26, 27 are each defined as a region between the bottom (high concentration region 10) of the single body region 20 and the multiple source regions 23, 24.
  • the first channel region 26 is defined as a region between the bottom (high concentration region 10) of the single body region 20 and the first source region 23, and forms a current path extending in the stacking direction along the sidewall of the gate structure 35.
  • the second channel region 27 is defined as a region between the bottom (high concentration region 10) of the single body region 20 and the second source region 24, and forms a current path extending in the stacking direction along the sidewall of the gate structure 35.
  • the semiconductor device 1E includes a termination region 40 (overlap region 41), multiple field regions 42, a peripheral insulating film 43, a gate wiring 44, an interlayer film 50, multiple source openings 54, multiple source recesses 55, multiple outer openings 56, multiple outer recesses 57, multiple gate openings 58, a source pad electrode 60, multiple first silicide portions 67, a source finger electrode 68, multiple second silicide portions 69, a gate finger electrode 70, a gate pad electrode 80, and a drain pad electrode 85. Descriptions of these configurations are omitted, as they are similar to those of the semiconductor device 1A.
  • FIG. 18 is a plan view showing a semiconductor device 1F according to a sixth embodiment.
  • FIG. 19 is a cross-sectional view taken along line XIX-XIX shown in FIG. 18.
  • the semiconductor device 1F is a semiconductor rectifier having a diode structure Di as an example of a device structure, instead of a transistor structure Tr.
  • the diode structure Di is an SBD structure (Schottky Barrier Diode structure).
  • semiconductor device 1F like semiconductor device 1A, includes chip 2, first semiconductor layer 6, second semiconductor layer 7, active region 8, peripheral region 9, high concentration region 10, low concentration region 11, region boundary 12, inner low concentration region 13, termination region 40, and multiple field regions 42. Description of these configurations is omitted, as they are similar to those of semiconductor device 1A.
  • the semiconductor device 1F includes an interlayer film 90 that selectively covers the first main surface 3.
  • the interlayer film 90 may have a single layer structure or a multilayer structure that includes at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the interlayer film 90 has a single layer structure that includes a silicon oxide film.
  • the interlayer film 90 covers the low concentration region 11, the termination region 40, and the multiple field regions 42 in the peripheral region 9.
  • the interlayer film 90 is continuous with the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D).
  • the interlayer film 90 may be formed at a distance inward from the periphery of the first main surface 3, exposing the second semiconductor layer 7 (low concentration region 11) from the periphery of the first main surface 3.
  • the semiconductor device 1F includes a contact opening 91 that exposes the high concentration region 10 in the interlayer film 90.
  • the contact opening 91 has an opening wall located above the termination region 40, exposing the high concentration region 10 and the inner edge of the termination region 40.
  • the opening wall is formed in a polygonal shape (a square shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, exposing the entire inner periphery of the termination region 40.
  • the semiconductor device 1F includes an anode pad electrode 92 disposed on the first main surface 3.
  • the anode pad electrode 92 is a terminal electrode to which an anode potential is applied from the outside.
  • the anode pad electrode 92 may be referred to as a "first pad electrode,” a “first main surface electrode,” a “first terminal electrode,” or the like.
  • the anode pad electrode 92 is disposed at a distance inward from the periphery of the chip 2.
  • the anode pad electrode 92 is formed in a polygonal shape (a square shape in this embodiment) that follows the periphery of the chip 2 in a plan view.
  • the anode pad electrode 92 penetrates the contact opening 91 from above the interlayer film 90, and is electrically connected within the contact opening 91 to the inner edge of the high concentration region 10 and the termination region 40.
  • the anode pad electrode 92 forms a Schottky junction with the high concentration region 10. This forms a diode structure Di including the high concentration region 10.
  • the anode pad electrode 92 has a portion that faces the high concentration region 10 within the contact opening 91, with the termination region 40 in between.
  • the anode pad electrode 92 has a peripheral portion that covers the termination region 40 with the interlayer film 90 in between.
  • the peripheral portion of the anode pad electrode 92 has a portion that faces the high concentration region 10 in the stacking direction.
  • the peripheral portion of the anode pad electrode 92 may have a portion that crosses the region boundary portion 12 in the horizontal direction and covers the low concentration region 11 with the interlayer film 90 in between.
  • the peripheral portion of the anode pad electrode 92 may be formed at a distance inward from the innermost field region 42.
  • the peripheral portion of the anode pad electrode 92 may have a portion that covers the innermost field region 42 with the interlayer film 90 in between.
  • the peripheral portion of the anode pad electrode 92 may cover multiple field regions 42 with the interlayer film 90 in between.
  • the semiconductor device 1F includes a cathode pad electrode 93 covering the second main surface 4.
  • the cathode pad electrode 93 is a terminal electrode to which a cathode potential is applied from the outside.
  • the cathode pad electrode 93 may also be referred to as a "second pad electrode,” a “second main surface electrode,” a “second terminal electrode,” etc.
  • the cathode pad electrode 93 is electrically connected to the base region 14.
  • the cathode pad electrode 93 has a portion facing the high concentration region 10 across the base region 14, and a portion facing the low concentration region 11 across the base region 14.
  • the cathode pad electrode 93 may cover the entire second main surface 4 so as to be continuous with the periphery of the second main surface 4 (first to fourth side surfaces 5A to 5D).
  • the cathode pad electrode 93 may partially cover the second main surface 4 so as to expose the periphery of the second main surface 4.
  • the breakdown voltage that can be applied between the anode pad electrode 92 and the cathode pad electrode 93 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less.
  • the breakdown voltage may have a value that belongs to at least one of the following ranges: 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.
  • FIG. 20 is a cross-sectional view showing semiconductor device 1G according to the seventh embodiment.
  • Figure 21 is a cross-sectional view showing semiconductor device 1H according to the eighth embodiment.
  • Figure 22 is a cross-sectional view showing semiconductor device 1I according to the ninth embodiment.
  • semiconductor device 1G has a configuration in which semiconductor device 1F is combined with high concentration region 10 and low concentration region 11 of semiconductor device 1B (see FIG. 12).
  • semiconductor device 1H has a configuration in which semiconductor device 1F is combined with high concentration region 10 and low concentration region 11 of semiconductor device 1C (see FIG. 13 and FIG. 14).
  • semiconductor device 1I has a configuration in which semiconductor device 1F is combined with high concentration region 10, low concentration region 11 and outer high concentration region 15 of semiconductor device 1D (see FIG. 15).
  • FIG. 23 is a cross-sectional view showing a modified example of the outer body region 21.
  • FIG. 23 illustrates a configuration in which the modified example is applied to semiconductor device 1A (first embodiment), but the modified example can be applied to all of semiconductor devices 1A to 1I (first to ninth embodiments).
  • the outer body region 21 was formed at a distance inward from the periphery of the high concentration region 10.
  • the outer edge of the outer body region 21 may cross the periphery of the high concentration region 10 and be located in the low concentration region 11.
  • the outer body region 21 may be located in the surface layer of the low concentration region 11 in the peripheral region 9, and may have a portion (outer edge portion) that forms a pn junction with the low concentration region 11.
  • the depletion layer extends directly from the outer body region 21 to the low concentration region 11. Therefore, the range of the depletion layer is appropriately expanded in the peripheral portion (peripheral region 9) of the chip 2.
  • the termination region 40 is located on the peripheral side of the chip 2 relative to the peripheral portion of the high concentration region 10 in the surface portion of the low concentration region 11. In other words, the entire termination region 40 is located on the surface portion of the low concentration region 11.
  • the inner edge of the termination region 40 is connected to the outer edge of the outer body region 21 in the surface portion of the low concentration region 11. In other words, the termination region 40 forms an overlap region 41 with the outer body region 21 in the surface portion of the low concentration region 11.
  • the depletion layer extends directly from the entire termination region 40 to the low concentration region 11. Therefore, the range of the depletion layer is appropriately extended in the peripheral portion (peripheral region 9) of the chip 2.
  • the termination region 40 has a p-type impurity concentration approximately equal to the p-type impurity concentration of the outer body region 21, and may be formed as part of the outer body region 21 (the pull-out portion).
  • FIG. 24 is a cross-sectional view showing a modified example of the field region 42.
  • FIG. 24 illustrates a configuration in which the modified example is applied to semiconductor device 1A (first form), but the modified example can be applied to all of semiconductor devices 1A to 1I (first to ninth forms).
  • an example was shown in which multiple field regions 42 were formed in the surface layer of the low concentration region 11.
  • a single field region 42 may also be formed in the surface layer of the low concentration region 11.
  • the single field region 42 is formed in a region between the termination region 40 and the outer body region 21, spaced inward from the periphery of the first main surface 3.
  • the single field region 42 extends in a band along the termination region 40 in a planar view.
  • the single field region 42 has a portion that extends in a band in the first direction X and a portion that extends in a band in the second direction Y in a planar view, and partitions the active region 8 from multiple directions.
  • the single field region 42 surrounds the termination region 40 in a plan view and is partitioned into a polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3.
  • the single field region 42 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quadrant arc shape) in a plan view.
  • the ratio of the width of the single field region 42 to the width of the low concentration region 11 may be 0.1 or more and less than 1.
  • the width ratio may have a value that belongs to at least one of the following ranges: 0.1 or more and 0.2 or less, 0.2 or more and 0.4 or less, 0.4 or more and 0.6 or less, 0.6 or more and 0.8 or less, and 0.8 or more and less than 1.
  • the single field region 42 is formed at a distance from the bottom of the low concentration region 11 toward the first main surface 3, and faces the base region 14 across a portion of the low concentration region 11.
  • the single field region 42 is formed at a distance from the depth position of the bottom of the high concentration region 10 toward the first main surface 3. It is preferable that the single field region 42 is formed at a distance from the depth position of the middle part of the high concentration region 10 toward the first main surface 3.
  • the single field region 42 may cross the depth position of the middle part of the high concentration region 10 in the thickness direction.
  • the single field region 42 has an inner edge on the termination region 40 side and an outer edge on the peripheral side of the first main surface 3.
  • the inner edge of the single field region 42 is connected to the outer edge of the termination region 40.
  • the single field region 42 is electrically connected to the termination region 40.
  • the inner edge of the single field region 42 is connected to the outer edge of the termination region 40 around the entire periphery.
  • the single field region 42 When the single field region 42 has a p-type impurity concentration approximately equal to the p-type impurity concentration of the termination region 40, the single field region 42 may be extended from the termination region 40 to the surface portion of the low concentration region 11 as an extension portion of the termination region 40. In other words, the termination region 40 may have a single field region 42 as an extension portion. Of course, the single field region 42 may be formed at a distance from the termination region 40.
  • FIG. 25 is a cross-sectional view showing a first modified example of the source pad electrode 60.
  • FIG. 25 illustrates a configuration in which the modified example is applied to the semiconductor device 1A (first form), but the modified example can be applied to all of the semiconductor devices 1A to 1E (first to fifth forms).
  • the multiple first buried electrodes 62 are buried in the multiple source openings 54 so as to expose the insulating surface 51.
  • the source pad electrode 60 may have multiple first buried electrodes 62 that are pulled out from the multiple source openings 54 onto the insulating surface 51 and cover the insulating surface 51.
  • the multiple first buried electrodes 62 cover the first base electrode film 61 on the insulating surface 51, and have a portion that covers the insulating surface 51 with the first base electrode film 61 in between.
  • the multiple first buried electrodes 62 each have a first buried electrode surface 66 that is exposed from the multiple source openings 54 above the insulating surface 51.
  • the multiple first buried electrodes 62 have a portion that faces the gate electrode 32 with the first base electrode film 61 and interlayer film 50 in between in the stacking direction (vertical direction Z).
  • the multiple first buried electrodes 62 are integrated on the insulating surface 51 to form a single intermediate electrode 95.
  • the intermediate electrode 95 (multiple first buried electrodes 62) covers the entire area of the first base electrode film 61.
  • the electrode surface (first buried electrode surface 66) of the intermediate electrode 95 is positioned above the insulating surface 51.
  • the first main electrode film 63 is mechanically and electrically connected to the first buried electrode surfaces 66 of the multiple first buried electrodes 62 (intermediate electrodes 95) above the insulating surface 51.
  • the first main electrode film 63 has a portion that faces the insulating surface 51, sandwiching the multiple first buried electrodes 62 (intermediate electrodes 95).
  • the first main electrode film 63 does not have a mechanical connection to the first base electrode film 61.
  • the configuration of the multiple first buried electrodes 62 (intermediate electrodes 95) in the modified example can also be applied to the multiple first buried electrodes 62 of the source finger electrodes 68.
  • the configuration of the multiple first buried electrodes 62 (intermediate electrodes 95) in the modified example can also be applied to the multiple second buried electrodes 72 of the gate finger electrodes 70.
  • FIG. 26 is a cross-sectional view showing a second modified example of the source pad electrode 60.
  • FIG. 26 illustrates an example in which the configuration of the modified example is applied to the semiconductor device 1A (first form), but the configuration of the modified example is applicable to all of the semiconductor devices 1A to 1E (first to fifth forms).
  • the source pad electrode 60 has a plurality of first buried electrodes 62.
  • the source pad electrode 60 does not necessarily have to have a first buried electrode 62.
  • the first main electrode film 63 of the source pad electrode 60 penetrates into the plurality of source openings 54 from above the interlayer film 50, and is electrically connected to the body region 20, etc., within the plurality of source openings 54.
  • the source finger electrode 68 does not necessarily have to have the first buried electrode 62.
  • the first main electrode film 63 of the source finger electrode 68 enters the multiple outer openings 56 from above the interlayer film 50 and is electrically connected to the termination region 40 (overlap region 41) within the multiple outer openings 56.
  • the gate finger electrode 70 does not necessarily have to have the second buried electrode 72.
  • the second main electrode film 73 of the gate finger electrode 70 penetrates into the multiple gate openings 58 from above the interlayer film 50 and is electrically connected to the gate wiring 44 within the multiple gate openings 58.
  • Semiconductor devices 1A to 1E may have a first buried electrode 62 associated with a source pad electrode 60, but may not have a first buried electrode 62 associated with a source finger electrode 68. Semiconductor devices 1A to 1E may have a first buried electrode 62 associated with a source finger electrode 68, but may not have a first buried electrode 62 associated with a source pad electrode 60.
  • Semiconductor devices 1A to 1E may have a first buried electrode 62 associated with the source pad electrode 60, but may not have a second buried electrode 72. Semiconductor devices 1A to 1E may have a second buried electrode 72, but may not have a first buried electrode 62 associated with the source pad electrode 60. Semiconductor devices 1A to 1E may have a first buried electrode 62 associated with the source finger electrode 68, but may not have a second buried electrode 72. Semiconductor devices 1A to 1E may have a second buried electrode 72, but may not have a first buried electrode 62 associated with the source finger electrode 68.
  • the chip 2 including a SiC single crystal is used.
  • the chip 2 may include a single crystal of a wide band gap semiconductor other than a SiC single crystal.
  • a wide band gap semiconductor is a semiconductor that has a band gap larger than the band gap of silicon. Examples of single crystals of wide band gap semiconductors include gallium nitride, gallium oxide, diamond, etc.
  • the chip 2 may also include a silicon single crystal.
  • the first semiconductor layer 6 may contain a single crystal of a wide band gap semiconductor other than a SiC single crystal.
  • the first semiconductor layer 6 may contain gallium nitride, gallium oxide, diamond, etc.
  • the first semiconductor layer 6 may contain a silicon single crystal.
  • the second semiconductor layer 7 may contain a single crystal of a wide band gap semiconductor other than a SiC single crystal.
  • the second semiconductor layer 7 may contain gallium nitride, gallium oxide, diamond, etc.
  • the second semiconductor layer 7 may also contain a silicon single crystal.
  • an n-type base region 14 is shown.
  • a p-type base region 14 may be used instead of the n-type base region 14.
  • an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of the MISFET structure.
  • the "source” of the MISFET structure is replaced with the "emitter” of the IGBT structure, and the "drain” of the MISFET structure is replaced with the "collector” of the IGBT structure.
  • the p-type base region 14 may be an impurity region containing p-type impurities introduced into the surface layer of the second main surface 4 of the chip 2 (n-type chip 2) by ion implantation.
  • the diode structure Di may include at least one of a pn junction diode, a pin junction diode, a Zener diode, and a fast recovery diode.
  • the diode structure Di may include one or more p-type anode regions that form a pn junction with the high concentration region 10 in the surface layer portion of the high concentration region 10.
  • a semiconductor device (1A-1I) including a chip (2) having a main surface (3), a high concentration region (10) of a first conductivity type (n-type) formed on the surface layer of the main surface (3) on the inner side of the chip (2), and a low concentration region (11) of the first conductivity type (n-type) formed on the surface layer of the main surface (3) on the peripheral side of the chip (2) and having an impurity concentration lower than the impurity concentration of the high concentration region (10).
  • n-type first conductivity type
  • n-type first conductivity type
  • a semiconductor device (1A-1I) including a chip (2) having a main surface (3), an active region (8) provided in the inner part of the main surface (3), an outer peripheral region (9) provided on the periphery of the main surface (3), a high concentration region (10) of a first conductivity type (n-type) formed in the surface layer of the main surface (3) in the active region (8), and a low concentration region (11) of a first conductivity type (n-type) formed in the surface layer of the main surface (3) in the outer peripheral region (9) and having an impurity concentration lower than the impurity concentration of the high concentration region (10).
  • p-type second conductivity type

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002134749A (ja) * 2000-10-30 2002-05-10 Shindengen Electric Mfg Co Ltd 電界効果トランジスタ
JP2006013552A (ja) * 2005-09-21 2006-01-12 Shindengen Electric Mfg Co Ltd 半導体デバイスの製造方法
JP2013069784A (ja) * 2011-09-21 2013-04-18 Toshiba Corp 電力用半導体装置
JP2017168507A (ja) * 2016-03-14 2017-09-21 富士電機株式会社 半導体装置及びその製造方法
JP2021057367A (ja) * 2019-09-26 2021-04-08 富士電機株式会社 窒化ガリウム半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002134749A (ja) * 2000-10-30 2002-05-10 Shindengen Electric Mfg Co Ltd 電界効果トランジスタ
JP2006013552A (ja) * 2005-09-21 2006-01-12 Shindengen Electric Mfg Co Ltd 半導体デバイスの製造方法
JP2013069784A (ja) * 2011-09-21 2013-04-18 Toshiba Corp 電力用半導体装置
JP2017168507A (ja) * 2016-03-14 2017-09-21 富士電機株式会社 半導体装置及びその製造方法
JP2021057367A (ja) * 2019-09-26 2021-04-08 富士電機株式会社 窒化ガリウム半導体装置

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