WO2024164597A1 - 用于扫描测试的电路系统、方法、装置、介质和程序产品 - Google Patents

用于扫描测试的电路系统、方法、装置、介质和程序产品 Download PDF

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Publication number
WO2024164597A1
WO2024164597A1 PCT/CN2023/130358 CN2023130358W WO2024164597A1 WO 2024164597 A1 WO2024164597 A1 WO 2024164597A1 CN 2023130358 W CN2023130358 W CN 2023130358W WO 2024164597 A1 WO2024164597 A1 WO 2024164597A1
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Prior art keywords
observation
value
misr
scan
shift
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PCT/CN2023/130358
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English (en)
French (fr)
Inventor
黄宇
王柳峥
王亚宁
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华为技术有限公司
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Publication of WO2024164597A1 publication Critical patent/WO2024164597A1/zh

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3177—Testing of logic operation, e.g. by logic analysers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/333—Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]

Definitions

  • Embodiments of the present disclosure generally relate to the field of chip design tools. More specifically, embodiments of the present disclosure relate to circuit systems, methods, devices, apparatuses, computer-readable storage media, and computer program products for scan testing.
  • EDA Electronic design automation
  • chip testing can be used to select chips with defects due to problems such as process and material during the manufacturing and packaging process.
  • Chip testing can be performed efficiently using EDA tools.
  • DFT structures such as scan chains can be added to the chip during the design phase.
  • a test vector generator can be used to generate a test pattern to input into the chip to be tested. The chip can be tested by comparing whether the test response of the chip under test is consistent with the expected response.
  • the difficulty of chip testing also increases. Therefore, an efficient chip testing solution is expected to reduce the time and cost of chip testing.
  • an embodiment of the present disclosure provides a solution for scan testing.
  • a circuit system for scan testing includes: a first observation unit configured to generate a first scan observation value based on a first shift value and a value at a first observation point in a circuit to be tested in a test response compression mode; and a second observation unit connected in series with the first observation unit to form a multi-input feature register MISR with a feedback path, wherein the second observation unit is configured to generate a second scan observation value based on the first scan observation value, a second shift value and a value at a second observation point in the circuit to be tested in the test response compression mode, wherein at least one of the first scan observation value and the second scan observation value is used to observe a fault in the circuit to be tested.
  • the MISR is configured to, in a feature-out mode, shift the second scan observation out of the MISR as at least a portion of a feature value of the MISR. In some embodiments of the first aspect, the MISR is configured to, in the test response compression mode, shift the first scan observation out of the MISR.
  • the circuit system further comprises a second MISR connected to the MISR, the second MISR being configured to: operate independently of the MISR or receive scanned observations output by the MISR as input in the test response compression mode.
  • the second observation unit includes: a signal combiner, configured to generate a first combined value at a first output of the signal combiner based on the first scanned observation value, the second shift value and the value at the second observation point in the test response compression mode; and a scanning unit, configured to generate the second scanned observation value based on the first combined value in the test response compression mode.
  • the signal combiner is further configured to generate a second combined value at the first output of the signal combiner based on the second shift value in a feature shift-out mode; and the scanning unit is further configured to generate an output value identical to the second combined value based on the second combined value in the feature shift-out mode.
  • the signal combiner comprises: an AND gate configured to receive the use of the test response compression mode an AND signal and a value at the second observation point; a first XOR gate configured to generate a first XOR value based on the second shift value and the first scan observation value; and a second XOR gate configured to generate a value at the first output of the signal combiner based on the output of the AND gate and the first XOR value.
  • the first XOR gate is associated with the feedback path of the MISR.
  • the circuit system further comprises a plurality of scan chains configured to test the circuit under test, the plurality of scan chains being in a compressed scan mode or a non-compressed scan mode.
  • the plurality of scan chains are configured to shift in a test vector and drive the circuit under test, and the MISR is configured to capture a plurality of values at a plurality of observation points in the circuit under test and compress the plurality of values to generate a plurality of scan observation values.
  • the plurality of scan chains are configured to capture corresponding test responses from a plurality of functional logic connection points in the circuit under test, and the MISR is configured to capture a plurality of values at a plurality of observation points in the circuit under test and compress the plurality of values to generate a plurality of scan observation values.
  • a method for scan testing includes: shifting an input vector for observing faults in a circuit to be tested into a multi-input feature register MISR including a plurality of observation units connected in series and having a feedback path; obtaining a plurality of scan observation values generated by the MISR based on a plurality of values captured at a plurality of observation points in the circuit to be tested in a test response compression mode and the input vector; and determining the faults in the circuit to be tested based on the plurality of scan observation values.
  • the plurality of observation units include: a first observation unit configured to generate a first scan observation value based on a first shift value and a value at a first observation point in the circuit to be tested in the test response compression mode; and a second observation unit configured to generate a second scan observation value based on the first scan observation value, a second shift value and a value at a second observation point in the circuit to be tested in the test response compression mode.
  • a device comprising: a vector shift unit configured to shift an input vector for observing a fault in the circuit under test into a multi-input feature register MISR including a plurality of observation units connected in series and having a feedback path; an observation value acquisition unit configured to acquire a plurality of scanned observation values generated by the MISR based on a plurality of values captured at a plurality of observation points in the circuit under test in a test response compression mode and the input vector; and a fault determination unit configured to determine the fault in the circuit under test based on the plurality of scanned observation values.
  • the plurality of observation units comprise: a first observation unit configured to generate a first scanned observation value based on a first shift value and a value at a first observation point in the circuit under test in the test response compression mode; and a second observation unit configured to generate a second scanned observation value based on the first scanned observation value, a second shift value and a value at a second observation point in the circuit under test in the test response compression mode.
  • an electronic device comprising: at least one computing unit; and at least one memory, wherein the at least one memory is coupled to the at least one computing unit and stores instructions for execution by the at least one computing unit, and when the instructions are executed by the at least one computing unit, the device implements the method provided in the second aspect.
  • a computer-readable storage medium on which a computer program is stored, wherein the computer program is executed by a processor to implement the method provided in the second aspect.
  • a computer program product comprising computer executable instructions, which implement part or all of the steps of the method of the second aspect when the instructions are executed by a processor.
  • the device of the third aspect, the electronic device of the fourth aspect, the computer storage medium of the fifth aspect, or the computer program product of the sixth aspect provided above are all used to execute the method provided by the second aspect.
  • the explanation or description of the first aspect is also applicable to the second aspect, the third aspect, the fourth aspect, the fifth aspect, and the sixth aspect.
  • the beneficial effects that can be achieved in the second aspect, the third aspect, the fourth aspect, the fifth aspect, and the sixth aspect can refer to the beneficial effects in the corresponding circuit system, which will not be repeated here.
  • FIG1 shows a flow chart of the chip design and manufacturing process
  • FIG2 shows a schematic diagram of an example environment in which various embodiments of the present disclosure can be implemented
  • FIG3 shows a schematic diagram of an example observation unit according to some embodiments of the present disclosure
  • FIG. 4 shows a schematic diagram of an example observation unit including a logic gate and a scanning unit according to some embodiments of the present disclosure
  • FIG5 shows a schematic diagram of a first example of a circuit system for scan testing according to some embodiments of the present disclosure
  • FIG6 shows a schematic diagram of a second example of a circuit system for scan testing according to some embodiments of the present disclosure
  • FIG7 is a schematic diagram showing control signals and clock signals in a scan test according to some embodiments of the present disclosure.
  • FIG8 shows a schematic diagram of a first circuit system including a plurality of MISRs according to some embodiments of the present disclosure
  • FIG9 shows a schematic diagram of a second circuit system including a plurality of MISRs according to some embodiments of the present disclosure
  • FIG10 is a schematic block diagram showing an example process of a method for scan testing according to some embodiments of the present disclosure
  • FIG11 shows a schematic block diagram of an apparatus for scan testing according to some embodiments of the present disclosure.
  • FIG. 12 illustrates a block diagram of a computing device capable of implementing various embodiments of the present disclosure.
  • a test circuit can be constructed to test the circuit to be tested in the same chip.
  • the test circuit can include a testability design such as a scan chain.
  • the scan chain includes a plurality of "shift registers (also called scan cells)" connected by triggers in a sequential circuit, and the input and output of each shift register can be observed separately.
  • shift registers also called scan cells
  • each scanning unit may include a data input port D, a shift input port SI, a shift enable input port SE and one output port Q. Except for the scanning units at the head and tail of the scan chain, each scanning unit may be connected to the output port Q of the previous scanning unit through its shift input port SI. Based on the control of the shift enable signal (se), the scanning unit may have a shift mode and a capture mode.
  • the test vector is input from the shift input port SI of the scan unit and shifted on the scan chain through the first connected scan unit.
  • the output port Q of the scan unit drives the combinational logic in the circuit under test, and the combinational logic outputs the corresponding value through the data input port D of the scan unit connected to it.
  • each scan unit can enter the capture mode. In the capture mode, each time the clock signal jumps, the scan unit will capture the value of the current data input port D. After one or more capture cycles, each scan unit enters the feature shift-out mode again. In the feature shift-out mode, the captured value is shifted out from the output port of the scan chain one by one for comparison with the preset correct value. If the combinational logic has a fault and is stimulated by the current test vector, the fault can be detected by the difference between the shifted value and the correct value.
  • a circuit system for scan testing includes a first observation unit and a second observation unit connected in series with the first observation unit to form a multi-input signature register (MISR) with a feedback path.
  • the first observation unit is configured to generate a first scan observation value based on a first shift value and a value at a first observation point in a circuit to be tested in a test response compression mode.
  • the second observation unit is configured to generate a second scan observation value based on the first scan observation value, the second shift value and the value at a second observation point in the circuit to be tested in a test response compression mode.
  • FIG. 1 shows a flow chart of a chip design and manufacturing process 100.
  • the design and manufacturing process 100 begins with specification formulation 110.
  • specification formulation 110 the requirements for the functions and performances that the integrated circuit needs to achieve are determined.
  • circuit design 120 circuit design is performed with the aid of EDA software to obtain, for example, a layout file for chip manufacturing. Based on the difference in circuits (e.g., digital circuits or analog circuits), the design 120 may include different design links.
  • integrated circuits are formed on wafers through processes such as photolithography, etching, ion implantation, thin film deposition, and polishing.
  • the wafer is cut to obtain a bare die, and the bare die is packaged to obtain a chip through processes such as pasting, welding, and mold sealing.
  • the obtained chip is tested at the stage of testing 160 to ensure that the performance of the finished chip meets the requirements determined in the specification formulation 110.
  • the chip 170 that passes the test can be delivered to the customer. It can be understood that the above process is only illustrative and does not limit the scope of the present disclosure.
  • the design and manufacturing process of the chip may be different. For example, tape-out may be performed before manufacturing 140. A small number of chips obtained from the tape-out may be used for testing to verify whether the chip design meets expectations. If it does not meet expectations, this indicates that the tape-out has failed and the chip design may need to be adjusted or redesigned.
  • Functional simulation 125 is also called RTL-level behavioral simulation or front-end simulation.
  • the purpose of functional simulation is to analyze the correctness of the logical relationship of the design circuit.
  • Synthesis 127 can convert RTL into a gate-level netlist.
  • Synthesis 127 may include, for example, translation, optimization, and mapping.
  • the EDA software used for synthesis may first convert the RTL code into a general Boolean equation and compile it.
  • the netlist may be optimized according to the constraints imposed by the designer, such as delay and area, and then the RTL netlist may be mapped to the process library to generate a gate-level netlist.
  • Timing analysis 129 is usually static timing analysis, which mainly involves the calculation and prediction of the timing of digital circuits. Timing analysis is performed on the paths in the digital circuit to determine whether timing convergence is achieved, thereby ensuring whether the timing of various circuits meets various timing requirements. The verification of such digital circuits is usually completed statically and does not require simulation of digital logic.
  • various hardware logics for improving chip testability can be embedded in the design. By using this part of logic, test vectors can be generated to achieve the purpose of testing large-scale digital circuits.
  • DFT can, for example, include a scan chain-based test method or a built-in self-test circuit (BIST).
  • the circuit can be formally verified and/or equivalence checked.
  • Formal verification can use mathematical methods to prove its correctness or incorrectness based on one or more formal specifications or attributes.
  • Formal verification can include, for example, abstract interpretation, formal model checking (also known as property checking), and theory prover.
  • Equivalence checking can be used to verify whether the register transfer level design is consistent with the gate level netlist, and between the gate level netlist and the gate level netlist.
  • the chip circuit can be laid out (placement) and routed (routing).
  • the layout can reasonably arrange the gate-level netlist generated by logic synthesis 127 in a rectangular area corresponding to the chip based on considerations such as area, critical path delay length, and power consumption. After this, the various components or sub-circuits that have been laid out can be routed to connect them. Routing generally expects the total routing to be short, the routing delay to meet the timing requirements, and to comply with the routing rules in the process (such as routing density).
  • layout and routing are described separately here, this is only illustrative and does not limit the scope of the present disclosure. In some cases, layout and routing can be performed simultaneously or alternately to achieve optimization of layout and routing.
  • the layout can be checked for potential open circuits, short circuits or adverse effects caused by violations of design rules.
  • a file representing the layout such as a GDSII file, can be generated 139 by the EDA software.
  • FIG2 shows a schematic diagram of an example environment 200 in which various embodiments of the present disclosure can be implemented.
  • a MISR 202 including a plurality of observation units e.g., observation units 210, 220, 230, and 240
  • a MISR 202 can capture a plurality of corresponding values from a plurality of observation points in the circuit under test 201, and compress the captured plurality of values into characteristic values of the MISR using a feedback path of the MISR 202 for observing faults in the circuit under test 201.
  • the input vector for observing the fault in the circuit under test 201 is input from the input terminal of the MISR 202.
  • the gate is shifted into MISR 202.
  • Each observation unit in MISR 202 generates a scanned observation value based on the input vector or the value at the corresponding observation point in the previous timing gate and the circuit under test 201 (as well as feedback from one or more observation units, which may include the observation unit itself).
  • the scanned observation value is shifted into the next observation unit or out of MISR 202 for observing the fault in the circuit under test 201. Based on the comparison of the scanned observation value with the preset correct value, it can be determined whether there is a fault in the circuit under test 201.
  • the preset correct value can be determined based on the input vector shifted into MISR 202.
  • the observation unit 240 is configured to generate a first scan observation value based on the first shift value output from the observation unit 230 and the value at the first observation point in the circuit under test 201 in the test response compression mode.
  • the first scan value is fed back to the observation unit 210 based on the first feedback path.
  • the observation unit 210 is configured to generate a second scan observation value based on the first scan observation value, the second shift value and the value at the second observation point in the circuit under test 201 in the test response compression mode.
  • the second shift value may be at least a portion of the input vector shifted in.
  • the second shift value may be a value output by a previous observation unit of the observation unit 210.
  • the second scanning observation value is input to the observation unit 220.
  • the observation unit 220 is configured to generate a third scanning observation value based on the second scanning observation value and the value at the third observation point in the circuit under test 201.
  • the third scanning observation value is input to the observation unit 230.
  • the observation unit 230 is configured to generate a fourth scanning observation value based on the third scanning observation value and the value at the fourth observation point in the circuit under test 201.
  • the fourth scanning observation value is input to the observation unit 240.
  • the observation unit 240 is configured to generate a new scanning observation value based on the fourth scanning observation value as a new shift value and the new value at the first observation point in the circuit under test 201.
  • the scanned observations may be shifted out of the MISR 202 in a feature shift-out mode.
  • the corresponding scanned observations generated by the observation units 210, 220, 230, and 240 may be shifted out of the MISR 202 one by one as feature values of the MISR 202.
  • Each corresponding scanned observation generated by the observation units 210, 220, 230, and 240 may be considered as part of the feature value of the MISR 202.
  • the scanned observations may be shifted out of MISR 202 in the test response compression mode.
  • an observation unit e.g., observation unit 240
  • MISR 202 may shift out the scanned observations generated in the corresponding cycle in each shift cycle.
  • This mode may also be referred to as a test response continuous shift-out mode.
  • MISR 202 may include two feedback paths, namely, a first feedback path from observation unit 240 to observation unit 210 and a second feedback path from observation unit 240 to observation unit 240 itself. It should be understood that in some embodiments, MISR 202 may include more or fewer feedback paths. In addition, MISR 202 may include a feedback path that is different from the first feedback path and the second feedback path.
  • the environment 200 shown in FIG2 is merely exemplary and does not constitute a limitation on the scope of the present disclosure.
  • the number of observation units may be any suitable value, and the feedback paths between observation units may be different from the example in FIG2 .
  • the observation unit 300 may be a specific implementation of the observation units 210, 220, 230, and 240. As shown in FIG3 , the observation unit 300 may include a signal combiner 310 and a scanning unit 320.
  • the first input of the signal combiner 310 may be connected to an observation point in the circuit under test 201.
  • the position of the observation point may be selected so that the observation unit can observe faults in the circuit under test 201 that are difficult to be observed by ordinary scan units in the scan chain.
  • the faults in the circuit under test 201 may be transmitted from the observation point to the observation unit through the logic cone, thereby improving the test coverage.
  • the second input of the signal combiner 310 can be connected to the output of the previous observation unit or the generator of the input vector.
  • the second input of the signal combiner in the observation unit 210 can directly receive the input vector.
  • the second input of the signal combiner in the observation unit 220 can receive the scan observation value generated by the observation unit 210 in the previous shift cycle.
  • the first output and the second output of the signal combiner 310 are respectively connected to corresponding inputs of the scanning unit 320.
  • the scanning unit 320 may include a D terminal associated with a value at an observation point, an SI terminal associated with an output or input vector of a previous observation unit, an SE terminal associated with an enable signal of a test response compression mode, and an output Q terminal.
  • the observation unit 300 is configured to operate in a feature shift-out mode, a test response compression mode, and a circuit operation mode.
  • the signal combiner 310 is configured to generate a first combined value at the first output (the output corresponding to the SI terminal) of the signal combiner 310 based on the value at the observation point in the circuit under test 201 and the shift value or input vector output by a previous observation unit (and feedback from one or more observation units, not shown in FIG. 3 ).
  • the scanning unit 320 is configured to generate a scanned observation value based on the first combined value to be output from the Q terminal.
  • the signal combiner 310 is configured to generate a second combined value at the first output (the output corresponding to the SI terminal) of the signal combiner 310 based on the shift value or input vector output by the previous observation unit.
  • the second shift value is the same as the shift value output by a previous observation unit or the value of the input vector shifted in.
  • FIG4 shows a schematic diagram of an example observation unit 400 including a logic gate and a scanning unit according to some embodiments of the present disclosure.
  • the observation unit 400 may be a specific example of the observation unit 300.
  • the signal combiner in the observation unit 400 may include an AND gate 401 and an XOR gate 402.
  • the observation unit 400 may also include a scanning unit 450.
  • the observation unit 400 may include a plurality of input ports and an output port. As shown in the figure, the observation unit 400 may include a feature compression enable port en for receiving an enable signal of a test response compression mode, an observation input port od for receiving a value at an observation point, a shift input port si for receiving a previous timing gate or an input vector initially shifted in, a shift enable port se for receiving a shift enable signal, and a clock input port clk for receiving a clock signal.
  • the observation unit 400 may also include a reset port rn for receiving a trigger reset signal and an output port q for output. The output of the observation unit 400 may be input to the next timing gate or shifted out through the output port of the MISR.
  • Table 1 shows information of ports of the observation unit 400 .
  • AND gate 401 is configured to receive an enable signal of the test response compression mode and a value at an observation point, and generate a value corresponding to the D terminal of the scanning unit 450.
  • XOR gate 402 is configured to generate a value corresponding to the SI terminal of the scanning unit 450 based on the output of AND gate 401 and the last timing gate (e.g., the shift value previously shifted out of the observation unit) or the input vector initially shifted in.
  • the observation unit 400 can be operated in the corresponding working mode.
  • Table 2 shows the working mode of the observation unit 400.
  • the test response compression mode is turned on.
  • the observation unit 400 receives the value of the previous timing gate (for example, the scan observation value output by the previous observation unit) and captures the value at the observation point at the same time, so as to observe the circuit in the shift cycle, so that the fault that can only be captured in the capture process can also be captured in the shift cycle, thereby greatly improving the test efficiency.
  • the previous timing gate for example, the scan observation value output by the previous observation unit
  • FIG5 shows a schematic diagram of a first example of a circuit system for scan testing according to some embodiments of the present disclosure.
  • the circuit system for scan testing the circuit under test 201 may include observation units 510, 520, 530, and 540, and the observation units 510, 520, 530, and 540 are connected in series to form a MISR with two feedback paths.
  • the MISR is configured to receive an input vector from an input port in (or a main input port PI).
  • the MISR can capture corresponding multiple values from multiple observation points in the circuit under test 201, and compress the captured multiple values into characteristic values of the MISR using the feedback path of the MISR.
  • the MISR is also configured to move the characteristic values of the MISR out of the MISR through an output port out (or a main output port PO).
  • the observation unit that receives the feedback value can generate a scan observation value based on the scan observation value generated by the observation unit input by the feedback path in the previous clock cycle, the shift value output by the previous observation unit or the value of the input vector initially shifted in, and the value at the observation point corresponding to itself in the circuit under test.
  • observation units 520 and 530 that are not related to the feedback path can be directly implemented by the observation unit 400 shown in Figure 4.
  • the observation unit 510 associated with the feedback path is further supplemented with an XOR gate 551
  • the observation unit 540 associated with the feedback path is further supplemented with an XOR gate 552.
  • observation unit 400 shown in FIG. 4 may be additionally provided with an XOR gate to implement the observation associated with the feedback path.
  • Units such as observation units 510 and 540.
  • XOR gate 402 does not directly receive the scanned observation value output by the previous observation unit (such as observation unit 530). Instead, the scanned observation value output by the previous observation unit (such as observation unit 530) and the feedback of the observation unit are input to an additional XOR gate (such as XOR gate 551 or 552), and the output of the additional XOR gate and the output of AND gate 401 are input to XOR gate 402.
  • additional XOR gate such as XOR gate 551 or 552
  • an AND gate (e.g., AND gate 561 or 562) is additionally added to the observation unit 400 as shown in FIG4 to receive the enable signal of the test response compression mode and the feedback of the observation unit.
  • the enable signal en of the test response compression mode is set to a high level
  • the test response compression mode is turned on and the MISR is configured to capture the corresponding multiple values from multiple observation points in the circuit under test 201, and the captured multiple values are compressed into the characteristic values of the MISR using the feedback path of the MISR.
  • the test response compression mode When the enable signal en of the test response compression mode is set to a low level and the enable signal se of the characteristic shift-out mode is set to a high level, the test response compression mode is turned off and the characteristic shift-out mode is turned on, and the characteristic values of the generated MISR are shifted out of the MISR.
  • FIG6 shows a schematic diagram of a second example of a circuit system for scan testing according to some embodiments of the present disclosure.
  • the circuit system for performing scan testing on the circuit under test 201 may include observation units 610, 620, 630, and 640, and the observation units 610, 620, 630, and 640 are connected in series to form a MISR with a feedback path.
  • the MISR can capture corresponding multiple values from multiple observation points in the circuit under test 201, and compress the captured multiple values into characteristic values of the MISR using the feedback path of the MISR.
  • observation units 610, 620 and 630 are respectively attached with XOR gates 651, 652 and 653 associated with the feedback path.
  • observation units 610, 620 and 630 are respectively attached with AND gates 663, 664 and 665 for receiving the enable signal of the test response compression mode and the feedback value of the observation unit.
  • each observation unit can receive feedback values from one or more observation units, and can receive feedback values from itself.
  • the feedback value can be a scanned observation value output by the observation unit in the previous cycle.
  • the observation unit 610 can receive feedback values from the observation unit 620 and feedback values from the observation unit 610 itself.
  • the observation unit 620 can receive feedback values from the observation unit 630.
  • the observation unit 630 can receive feedback values from the observation unit 620 and feedback values from the observation unit 630 itself and feedback values from the observation unit 640.
  • an observation unit that receives multiple feedback values can generate a scanned observation value based on multiple scanned observation values generated by multiple observation units input by multiple feedback paths in the previous clock cycle, a shift value output by a previous observation unit or a value of an input vector initially shifted in, and a value at an observation point corresponding to itself in the circuit under test.
  • the observation unit when the observation unit receives feedback values from multiple observation units, that is, when associated with multiple feedback paths, the observation unit may be additionally provided with an XOR gate (e.g., XOR gates 661 and 662).
  • the additional XOR gate is configured to receive feedback values from multiple observation units.
  • the observation unit in the MISR can be used together with multiple scan chains to test the circuit under test 201.
  • each scan chain is configured to shift in a corresponding test vector in a shift cycle, and to obtain a test response from a corresponding functional logic connection point in the circuit under test 201 in a capture cycle. The test response can be shifted out to detect whether there is a fault in the circuit under test 201.
  • multiple scan chains can utilize test compression technology.
  • the test vectors input from a few ports can be expanded to a width equal to the number of scan chains by decompression through a decompressor so as to be simultaneously input into each scan chain.
  • the test response output from the scan chain can be compressed into an output value of a few port widths by a compressor, thereby reducing the number of test vector input and output ports required for the test.
  • multiple scan chains may be operated without utilizing compression scan technology.
  • Figure 7 shows a schematic diagram of control signals and clock signals in a scan test according to some embodiments of the present disclosure.
  • Figure 7 shows the changes of the clock signal clk1 of the scan chain, the shift enable signal se, the enable signal en (at a high level) of the test response compression mode, and the clock signal clk2 of the observation unit in the MISR.
  • the control signals en and se are both high, the scan chain operates in the shift mode and the MISR operates in the test response compression mode.
  • the multiple scan units in the scan chain each shift in the value of the test vector or the previous timing gate, and output a value to drive the circuit under test 201.
  • the multiple observation units in the MISR capture multiple values from the corresponding multiple observation points in the circuit under test 201 while shifting, and use the feedback path to compress the captured multiple values into multiple scan observation values (that is, the characteristic value of the MISR) with the same number of observation units.
  • the control signal en is kept at a high level and the se signal is set to a low level, and the scan chain and the multiple observation units in the MISR are operated in the capture mode.
  • the scan unit in the scan chain obtains the test response from the functional logic connection point in the circuit under test 201 (that is, performs capture).
  • the multiple observation units in the MISR capture multiple values from multiple observation points in the circuit under test 201 and use the feedback path to compress the captured multiple values into multiple scan observation values (that is, the characteristic values of the MISR) with the same number as the observation units.
  • MISR can capture the values at multiple observation points in the circuit under test in both the shift and capture cycles of the scan chain, and can compress the large number of values captured from the multiple observation points into a small number of scan observation values that are the same as the number of observation units, thereby improving the test efficiency. For example, after a long period of testing, it can be determined whether a fault is observed in the circuit under test based only on the compressed small number of scan observation values (i.e., the characteristic values of MISR).
  • multiple observation units in the MISR can operate in a conventional shift mode and a capture mode together with the scan chain. That is, a test vector is shifted in (or a test response is shifted out) or the value of the previous timing gate in a shift cycle, and a test response is captured from the circuit under test in the capture mode.
  • FIG8 shows a schematic diagram of a first circuit system 800 including multiple MISRs according to some embodiments of the present disclosure.
  • the first circuit system 800 includes multiple scan chains in a compressed scan mode.
  • the multiple scan chains receive test vectors generated by a decompressor 801, and the test responses output by the multiple scan chains are compressed by a compressor 802.
  • the first circuit system 800 also includes a MISR 810 and a MISR 820.
  • MISR 810 is connected to an input port PI for receiving an input vector and the output of MISR 810 is connected to the input of MISR 820.
  • MISR 820 is connected to an output port PO for outputting scan observation values.
  • MISR 810 and MISR 820 can work independently. In other words, MISR 820 does not receive the output from MISR 810 as input. MISR 810 and MISR 820 each perform the process of capturing multiple values at the observation point and compressing the multiple values to generate characteristic values. When the test is completed, MISR 810 and 820 enter the characteristic shift-out mode, and the characteristic value of MISR 810 and the characteristic value of MISR 820 are shifted out of the output port PO one by one in the shift cycle for observing faults in the circuit under test.
  • MISR 810 and MISR 820 can work together.
  • MISR 820 receives the output of MISR 810 as input.
  • MISR 820 can output a scan observation value to output port PO for observing faults in the circuit under test in each shift cycle. It should be understood that since the MISR has a separate input port PI and output port PO, interference with the scan chain working with it can be reduced.
  • Fig. 10 is a schematic block diagram of an example process of a method 1000 for scan testing according to some embodiments of the present disclosure.
  • the method 1000 may be executed by any suitable processor, such as a processor implementing EDA software functions.
  • an input vector for observing faults in a circuit under test is shifted into a multi-input feature register MISR including a plurality of observation units connected in series and having a feedback path.
  • the plurality of observation units include a first observation unit and a second observation unit.
  • the first observation unit is configured to generate a first scanned observation value based on a first shift value and a value at a first observation point in the circuit under test in the test response compression mode.
  • the second observation unit is configured to generate a second scanned observation value based on the first scanned observation value, a second shift value and a value at a second observation point in the circuit under test in the test response compression mode.
  • the second observation unit includes: a signal combiner, configured to generate a first combined value at a first output of the signal combiner based on the first scanned observation value, the second shift value and the value at the second observation point in the test response compression mode; and a scanning unit, configured to generate the second scanned observation value based on the first combined value in the test response compression mode.
  • the signal combiner is further configured to generate a second combined value at the first output of the signal combiner based on the second shift value in a feature shift-out mode; and the scanning unit is further configured to generate an output value based on the second combined value in the feature shift-out mode.
  • the signal combiner includes: an AND gate configured to receive an enable signal of the test response compression mode and a value at the second observation point; a first XOR gate configured to generate a first XOR value based on the second shift value and the first scan observation value; and a second XOR gate configured to generate a value at the first output of the signal combiner based on the output of the AND gate and the first XOR value.
  • the first XOR gate is associated with the feedback path of the MISR.
  • a plurality of scanned observation values generated by the MISR based on a plurality of values captured at a plurality of observation points in the circuit under test in a test response compression mode and the input vector are obtained.
  • acquiring the plurality of scan observations includes: in a feature-shift-out mode, shifting the second scan observation out of the MISR as at least a portion of a feature value of the MISR.
  • acquiring the plurality of scan observations comprises: in the test response compression mode, shifting the first scan observation out of the MISR.
  • a fault in the circuit under test is determined based on the plurality of scanned observations.
  • method 1000 also includes: determining a fault in the circuit under test using a second MISR connected to the MISR, wherein the second MISR is configured to: operate independently of the MISR in the test response compression mode, or receive the multiple scanned observation values output by the MISR as input.
  • method 1000 further includes: testing the circuit under test using a plurality of scan chains together with the MISR.
  • the plurality of scan chains are configured to shift in a test vector and drive the circuit under test
  • the MISR is configured to capture a plurality of values at a plurality of observation points in the circuit under test and compress the plurality of values to generate a plurality of scan observation values.
  • the multiple scan chains are configured to capture corresponding test responses from multiple functional logic connection points in the circuit under test
  • the MISR is configured to capture multiple values at multiple observation points in the circuit under test and compress the multiple values to generate multiple scan observation values.
  • FIG. 11 shows a block diagram of an apparatus 1100 for scan testing according to an embodiment of the present disclosure.
  • the apparatus 1100 may be an EDA software apparatus.
  • the apparatus 1100 may include a plurality of modules for performing corresponding steps in the process 1000 as discussed in FIG. 10 .
  • the apparatus 1100 includes a vector shift unit 1110 configured to shift an input vector for observing a fault in the circuit under test into a multi-input feature register MISR including a plurality of observation units connected in series and having a feedback path.
  • MISR multi-input feature register
  • the plurality of observation units include: a first observation unit configured to generate a first scan observation value based on a first shift value and a value at a first observation point in the circuit under test in the test response compression mode; and a second observation unit configured to generate a second scan observation value based on the first scan observation value, a second shift value and a value at a second observation point in the circuit under test in the test response compression mode.
  • the second observation unit includes: a signal combiner, configured to generate a first combined value at a first output of the signal combiner based on the first scanned observation value, the second shift value and the value at the second observation point in the test response compression mode; and a scanning unit, configured to generate the second scanned observation value based on the first combined value in the test response compression mode.
  • the signal combiner is further configured to generate a second combined value at the first output of the signal combiner based on the second shift value in a feature shift-out mode; and the scanning unit is further configured to generate an output value based on the second combined value in the feature shift-out mode.
  • the signal combiner includes: an AND gate configured to receive an enable signal of the test response compression mode and a value at the second observation point; a first XOR gate configured to generate a first XOR value based on the second shift value and the first scan observation value; and a second XOR gate configured to generate a value at the first output of the signal combiner based on the output of the AND gate and the first XOR value.
  • the first XOR gate is associated with the feedback path of the MISR.
  • the apparatus 1100 further includes an observation value acquisition unit 1120, which is configured to acquire a plurality of scanned observation values generated by the MISR based on a plurality of values captured at a plurality of observation points in the circuit under test in a test response compression mode and the input vector.
  • the apparatus 1100 further includes a fault determination unit 1130, which is configured to determine a fault in the circuit under test based on the plurality of scanned observation values.
  • the observation value acquisition unit 1120 is configured to: in a feature removal mode, remove the second scan observation value as at least a part of the feature value of the MISR out of the MISR.
  • the observation acquisition unit 1120 is configured to: in the test response compression mode, move the first scan observation out of the MISR.
  • the device 1100 also includes a multi-MISR test unit, which is configured to determine a fault in the circuit under test using a second MISR connected to the MISR, wherein the second MISR is configured to: operate independently of the MISR in the test response compression mode, or receive the multiple scanned observation values output by the MISR as input.
  • a multi-MISR test unit which is configured to determine a fault in the circuit under test using a second MISR connected to the MISR, wherein the second MISR is configured to: operate independently of the MISR in the test response compression mode, or receive the multiple scanned observation values output by the MISR as input.
  • FIG. 12 shows a schematic block diagram of an example device 1200 that can be used to implement an embodiment of the present disclosure.
  • the device 1200 includes a computing unit 1201, which can perform various appropriate actions and processes according to computer program instructions stored in a random access memory (RAM) 1203 and/or a read-only memory (ROM) 1202 or computer program instructions loaded from a storage unit 1208 into the RAM 1203 and/or ROM 1202.
  • RAM random access memory
  • ROM read-only memory
  • Various programs and data required for the operation of the device 1200 can also be stored in the RAM 1203 and/or ROM 1202.
  • the computing unit 1201 and the RAM 1203 and/or ROM 1202 are connected to each other via a bus 1204.
  • An input/output (I/O) interface 1205 is also connected to the bus 1204.
  • a number of components in the device 1200 are connected to the I/O interface 1205, including: an input unit 1206, such as a keyboard, a mouse, etc.; an output unit 1207, such as various types of displays, speakers, etc.; a storage unit 1208, such as a disk, an optical disk, etc.; and a communication unit 1209, such as a network card, a modem, a wireless communication transceiver, etc.
  • the communication unit 1209 allows the device 1200 to exchange information/data with other devices through a computer network such as the Internet and/or various telecommunication networks.
  • the computing unit 1201 may be a variety of general and/or special processing components with processing and computing capabilities. Some examples of the computing unit 1201 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc.
  • the computing unit 1201 performs the various methods and processes described above, such as process 1000.
  • process 1000 may be implemented as a computer software program, specifically an EDA program, which is tangibly contained in a machine-readable medium, such as a storage unit 1208.
  • part or all of the computer program may be loaded and/or installed on the device 1200 via RAM and/or ROM and/or communication unit 1209.
  • the computer program When the computer program is loaded into RAM and/or ROM and executed by the computing unit 1201, one or more steps of the process 1000 described above may be performed.
  • the computing unit 1201 may be configured to perform the process 1000 in any other suitable manner (eg, by means of firmware).

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Abstract

本公开的实施例提供了用于扫描测试的电路系统、方法、装置、介质和程序产品，涉及芯片设计工具领域。所提供的电路系统包括第一观测单元以及与第一观测单元串联连接以形成具有反馈路径的多输入特征寄存器(multi-input signature register,MISR)的第二观测单元。第一观测单元被配置为在测试响应压缩模式中，至少基于第一移位值和待测电路中的第一观测点处的值，生成第一扫描观测值。第二观测单元被配置为在测试响应压缩模式中，基于第一扫描观测值、第二移位值和待测电路中的第二观测点处的值，生成第二扫描观测值。以此方式，通过在移位周期中捕获待测电路中的观测点处的多个值，并且将多个值压缩为用于观测故障的扫描观测值，可以提高芯片测试的效率。

Description

用于扫描测试的电路系统、方法、装置、介质和程序产品
本申请要求于2023年2月8日提交中国专利局、申请号为202310152290.0、发明名称为“用于扫描测试的电路系统、方法、装置、介质和程序产品”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开的实施例主要涉及芯片设计工具领域。更具体地，本公开的实施例涉及用于扫描测试的电路系统、方法、装置、设备、计算机可读存储介质以及计算机程序产品。
背景技术
电子设计自动化(electronic design automation，EDA)软件被广泛应用于芯片的设计。借助于各种EDA软件，工程师可以方便地进行芯片的设计，例如架构设计和寄存器传输级(register-transfer level,RTL)代码设计、综合(synthesis)、可测性设计(design for test，DFT)、物理实现(physical development)以及签核(signoff)等。
作为芯片设计和制造过程中重要的一环，芯片测试可以用来挑选在制造和封装过程中由于诸如工艺和材料问题而具有缺陷的芯片。利用EDA工具可以高效地进行芯片测试。通常，在设计阶段可以在芯片中添加诸如扫描链(scan chain)之类的DFT结构。在测试阶段，可以利用测试向量生成器生成测试向量(test pattern)以输入到待测芯片中。通过比较被测芯片的测试响应与预期响应是否一致，可以对芯片进行测试。随着芯片集成度和复杂度的不断提高，芯片测试的难度也随之增加。因此，期望一种高效的芯片测试方案以减少芯片测试的时间和成本。
发明内容
鉴于上述问题，本公开的实施例提供了一种用于扫描测试的方案。
在本公开的第一方面，提供了用于扫描测试的电路系统。电路系统包括：第一观测单元，被配置为在测试响应压缩模式中，基于第一移位值和待测电路中的第一观测点处的值，生成第一扫描观测值；以及第二观测单元，与所述第一观测单元串联连接以形成具有反馈路径的多输入特征寄存器MISR，所述第二观测单元被配置为在所述测试响应压缩模式中，基于所述第一扫描观测值、第二移位值和所述待测电路中的第二观测点处的值，生成第二扫描观测值，其中所述第一扫描观测值和所述第二扫描观测值中的至少一项用于观测所述待测电路中的故障。
以此方式，通过利用MISR中的多个观测单元在移位周期中捕获待测电路中的对应观测点处的多个值，并且利用MISR中的反馈路径将所捕获的多个值压缩为作为MISR的特征值的扫描观测值，可以基于经压缩的扫描观测值来高效地确定待测电路中是否存在故障，从而提高芯片测试的效率。
在第一方面的一些实施例中，所述MISR被配置为在特征移出模式中，将所述第二扫描观测值作为所述MISR的特征值的至少一部分移出所述MISR。在第一方面的一些实施例中，所述MISR被配置为在所述测试响应压缩模式中，将所述第一扫描观测值移出所述MISR。
在第一方面的一些实施例中，电路系统还包括连接到所述MISR的第二MISR，所述第二MISR被配置为在所述测试响应压缩模式中：独立于所述MISR工作，或者接收所述MISR输出的扫描观测值以作为输入。
在第一方面的一些实施例中，所述第二观测单元包括：信号组合器，被配置为在所述测试响应压缩模式中，基于所述第一扫描观测值、所述第二移位值和所述第二观测点处的值，生成所述信号组合器的第一输出处的第一组合值；以及扫描单元，被配置为在所述测试响应压缩模式中，基于所述第一组合值，生成所述第二扫描观测值。
在第一方面的一些实施例中，所述信号组合器进一步被配置为在特征移出模式中，基于所述第二移位值，生成所述信号组合器的第一输出处的第二组合值；并且所述扫描单元进一步被配置为在所述特征移出模式中，基于所述第二组合值，生成与所述第二组合值相同的输出值。
在第一方面的一些实施例中，所述信号组合器包括：与门，被配置为接收所述测试响应压缩模式的使 能信号和所述第二观测点处的值；第一异或门，被配置为基于所述第二移位值和所述第一扫描观测值，生成第一异或值；以及第二异或门，被配置为基于所述与门的输出和所述第一异或值，生成所述信号组合器的所述第一输出处的值。
在第一方面的一些实施例中，所述第一异或门与所述MISR的所述反馈路径相关联。在第一方面的一些实施例中，电路系统还包括被配置为测试所述待测电路的多个扫描链，所述多个扫描链处于压缩扫描模式或非压缩扫描模式。
在第一方面的一些实施例中，在所述多个扫描链的移位周期中，所述多个扫描链被配置为移入测试向量并且驱动所述待测电路，并且所述MISR被配置为在所述待测电路中的多个观测点处捕获多个值并且压缩所述多个值以生成多个扫描观测值。在一些实施例中，在所述多个扫描链的捕获周期中，所述多个扫描链被配置为从所述待测电路中的多个功能逻辑连接点处捕获对应的测试响应，并且所述MISR被配置为在所述待测电路中的多个观测点处捕获多个值并且压缩所述多个值以生成多个扫描观测值。
在本公开的第二方面，提供了一种用于扫描测试的方法。方法包括：向包括串联连接的多个观测单元并且具有反馈路径的多输入特征寄存器MISR移入用于观测待测电路中的故障的输入向量；获取由所述MISR基于在测试响应压缩模式中在所述待测电路中的多个观测点处捕获的多个值和所述输入向量而生成的多个扫描观测值；以及基于所述多个扫描观测值，确定所述待测电路中的故障。其中多个观测单元包括：第一观测单元，被配置为在所述测试响应压缩模式中，基于第一移位值和所述待测电路中的第一观测点处的值，生成第一扫描观测值；以及第二观测单元，被配置为在所述测试响应压缩模式中，基于所述第一扫描观测值、第二移位值和所述待测电路中的第二观测点处的值，生成第二扫描观测值。
在本公开的第三方面，提供了一种装置，包括：向量移位单元，被配置为向包括串联连接的多个观测单元并且具有反馈路径的多输入特征寄存器MISR移入用于观测所述待测电路中的故障的输入向量；观测值获取单元，被配置为获取由所述MISR基于在测试响应压缩模式中在所述待测电路中的多个观测点处捕获的多个值和所述输入向量而生成的多个扫描观测值；以及故障确定单元，被配置为基于所述多个扫描观测值，确定所述待测电路中的故障。其中多个观测单元包括：第一观测单元，被配置为在所述测试响应压缩模式中，基于第一移位值和所述待测电路中的第一观测点处的值，生成第一扫描观测值；以及第二观测单元，被配置为在所述测试响应压缩模式中，基于所述第一扫描观测值、第二移位值和所述待测电路中的第二观测点处的值，生成第二扫描观测值。
在本公开的第四方面，提供了一种电子设备，包括：至少一个计算单元；至少一个存储器，至少一个存储器被耦合到至少一个计算单元并且存储用于由至少一个计算单元执行的指令，指令当由至少一个计算单元执行时，使得设备实现第二方面所提供的方法。
在本公开的第五方面，提供了一种计算机可读存储介质，其上存储有计算机程序，其中计算机程序被处理器执行实现第二方面所提供的方法。
在本公开的第六方面，提供一种计算机程序产品，包括计算机可执行指令，当指令在被处理器执行时实现第二方面的方法的部分或全部步骤。
可以理解地，上述提供的第三方面的装置、第四方面的电子设备、第五方面的计算机存储介质或者第六方面的计算机程序产品均用于执行第二方面所提供的方法。关于第一方面的解释或者说明同样适用于第二方面、第三方面、第四方面、第五方面和第六方面。此外，第二方面、第三方面、第四方面、第五方面和第六方面所能达到的有益效果可参考对应电路系统中的有益效果，此处不再赘述。
附图说明
结合附图并参考以下详细说明，本公开各实施例的上述和其他特征、优点及方面将变得更加明显。在附图中，相同或相似的附图标注表示相同或相似的元素，其中：
图1示出了芯片的设计制造过程的流程图；
图2示出了本公开的多个实施例能够在其中实现的示例环境的示意图；
图3示出了根据本公开的一些实施例的示例观测单元的示意图；
图4示出了根据本公开的一些实施例的包括逻辑门和扫描单元的示例观测单元的示意图；
图5示出了根据本公开的一些实施例的用于扫描测试的电路系统的第一示例的示意图；
图6示出了根据本公开的一些实施例的用于扫描测试的电路系统的第二示例的示意图；
图7示出了根据本公开的一些实施例的扫描测试中的控制信号和时钟信号的示意图；
图8示出了根据本公开的一些实施例的包括多个MISR的第一电路系统的示意图；
图9示出了根据本公开的一些实施例的包括多个MISR的第二电路系统的示意图；
图10示出了根据本公开的一些实施例的用于扫描测试的方法的示例过程的示意性框图；
图11示出了根据本公开的一些实施例的用于扫描测试的装置的示意性框图；以及
图12示出了能够实施本公开的多个实施例的计算设备的框图。
具体实施方式
下面将参照附图更详细地描述本公开的实施例。虽然附图中显示了本公开的某些实施例，然而应当理解的是，本公开可以通过各种形式来实现，而且不应该被解释为限于这里阐述的实施例，相反提供这些实施例是为了更加透彻和完整地理解本公开。应当理解的是，本公开的附图及实施例仅用于示例性作用，并非用于限制本公开的保护范围。
在本公开的实施例的描述中，术语“包括”及其类似用语应当理解为开放性包含，即“包括但不限于”。术语“基于”应当理解为“至少部分地基于”。术语“一个实施例”或“该实施例”应当理解为“至少一个实施例”。术语“第一”、“第二”等等可以指代不同的或相同的对象。下文还可能包括其他明确的和隐含的定义。
应理解，本申请实施例提供的技术方案，在以下具体实施例的介绍中，某些重复之处可能不再赘述，但应视为这些具体实施例之间已有相互引用，可以相互结合。
如上文所简要描述的，在利用EDA工具或软件进行芯片测试的过程中，可以构建测试电路以用于测试同一芯片中的待测电路。测试电路可以包括诸如扫描链之类的可测性设计。扫描链包括由时序电路中的触发器连接成的多个“移位寄存器(也称为扫描单元，scan cell)”，并且每个移位寄存器的输入和输出都可以被单独观测。利用扫描链，可以将对复杂时序电路的测试转化为对组合电路的测试。
具体地，每个扫描单元可以包括数据输入端口D、移位输入端口SI、移位使能输入端口SE和1个输出端口Q。除了扫描链的链首和链尾处的扫描单元之外，每个扫描单元可以通过其移位输入端口SI与前一个扫描单元的输出端口Q连接。基于移位使能信号(se)的控制，扫描单元可以具有移位(shift)模式和捕获(capture)模式。
在特征移出模式中，每当时钟信号(clk)跳变，测试向量会从扫描单元的移位输入端口SI输入，并且通过首位相连的扫描单元而在扫描链上移位。扫描单元的输出端口Q会驱动待测电路中的组合逻辑，并且组合逻辑会通过连接到其的扫描单元的数据输入端口D而输出对应的值。
当测试向量移位完成，各个扫描单元可以进入捕获模式。在捕获模式中，每当时钟信号跳变，扫描单元会捕获当前数据输入端口D的值。在一个或多个捕获周期之后，各个扫描单元再次进入特征移出模式。在特征移出模式中，所捕获的值从扫描链的输出端口逐位移出，以用于与预设的正确值进行对比。如果组合逻辑有故障并且被当前测试向量激发，则该故障可以通过所移出的值与正确值之间的区别而被检测到。
然而，在这种扫描测试方案中，需要在将测试向量移入扫描链之后捕获组合逻辑中的值，并且所捕获的值需要逐位移出扫描链以用于与正确值进行比较。考虑到移位过程与捕获过程相比耗时久得多，芯片测试的时间绝大部分花费在移位过程中，使得测试效率较低。例如，如果将测试向量移入整个扫描链需要N个周期(N大于等于最大链长)，并且进行仅耗时一个周期的单捕获扫描测试，则故障测试时间仅占总测试时间的约1/N。因此，传统的扫描测试方案测试时间长并且测试效率低。
为了至少部分地解决上述问题以及其他潜在问题，本公开的各种实施例提供了一种用于扫描测试的方案。根据在此描述的各种实施例，提供了一种用于扫描测试的电路系统。该电路系统包括第一观测单元以及与第一观测单元串联连接以形成具有反馈路径的多输入特征寄存器(multi-input signature register,MISR)的第二观测单元。第一观测单元被配置为在测试响应压缩模式中，基于第一移位值和待测电路中的第一观测点处的值，生成第一扫描观测值。第二观测单元被配置为在测试响应压缩模式中，基于第一扫描观测值、第二移位值和待测电路中的第二观测点处的值，生成第二扫描观测值。
根据本公开的方案，通过利用MISR中的多个观测单元在移位周期中捕获待测电路中的对应观测点处的多个值，并且利用MISR中的反馈路径将所捕获的多个值压缩为作为MISR的特征值的扫描观测值，可以高效地基于扫描观测值来确定待测电路中是否存在故障，从而提高芯片测试的效率。
以下参考附图来描述本公开的各种示例实施例。
图1示出了芯片的设计制造过程100的流程图。设计制造过程100开始于规格制定110。在规格制定110的阶段，确定集成电路需要达到的功能和性能方面的要求。在芯片设计120的阶段，借助于EDA软件来进行电路设计，以获得例如用于芯片制造的版图文件。基于电路的不同(例如数字电路或模拟电路)，设计120可以包括不同的设计环节。在制造140的阶段中，通过光刻、刻蚀、离子注入、薄膜沉积、抛光等工艺在晶圆上形成集成电路。在封装150的阶段，对晶圆进行切割得到裸片，并通过黏贴、焊接、模封等工艺对裸片进行封装得到芯片。所得到的芯片在测试160的阶段中被测试，以确保成品芯片的性能满足规格制定110中所确定的要求。测试合格的芯片170可以被交付客户。可以理解，上述过程仅是示意，而非对本公开的范围进行限制。在一些情形下，芯片的设计制造过程可以有所不同。例如，在制造140之前可以进行流片(tape-out)。流片所得的少量芯片可以用于进行测试以验证芯片设计是否达到预期。如果未达到预期，则这表明流片失败，并且可能需要调整芯片设计或重新设计芯片。
在一些实施例中，数字电路的设计120可以示例性地包括架构设计121、RTL设计123、功能仿真125、综合(synthesis)127、时序分析129、DFT 131、验证检查133、布局布线135、设计规则检查(design rule check，DRC)137以及生成版图139。架构设计121例如包括对芯片的架构进行设计。例如，可以使用EDA软件确定芯片系统所包括的组件或子电路的类别和数量、以及各个组件或子电路的功能、连接和交互。在RTL设计123的阶段，可以使用诸如Verilog或VHDL之类的硬件编程语言将经过确定的芯片架构在RTL级进行代码描述。功能仿真125也被称作RTL级行为仿真或前端仿真。功能仿真目的是分析设计电路逻辑关系的正确性。综合127可以将RTL转换成门级网表(gate-level netlist)。综合127例如可以包括转换(translation)、优化(optimization)和映射(mapping)。在一个实施例中，用于综合的EDA软件可以先将RTL代码转化成通用的布尔等式，并且对其进行编译。可以根据设计者施加的延时、面积等约束对网表进行优化，并且继而将RTL网表映射到工艺库以生成门级网表。
时序分析129通常为静态时序分析，其主要涉及对数字电路的时序计算和预计。通过对数字电路中的路径进行时序分析来确定是否实现时序收敛，从而确保各种电路的时序是否满足各种时序要求。这种数字电路的验证通常是静态完成的，并且不需要数字逻辑的模拟。在DFT 131的阶段，可以在设计中嵌入各种用于提高芯片可测试性(包括可控制性和可观测性)的硬件逻辑。通过使用这部分逻辑，可以生成测试向量以实现大规模数字电路的测试的目的。DFT例如可以包括基于扫描链(scan chain)的测试方法或内建自测试电路(built-in self-test，BIST)。在验证检查133的阶段，可以对电路进行形式验证和/或等价性检查。形式验证可以根据某个或某些形式规范或属性，使用数学的方法证明其正确性或非正确性。形式验证例如可以包括抽象解释(abstract interpretation)、形式模型检查(formal model checking，也被称作特性检查)和定理证明(theory prover)。等价性检查可以用于验证寄存器传输级设计与门级网表之间、门级网表与门级网表之间是否一致。
在布局布线135的阶段，可以对芯片电路进行布局(placement)和布线(routing)。布局可以基于面积、关键路径延时长度、功耗等因素的考量把逻辑综合127生成的门级网表合理地排布在与芯片对应的一个矩形区域内。在此之后，可以对经布局的各个组件或子电路进行布线以将其连接。布线通常期望总的走线较短、走线延时满足时序要求、符合工艺上的走线规则(如布线密度)。虽然在此将布局和布线分开描述，但这仅是示意性的而非对本公开的范围进行限制。在一些情形下，布局和布线可以同时进行或交替进行以实现布局布线的优化。
在DRC 137的阶段，可以检查版图是否存在违反设计规则而引起潜在断路、短路或不良效应。在通过DRC之后，可以由EDA软件生成139表示版图的文件，例如GDSII文件。可以理解，上述环节仅为示例性而非对本公开的范围进行限制，在实际设计过程中，可以根据设计需要对上述环节进行增加、删减或修改。此外，上述环节中的一些环节可以由不同的EDA软件实现，也可以被集成在一个或多个EDA软件中实现。本公开对此不进行限制。
图2示出了根据本公开的多个实施例能够在其中实现的示例环境200的示意图。如图2所示，在环境200中，针对待测电路201，包括串联连接的多个观测单元(例如，观测单元210、220、230和240)的MISR 202可以从待测电路201中的多个观测点处捕获对应的多个值，并且利用MISR 202的反馈路径将所捕获的多个值压缩为MISR的特征值，以用于观测待测电路201中的故障。
具体地，在测试响应压缩模式中，用于观测待测电路201中的故障的输入向量从MISR 202的输入端 口移入MISR 202。MISR 202中的每个观测单元基于输入向量或前一个时序门和待测电路201中对应的观测点处的值(以及一个或多个观测单元的反馈，该一个或多个观测单元可以包括该观测单元本身)，生成扫描观测值。扫描观测值被移入下一个观测单元或移出MISR 202以用于观测待测电路201中的故障。基于扫描观测值与预设的正确值的比较，可以确定待测电路201中是否存在故障。预设的正确值可以是基于移入MISR 202的输入向量而被确定的。
在图2所示的示例中，观测单元240被配置为在测试响应压缩模式中，基于从观测单元230输出的第一移位值和待测电路201中的第一观测点处的值，生成第一扫描观测值。第一扫描值基于第一反馈路径被反馈到观测单元210。观测单元210被配置为在测试响应压缩模式中，基于第一扫描观测值、第二移位值和待测电路201中的第二观测点处的值，生成第二扫描观测值。在图2所示的示例中，第二移位值可以是所移入的输入向量的至少一部分。备选地，第二移位值可以是观测单元210的前一个观测单元所输出的值。
第二扫描观测值被输入到观测单元220。观测单元220被配置为基于第二扫描观测值和待测电路201中的第三观测点处的值，生成第三扫描观测值。第三扫描观测值被输入到观测单元230。观测单元230被配置为基于第三扫描观测值和待测电路201中的第四观测点处的值，生成第四扫描观测值。第四扫描观测值被输入到观测单元240。观测单元240被配置为基于作为新的移位值的第四扫描观测值和待测电路201中的第一观测点处的新的值，生成新的扫描观测值。
在一些实施例中，扫描观测值可以在特征移出模式中被移出MISR 202。具体地，在特征移出模式的移位周期中，观测单元210、220、230和240所生成的对应的扫描观测值可以作为MISR 202的特征值而被逐位移出MISR 202。观测单元210、220、230和240所生成的对应的每个扫描观测值可以被视为MISR 202的特征值的一部分。
备选地或附加地，扫描观测值可以在测试响应压缩模式中被移出MISR 202。具体地，在测试响应压缩模式的移位周期中，与MISR 202的输出端口连接的观测单元(例如观测单元240)可以在每个移位周期中移出相应周期中所生成的扫描观测值。这种模式也可称为测试响应连续移出模式。
在一些实施例中，如图2所示，MISR 202可以包括两个反馈路径，也即从观测单元240反馈到观测单元210的第一反馈路径和从观测单元240反馈到观测单元240自身的第二反馈路径。应理解，在一些实施例中，MISR 202可以包括更多或更少的反馈路径。此外，MISR 202可以包括与第一反馈路径和第二反馈路径不同的反馈路径。
应理解，图2中所示的环境200仅是示例性的，而不构成对本公开的范围的限制。例如，观测单元的数目可以是任意合适的数值，并且观测单元之间的反馈路径可以不同于图2中的示例。
图3示出了根据本公开的一些实施例的观测单元300的示意图。观测单元300可以是观测单元210、220、230和240的具体实现方式。如图3所示，观测单元300可以包括信号组合器310和扫描单元320。
信号组合器310的第一输入可以连接到待测电路201中的观测点。观测点的位置可以被选择为使得观测单元能够观测到待测电路201中难以通过扫描链中的普通扫描单元观测到的故障。换言之，通过在待测电路201中设置观测点，可以将待测电路201中的故障通过逻辑锥从观测点传进观测单元，从而提升测试覆盖率。
信号组合器310的第二输入可以连接到先前一个观测单元的输出或输入向量的生成器。例如，观测单元210中的信号组合器的第二输入可以直接接收输入向量。观测单元220中的信号组合器的第二输入可以接收观测单元210在上一移位周期中生成的扫描观测值。
信号组合器310的第一输出和第二输出分别连接到扫描单元320的对应输入。扫描单元320可以包括与观测点处的值关联的D端、与先前一个观测单元的输出或输入向量关联的SI端、与测试响应压缩模式的使能信号关联的SE端以及输出Q端。
观测单元300被配置为在特征移出模式、测试响应压缩模式和电路工作模式中操作。在测试响应压缩模式中，信号组合器310被配置为基于待测电路201中的观测点处的值与先前一个观测单元所输出的移位值或输入向量(以及一个或多个观测单元的反馈，图3中未示出)，生成信号组合器310的第一输出(与SI端对应的输出)处的第一组合值。扫描单元320被配置为基于第一组合值，生成扫描观测值，以从Q端输出。
在特征移出模式中，信号组合器310被配置为基于先前一个观测单元所输出的移位值或输入向量，生成信号组合器310的第一输出(与SI端对应的输出)处的第二组合值。扫描单元320被配置为基于第二组 合值生成第二移位值。第二移位值与先前一个观测单元所输出的移位值或所移入的输入向量的值相同。
观测单元300在上述各个模式中操作的细节将在下文参考图4至图6来描述。
图4示出了根据本公开的一些实施例的包括逻辑门和扫描单元的示例观测单元400的示意图。观测单元400可以是观测单元300的一个具体示例。如图4所示，观测单元400中的信号组合器可以包括与门401和异或门402。观测单元400还可以包括扫描单元450。
观测单元400可以包括多个输入端口和一个输出端口。如图所示，观测单元400可以包括用于接收测试响应压缩模式的使能信号的特征压缩使能端口en、用于接收观测点处的值的观测输入端口od、用于接收先前一个时序门或初始移入的输入向量的移位输入端口si、用于接收移位使能信号的移位使能端口se以及用于接收时钟信号的时钟输入端口clk。观测单元400还可以包括用于接收触发器复位信号的复位端口rn和用于输出的输出端口q。观测单元400的输出可以被输入到下一个时序门或者通过MISR的输出端口被移出。
表1示出了观测单元400的端口的信息。
表1：
如图4所示，与门401被配置为接收测试响应压缩模式的使能信号和观测点处的值，生成与扫描单元450的D端对应的值。异或门402被配置为基于与门401的输出和上一个时序门(例如，先前观测单元移出的移位值)或初始移入的输入向量，生成与扫描单元450的SI端对应的值。通过控制en端口和se端口处的信号，可以使得观测单元400在相应的工作模式中操作。表2示出了观测单元400的工作模式。
表2：
当en端和se端的输入信号均置为1时，测试响应压缩模式开启。在测试响应压缩模式中，在移位周期中，观测单元400接收上一个时序门的值(例如，前一个观测单元输出的扫描观测值)的同时捕获观测点处的值，以此实现在移位周期中对电路进行观测，使得原本仅在捕获过程中才能捕获的故障也能在移位周期中被捕获，从而极大地提升测试效率。
图5示出了根据本公开的一些实施例的用于扫描测试的电路系统的第一示例的示意图。如图5所示，用于对待测电路201进行扫描测试的电路系统可以包括观测单元510、520、530和540，并且观测单元510、520、530和540被串联为具有两个反馈路径的MISR。该MISR被配置为从输入端口in(或主输入端口PI)接收输入向量。MISR可以从待测电路201中的多个观测点处捕获对应的多个值，并且利用MISR的反馈路径将所捕获的多个值压缩为MISR的特征值。MISR还被配置为将MISR的特征值通过输出端口out(或主输出端口PO)移出MISR。
在图5所示的电路系统中，接收反馈值的观测单元(例如，观测单元510和540)可以基于由反馈路径输入的观测单元在上一个时钟周期生成的扫描观测值、先前一个观测单元输出的移位值或初始移入的输入向量的值、以及待测电路中与其自身对应的观测点处的值，生成扫描观测值。
在一些实施例中，与反馈路径无关的观测单元520和530可以由图4中所示的观测单元400直接实现。与之相反，如图5所示，与反馈路径关联的观测单元510还附加有异或门551，并且与反馈路径关联的观测单元540还附加有异或门552。
换言之，如图4所示的观测单元400可以附加地增加一个异或门，以用于实现与反馈路径关联的观测 单元，例如观测单元510和540。在这种实施例中，异或门402不直接接收先前观测单元(例如观测单元530)输出的扫描观测值。相反，先前观测单元(例如观测单元530)输出的扫描观测值与观测单元的反馈被输入到附加的异或门(例如异或门551或552)，并且该附加的异或门的输出以及与门401的输出被输入到异或门402。
在一些实施例中，如图4所示的观测单元400中还附加地增加一个与门(例如与门561或562)，以用于接收测试响应压缩模式的使能信号和观测单元的反馈。当测试响应压缩模式的使能信号en置于高电平时，测试响应压缩模式开启并且MISR被配置为从待测电路201中的多个观测点处捕获对应的多个值，并且利用MISR的反馈路径将所捕获的多个值压缩为MISR的特征值。当测试响应压缩模式的使能信号en置于低电平并且特征移出模式的使能信号se置于高电平时，测试响应压缩模式关闭并且特征移出模式开启，所生成的MISR的特征值被移出MISR。
图6示出了根据本公开的一些实施例的用于扫描测试的电路系统的第二示例的示意图。如图6所示，用于对待测电路201进行扫描测试的电路系统可以包括观测单元610、620、630和640，并且观测单元610、620、630和640被串联为具有反馈路径的MISR。该MISR可以从待测电路201中的多个观测点处捕获对应的多个值，并且利用MISR的反馈路径将所捕获的多个值压缩为MISR的特征值。
如图6所示，观测单元610、620和630分别附加有与反馈路径关联的异或门651、652和653。此外，观测单元610、620和630分别附加有用于接收测试响应压缩模式的使能信号和观测单元的反馈值的与门663、664和665。
在一些实施例中，每个观测单元可以接收来自一个或多个观测单元的反馈值，并且可以接收来自自身的反馈值。反馈值可以是观测单元在上一个周期中输出的扫描观测值。例如，如图6所示，观测单元610可以接收来自观测单元620的反馈值以及来自观测单元610自身的反馈值。观测单元620可以接收来自观测单元630的反馈值。观测单元630可以接收来自观测单元620的反馈值以及来自观测单元630自身的反馈值和来自观测单元640的反馈值。
在这种情况下，接收多个反馈值的观测单元(例如，观测单元610和630)可以基于由多个反馈路径输入的多个观测单元在上一个时钟周期生成的多个扫描观测值、先前一个观测单元输出的移位值或初始移入的输入向量的值、以及待测电路中与其自身对应的观测点处的值，生成扫描观测值。
在一些实施例中，当观测单元接收来自多个观测单元的反馈值时，也即与多条反馈路径相关联时，该观测单元可以附加有异或门(例如，异或门661和662)。该附加的异或门被配置为接收来自多个观测单元的反馈值。
在一些实施例中，MISR中的观测单元可以与多个扫描链一起来测试待测电路201。如上文所描述的，每个扫描链被配置为在移位周期中移入相应的测试向量，并且在捕获周期中从待测电路201中对应的功能逻辑连接点处获取测试响应。测试响应可以被移出以用于检测待测电路201中是否存在故障。
在一些实施例中，多个扫描链可以利用测试压缩技术。通过解压器可以将从少数端口输入的测试向量通过解压缩的方式扩展到等同于扫描链数量的宽度以同时输入到各个扫描链中。此外，从扫描链输出的测试响应又可以通过压缩器被压缩成少数端口宽度的输出值，从而减少了测试需要的测试向量输入输出端口的数目。备选地，可以不利用压缩扫描技术来操作多个扫描链。
图7示出了根据本公开的一些实施例的扫描测试中的控制信号和时钟信号的示意图。图7示出了扫描链的时钟信号clk1、移位使能信号se、测试响应压缩模式的使能信号en(处于高电平)以及MISR中的观测单元的时钟信号clk2的变化。
如图7所示，在扫描链的移位周期中，控制信号en与se均为高电平，扫描链在移位模式中操作并且MISR在测试响应压缩模式中操作。具体地，扫描链中的多个扫描单元各自移入测试向量或前一个时序门的值，并且输出值以驱动待测电路201。MISR中的多个观测单元在移位的同时从待测电路201中对应的多个观测点处捕获多个值，并且利用反馈路径将所捕获的多个值压缩为与观测单元数目相同的多个扫描观测值(也即，MISR的特征值)。
在扫描链的捕获周期中，控制信号en保持为高电平而se信号置为低电平，扫描链和MISR中的多个观测单元均在捕获模式中操作。具体地，扫描链中的扫描单元从待测电路201中的功能逻辑连接点处获取测试响应(也即，进行捕获)。MISR中的多个观测单元从待测电路201中的多个观测点处捕获多个值并且利用反馈路径将所捕获的多个值压缩为与观测单元数目相同的多个扫描观测值(也即，MISR的特征值)。
这样，MISR可以在扫描链的移位和捕获周期中均捕获待测电路中的多个观测点处的值，并且可以将从多个观测点处捕获到的大量值压缩为与观测单元数目相同的少数数目的扫描观测值，从而提高测试效率。例如，在长时间的测试之后，可以仅根据压缩得到的少数数目的扫描观测值(也即，MISR的特征值)来确定待测电路中是否有故障被观测到。
尽管未示出，当控制信号en置为低电平时，MISR中的多个观测单元可以与扫描链一起在传统的移位模式和捕获模式中操作。也即，在移位周期移入测试向量(或移出测试响应)或前一个时序门的值，并且在捕获模式中从待测电路捕获测试响应。
在一些实施例中，用于扫描测试的电路系统可以包括串联连接的多个MISR。每个MISR可以包括一组观测单元。在一些实施例中，可以基于观测单元的位置来确定观测单元属于哪个MISR。备选地或附加地，可以基于与观测单元对应的观测点的位置来确定观测单元属于哪个MISR。以此方式，可以减小观测单元与观测点之间的走线和/或多个观测单元之间的走线的难度。下文将参考图8和图9来描述用于扫描测试的包括多个MISR的电路系统的细节。
图8示出了根据本公开的一些实施例的包括多个MISR的第一电路系统800的示意图。如图8所示，第一电路系统800包括处于压缩扫描模式的多个扫描链。多个扫描链接收由解压器801生成的测试向量，并且多个扫描链输出的测试响应被压缩器802压缩。第一电路系统800还包括MISR 810和MISR 820。MISR 810连接到用于接收输入向量的输入端口PI并且MISR 810的输出连接到MISR 820的输入。MISR 820连接到用于输出扫描观测值的输出端口PO。
在一些实施例中，在测试响应压缩模式中，MISR 810和MISR 820可以独立地工作。换言之，MISR 820不接收来自MISR 810的输出作为输入。MISR 810和MISR 820各自执行捕获观测点处的多个值和压缩多个值以生成特征值的过程。当测试完成后，MISR 810和820进入特征移出模式，MISR 810的特征值和MISR 820的特征值在移位周期中逐位移出输出端口PO，以用于观测待测电路中的故障。
备选地，在测试响应压缩模式中，MISR 810和MISR 820可以一起工作。换言之，在每个移位周期中，MISR 820接收来MISR 810的输出作为输入。此外，在每个移位周期中，MISR 820可以向输出端口PO输出一个扫描观测值，以用于在每个移位周期中观测待测电路中的故障。应理解，由于MISR具有单独的输入端口PI和输出端口PO，可以减少对与其一起工作的扫描链的干扰。
图9示出了根据本公开的一些实施例的包括多个MISR的第二电路系统900的示意图。如图9所示，第二电路系统900包括处于非压缩扫描模式的多个扫描链。第二电路系统900还包括MISR 910和MISR 920。与图8类似地，MISR 910和MISR 920可以在测试响应压缩模式中独立地工作或一起工作。
图10示出了根据本公开的一些实施例的用于扫描测试的方法1000的示例过程的示意性框图。方法1000可以由任意合适的处理器执行，例如实现EDA软件功能的处理器。
在框1010，向包括串联连接的多个观测单元并且具有反馈路径的多输入特征寄存器MISR移入用于观测待测电路中的故障的输入向量。多个观测单元包括第一观测单元和第二观测单元。第一观测单元被配置为在所述测试响应压缩模式中，基于第一移位值和所述待测电路中的第一观测点处的值，生成第一扫描观测值。第二观测单元被配置为在所述测试响应压缩模式中，基于所述第一扫描观测值、第二移位值和所述待测电路中的第二观测点处的值，生成第二扫描观测值。
在一些实施例中，所述第二观测单元包括：信号组合器，被配置为在所述测试响应压缩模式中，基于所述第一扫描观测值、所述第二移位值和所述第二观测点处的值，生成所述信号组合器的第一输出处的第一组合值；以及扫描单元，被配置为在所述测试响应压缩模式中，基于所述第一组合值，生成所述第二扫描观测值。
在一些实施例中，所述信号组合器进一步被配置为在特征移出模式中，基于所述第二移位值，生成所述信号组合器的第一输出处的第二组合值；并且所述扫描单元进一步被配置为在所述特征移出模式中，基于所述第二组合值，生成输出值。
在一些实施例中，所述信号组合器包括：与门，被配置为接收所述测试响应压缩模式的使能信号和所述第二观测点处的值；第一异或门，被配置为基于所述第二移位值和所述第一扫描观测值，生成第一异或值；以及第二异或门，被配置为基于所述与门的输出和所述第一异或值，生成所述信号组合器的所述第一输出处的值。
在一些实施例中，所述第一异或门与所述MISR的所述反馈路径相关联。
在框1020，获取由所述MISR基于在测试响应压缩模式中在所述待测电路中的多个观测点处捕获的多个值和所述输入向量而生成的多个扫描观测值。
在一些实施例中，获取所述多个扫描观测值包括：在特征移出模式中，将所述第二扫描观测值作为所述MISR的特征值的至少一部分移出所述MISR。
在一些实施例中，获取所述多个扫描观测值包括：在所述测试响应压缩模式中，将所述第一扫描观测值移出所述MISR。
在框1030，基于所述多个扫描观测值，确定所述待测电路中的故障。
在一些实施例中，方法1000还包括：利用连接到所述MISR的第二MISR，确定所述待测电路中的故障，其中所述第二MISR被配置为在所述测试响应压缩模式中：独立于所述MISR工作，或者接收所述MISR输出的所述多个扫描观测值以作为输入。
在一些实施例中，方法1000还包括：利用多个扫描链与所述MISR一起来测试待测电路。在所述多个扫描链的移位周期中，所述多个扫描链被配置为移入测试向量并且驱动所述待测电路，并且所述MISR被配置为在所述待测电路中的多个观测点处捕获多个值并且压缩所述多个值以生成多个扫描观测值。
在一些实施例中，在所述多个扫描链的捕获周期中，所述多个扫描链被配置为从所述待测电路中的多个功能逻辑连接点处捕获对应的测试响应，并且所述MISR被配置为在所述待测电路中的多个观测点处捕获多个值并且压缩所述多个值以生成多个扫描观测值。
示例装置和设备
图11示出了根据本公开实施例的用于扫描测试的装置1100的框图。具体地，装置1100可以是EDA软件装置。装置1100可以包括多个模块，以用于执行如图10中所讨论的过程1000中的对应步骤。如图11所示，装置1100包括向量移位单元1110，其被配置为向包括串联连接的多个观测单元并且具有反馈路径的多输入特征寄存器MISR移入用于观测所述待测电路中的故障的输入向量。多个观测单元包括：第一观测单元，被配置为在所述测试响应压缩模式中，基于第一移位值和所述待测电路中的第一观测点处的值，生成第一扫描观测值；以及第二观测单元，被配置为在所述测试响应压缩模式中，基于所述第一扫描观测值、第二移位值和所述待测电路中的第二观测点处的值，生成第二扫描观测值。
在一些实施例中，所述第二观测单元包括：信号组合器，被配置为在所述测试响应压缩模式中，基于所述第一扫描观测值、所述第二移位值和所述第二观测点处的值，生成所述信号组合器的第一输出处的第一组合值；以及扫描单元，被配置为在所述测试响应压缩模式中，基于所述第一组合值，生成所述第二扫描观测值。
在一些实施例中，所述信号组合器进一步被配置为在特征移出模式中，基于所述第二移位值，生成所述信号组合器的第一输出处的第二组合值；并且所述扫描单元进一步被配置为在所述特征移出模式中，基于所述第二组合值，生成输出值。
在一些实施例中，所述信号组合器包括：与门，被配置为接收所述测试响应压缩模式的使能信号和所述第二观测点处的值；第一异或门，被配置为基于所述第二移位值和所述第一扫描观测值，生成第一异或值；以及第二异或门，被配置为基于所述与门的输出和所述第一异或值，生成所述信号组合器的所述第一输出处的值。
在一些实施例中，所述第一异或门与所述MISR的所述反馈路径相关联。
装置1100还包括观测值获取单元1120，其被配置为获取由所述MISR基于在测试响应压缩模式中在所述待测电路中的多个观测点处捕获的多个值和所述输入向量而生成的多个扫描观测值。装置1100还包括故障确定单元1130，其被配置为基于所述多个扫描观测值，确定所述待测电路中的故障。
在一些实施例中，观测值获取单元1120被配置为：在特征移出模式中，将所述第二扫描观测值作为所述MISR的特征值的至少一部分移出所述MISR。
在一些实施例中，观测值获取单元1120被配置为：在所述测试响应压缩模式中，将所述第一扫描观测值移出所述MISR。
在一些实施例中，装置1100还包括多MISR测试单元，其被配置为利用连接到所述MISR的第二MISR，确定所述待测电路中的故障，其中所述第二MISR被配置为在所述测试响应压缩模式中：独立于所述MISR工作，或者接收所述MISR输出的所述多个扫描观测值以作为输入。
图12示出了可以用来实施本公开的实施例的示例设备1200的示意性框图。如图所示，设备1200包括计算单元1201，其可以根据存储在随机存取存储器(RAM)1203和/或只读存储器(ROM)1202的计算机程序指令或者从存储单元1208加载到RAM 1203和/或ROM 1202中的计算机程序指令，来执行各种适当的动作和处理。在RAM 1203和/或ROM 1202中，还可存储设备1200操作所需的各种程序和数据。计算单元1201和RAM 1203和/或ROM 1202通过总线1204彼此相连。输入/输出(I/O)接口1205也连接至总线1204。
设备1200中的多个部件连接至I/O接口1205，包括：输入单元1206，例如键盘、鼠标等；输出单元1207，例如各种类型的显示器、扬声器等；存储单元1208，例如磁盘、光盘等；以及通信单元1209，例如网卡、调制解调器、无线通信收发机等。通信单元1209允许设备1200通过诸如因特网的计算机网络和/或各种电信网络与其他设备交换信息/数据。
计算单元1201可以是各种具有处理和计算能力的通用和/或专用处理组件。计算单元1201的一些示例包括但不限于中央处理单元(CPU)、图形处理单元(GPU)、各种专用的人工智能(AI)计算芯片、各种运行机器学习模型算法的计算单元、数字信号处理器(DSP)、以及任何适当的处理器、控制器、微控制器等。计算单元1201执行上文所描述的各个方法和处理，例如过程1000。例如，在一些实施例中，过程1000可被实现为计算机软件程序，具体可以是EDA程序，其被有形地包含于机器可读介质，例如存储单元1208。在一些实施例中，计算机程序的部分或者全部可以经由RAM和/或ROM和/或通信单元1209而被载入和/或安装到设备1200上。当计算机程序加载到RAM和/或ROM并由计算单元1201执行时，可以执行上文描述的过程1000的一个或多个步骤。备选地，在其他实施例中，计算单元1201可以通过其他任何适当的方式(例如，借助于固件)而被配置为执行过程1000。
在上述实施例中，方法流程可以全部或部分地通过软件、硬件、固件或者其任意组合来实现，当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令，在服务器或终端上加载和执行所述计算机程序指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴光缆、光纤、数字用户线)或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是服务器或终端能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质(如软盘、硬盘和磁带等)，也可以是光介质(如数字视盘(digital video disk，DVD)等)，或者半导体介质(如固态硬盘等)。
此外，虽然采用特定次序描绘了各操作，但是这应当理解为要求这样操作以所示出的特定次序或以顺序次序执行，或者要求所有图示的操作应被执行以取得期望的结果。在一定环境下，多任务和并行处理可能是有利的。同样地，虽然在上面论述中包含了若干具体实现细节，但是这些不应当被解释为对本公开的范围的限制。在单独的实施例的上下文中描述的某些特征还可以组合地实现在单个实现中。相反地，在单个实现的上下文中描述的各种特征也可以单独地或以任何合适的子组合的方式实现在多个实现中。
尽管已经采用特定于结构特征和/或方法逻辑动作的语言描述了本主题，但是应当理解所附权利要求书中所限定的主题未必局限于上面描述的特定特征或动作。相反，上面所描述的特定特征和动作仅仅是实现权利要求书的示例形式。

Claims (23)

  1. 一种用于扫描测试的电路系统，包括：
    第一观测单元，被配置为在测试响应压缩模式中，基于第一移位值和待测电路中的第一观测点处的值，生成第一扫描观测值；以及
    第二观测单元，与所述第一观测单元串联连接以形成具有反馈路径的多输入特征寄存器MISR，所述第二观测单元被配置为在所述测试响应压缩模式中，基于所述第一扫描观测值、第二移位值和所述待测电路中的第二观测点处的值，生成第二扫描观测值，
    其中所述第一扫描观测值和所述第二扫描观测值中的至少一项用于观测所述待测电路中的故障。
  2. 根据权利要求1所述的电路系统，其中所述MISR被配置为在特征移出模式中，将所述第二扫描观测值作为所述MISR的特征值的至少一部分移出所述MISR。
  3. 根据权利要求1或2所述的电路系统，其中所述MISR被配置为在所述测试响应压缩模式中，将所述第一扫描观测值移出所述MISR。
  4. 根据权利要求1至3中任一项所述的电路系统，还包括连接到所述MISR的第二MISR，所述第二MISR被配置为在所述测试响应压缩模式中：
    独立于所述MISR工作，或者
    接收所述MISR输出的扫描观测值以作为输入。
  5. 根据权利要求1至4中任一项所述的电路系统，其中所述第二观测单元包括：
    信号组合器，被配置为在所述测试响应压缩模式中，基于所述第一扫描观测值、所述第二移位值和所述第二观测点处的值，生成所述信号组合器的第一输出处的第一组合值；以及
    扫描单元，被配置为在所述测试响应压缩模式中，基于所述第一组合值，生成所述第二扫描观测值。
  6. 根据权利要求5所述的电路系统，其中：
    所述信号组合器进一步被配置为在特征移出模式中，基于所述第二移位值，生成所述信号组合器的第一输出处的第二组合值；并且
    所述扫描单元进一步被配置为在所述特征移出模式中，基于所述第二组合值，生成输出值，所述输出值与所述第二组合值相同。
  7. 根据权利要求5或6所述的电路系统，其中所述信号组合器包括：
    与门，被配置为接收所述测试响应压缩模式的使能信号和所述第二观测点处的值；
    第一异或门，被配置为基于所述第二移位值和所述第一扫描观测值，生成第一异或值；以及
    第二异或门，被配置为基于所述与门的输出和所述第一异或值，生成所述信号组合器的所述第一输出处的值。
  8. 根据权利要求7所述的电路系统，其中所述第一异或门与所述MISR的所述反馈路径相关联。
  9. 根据权利要求1至8中任一项所述的电路系统，还包括被配置为测试所述待测电路的多个扫描链，所述多个扫描链处于压缩扫描模式或非压缩扫描模式。
  10. 根据权利要求9所述的电路系统，其中：
    在所述多个扫描链的移位周期中，所述多个扫描链被配置为移入测试向量并且驱动所述待测电路，并且所述MISR被配置为在所述待测电路中的多个观测点处捕获多个值并且压缩所述多个值以生成多个扫描观测值。
  11. 根据权利要求9至10中任一项所述的电路系统，其中：
    在所述多个扫描链的捕获周期中，所述多个扫描链被配置为从所述待测电路中的多个功能逻辑连接点处捕获对应的测试响应，并且所述MISR被配置为在所述待测电路中的多个观测点处捕获多个值并且压缩所述多个值以生成多个扫描观测值。
  12. 一种用于扫描测试的方法，包括：
    向包括串联连接的多个观测单元并且具有反馈路径的多输入特征寄存器MISR移入用于观测待测电路中的故障的输入向量；
    获取由所述MISR基于在测试响应压缩模式中在所述待测电路中的多个观测点处捕获的多个值和所述输入向量而生成的多个扫描观测值；以及
    基于所述多个扫描观测值，确定所述待测电路中的故障，
    其中多个观测单元包括：
    第一观测单元，被配置为在所述测试响应压缩模式中，基于第一移位值和所述待测电路中的第一观测点处的值，生成第一扫描观测值；以及
    第二观测单元，被配置为在所述测试响应压缩模式中，基于所述第一扫描观测值、第二移位值和所述待测电路中的第二观测点处的值，生成第二扫描观测值。
  13. 根据权利要求12所述的方法，其中获取所述多个扫描观测值包括：
    在特征移出模式中，将所述第二扫描观测值作为所述MISR的特征值的至少一部分移出所述MISR。
  14. 根据权利要求12或13所述的方法，其中获取所述多个扫描观测值包括：
    在所述测试响应压缩模式中，将所述第一扫描观测值移出所述MISR。
  15. 根据权利要求12至14中任一项所述的方法，还包括：
    利用连接到所述MISR的第二MISR，确定所述待测电路中的故障，其中所述第二MISR被配置为在所述测试响应压缩模式中：
    独立于所述MISR工作，或者
    接收所述MISR输出的所述多个扫描观测值以作为输入。
  16. 根据权利要求12至15中任一项所述的方法，其中所述第二观测单元包括：
    信号组合器，被配置为在所述测试响应压缩模式中，基于所述第一扫描观测值、所述第二移位值和所述第二观测点处的值，生成所述信号组合器的第一输出处的第一组合值；以及
    扫描单元，被配置为在所述测试响应压缩模式中，基于所述第一组合值，生成所述第二扫描观测值。
  17. 根据权利要求16所述的方法，其中：
    所述信号组合器进一步被配置为在特征移出模式中，基于所述第二移位值，生成所述信号组合器的第一输出处的第二组合值；并且
    所述扫描单元进一步被配置为在所述特征移出模式中，基于所述第二组合值，生成与所述第二组合值相同的输出值。
  18. 根据权利要求16或17所述的方法，其中所述信号组合器包括：
    与门，被配置为接收所述测试响应压缩模式的使能信号和所述第二观测点处的值；
    第一异或门，被配置为基于所述第二移位值和所述第一扫描观测值，生成第一异或值；以及
    第二异或门，被配置为基于所述与门的输出和所述第一异或值，生成所述信号组合器的所述第一输出处的值。
  19. 根据权利要求18所述的方法，其中所述第一异或门与所述MISR的所述反馈路径相关联。
  20. 一种装置，包括：
    向量移位单元，被配置为向包括串联连接的多个观测单元并且具有反馈路径的多输入特征寄存器MISR移入用于观测所述待测电路中的故障的输入向量；
    观测值获取单元，被配置为获取由所述MISR基于在测试响应压缩模式中在所述待测电路中的多个观测点处捕获的多个值和所述输入向量而生成的多个扫描观测值；以及
    故障确定单元，被配置为基于所述多个扫描观测值，确定所述待测电路中的故障，
    其中多个观测单元包括：
    第一观测单元，被配置为在所述测试响应压缩模式中，基于第一移位值和所述待测电路中的第一观测点处的值，生成第一扫描观测值；以及
    第二观测单元，被配置为在所述测试响应压缩模式中，基于所述第一扫描观测值、第二移位值和所述待测电路中的第二观测点处的值，生成第二扫描观测值。
  21. 一种电子设备，包括：
    至少一个计算单元；
    至少一个存储器，所述至少一个存储器被耦合到所述至少一个计算单元并且存储用于由所述至少一个计算单元执行的指令，所述指令当由所述至少一个计算单元执行时，使所述电子设备执行根据权利要求12-19中任一项所述的方法。
  22. 一种计算机可读存储介质，其上存储有计算机程序，所述程序被处理器执行时实现根据权利要求 12-19中任一项所述的方法。
  23. 一种计算机程序产品，包括计算机可执行指令，其中所述计算机可执行指令在被处理器执行时实现根据权利要求12-19中任一项所述的方法。
PCT/CN2023/130358 2023-02-08 2023-11-08 用于扫描测试的电路系统、方法、装置、介质和程序产品 WO2024164597A1 (zh)

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