WO2024162999A1 - Prédistorsion analogique (apd) basée sur un rapport crête sur moyenne (par) dans un module frontal - Google Patents

Prédistorsion analogique (apd) basée sur un rapport crête sur moyenne (par) dans un module frontal Download PDF

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Publication number
WO2024162999A1
WO2024162999A1 PCT/US2023/035072 US2023035072W WO2024162999A1 WO 2024162999 A1 WO2024162999 A1 WO 2024162999A1 US 2023035072 W US2023035072 W US 2023035072W WO 2024162999 A1 WO2024162999 A1 WO 2024162999A1
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WO
WIPO (PCT)
Prior art keywords
fem
par
detector
power amplifier
coupled
Prior art date
Application number
PCT/US2023/035072
Other languages
English (en)
Inventor
George Maxim
Baker Scott
Nadim Khlat
Original Assignee
Qorvo Us, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qorvo Us, Inc. filed Critical Qorvo Us, Inc.
Publication of WO2024162999A1 publication Critical patent/WO2024162999A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
    • H03F1/0216—Continuous control
    • H03F1/0222—Continuous control by using a signal derived from the input signal
    • H03F1/0227—Continuous control by using a signal derived from the input signal using supply converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0261—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the polarisation voltage or current, e.g. gliding Class A
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3241—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
    • H03F1/3247—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits using feedback acting on predistortion circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3241—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
    • H03F1/3258—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits based on polynomial terms
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/105—A non-specified detector of the power of a signal being used in an amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]

Definitions

  • the technology of the disclosure relates generally to front-end modules and, more particularly, to ways to normalize a distortion profile for a front-end module in a transceiver.
  • aspects disclosed in the detailed description include peak-to-average ratio (PAR)-based analog predistortion (APD) in a front-end module (FEM).
  • PAR peak-to-average ratio
  • FEM front-end module
  • exemplary aspects of the present disclosure contemplate acquiring a PAR measurement in the FEM and adjusting operating parameters (i.e., APD) within the FEM to create a normalized distortion profile that may simplify digital predistortion (DPD) in a baseband processor (BBP).
  • APD operating parameters
  • PAR measurements may be triggered by various events such as on a per symbol, per slot, or per frame basis and may be tied to changes in a supply voltage level or command to change the supply voltage.
  • Providing such APD may improve efficiency of the operation of the FEM.
  • providing a normalized distortion profile may simplify design requirements for the BBP.
  • a method of normalizing a distortion profile for a FEM comprises measuring a PAR in the FEM.
  • the method also comprises adjusting an operating parameter to change the distortion profile for the FEM.
  • a FEM comprises a power amplifier chain having a PAR characteristic.
  • the FEM also comprises a PAR detector coupled to the power amplifier chain to measure the PAR characteristic.
  • the FEM also comprises a control circuit coupled to the PAR detector. The control circuit is configured, based on measurements from the PAR detector, to adjust an operating parameter of the FEM.
  • a wireless communication device in another aspect, includes a transmission chain comprising a FEM.
  • the FEM includes a power amplifier chain having a PAR characteristic and a PAR detector coupled to the power amplifier chain to measure the PAR characteristic.
  • the FEM further includes a control circuit coupled to the PAR detector and configured to, based on measurements from the PAR detector, adjust an operating parameter of the FEM.
  • FIG. 1 is a block diagram of a conventional front-end module (FEM) coupled to a baseband processor (BBP) through a radio frequency front end (RFFE) bus as part of a transmission chain;
  • FEM front-end module
  • BBP baseband processor
  • RFFE radio frequency front end
  • Figure 2 is a signal diagram showing supply voltage changes versus time relative to slots and symbols for various types of power control circuits, along with supply voltage change commands that may appear on the RFFE bus;
  • Figure 3 is a block diagram of a FEM coupled to a BBP that uses information from an RFFE bus to assist in triggering peak-to-average ratio (PAR) measurements in the FEM according to exemplary aspects of the present disclosure
  • Figure 4 is a block diagram of a FEM with a PAR detector that measures PAR within the FEM to adjust operating parameters of the FEM according to exemplary aspects of the present disclosure
  • Figure 5 is a block diagram of a BBP-FEM pair with a PAR detector that measures PAR within the FEM to adjust operating parameters of the of the FEM according to exemplary aspects of the present disclosure
  • FIG. 6 is a block diagram of a hybrid complementary metal oxide semiconductor (CMOS)-bipolar FEM that may implement portions of the present disclosure in the different technologies;
  • CMOS complementary metal oxide semiconductor
  • Figure 7 is a block diagram similar to Figure 6 but with a different distribution of aspects of the present disclosure between the different technologies;
  • Figure 8 is a block diagram of a hybrid CMOS-bipolar FEM with an integrated PAR detector
  • Figure 9 is a block diagram of the PAR detector of the present disclosure being used in a receive portion of a FEM.
  • Figure 10 is a block diagram of a mobile terminal, which may include the FEM of Figures 3-9 according to the present disclosure.
  • aspects disclosed in the detailed description include peak-to-average ratio (PAR)-based analog predistortion (APD) in a front-end module (FEM).
  • PAR peak-to-average ratio
  • FEM front-end module
  • exemplary aspects of the present disclosure contemplate acquiring a PAR measurement in the FEM and adjusting operating parameters (i.e., APD) within the FEM to create a normalized distortion profile that may simplify digital predistortion (DPD) in a baseband processor (BBP).
  • APD operating parameters
  • PAR measurements may be triggered by various events such as on a per symbol, per slot, or per frame basis and may be tied to changes in a supply voltage level or command to change the supply voltage.
  • Providing such APD may improve efficiency of the operation of the FEM.
  • providing a normalized distortion profile may simplify design requirements for the BBP.
  • FIG. 1 is a block diagram of a transmission chain 100.
  • the transmission chain 100 may include a BBP 102 and a FEM 104.
  • the BBP 102 communicates with the FEM 104 through an RFFE bus 106.
  • the BBP 102 has a bus interface 108, which may be a digital RFFE interface.
  • the FEM 104 may include a bus interface 110 that couples to a digital control circuit 112.
  • the digital control circuit 112 may control aspects of a power amplifier chain 114.
  • the power amplifier chain 114 may include a bias circuit 116, which may provide a static bias to a power amplifier stage 118 within the power amplifier chain 114.
  • the FEM 104 may include a power management integrated circuit (PMIC) that receives power management signals such as envelope tracking (ET) or average power tracking (APT) that sets the bias level in such a way so as to maintain efficiency by keeping the supply voltage at a level appropriate to the desired level of the signal to be transmitted.
  • PMIC power management integrated circuit
  • ET envelope tracking
  • APT average power tracking
  • 5G-NR fifth generation - new radio
  • uplink symbols may vary and changes can be done on a symbol-to-symbol basis, mandating fast settlings within the system.
  • uplink modulations may vary from quadrature phase shift keying (QPSK) up to 256 quadrature amplitude modulation (QAM).
  • QPSK quadrature phase shift keying
  • QAM quadrature amplitude modulation
  • While ET or APT information may pass from the BBP 102 to the FEM 104, there is currently no transfer of information relating to the modulation type between the BBP 102 and the FEM 104.
  • the PAR of the signal may vary significantly depending on the modulation scheme used. PAR has fundamental implications on the linearity of the behavior of the power amplifier chain 114. Because the PAR may impact the compression of the power amplifier stage 118, this absence of communication impacts the operation of the BBP 102. Specifically, there is likely to be more distortion in the power amplifier chain 114, and the BBP 102 is likely to have more DPD to offset this non-linear behavior in the power amplifier chain 114.
  • FIG. 2 illustrates a supply voltage (also referred to as Vcc) change command for various types of APT systems.
  • line 202 corresponding to a traditional slow APT, there may be two supply voltage change commands 204A, 204B per frame 206 on the RFFE bus 106.
  • line 208 there may be multiple supply voltage change commands 210(1)- 210(M) per frame 212. This may cause changes in a supply voltage and power level, as seen by line 214.
  • the line 214 is merely an example, and the actual changes may vary according to the needs of the wireless system.
  • This normalized distortion profile allows the BBP to use a smaller set of DPD coefficients making overall operation simpler for the BBP (as well as saving memory space or the like).
  • the PAR detector may be positioned and there are a variety of adjustments that can be made. These variations are explored in the Figures below.
  • FIG. 3 is a block diagram of a transmission chain 300 that includes a BBP 302 and a FEM 304 coupled by an RFFE bus 306.
  • the BBP 302 may include a bus interface 308, a control circuit 310, and a digital signal processor (DSP) 312. While not shown, the BBP 302 may also include memory.
  • DSP digital signal processor
  • the FEM 304 may include a bus interface 314 coupled to the RFFE bus 306, a power amplifier chain 316, and a PAR detector 318.
  • the bus interface 314 extracts a trigger event from the RFFE bus 306 as better explained below and causes a trigger sense circuit 320 to cause the PAR detector 318 to measure the PAR in the power amplifier chain 316.
  • the RFFE bus 306 is also coupled to a power management integrated circuit (PMIC) 322.
  • the PMIC 322 may include a bus interface 324 and receive supply voltage change commands to adjust a supply voltage provided to the power amplifier chain 316. These supply voltage change commands may be sent from the BBP 302 to the PMIC 322 over the RFFE bus 306 and may be detected by the bus interface 314 and used as trigger events for the trigger sense circuit 320. What is not present on the RFFE bus 306 is any overt indication of a signal modulation scheme or an expected PAR value.
  • the FEM 304 may include a trigger extraction circuit 400 coupled to the bus interface 314.
  • the trigger extraction circuit 400 may send a command to the PAR detector 318.
  • the trigger extraction circuit 400 may provide this information to a decode circuit 402, which may calculate a value of the supply voltage written to the PMIC 322.
  • the output of the PAR detector 318 may be provided to a comparator 404, which compares the measured value to the calculated supply voltage.
  • the comparator 404 may be coupled to an APD control circuit 406, which may adjust operating parameters of the power amplifier chain 316.
  • the information from the PAR detector 318 may be provided back to the bus interface 314 and sent back out through the RFFE bus 306 to an external point (such as the BBP 302) for use as needed or desired.
  • the BBP 302 may include a DPD circuit 500 that is associated with a memory 502 that stores coefficients for the DPD to be applied.
  • Exemplary aspects of the present disclosure normalize the distortion profile so that fewer sets of coefficients are required in the BBP 302. This reduction in DPD coefficient sets allows memory size to be reduced, which may also have the benefit of reducing power consumption.
  • the APD control circuit 406 may adjust, by way of example, a bias circuit 504 that biases one or more power amplifiers in the power amplifier chain 316. In addition, or as an alternative, the APD control circuit 406 may tune a load line 506.
  • the PAR detector 318 may be positioned at various locations in the FEM 304.
  • Figure 6 shows three possible locations.
  • the power amplifier chain 316 may include a driver amplifier stage 600 and an output stage 602 with an interstage node 604 therebetween. While not shown, there may be an intermediate amplifier stage located at the interstage node 604.
  • the PAR detector 318 may be positioned in front of the driver amplifier stage 600 at an input node 606, at the interstage node 604, or after the output stage 602 at an output node 608. While not shown, there may be a bias circuit 504 that may control the driver amplifier stage 600 or the output stage 602 or both.
  • the PAR detector 318 is at the input node 606, the lower signal levels at this point in the power amplifier chain 316 may require more sophisticated detector circuitry. If the PAR detector 318 is at the interstage node 604, a suitable compromise between signal levels and ease of detection may be achieved. If the PAR detector 318 is at the output node 608, the signal is easy to detect, but there may be compression of the signal, which may negatively impact PAR estimation. Other tradeoffs may exist for biasing the driver amplifier stage 600 or the output stage 602.
  • Figure 7 shows one possible implementation in a hybrid complementary metal oxide semiconductor (CMOS)-bipolar technology system 700.
  • the output stage 602 may be made from a bipolar technology such as gallium arsenide (GaAs).
  • the driver amplifier stage 600 and the bias circuits 504A, 504B are within a CMOS die 702.
  • the PAR detector 318 may also be in the CMOS die 702.
  • the load line 506 tuning may be bipolar or made on a silicon on insulator (Sol) die 704.
  • the PAR detector 318 may include a peak power detector 800 and an average power detector 802.
  • a digital controller 804 may subtract or compute the PAR based on signals from the peak power detector 800 and the average power detector 802.
  • tuning the load line 506 may be done through switched capacitors.
  • a receive chain 900 may include a low noise amplifier (LNA) 902 having a bias circuit 904.
  • LNA low noise amplifier
  • a PAR detector 906 may provide a PAR measurement that is used to set the bias of the bias circuit 904.
  • the concepts described above may be implemented in various types of user elements 1000, such as mobile terminals, smart watches, tablets, computers, navigation devices, access points, and like wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, and near field communications.
  • the user elements 1000 will generally include a control system 1002, a BBP 1004, transmit circuitry 1006, receive circuitry 1008, antenna switching circuitry 1010, multiple antennas 1012, and user interface circuitry 1014.
  • the control system 1002 can be a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), as an example.
  • FPGA field-programmable gate array
  • ASIC application-specific integrated circuit
  • the control system 1002 can include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s).
  • the receive circuitry 1008 receives radio frequency signals via the antennas 1012 and through the antenna switching circuitry 1010 from one or more base stations.
  • An LNA and a filter of the receive circuitry 1008 cooperate to amplify and remove broadband interference from the received signal for processing.
  • Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog-to-digital converter(s) (ADC).
  • ADC analog-to-digital converter
  • the BBP 1004 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations, as will be discussed on greater detail below.
  • the BBP 1004 is generally implemented in one or more DSPs and ASICs.
  • the BBP 1004 receives digitized data, which may represent voice, data, or control information, from the control system 1002, which it encodes for transmission.
  • the encoded data is output to the transmit circuitry 1006, where a digital- to-analog converter(s) (DAC) converts the digitally-encoded data into an analog signal and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies.
  • DAC digital- to-analog converter(s)
  • a power amplifier will amplify the modulated carrier signal to a level appropriate for transmission and deliver the modulated carrier signal to the antennas 1012 through the antenna switching circuitry 1010 to the antennas 1012.
  • the multiple antennas 1012 and the replicated transmit and receive circuitries 1006, 1008 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Algebra (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Amplifiers (AREA)

Abstract

L'invention concerne une prédistorsion analogique (APD) basée sur un rapport de crête sur moyenne (PAR) dans un module frontal (FEM). Selon un aspect, un FEM acquiert une mesure PAR et ajuste des paramètres de fonctionnement (c'est-à-dire, APD) à l'intérieur du FEM pour créer un profil de distorsion normalisé qui peut simplifier une prédistorsion numérique dans un processeur de bande de base (BBP). Des mesures PAR peuvent être déclenchées par divers événements tels que sur une base par symbole, par intervalle, ou par trame et peuvent être liées à des variations d'un niveau de tension d'alimentation ou à une commande pour faire varier la tension d'alimentation. La fourniture d'un tel APD peut améliorer l'efficacité du fonctionnement du FEM. De même, la fourniture d'un profil de distorsion normalisé peut simplifier les exigences de conception pour le BBP.
PCT/US2023/035072 2023-01-30 2023-10-13 Prédistorsion analogique (apd) basée sur un rapport crête sur moyenne (par) dans un module frontal WO2024162999A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US202363482093P 2023-01-30 2023-01-30
US63/482,093 2023-01-30

Publications (1)

Publication Number Publication Date
WO2024162999A1 true WO2024162999A1 (fr) 2024-08-08

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5598127A (en) * 1992-12-23 1997-01-28 Italtel S.P.A. Procedure and circuit for adaptive compensation of the gain distortions of a microwave amplifier with linearizer
US6166598A (en) * 1999-07-22 2000-12-26 Motorola, Inc. Power amplifying circuit with supply adjust to control adjacent and alternate channel power
US6438360B1 (en) * 1999-07-22 2002-08-20 Motorola, Inc. Amplifier system with load control to produce an amplitude envelope
US20150042406A1 (en) * 2013-08-08 2015-02-12 Peregrine Semiconductor Corporation Peak-to-Average Ratio Detector
US9985590B2 (en) * 2016-01-27 2018-05-29 Mediatek Inc. Adaptive power amplifier supply with pre-distortion mechanism
US20180241350A1 (en) * 2017-02-17 2018-08-23 Qorvo Us, Inc. Rf power amplifier dynamic supply boosting circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5598127A (en) * 1992-12-23 1997-01-28 Italtel S.P.A. Procedure and circuit for adaptive compensation of the gain distortions of a microwave amplifier with linearizer
US6166598A (en) * 1999-07-22 2000-12-26 Motorola, Inc. Power amplifying circuit with supply adjust to control adjacent and alternate channel power
US6438360B1 (en) * 1999-07-22 2002-08-20 Motorola, Inc. Amplifier system with load control to produce an amplitude envelope
US20150042406A1 (en) * 2013-08-08 2015-02-12 Peregrine Semiconductor Corporation Peak-to-Average Ratio Detector
US9985590B2 (en) * 2016-01-27 2018-05-29 Mediatek Inc. Adaptive power amplifier supply with pre-distortion mechanism
US20180241350A1 (en) * 2017-02-17 2018-08-23 Qorvo Us, Inc. Rf power amplifier dynamic supply boosting circuit

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