WO2024160156A1 - 一种译码方法、第一裸片和第二裸片 - Google Patents

一种译码方法、第一裸片和第二裸片 Download PDF

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Publication number
WO2024160156A1
WO2024160156A1 PCT/CN2024/074317 CN2024074317W WO2024160156A1 WO 2024160156 A1 WO2024160156 A1 WO 2024160156A1 CN 2024074317 W CN2024074317 W CN 2024074317W WO 2024160156 A1 WO2024160156 A1 WO 2024160156A1
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Prior art keywords
die
access request
address
address space
bare chip
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PCT/CN2024/074317
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English (en)
French (fr)
Inventor
刘康
郑锦涛
张俊
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华为技术有限公司
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Publication of WO2024160156A1 publication Critical patent/WO2024160156A1/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders

Definitions

  • the embodiments of the present application relate to the field of chip technology, and in particular to a decoding method, a first bare chip, and a second bare chip.
  • the chiplet includes various functional modules, such as processor core, accelerator and double data rate synchronous dynamic random-access memory (DDR SDRAM).
  • Various functional modules are connected through a bus, where the bus can be a ring, mesh crossbar or crossbar structure.
  • the functional modules visit each other through the "request-response" handshake method.
  • the request of the functional module passes through the decoding node before entering the bus.
  • the decoding node uses the mapping relationship between the address and the destination module to translate the address in the request and provide the address information of the corresponding destination module, providing a basis for bus routing.
  • An embodiment of the present application provides a decoding method, a first bare chip, and a second bare chip.
  • a decoding method Through hierarchical decoding, only the address space information of the module of the first bare chip and the address space information of other bare chips are configured at the first bare chip, thereby reducing the configuration information of the first bare chip and reducing the complexity of decoding.
  • an embodiment of the present application provides a decoding method, which is applied to a first bare chip, the first bare chip includes multiple functional modules, the first bare chip is configured with first address space information, the first address space information includes address space information of each functional module in the first bare chip and address space information of other bare chips except the first bare chip, the method includes: the first bare chip determines whether the first access request is used to access the first bare chip according to the first address space information and the first address information carried by the first access request; if the first bare chip determines that the first access request is not used to access the first bare chip, the first bare chip decodes according to the first address information to obtain a bare chip identification of the second bare chip, and sends a second access request to the second bare chip, the second access request includes the first address information and the bare chip identification of the second bare chip, and the second access request is used for the second bare chip to decode to obtain the module identification of the functional module of the first access request to access
  • the first die is only configured with the address space information of each functional module in the first die and the address space information of other die, but not with the address space information of each functional module in other die, thereby reducing the configuration information of the first die and reducing the circuit area of the decoding node.
  • the first die adopts a hierarchical decoding method, and before the first access request is put on the bus, it will first determine whether the first access request is used to access the first die. If the first access request is not used to access the first die, the first die will obtain the die identification of the second die according to the first address information carried by the first access request, and decode at the second die to obtain the module identification of the functional module accessed by the first access request.
  • hierarchical decoding reduces the complexity of decoding and helps the timing convergence of decoding.
  • hierarchical decoding reduces the complexity of decoding and helps the timing convergence of decoding.
  • each die only the architecture of the die connected to the first die is concerned, and there is no need to pay attention to the internal topological structure of the connected die, which simplifies the design requirements of multi-die interconnection and realizes the flexible expansion of decoding under any die interconnection structure.
  • there is no need to design different decoding principles thus ensuring the feasibility of bare chip sharing.
  • the method further includes: if the first bare chip determines that the first access request is for accessing the first bare chip, the first bare chip decodes according to the first address information to obtain a module identifier of a functional module for accessing the first bare chip by the first access request.
  • the first bare chip since the address space information of each functional module is configured in the first bare chip, if the first access request is used to access the first bare chip, the first bare chip decodes and obtains the complete chip identification, bare chip identification and module identification corresponding to the first address information to complete the mutual access of the functional modules in the first bare chip.
  • the address space information of each functional module in the first die includes the base address of each functional module in the first die and the address space size of each functional module in the first die
  • the address space information of other die includes the base address of other die and the address space size of other die
  • the address space information of the functional module can be understood as an address range, and the address space information of other bare chips can also be understood as an address range.
  • the address space information of other bare chips can also be understood as an address range.
  • the configuration information of the first bare chip is reduced, and the reserved window can be used for cross-bare chip interconnection. There is no need to pay attention to the internal topological structure of the connected bare chips, which simplifies the design requirements of multi-bare chip interconnection and realizes the flexible expansion of decoding under any bare chip interconnection structure.
  • the first address information is used to decode and obtain a chip identifier, a die identifier, and a module identifier corresponding to the functional module accessed by the first access request.
  • the process of decoding the first address information to obtain the chip identification, die identification and module identification corresponding to the functional module is essentially a table lookup process.
  • the first address information corresponds to an address in the first address space information, and the functional module corresponding to the address can be determined, thereby determining the chip identification, die identification and module identification corresponding to the functional module.
  • the first bare chip determines whether the first access request is used to access the first bare chip based on the first address space information and the first address information carried by the first access request, including: when the first bare chip determines that the first address information is within the address range of the address space information of other bare chips, the first bare chip determines that the first access request is not used to access the first bare chip; when the first bare chip determines that the first address information is within the address range of the address space information of a functional module in the first bare chip, the first bare chip determines that the first access request is used to access the first bare chip.
  • the first die before the first decoding, the first die will first perform address matching, and by determining whether the first address information corresponds to the address range of other die or the address range of the functional module, it is determined whether the first access request is for accessing the first die. For the first access request to access the first die, the first decoding node decodes to obtain the complete functional module identification. For the first access request not to access the first die, the first decoding node decodes only to obtain the chip identification and the die identification. As a result, the complexity of decoding is reduced, which helps the timing convergence of decoding.
  • an embodiment of the present application provides a decoding method, which is applied to a second bare chip, and the method includes: the second bare chip receives a second access request sent by the first bare chip, and the second access request includes first address information and a bare chip identifier obtained by decoding the first bare chip; when the second bare chip determines that the bare chip identifier is the bare chip identifier of the second bare chip, the second bare chip decodes according to the first address information to obtain a module identifier of a functional module of the second bare chip accessed by the second access request.
  • the second decoding before the second decoding is performed at the cross-die interface of the second die, it is first determined whether the die identifier obtained by decoding the first die in the second access request is the second die identifier. If the die identifier is the die identifier of the second die, the second decoding will be performed at the cross-die interface of the second die. As a result, the decoding node at the second die only needs to configure the address space information of the second die and the address space information of other die, which can greatly reduce the configuration information of each decoding node and reduce the circuit area required for decoding. At the same time, hierarchical decoding also reduces the complexity of decoding, which helps the timing convergence of decoding.
  • the method further includes: when the second die determines that the die identifier is not the die identifier of the second die, the second die transmits the second access request to the third die.
  • the second die transparently transmits the second access request to the third die without decoding, thereby reducing the number of decodings and improving the efficiency of access request transmission.
  • the second die includes multiple functional modules, and the second die is configured with second address space information, which includes address space information of each functional module in the second die and address space information of other die except the second die.
  • the first die and the second die in the chip system are only configured with the address space information of the functional modules of the die and the address space information of other die, thereby reducing the configuration information of the first die and the second die and reducing the circuit area of the decoding node.
  • the address space information of each functional module in the second die includes the base address of each functional module in the second die and the address space size of each functional module in the second die
  • the address space information of other die includes the base address of other die and the address space size of other die
  • an embodiment of the present application provides a first bare chip, the first bare chip includes multiple functional modules, the first bare chip is configured with first address space information, the first address space information includes address space information of each functional module in the first bare chip and address space information of other bare chips except the first bare chip, the first bare chip also includes: a determination unit, used to determine whether the first access request is used to access the first bare chip based on the first address space information and the first address information carried by the first access request; a first decoding unit, used to decode according to the first address information to obtain a bare chip identification of the second bare chip if the first bare chip determines that the first access request is not used to access the first bare chip, and send a second access request to the second bare chip, the second access request includes the first address information and the bare chip identification of the second bare chip, the second access request is used for the second bare chip to decode to obtain the module identification of the functional module of the first access request to access the second bare chip
  • the first decoding unit is further used to, if the first bare chip determines that the first access request is for accessing the first bare chip, decode the first bare chip according to the first address information to obtain a module identifier of a functional module for accessing the first bare chip by the first access request.
  • the address space information of each functional module in the first die includes the base address of each functional module in the first die and the address space size of each functional module in the first die
  • the address space information of other die includes the base address of other die and the address space size of other die
  • the first address information is used to decode and obtain a chip identifier, a die identifier, and a module identifier corresponding to the functional module accessed by the first access request.
  • the determination unit is also used to, when the first die determines that the first address information is within the address range of the address space information of other die, determine that the first access request is not used to access the first die; when the first die determines that the first address information is within the address range of the address space information of a functional module in the first die, determine that the first access request is used to access the first die.
  • an embodiment of the present application provides a second bare chip, the second bare chip comprising: a receiving unit, used to receive a second access request sent by the first bare chip, the second access request comprising first address information and a bare chip identifier obtained by decoding the first bare chip; a second decoding unit, used to decode according to the first address information to obtain a module identifier of a functional module of the second bare chip accessed by the second access request when the second bare chip determines that the bare chip identifier is the bare chip identifier of the second bare chip.
  • the second die further includes: a transmission unit, configured to transmit the second access request to the third die when the second die determines that the die identifier is not the die identifier of the second die.
  • the second die includes multiple functional modules, and the second die is configured with second address space information, which includes address space information of each functional module in the second die and address space information of other die except the second die.
  • the address space information of each functional module in the second die includes the base address of each functional module in the second die and the address space size of each functional module in the second die
  • the address space information of other die includes the base address of other die and the address space size of other die
  • an embodiment of the present application provides a computer-readable storage medium, including computer instructions.
  • the computer instructions When the computer instructions are executed on an electronic device, the electronic device executes the decoding method in any of the above aspects and any possible implementation methods.
  • an embodiment of the present application provides a computer program product.
  • the computer program product runs on a computer or a processor
  • the computer or the processor executes the decoding method in any of the above aspects and any possible implementation methods.
  • any of the first bare chip, second bare chip, computer-readable storage medium or computer program product provided above can be applied to the corresponding method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding method and will not be repeated here.
  • FIG1 is a schematic diagram of the structure of a chip system provided in an embodiment of the present application.
  • FIG2 is a topological diagram of a different bus provided in an embodiment of the present application.
  • FIG3 is a structural diagram of a chip system based on ring bus mutual access provided by an embodiment of the present application.
  • FIG4 is a schematic diagram of the structure of an execution device provided in an embodiment of the present application.
  • FIG5 is a schematic diagram of an address space configuration of a first decoding node provided in an embodiment of the present application.
  • FIG6 is a schematic diagram of the structure of another chip system provided in an embodiment of the present application.
  • FIG7 is a flowchart of a decoding method provided in an embodiment of the present application.
  • FIG8 is a flow chart of another decoding method provided in an embodiment of the present application.
  • FIG. 9 is a flowchart of a first bare chip access request processing provided by an embodiment of the present application.
  • FIG10 is a flowchart of another decoding method provided in an embodiment of the present application.
  • FIG. 11 is a flowchart of an access request processing of a second die provided by an embodiment of the present application.
  • FIG. 12 is a flowchart of another access request processing of a second die provided in an embodiment of the present application.
  • FIG13 is a schematic diagram of address space configuration of a first decoding node and a second decoding node provided in an embodiment of the present application;
  • FIG14 is a schematic diagram of a possible composition of a first bare chip provided in an embodiment of the present application.
  • FIG. 15 is a schematic diagram of a possible composition of a second bare chip provided in an embodiment of the present application.
  • Interposer a silicon interposer, the logic chip placed on the interposer is connected through through silicon via (TSV) microelectrodes.
  • TSV silicon via
  • Mesh bus all functional modules in the mesh bus are interconnected, and each functional module is connected to at least two other functional modules, forming an integrated chip system between all functional modules.
  • Ring bus (ring bus), the ring bus consists of four independent "rings", namely data ring, request ring, response ring and listening ring. Each node of each "ring” can receive 32 bytes of data in each clock cycle. This division mode allows the access of the "ring” to automatically select the shortest path to shorten the delay.
  • Crossbar switch matrix the physical connection from the functional module to the switching structure in the crossbar switch matrix bus is simplified to a point-to-point connection, which can ensure the stability of data transmission.
  • multiple functional modules connected to the crossbar switch matrix bus can transmit data simultaneously, which can improve the efficiency of data transmission.
  • first and second are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.
  • a feature defined as “first” or “second” may explicitly or implicitly include one or more of the features.
  • plural means two or more.
  • chiplet technology is a technology that uses TSV packaging technology to package multiple different wafers or dies in a chip (chip), and completes the functions of a complex chip through the combination of different dies.
  • the chip structure using TSV packaging technology is called chiplet architecture, as shown in Figure 1, which is a structural schematic diagram of a chip system provided in an embodiment of the present application.
  • the chip system may include DIE0 and DIE1, DIE0 may be a logic die, and DIE1 may be a high bandwidth memory (HBM).
  • DIE0 and DIE1 are coupled through an interposer and a substrate, thereby forming a chip system.
  • the chip system includes various functional modules, such as core, accelerator and DDR SDRAM.
  • Various functional modules are connected through a bus, as shown in Figure 2, which is a topological structure diagram of a different bus provided in an embodiment of the present application.
  • Figure 2 shows the topological structure diagram of a mesh bus, a ring bus and a cross switch matrix bus.
  • the bus connects a total of 16 functional modules, namely functional modules 0-15, and its topological structure is a 4x4 mesh structure.
  • the bus connects a total of 4 functional modules, namely functional modules 0-3.
  • All functional modules in the ring bus are connected to the ring bus, and the interaction between each functional module is convenient and flexible, without the need for transfer in the processor.
  • the bus connects a total of 8 functional modules, namely functional modules 0-7.
  • FIG. 3 is a structural diagram of a chip system based on ring bus mutual access provided by an embodiment of the present application.
  • the chip system includes DIE1 and DIE0, wherein DIE0 includes functional module A and functional module B, DIE1 includes functional module C and functional module D, and DIE0 and DIE1 are coupled through a cross-bare chip interface.
  • the functional module D issues an access request and carries the address information of the functional module A.
  • the access request passes through the decoding node before entering the bus.
  • the decoding node determines that the address information corresponds to the functional module A through the address information, and attaches the target node identification (target identity document, tgtid) of the functional module A in the request.
  • the access request enters the bus, enters the bus of DIE0 through the cross-bare chip interface between DIE0 and DIE1, and reaches the functional module A.
  • the function module A replies with a response or data, thereby completing the process of the function module D accessing the function module A.
  • tgtid includes chip identification (socket identity document, sktid), die identification (die identity document, dieid) and module identification (port identity document, portid).
  • sktid is the chip identification of the chip where the destination node is located
  • dieid is the die identification of the die where the destination node is located
  • portid is the module identification of the functional module where the destination node is located.
  • the bus of DIE1 recognizes that sktid is this chip, but dieid is not this die, so it sends the request to the cross-die interface to reach the destination die, and the bus of DIE0 then uses portid to send the request to functional module A.
  • decoding is to translate the address in the access request by using the mapping relationship between address information and functional modules.
  • the mapping relationship is shown in Table 1.
  • the base address, address space size (size) and tgtid are configured.
  • the base address and address space size can determine an address range.
  • the corresponding tgtid is the tgtid configured for the window.
  • an address window is configured for each address segment.
  • the decoding process of the access request is essentially a table lookup process.
  • on-chip decoding is generally implemented based on the principle of leveling, that is, each decoding node can obtain the topological structure of the entire chip system.
  • complex topological structures will lead to an increase in the configuration information of the decoding nodes, and all of this configuration information needs to be stored and calculated, thereby increasing the area overhead of the circuit.
  • the leveling principle will in turn limit the expansion space and reduce the flexibility of complex topologies. For example, each decoding node is designed with 32 windows, and each die requires 8 windows, then the chip system can only support the interconnection of up to 4 dies.
  • an embodiment of the present application provides a decoding method, which is applied to a first bare chip in a chip system.
  • the chip system is first introduced below.
  • the chiplet system can be applied to different devices, such as the execution device 40 shown in FIG4 , which is a schematic diagram of the structure of an execution device provided in an embodiment of the present application.
  • the execution device 40 can be a terminal, such as a server 41, a mobile terminal 42, a tablet computer 43, a laptop computer 44, an augmented reality (AR) device (not shown in FIG4 ), a virtual reality (VR) device (not shown in FIG4 ), a vehicle-mounted terminal (not shown in FIG4 ), etc.
  • AR augmented reality
  • VR virtual reality
  • the chip system includes multiple bare chips (dies) with specific functions that can be modularly assembled with each other.
  • bare chips can realize functions such as data storage, computing, signal processing, and data flow management.
  • IP intellectual property core
  • the chiplet system proposes the concept of IP chip (IP as a chiplet, IaaC), aiming to realize the "plug and play" of special function IP with bare chips.
  • bare chips can be graphics processing unit (GPU) IP, neural network processor (NPU) IP, video processor (VPU) IP, digital signal processor (DSP) IP, image signal processor (ISP) IP, and display processor IP.
  • bare chips can also be mixed digital and analog IPs and radio frequency IPs.
  • the chiplet system in this application can also be called a chip system or a core particle system. That is, a bare die can also be called a small chip or a core particle.
  • the chiplet system can be applied to a system-on-a-chip (SoC), on which a die with multiple functions is integrated.
  • SoC system-on-a-chip
  • the chip system includes the first die provided in the embodiment of the present application, wherein the first die includes multiple functional modules, such as functional module A and functional module B, etc.
  • the functional modules may be cores, accelerators, and DDR SDRAM, etc.
  • the first die is configured with first address space information, and the first address space information includes address space information of each functional module in the first die and address space information of other die except the first die.
  • the first bare chip may include a first decoding node, and the first decoding node is configured with first address space information.
  • the first decoding node may be implemented by hardware, for example, the first decoding node may be a group of multi-input multi-output logic circuits.
  • FIG5 is a schematic diagram of the address space configuration of a first decoding node provided by an embodiment of the present application. Each segment of the address space corresponds to a decoding window.
  • the shared address space is an address space for storing functional modules shared by each bare chip due to the configuration requirements of the chip system
  • the address space of functional module A is the address space allocated to functional module A
  • the address space of functional module B is the address space allocated to functional module B
  • the address space of other bare chips is the address space allocated to other bare chips
  • the other bare chips may be the second bare chip and the third bare chip, etc.
  • the configuration method of the address space of the first decoding node in the embodiment of the present application only configures the address space of each functional module of the first die and the address space of other die, but does not configure the address space of the functional modules in other die, which can reduce the configuration information of the decoding node and reduce the space occupied by the decoding node. circuit area.
  • the embodiment of the present application provides a decoding method, in which the first die adopts a hierarchical decoding method. Before the first access request is put on the bus, it will first determine whether the first access request is used to access the first die. If the first access request is not used to access the first die, the first die will obtain the die identification of the second die according to the first address information carried by the first access request, and decode at the second die to obtain the module identification of the functional module accessed by the first access request. Compared with the prior art in which the first die obtains the complete identification of the functional module accessed by the first access request according to the first address information, hierarchical decoding reduces the complexity of decoding and helps the timing convergence of decoding.
  • FIG. 6 is a structural schematic diagram of another chip system provided in the embodiment of the present application.
  • Two bare chips are shown in Figure 6, namely DIE0 and DIE1, wherein DIE0 includes functional module A and functional module B, DIE1 includes functional module C and functional module D, and DIE0 and DIE1 are coupled through the cross-die interface.
  • DIE1 also includes a first decoding node and a fourth decoding node, wherein the first decoding node is arranged between functional module D and the bus, and the fourth decoding node is arranged between the cross-die interface and the bus.
  • DIE0 also includes a second decoding node and a third decoding node, wherein the second decoding node is arranged between the cross-die interface and the bus, and the third decoding node is arranged between functional module A and the bus.
  • the embodiment of the present application provides a decoding method, as shown in FIG7 , which is a flow chart of a decoding method provided by the embodiment of the present application.
  • the method includes the following process.
  • Step 701 A first die determines whether a first access request is for accessing the first die according to first address space information and first address information carried in a first access request.
  • the first decoding node when configuring the address space of the first decoding node of the first die, only the address space information of each functional module of the first die and the address space information of other die are configured. Therefore, before the first access request enters the bus, at the first decoding node, it will be determined whether the first access request is used to access the first die. If the first access request is used to access the first die, that is, the first access request is for the functional module in the first die to access the functional module in the first die, at this time, the first decoding node should determine the address space information of the functional module accessed by the first access request based on the first address information carried by the first access request, thereby completing the access between the functional modules in the first die.
  • the first decoding node should determine the address space information of the other die accessed by the first access request based on the first address information carried by the first access request, thereby completing the process of sending the first access request to other die.
  • the address space information of each functional module in the first die includes the base address of each functional module in the first die and the address space size of each functional module in the first die, and the address space information of other die includes the base address of other die and the address space size of other die.
  • the address space information of the functional module can be understood as an address range, that is, the address space is an address range starting from the base address and having a size equal to the address space size.
  • the address space information of other bare chips can also be understood as an address range.
  • each functional module is independent of the address space size of other bare chips and can be divided according to the required address space size of each functional module.
  • Step 702 If the first die determines that the first access request is not used to access the first die, the first die decodes the first address information to obtain the die identification of the second die, and sends a second access request to the second die, where the second access request includes the first address information and the die identification of the second die, and the second access request is used by the second die to decode to obtain the module identification of the functional module of the second die accessed by the first access request.
  • the first address information is used to decode and obtain the chip identification, die identification and module identification corresponding to the functional module accessed by the first access request.
  • the process of decoding the first address information to obtain the chip identification, die identification and module identification corresponding to the functional module is essentially a table lookup process.
  • the first address information corresponds to an address in the first address space information, and the functional module corresponding to the address can be determined, thereby determining the chip identification, die identification and module identification corresponding to the functional module.
  • the first die may determine that the first access request is not for accessing the first die.
  • the address space information of each functional module in other bare chips is set, and the decoding at the first decoding node can only obtain the bare chip identification of the second bare chip.
  • the first bare chip sends the second access request to the cross-bare chip interface between the second bare chip and the first bare chip through the bus.
  • the second access request carries the first address information and the bare chip identification of the second bare chip. So that the second decoding node at the second bare chip decodes the first address information again to obtain the module identification of the functional module of the second bare chip accessed by the first access request.
  • each decoding node only needs to configure the address space information of each bare chip and the address space information of each functional module in the bare chip, which can greatly reduce the configuration information of each decoding node and reduce the circuit area required for decoding.
  • hierarchical decoding also reduces the complexity of decoding, which is conducive to the timing convergence of decoding.
  • each bare chip when designing each bare chip, only the architecture of the bare chip connected to the first bare chip is concerned, and there is no need to pay attention to the internal topological structure of the connected bare chip, which simplifies the design requirements of multi-bare chip interconnection and realizes flexible expansion of decoding under any bare chip interconnection structure. And for different connected bare chips, there is no need to design different decoding principles, which can ensure the feasibility of bare chip sharing.
  • FIG8 is a flowchart of another decoding method provided in an embodiment of the present application.
  • the method may further include step 703 .
  • Step 703 If the first die determines that the first access request is for accessing the first die, the first die decodes the first address information to obtain a module identifier of a functional module for accessing the first die by the first access request.
  • the first die can determine that the first access request is for accessing the first die. Since the address space information of each functional module in the first die is configured at the first decoding node, the first decoding node can decode the chip identifier, die identifier, and module identifier of the functional module for accessing the first die by the first access request based on the first address information. At this time, the chip identifier of the functional module is the chip identifier of the chip where the first die is located, and the die identifier of the functional module is the die identifier of the first die.
  • the process at the first decoding node is as shown in Figure 9, which is a flowchart of a first bare chip access request processing provided by an embodiment of the present application.
  • the process may include: the first bare chip performs a first address information match, if the first address information corresponds to the address space of the functional module in the first bare chip, then the first decoding node performs decoding to obtain the complete tgtid of the functional module accessed by the first access request, that is, obtains sktid, dieid and portid.
  • the first decoding node performs decoding to obtain the chip identifier and bare chip identifier of the functional module accessed by the first access request, that is, obtains sktid and dieid.
  • the first decoding node can also decode to obtain the complete tgtid of the functional module accessed by the first access request, that is, to obtain sktid, dieid and portid.
  • the decoding node at the cross-die interface should ensure that the tgtid remains unchanged after re-decoding.
  • step 701 may include: when the first die determines that the first address information is within an address range of address space information of another die, the first die determines that the first access request is not for accessing the first die.
  • the first address space information includes the base address Addr_DIE1 of DIE1, assuming that the address space size of DIE1 is 4G.
  • the address space corresponding to DIE1 is an address space starting from Addr_DIE1 and having a size of 4G. If the first address information is within the address range of the address space information of DIE1, it can be considered that the first access request is used to access DIE1, and the first access request is sent to DIE1.
  • step 701 may also include: when the first die determines that the first address information is within an address range of address space information of a functional module in the first die, the first die determines that the first access request is used to access the first die.
  • the first address space information includes the base address Addr_A of the function module A, assuming that the address space size of the function module A is 2G.
  • the address space corresponding to the function module A is an address space starting from Addr_A and having a size of 2G. If the first address information is within the address range of the address space information of the function module A in the first bare chip, it can be considered that the first access request is used to access the function module A.
  • the embodiment of the present application provides another decoding method, which is applied to the second bare chip, as shown in FIG10 , which is a flow chart of another decoding method provided by the embodiment of the present application.
  • the decoding method includes the following process.
  • Step 1001 A second bare chip receives a second access request sent by a first bare chip, where the second access request includes first address information and a bare chip identifier obtained by decoding the first bare chip.
  • the first die and the second die are coupled via an inter-die interface, and the second die receives a second access request sent by the first die via the inter-die interface, wherein the second access request carries the first address information and a die identifier decoded by the first die.
  • Step 1002 When the second die determines that the die identifier is the die identifier of the second die, the second die decodes the first address information to obtain the module identifier of the functional module of the second die accessed by the second access request.
  • a second decoding node is provided at the inter-die interface between the second die and the first die, and the second decoding node is configured with address space information of each functional module in the second die. If the die identifier is the die identifier of the second die, the second access request is used to access the functional module in the second die. The second decoding node decodes the first address information to obtain the module identifier of the functional module of the second die accessed by the second access request.
  • FIG11 is a flowchart of an access request processing of a second bare chip provided by an embodiment of the present application. If a second access request is received at the cross-bare-die interface of the second bare chip, it is determined whether it is an access request of the present bare chip. If it is an access request of the present bare chip, the second decoding node performs decoding to obtain the module identifier of the functional module accessed by the second access request, and the second access request is aggregated on the bus of the second bare chip to be sent to the functional module accessed by the second access request. If it is not an access request of the present bare chip, the second access request is aggregated on the bus and sent to the cross-bare-die interface between the second bare chip and other bare chips.
  • Step 1003 When the second die determines that the die identifier is not the die identifier of the second die, the second die transmits a second access request to the third die.
  • the chip system includes a first die, a second die, and a third die, wherein the first die and the second die are coupled via an inter-die interface, and the second die and the third die are coupled via an inter-die interface. If the second die determines that the die identifier is not the die identifier of the second die, taking the function module in the first die accessing the function module in the third die as an example, the second die receives a second access request, determines that the second access request is not an access request of the die, and the second decoding node at the inter-die interface of the second die does not decode the first address information carried by the second access request, that is, the second decoding node transparently transmits the second access request.
  • the second access request is aggregated on the bus and sent to the inter-die interface of the second die and the third die, the third die determines that the die identifier is the die identifier of the third die, and the decoding node at the inter-die interface of the third die decodes the first address information carried by the second access request to obtain the module identifier of the function module of the third die accessed by the second access request.
  • Figure 12 is another access request processing flow chart of the second bare chip provided by an embodiment of the present application.
  • the second access request is received at the cross-bare chip interface of the second bare chip, and the second access request carries the chip identifier of the second bare chip and the die identifier of the second bare chip, that is, the second access request carries sktid and dieid.
  • the second bare chip matches sktid and dieid. If sktid and dieid are not the chip or the bare chip, the second access request is transparently transmitted, that is, the second access request is transmitted to the cross-bare chip interface of the second bare chip and other bare chips through the bus.
  • non-chip and bare chip include the situation of non-chip and non-bare chip, and the situation of non-chip and non-bare chip. If sktid and dieid are the chip or the bare chip, the second decoding node performs address matching based on the first address information, and decodes to obtain the module identifier of the functional module of the second bare chip accessed by the second access request.
  • the second die includes a plurality of functional modules, the second die is configured with second address space information, and the second address space information includes address space information of each functional module in the second die and address space information of other die except the second die.
  • the address space information of each functional module in the second die includes a base address of each functional module in the second die and an address space size of each functional module in the second die, and the address space information of other die includes base addresses of other die and address space sizes of other die.
  • the second bare chip may include a second decoding node, and the second decoding node is configured with second address space information.
  • the second decoding node may also be implemented by hardware, for example, the second decoding node may be a group of multi-input multi-output logic circuits.
  • the first bare chip includes a first decoding node
  • the second bare chip includes a second decoding node.
  • the first decoding node or the second decoding node may be a decoding node between a functional module and a bus
  • the first decoding node or the second decoding node may also be a decoding node between a bus and a cross-bare chip interface.
  • FIG13 is a schematic diagram of an address space configuration of a first decoding node and a second decoding node provided in an embodiment of the present application.
  • each segment of the address space corresponds to a decoding window.
  • the shared address space is an address space for storing functional modules shared by each bare chip due to the configuration requirements of the chip system, that is, the first decoding node and the second decoding node are both configured with a shared address space.
  • the first decoding node is also configured with the address space of the function module A of the first die, the address space of the function module B of the first die, and the address space of the second die.
  • the second decoding node is also configured with the address space of the function module C of the second die, the address space of the function module D of the second die, and the address space of the first die.
  • the first decoding node and the second decoding node are only configured with the address space of each functional module of the bare chip and the address space of other bare chips, but not with the address space of the functional modules in other bare chips, which can reduce the configuration information of the decoding nodes and reduce the circuit area occupied by the decoding nodes.
  • the first bare die is DIE1 and the second bare die is DIE0.
  • function module D requests to access function module A as an example
  • function module D issues a first access request and carries the first address information of function module A.
  • DIE1 will first determine whether the first access request is a request to access the function module in DIE1. Since the first access request is to access function module A in DIE0, the first decoding node can decode the bare die identification of DIE0 based on the first address information. The first decoding node sends the second access request through the bus in DIE1 to the cross-bare die interface between DIE0 and DIE1.
  • the second access request carries the first address information of function module A and the bare die identification of DIE0.
  • DIE0 determines whether the second access request carries The die identifier is the die identifier of DIE0, and the second decoding node performs decoding according to the first address information to obtain the module identifier of the functional module A in DIE0.
  • DIE0 sends the second access request to the functional module A through the bus in DIE0.
  • the functional module A replies with a response or data, thereby completing the process of the functional module D accessing the functional module A.
  • the third decoding node performs the same processing as the first decoding node
  • the fourth decoding node performs the same processing as the second decoding node, which will not be described in detail here.
  • the decoding method provided by the embodiment of the present application reduces the configuration information of the decoding nodes and reduces the complexity of decoding through hierarchical decoding.
  • a limited window can be reserved for cross-die interconnection, and there is no need to pay attention to the topological interface inside the die interconnected with the cross-die interface, which simplifies the design requirements of multi-die interconnection and realizes flexible expansion of decoding under any multi-die interconnection structure.
  • the electronic device includes hardware and/or software modules corresponding to the execution of each function.
  • the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application in combination with the embodiments, but such implementation should not be considered to be beyond the scope of the present application.
  • the electronic device can be divided into functional modules according to the above method example.
  • each functional module can be divided according to each function, or two or more functions can be integrated into one processing module.
  • the above integrated module can be implemented in the form of hardware. It should be noted that the division of modules in this embodiment is schematic and is only a logical function division. There may be other division methods in actual implementation.
  • an electronic device may include a first die and a second die.
  • FIG14 shows a possible composition diagram of the first bare chip 1400 involved in the above embodiment.
  • the first bare chip 1400 may include: a determination unit 1401 and a first decoding unit 1402 .
  • the determining unit 1401 may be used for the first die 1400 to perform the above step 701 and/or other processes of the technology described herein.
  • the first decoding unit 1402 may be used to support the first die 1400 to execute the above steps 702 and 703 , etc., and/or other processes of the technology described herein.
  • Figure 15 shows a possible composition diagram of the second bare chip 1500 involved in the above embodiment.
  • the second bare chip 1500 may include: a receiving unit 1501, a second decoding unit 1502 and a transmission unit 1503.
  • the receiving unit 1501 may be used for the second bare chip 1500 to perform the above step 1001 and/or other processes of the technology described herein.
  • the second decoding unit 1502 may be used to support the second die 1500 to perform the above step 1002 and/or other processes of the technology described herein.
  • the transmission unit 1503 may be used to support the second die 1500 to perform the above step 1003 and/or other processes of the technology described herein.
  • the first die 1400 and the second die 1500 provided in this embodiment are used to execute the above decoding method, and thus can achieve the same effect as the above implementation method.
  • the electronic device may include a processing module, a storage module and a communication module.
  • the processing module can be used to control and manage the actions of the electronic device, for example, it can be used to support the electronic device to execute the steps performed by the above-mentioned determination unit 1401 and the first decoding unit 1402. It can also be used to support the electronic device to execute the steps performed by the above-mentioned receiving unit 1501 and the second decoding unit 1502.
  • the storage module can be used to support the electronic device to store program codes and data, etc.
  • the communication module can be used to support the communication between the electronic device and other devices, such as communication with a wireless access device.
  • the processing module can be a processor or a controller. It can implement or execute various exemplary logic boxes, modules and circuits described in conjunction with the disclosure of this application.
  • the processor can also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of digital signal processing (DSP) and a microprocessor, etc.
  • the storage module can be a memory.
  • the communication module can specifically be a device that interacts with other electronic devices, such as a radio frequency circuit, a Bluetooth chip, a Wi-Fi chip, etc.
  • the electronic device involved in this embodiment may be a chip system having the structure shown in FIG. 6 .
  • the embodiment of the present application also provides an electronic device, including one or more processors and one or more memories.
  • the one or more memories are coupled to the one or more processors, and the one or more memories are used to store computer program codes, and the computer program codes include computer instructions.
  • the electronic device executes the above-mentioned related method steps to implement the decoding method in the above-mentioned embodiment.
  • An embodiment of the present application further provides a computer storage medium, in which computer instructions are stored.
  • the computer instructions When the computer instructions are executed on an electronic device, the electronic device executes the above-mentioned related method steps to implement the decoding method in the above-mentioned embodiment.
  • the embodiments of the present application further provide a computer program product.
  • the computer program product When the computer program product is run on a computer, the computer is caused to execute the above-mentioned related steps to implement the decoding method executed by the electronic device in the above-mentioned embodiment.
  • an embodiment of the present application also provides a device, which can specifically be a chip, component or module, and the device may include a connected processor and memory; wherein the memory is used to store computer-executable instructions, and when the device is running, the processor can execute the computer-executable instructions stored in the memory so that the chip executes the decoding method executed by the electronic device in the above-mentioned method embodiments.
  • the electronic device, computer storage medium, computer program product or chip provided in this embodiment is used to execute the corresponding method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding method provided above and will not be repeated here.
  • the disclosed devices and methods can be implemented in other ways.
  • the device embodiments described above are only schematic.
  • the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed.
  • Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple different places. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.
  • the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium.
  • the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions to enable a device (which can be a single-chip microcomputer, chip, etc.) or a processor (processor) to execute all or part of the steps of the method described in each embodiment of the present application.
  • the aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

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Abstract

本申请实施例提供一种译码方法、第一裸片和第二裸片，涉及芯片技术领域，减少了第一裸片处的配置信息。具体方案为：第一裸片根据第一地址空间信息和第一访问请求携带的第一地址信息确定第一访问请求是否用于访问第一裸片（701）；若第一裸片确定第一访问请求不用于访问第一裸片，第一裸片根据第一地址信息译码得到第二裸片的裸片标识，并向第二裸片发送第二访问请求，第二访问请求包括第一地址信息和第二裸片的裸片标识，第二访问请求用于第二裸片进行译码得到第一访问请求访问第二裸片的功能模块的模块标识（702）。本申请实施例用于多个功能模块互相访问的过程。

Description

一种译码方法、第一裸片和第二裸片
本申请要求于2023年1月31日提交国家知识产权局、申请号为202310116104.8、申请名称为“一种译码方法、第一裸片和第二裸片”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及芯片技术领域，尤其涉及一种译码方法、第一裸片和第二裸片。
背景技术
对于应用芯粒(chiplet)技术的芯片而言，芯粒中包括各种功能模块，如处理器核(core)、加速器和双倍速率同步动态随机存储器(double data rate synchronous dynamic random-access memory，DDR SDRAM)等。各种功能模块通过总线相连，其中，总线可以为环形(ring)、网状(mesh)交叉开关矩阵或纵横式交换矩阵(crossbar)等结构。
功能模块之间互访通过“请求-响应”握手的方式进行，功能模块的请求在进入总线之前经过译码结点。译码结点处利用地址和目的模块之间的映射关系，对请求中的地址进行翻译，提供对应的目的模块的地址信息，为总线路由提供依据。
随着chiplet技术的兴起，多种功能不同的裸片(die)组合成一颗芯片。die间结构上的巨大差异性，以及对复杂拓扑和灵活扩展的强烈需求，使得芯片中划分的地址段越来越多，即配置信息越来越多，而译码的查表过程也随着配置信息的增多而日趋复杂，对译码的设计提出了更大的需求。
发明内容
本申请实施例提供一种译码方法、第一裸片和第二裸片，通过分级译码的方式，在第一裸片处只配置第一裸片的模块的地址空间信息和其他裸片的地址空间信息，减少了第一裸片的配置信息，且降低了译码的复杂度。
为达到上述目的，本申请实施例采用如下技术方案。
第一方面，本申请实施例提供一种译码方法，译码方法应用于第一裸片，第一裸片包括多个功能模块，第一裸片配置有第一地址空间信息，第一地址空间信息包括第一裸片中每个功能模块的地址空间信息和除第一裸片外的其他裸片的地址空间信息，方法包括：第一裸片根据第一地址空间信息和第一访问请求携带的第一地址信息确定第一访问请求是否用于访问第一裸片；若第一裸片确定第一访问请求不用于访问第一裸片，第一裸片根据第一地址信息译码得到第二裸片的裸片标识，并向第二裸片发送第二访问请求，第二访问请求包括第一地址信息和第二裸片的裸片标识，第二访问请求用于第二裸片进行译码得到第一访问请求访问第二裸片的功能模块的模块标识。
由此，第一裸片中只配置了第一裸片中每个功能模块的地址空间信息和其他裸片的地址空间信息，而没有配置其他裸片中每个功能模块的地址空间信息，由此可以减少第一裸片的配置信息，减少关于译码结点的电路面积。另外，第一裸片采用分级译码的方式，第一访问请求在上总线之前，会先确定第一访问请求是否用于访问第一裸片。若第一访问请求不用于访问第一裸片，第一裸片会根据第一访问请求携带的第一地址信息得到第二裸片的裸片标识，在第二裸片处译码得到第一访问请求所访问的功能模块的模块标识，相较于现有技术中第一裸片根据第一地址信息得到第一访问请求所访问的功能模块的完整的标识，分级译码降低了译码的复杂度，有助于译码的时序收敛。另外，各裸片在设计时，只关注与第一裸片连接的裸片的架构即可，无需关注连接的裸片的内部的拓扑结构，简化了多裸片互联的设计需求，实现了任意裸片互联结构下译码的灵活扩展。且对于连接的不同的裸片，无需设计不同的译码原则，可以保障裸片共用的可行性。
在一种可能的设计中，该方法还包括：若第一裸片确定第一访问请求用于访问第一裸片，第一裸片根据第一地址信息译码得到第一访问请求访问第一裸片的功能模块的模块标识。
这种设计中，由于第一裸片中配置了各个功能模块的地址空间信息，若第一访问请求用于访问第一裸片，则第一裸片处译码得到第一地址信息对应的完整的芯片标识、裸片标识和模块标识，以完成第一裸片中各功能模块的互访。
在一种可能的设计中，第一裸片中每个功能模块的地址空间信息包括第一裸片中每个功能模块的基地址和第一裸片中每个功能模块的地址空间大小，其他裸片的地址空间信息包括其他裸片的基地址和其他裸片的地址空间大小。
这种设计中，功能模块的地址空间信息可以理解为一段地址范围，其他裸片的地址空间信息也可以理解为一段地址范围。第一裸片中只需为其他裸片划分地址空间，而无需为其他裸片内部的功能模块划分地址空间。由此，减少了第一裸片的配置信息，预留的窗口用于跨裸片互联即可，无需关注连接的裸片的内部的拓扑结构，简化了多裸片互联的设计需求，实现了任意裸片互联结构下译码的灵活扩展。
在一种可能的设计中，第一地址信息用于译码得到第一访问请求所访问的功能模块对应的芯片标识、裸片标识和模块标识。
这种设计中，根据第一地址信息译码得到功能模块对应的芯片标识、裸片标识和模块标识的过程实质上为查表过程。其中，第一地址信息对应于第一地址空间信息中的一个地址，可以确定该地址对应的功能模块，从而确定功能模块对应的芯片标识、裸片标识和模块标识。
在一种可能的设计中，第一裸片根据第一地址空间信息和第一访问请求携带的第一地址信息确定第一访问请求是否用于访问第一裸片包括：第一裸片确定第一地址信息在其他裸片的地址空间信息的地址范围内时，第一裸片确定第一访问请求不用于访问第一裸片；第一裸片确定第一地址信息在第一裸片中的功能模块的地址空间信息的地址范围内时，第一裸片确定第一访问请求用于访问第一裸片。
这种设计中，在第一次译码之前，第一裸片会先进行地址匹配，通过确定第一地址信息对应的为其他裸片的地址范围还是功能模块的地址范围，从而确定第一访问请求是否用于访问第一裸片。对于访问第一裸片的第一访问请求，第一译码结点译码得到完整的功能模块的标识。对于不是访问第一裸片的第一访问请求，第一译码结点译码只得到芯片标识和裸片标识。由此，降低了译码的复杂度，有助于译码的时序收敛。
第二方面，本申请实施例提供一种译码方法，译码方法应用于第二裸片，该方法包括：第二裸片接收第一裸片发送的第二访问请求，第二访问请求包括第一地址信息和第一裸片译码得到的裸片标识；第二裸片确定裸片标识为第二裸片的裸片标识时，第二裸片根据第一地址信息译码得到第二访问请求访问的第二裸片的功能模块的模块标识。
这种设计中，第二裸片的跨裸片接口处进行第二次译码之前，先确定第二访问请求中第一裸片译码得到的裸片标识是否为第二裸片标识，若裸片标识为第二裸片的裸片标识，第二裸片的跨裸片接口处会进行第二次译码。由此，第二裸片处的译码结点只需配置第二裸片的地址空间信息和其他裸片的地址空间信息，可以极大地减少各译码结点的配置信息，减少了译码所需的电路面积。同时分级译码也降低了译码的复杂度，有助于译码的时序收敛。
在一种可能的设计中，该方法还包括：第二裸片确定裸片标识不为第二裸片的裸片标识时，第二裸片将第二访问请求传输至第三裸片。
这种设计中，对于不是访问第二裸片的访问请求，第二裸片处将第二访问请求透传至第三裸片，而不进行译码。从而可以减少译码的次数，提供访问请求传输的效率。
在一种可能的设计中，第二裸片包括多个功能模块，第二裸片配置有第二地址空间信息，第二地址空间信息包括第二裸片中每个功能模块的地址空间信息和除第二裸片外的其他裸片的地址空间信息。
这种设计中，芯片系统中的第一裸片和第二裸片均只配置本裸片的功能模块的地址空间信息和其他裸片的地址空间信息，由此可以减少第一裸片和第二裸片的配置信息，减少关于译码结点的电路面积。
在一种可能的设计中，第二裸片中每个功能模块的地址空间信息包括第二裸片中每个功能模块的基地址和第二裸片中每个功能模块的地址空间大小，其他裸片的地址空间信息包括其他裸片的基地址和其他裸片的地址空间大小。
第三方面，本申请实施例提供一种第一裸片，第一裸片包括多个功能模块，第一裸片配置有第一地址空间信息，第一地址空间信息包括第一裸片中每个功能模块的地址空间信息和除第一裸片外的其他裸片的地址空间信息，第一裸片还包括：确定单元，用于根据第一地址空间信息和第一访问请求携带的第一地址信息确定第一访问请求是否用于访问第一裸片；第一译码单元，用于若第一裸片确定第一访问请求不用于访问第一裸片，根据第一地址信息译码得到第二裸片的裸片标识，并向第二裸片发送第二访问请求，第二访问请求包括第一地址信息和第二裸片的裸片标识，第二访问请求用于第二裸片进行译码得到第一访问请求访问第二裸片的功能模块的模块标识。
第三方面的有益效果可参见第一方面的说明。
在一种可能的设计中，第一译码单元还用于，若第一裸片确定第一访问请求用于访问第一裸片，第一裸片根据第一地址信息译码得到第一访问请求访问第一裸片的功能模块的模块标识。
在一种可能的设计中，第一裸片中每个功能模块的地址空间信息包括第一裸片中每个功能模块的基地址和第一裸片中每个功能模块的地址空间大小，其他裸片的地址空间信息包括其他裸片的基地址和其他裸片的地址空间大小。
在一种可能的设计中，第一地址信息用于译码得到第一访问请求所访问的功能模块对应的芯片标识、裸片标识和模块标识。
在一种可能的设计中，确定单元还用于，第一裸片确定第一地址信息在其他裸片的地址空间信息的地址范围内时，确定第一访问请求不用于访问第一裸片；第一裸片确定第一地址信息在第一裸片中的功能模块的地址空间信息的地址范围内时，确定第一访问请求用于访问第一裸片。
第四方面，本申请实施例提供一种第二裸片，第二裸片包括：接收单元，用于接收第一裸片发送的第二访问请求，第二访问请求包括第一地址信息和第一裸片译码得到的裸片标识；第二译码单元，用于第二裸片确定裸片标识为第二裸片的裸片标识时，根据第一地址信息译码得到第二访问请求访问的第二裸片的功能模块的模块标识。
第四方面的有益效果可参见第二方面的说明。
在一种可能的设计中，第二裸片还包括：传输单元，用于第二裸片确定裸片标识不为第二裸片的裸片标识时，将第二访问请求传输至第三裸片。
在一种可能的设计中，第二裸片包括多个功能模块，第二裸片配置有第二地址空间信息，第二地址空间信息包括第二裸片中每个功能模块的地址空间信息和除第二裸片外的其他裸片的地址空间信息。
在一种可能的设计中，第二裸片中每个功能模块的地址空间信息包括第二裸片中每个功能模块的基地址和第二裸片中每个功能模块的地址空间大小，其他裸片的地址空间信息包括其他裸片的基地址和其他裸片的地址空间大小。
第五方面，本申请实施例提供了一种计算机可读存储介质，包括计算机指令，当计算机指令在电子设备上运行时，使得电子设备执行上述任一方面及任一项可能的实现方式中的译码方法。
第六方面，本申请实施例提供了一种计算机程序产品，当计算机程序产品在计算机或处理器上运行时，使得计算机或处理器执行上述任一方面及任一项可能的实现方式中的译码方法。
可以理解的是，上述提供的任一种第一裸片、第二裸片、计算机可读存储介质或计算机程序产品等均可以应用于上文所提供的对应的方法，因此，其所能达到的有益效果可参考对应的方法中的有益效果，此处不再赘述。
本申请的这些方面或其他方面在以下的描述中会更加简明易懂。
附图说明
图1为本申请实施例提供的一种芯片系统的结构示意图；
图2为本申请实施例提供的一种不同总线的拓扑结构图；
图3为本申请实施例提供的一种基于环形总线互访的芯片系统的结构图；
图4为本申请实施例提供的一种执行设备的结构示意图；
图5为本申请实施例提供的一种第一译码结点的地址空间配置示意图；
图6为本申请实施例提供的另一种芯片系统的结构示意图；
图7为本申请实施例提供的一种译码方法的流程图；
图8为本申请实施例提供的另一种译码方法的流程图；
图9为本申请实施例提供的一种第一裸片访问请求处理的流程图；
图10为本申请实施例提供的另一种译码方法的流程图；
图11为本申请实施例提供的一种第二裸片的访问请求处理的流程图；
图12为本申请实施例提供的另一种第二裸片的访问请求处理的流程图；
图13为本申请实施例提供的一种第一译码结点和第二译码结点的地址空间配置示意图；
图14为本申请实施例提供的一种第一裸片的一种可能的组成示意图；
图15为本申请实施例提供的一种第二裸片的一种可能的组成示意图。
具体实施方式
为了便于理解，示例的给出了部分与本申请实施例相关概念的说明以供参考。如下所示：
中介层(interposer)，一种硅中介层，放置于中介层上的逻辑芯片通过硅通孔(through silicon via，TSV)微电极连接。
网状总线(mesh bus)，网状总线中所有的功能模块都互相连接，并且每一个功能模块至少连接两个其他功能模块，所有的功能模块之间形成一个整体的芯片系统。
环形总线(ring bus)，环形总线由四条独立的“环”组成，分别是数据环、请求环、响应环和侦听环，每条“环”的每个节点在每个时钟周期内都能接收32字节的数据，此种划分模式让“环”的访问总能自动选择到最短的路径以缩短延迟。
交叉开关矩阵(crossbar)，交叉开关矩阵总线中功能模块到交换结构的物理连接简化为点对点连接，可以保证数据传输的稳定性，另外，交叉开关矩阵总线连接的多个功能模块可以同时传输数据，可以提高数据传输的效率。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。其中，在本申请实施例的描述中，除非另有说明，“/”表示或的意思，例如，A/B可以表示A或B；本文中的“和/或”仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，在本申请实施例的描述中，“多个”是指两个或多于两个。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
随着工艺的演进，业界为了能够维持摩尔定律，其中一个解决方案为采用chiplet技术。其中，chiplet技术为利用TSV封装技术在一个芯片(chip)内封装多个不同的晶圆或裸片(die)，通过不同的die的组合完成一个复杂芯片的功能的技术。采用TSV封装技术的芯片结构称为chiplet架构，如图1所示，图1为本申请实施例提供的一种芯片系统的结构示意图。其中，芯片系统可以包括DIE0和DIE1，DIE0可以是逻辑(logic)裸片，DIE1可以是高带宽存储器(high bandwidth memory，HBM)。DIE0和DIE1之间通过中介层(interposer)和基板(substrate)相耦合，由此组成一个芯片系统。
对于芯片系统而言，芯片系统内部包括各种功能模块，例如core、加速器和DDR SDRAM等。各种功能模块通过总线相连，如图2所示，图2为本申请实施例提供的一种不同总线的拓扑结构图。其中，图2中示出了网状总线、环形总线和交叉开关矩阵总线的拓扑结构图。对于网状总线，该总线共连接16个功能模块，分别是功能模块0-15，其拓扑结构为4x4网状结构。对于环形总线，该总线共连接4个功能模块，分别是功能模块0-3。环形总线中所有的功能模块均挂接在环形总线上，各个功能模块之间交互方便灵活，无需在处理器中转。对于交叉开关矩阵总线，也称纵横式交换矩阵总线，该总线共连接8个功能模块，分别是功能模块0-7。
其中，功能模块之间通过“请求-响应”握手的方式进行互访。功能模块之间为了实现灵活的拓扑结构，需要获得整个芯片系统的地址空间信息，而无法获得总线上的各个功能模块。如图3所示，图3为本申请实施例提供的一种基于环形总线互访的芯片系统的结构图。该芯片系统中包括DIE1和DIE0，其中，DIE0中包括功能模块A和功能模块B，DIE1中包括功能模块C和功能模块D，DIE0和DIE1之间通过跨裸片接口耦合。以功能模块D请求访问功能模块A为例，首先，功能模块D发出访问请求，并携带功能模块A的地址信息，该访问请求在进入总线之前经过译码结点，译码结点通过地址信息确定出该地址信息对应功能模块A，并在该请求中附上功能模块A的目的结点标识(target identity document，tgtid)。然后该访问请求进入总线，经过DIE0和DIE1之间的跨裸片接口进入DIE0的总线，到达功能模块A。功能模块A接收到访问请求后，回复响应或数据，由此功能模块D访问功能模块A的过程结束。
需要说明的是，为了降低路由难度，总线通过tgtid确定报文的路由路径。其中，tgtid包括芯片标识(socket identity document，sktid)、裸片标识(die identity document，dieid)和模块标识(port identity document，portid)。sktid为目的结点所在的芯片的芯片标识，dieid为目的结点所在的裸片的裸片标识，portid为目的结点所在的功能模块的模块标识。在功能模块D请求访问功能模块A的过程中，DIE1的总线识别到sktid是本芯片，但dieid不是本裸片，则将请求发送至跨裸片接口，以到达目的裸片，DIE0的总线再利用portid将请求发送至功能模块A。
简而言之，译码就是利用地址信息和功能模块之间的映射关系，对访问请求中的地址进行翻译， 得到对应的tgtid，为总线路由提供依据的过程。该映射关系如表1所示，对于每个窗口配置基地址、地址空间大小(size)和tgtid，其中，基地址和地址空间大小可以确定一段地址范围，对落到该地址范围的地址，其对应的tgtid即为该窗口配置的tgtid。在片上系统(system on chip，SOC)中，对每段地址都配置一个地址窗口。对访问请求的译码过程，本质上为一个查表的过程。
表1地址和模块的映射关系
当前，一般基于打平的原则实现片内译码，即每个译码结点均可以获得整个芯片系统的拓扑结构。但复杂的拓扑结构会导致译码结点的配置信息增加，而这些配置信息均需要存储和计算，由此增加电路的面积开销。而且，由于译码结点有限的资源规划，打平原则会反过来限制扩展的空间，降低复杂拓扑的灵活性。例如每个译码结点设计时有32个窗口，每个裸片需要8个窗口，则该芯片系统最多只能支持4个裸片的互联。另外，不同裸片开发时，需要考虑可能的对接裸片的结构，针对性地设计译码原则，导致不同裸片的开发无法解耦，互相之间会有制约，限制裸片在不同项目共用的可能性。
由此，本申请实施例提供一种译码方法，该译码方法应用于芯片系统中的第一裸片。下面先对芯片系统进行介绍。
芯片系统(chiplet系统)可以应用于不同的设备中，如应用于图4所示的执行设备40，图4为本申请实施例提供的一种执行设备的结构示意图。该执行设备40可以是终端，如服务器41、手机终端42、平板电脑43、笔记本电脑44、增强现实技术(augmented reality，AR)设备(图4中未示出)、虚拟现实技术(virtual reality，VR)设备(图4中未示出)、车载终端(图4中未示出)等。
其中，该芯片系统中包括多个具有特定功能、可相互进行模块化组装的裸片(die)，如裸片可实现数据存储、计算、信号处理、数据流管理等功能。基于丰富的知识产权核心(intellectual property core，IP)储备，chiplet系统提出了IP芯片化(IP as a chiplet，IaaC)的理念，旨在以裸片实现特殊功能IP的“即插即用”。例如，对于一些核心处理器IP，裸片可为图形处理器(graphics processing unit，GPU)IP、神经网络处理器(neural-network unit，NPU)IP、视频处理器(video processing unit，VPU)IP、数字信号处理器(digital signal processing，DSP)IP、图像信号处理器(image signal processor，ISP)IP和显示处理器IP等。此外，裸片还可以是数模混合IP和射频IP等。
本申请中的chiplet系统，还可以称为芯片系统或芯粒系统。即裸片还可以称为小芯片或芯粒。
示例性的，该chiplet系统可以应用在系统级芯片(system-on-a-chip，SoC)，在SoC上集成有多种功能的裸片。例如芯片系统包括本申请实施例提供的第一裸片，其中，第一裸片包括多个功能模块，例如功能模块A和功能模块B等，功能模块可以是core、加速器和DDR SDRAM等。
其中，第一裸片配置有第一地址空间信息，第一地址空间信息包括第一裸片中每个功能模块的地址空间信息和除所述第一裸片外的其他裸片的地址空间信息。
示例性的，第一裸片可以包括第一译码结点，第一译码结点处配置有第一地址空间信息。其中，第一译码结点可以通过硬件实现，例如，第一译码结点可以是一组多输入多输出的逻辑电路。在一个示例中，如图5所示，图5为本申请实施例提供的一种第一译码结点的地址空间配置示意图。其中，每一段地址空间都对应于一个译码窗口。共用的地址空间为存储因芯片系统的配置要求而各裸片共用的功能模块的地址空间，功能模块A的地址空间为分配给功能模块A的地址空间，功能模块B的地址空间为分配给功能模块B的地址空间，其他裸片的地址空间为分配给其他裸片的地址空间，其他裸片可以是第二裸片和第三裸片等。
在配置第一裸片的第一译码结点的地址空间时，首先，对于芯片系统中每个裸片配置一段地址空间。然后对于其中第一裸片对应的地址空间，进一步配置各功能模块的地址空间。由此，相较于现有技术中，对每个译码结点配置芯片系统中每个功能模块的地址空间，本申请实施例中第一译码结点的地址空间的配置方式，只配置第一裸片的各个功能模块的地址空间和其他裸片的地址空间，而不配置其他裸片中的功能模块的地址空间，可以减少译码结点的配置信息，减少译码结点所占用 的电路面积。
本申请实施例提供一种译码方法，第一裸片采用分级译码的方式，第一访问请求在上总线之前，会先确定第一访问请求是否用于访问第一裸片。若第一访问请求不用于访问第一裸片，第一裸片会根据第一访问请求携带的第一地址信息得到第二裸片的裸片标识，在第二裸片处译码得到第一访问请求所访问的功能模块的模块标识，相较于现有技术中第一裸片根据第一地址信息得到第一访问请求所访问的功能模块的完整的标识，分级译码降低了译码的复杂度，有助于译码的时序收敛。另外，各裸片在设计时，只关注与第一裸片连接的裸片的架构即可，无需关注连接的裸片的内部的拓扑结构，简化了多裸片互联的设计需求，实现了任意裸片互联结构下译码的灵活扩展。且对于连接的不同的裸片，无需设计不同的译码原则，可以保障裸片共用的可行性。
下面先对本申请实施例提供的译码方法应用的具体的芯片系统进行介绍。
相较于现有技术中，本申请实施例提供的芯片系统在裸片的跨裸片接口处新增一级译码结点。如图6所示，图6为本申请实施例提供的另一种芯片系统的结构示意图。图6中示出了两个裸片，分别是DIE0和DIE1，其中，DIE0中包括功能模块A和功能模块B，DIE1中包括功能模块C和功能模块D，DIE0和DIE1之间通过跨裸片接口耦合。另外，DIE1中还包括第一译码结点和第四译码结点，其中第一译码结点设置于功能模块D和总线之间，第四译码结点设置于跨裸片接口和总线之间。DIE0中还包括第二译码结点和第三译码结点，其中第二译码结点设置于跨裸片接口和总线之间，第三译码结点设置于功能模块A和总线之间。
应用于图6中所示的芯片系统，本申请实施例提供一种译码方法，如图7所示，图7为本申请实施例提供的一种译码方法的流程图。该方法包括如下流程。
步骤701、第一裸片根据第一地址空间信息和第一访问请求携带的第一地址信息确定第一访问请求是否用于访问第一裸片。
示例性的，由于在配置第一裸片的第一译码结点的地址空间时，只配置了第一裸片的各个功能模块的地址空间信息和其他裸片的地址空间信息。所以在第一访问请求进入总线之前，在第一译码结点处，会判断第一访问请求是否用于访问第一裸片。若第一访问请求用于访问第一裸片，即该第一访问请求为第一裸片中的功能模块访问第一裸片中的功能模块，此时第一译码结点处应当基于第一访问请求携带的第一地址信息确定出第一访问请求所访问的功能模块的地址空间信息，从而完成第一裸片中功能模块之间的访问。若第一访问请求不用于访问第一裸片，即该第一访问请求为第一裸片中的功能模块访问其他裸片中的功能模块，此时第一译码结点处应当基于第一访问请求携带的第一地址信息确定出第一访问请求所访问的其他裸片的地址空间信息，从而完成将第一访问请求发送至其他裸片的过程。
其中，第一裸片中每个功能模块的地址空间信息包括第一裸片中每个功能模块的基地址和第一裸片中每个功能模块的地址空间大小，其他裸片的地址空间信息包括其他裸片的基地址和其他裸片的地址空间大小。
示例性的，功能模块的地址空间信息可以理解为一段地址范围，即该段地址空间为以基地址为起始，大小为地址空间大小的一段地址范围。同样的，其他裸片的地址空间信息也可以理解为一段地址范围。
需要注意的是，每个功能模块的地址空间大小和其他裸片的地址空间大小无关，可根据每个功能模块的所需的地址空间大小进行划分。
步骤702、若第一裸片确定第一访问请求不用于访问第一裸片，第一裸片根据第一地址信息译码得到第二裸片的裸片标识，并向第二裸片发送第二访问请求，第二访问请求包括第一地址信息和第二裸片的裸片标识，第二访问请求用于第二裸片进行译码得到第一访问请求访问第二裸片的功能模块的模块标识。
其中，第一地址信息用于译码得到第一访问请求所访问的功能模块对应的芯片标识、裸片标识和模块标识。
示例性的，根据第一地址信息译码得到功能模块对应的芯片标识、裸片标识和模块标识的过程实质上为查表过程。其中，第一地址信息对应于第一地址空间信息中的一个地址，可以确定该地址对应的功能模块，从而确定功能模块对应的芯片标识、裸片标识和模块标识。
示例性的，若第一地址信息对应于其他裸片的地址空间中的一个地址，则第一裸片可以确定第一访问请求不用于访问第一裸片。由于第一译码结点处只配置了其他裸片的地址空间信息，而未配 置其他裸片中的各个功能模块的地址空间信息，第一译码结点处进行译码只能得到第二裸片的裸片标识。第一裸片通过总线将第二访问请求发送至第二裸片与第一裸片的跨裸片接口处，此时的第二访问请求携带第一地址信息和第二裸片的裸片标识。以便第二裸片处的第二译码结点对第一地址信息再次进行译码，以得到第一访问请求访问第二裸片的功能模块的模块标识。
由此，通过本申请实施例提供的分级译码的方式，基于层次化译码的原则，各译码结点只需配置各裸片的地址空间信息，以及本裸片中的各个功能模块的地址空间信息，可以极大地减少各译码结点的配置信息，减少了译码所需的电路面积。同时分级译码也降低了译码的复杂度，有助于译码的时序收敛。另外，各裸片在设计时，只关注与第一裸片连接的裸片的架构即可，无需关注连接的裸片的内部的拓扑结构，简化了多裸片互联的设计需求，实现了任意裸片互联结构下译码的灵活扩展。且对于连接的不同的裸片，无需设计不同的译码原则，可以保障裸片共用的可行性。
可选的，如图8所示，图8为本申请实施例提供的另一种译码方法的流程图。该方法还可以包括步骤703。
步骤703、若第一裸片确定第一访问请求用于访问第一裸片，第一裸片根据第一地址信息译码得到第一访问请求访问第一裸片的功能模块的模块标识。
示例性的，若第一地址信息对应于第一裸片中功能模块的地址空间中的一个地址，则第一裸片可以确定第一访问请求用于访问第一裸片。由于第一译码结点处配置了第一裸片中每个功能模块的地址空间信息，第一译码结点可以基于第一地址信息译码得到第一访问请求访问第一裸片的功能模块的芯片标识、裸片标识和模块标识。此时，功能模块的芯片标识即第一裸片所在的芯片的芯片标识，功能模块的裸片标识即第一裸片的裸片标识。
结合步骤701至步骤703，我们可以理解为第一译码结点处的流程如图9所示，图9为本申请实施例提供的一种第一裸片访问请求处理的流程图。该流程可以包括：第一裸片进行第一地址信息匹配，若第一地址信息对应于第一裸片中功能模块的地址空间，则第一译码结点进行译码，得到第一访问请求访问的功能模块的完整的tgtid，即得到sktid、dieid和portid。若第一地址信息对应于其他裸片的地址空间，则第一译码结点进行译码，得到第一访问请求访问的功能模块的芯片标识和裸片标识，即得到sktid和dieid。
另外，若第一裸片确定第一地址信息在第一裸片中的共用的地址空间的地址范围内，第一译码结点也可以译码得到第一访问请求访问的功能模块完整的tgtid，即得到sktid、dieid和portid。但是跨裸片接口处的译码结点应保证再次译码后的tgtid不变。
可选的，步骤701可以包括：第一裸片确定第一地址信息在其他裸片的地址空间信息的地址范围内时，第一裸片确定第一访问请求不用于访问第一裸片。
在另一个示例中，对于其他裸片，例如DIE1，第一地址空间信息中包括DIE1的基地址Addr_DIE1，假设DIE1的地址空间大小为4G。此时DIE1对应的地址空间为从Addr_DIE1开始，大小为4G的地址空间。若第一地址信息在DIE1的地址空间信息的地址范围内，则可以认为第一访问请求用于访问DIE1，则将第一访问请求发送至DIE1。
可选的，步骤701也可以包括：第一裸片确定第一地址信息在第一裸片中的功能模块的地址空间信息的地址范围内时，第一裸片确定第一访问请求用于访问第一裸片。
在一个示例中，对于第一裸片中的功能模块A，第一地址空间信息中包括功能模块A的基地址Addr_A，假设功能模块A的地址空间大小为2G。此时功能模块A对应的地址空间为从Addr_A开始，大小为2G的地址空间。若第一地址信息在第一裸片中的功能模块A的地址空间信息的地址范围内，则可以认为第一访问请求用于访问功能模块A。
应用于图6中所示的芯片系统，本申请实施例提供另一种译码方法，该译码方法应用于第二裸片，如图10所示，图10为本申请实施例提供的另一种译码方法的流程图。该译码方法包括如下流程。
步骤1001、第二裸片接收第一裸片发送的第二访问请求，第二访问请求包括第一地址信息和第一裸片译码得到的裸片标识。
示例性的，第一裸片和第二裸片通过跨裸片接口耦合，第二裸片通过跨裸片接口接收第一裸片发送的第二访问请求。其中，第二访问请求中携带了第一地址信息和第一裸片译码得到的裸片标识。
步骤1002、第二裸片确定裸片标识为第二裸片的裸片标识时，第二裸片根据第一地址信息译码得到第二访问请求访问的第二裸片的功能模块的模块标识。
示例性的，第二裸片和第一裸片的跨裸片接口处设置有第二译码结点，第二译码结点处配置有第二裸片中每个功能模块的地址空间信息。若裸片标识为第二裸片的裸片标识时，即第二访问请求用于访问第二裸片中的功能模块。第二译码结点根据第一地址信息译码得到第二访问请求访问的第二裸片的功能模块的模块标识。
由此，如图11所示，图11为本申请实施例提供的一种第二裸片的访问请求处理的流程图。若第二裸片的跨裸片接口处接收到第二访问请求，确定是否为本裸片的访问请求，若是本裸片的访问请求，第二译码结点进行译码，得到第二访问请求访问的功能模块的模块标识，将第二访问请求汇聚到第二裸片的总线上以发送至第二访问请求访问的功能模块。若不是本裸片的访问请求，将第二访问请求汇聚到总线上发送至第二裸片与其他裸片的跨裸片接口。
步骤1003、第二裸片确定裸片标识不为第二裸片的裸片标识时，第二裸片将第二访问请求传输至第三裸片。
在一种示例中，假设芯片系统中包括第一裸片、第二裸片和第三裸片，其中，第一裸片和第二裸片通过跨裸片接口耦合，第二裸片和第三裸片通过跨裸片接口耦合。若第二裸片确定裸片标识不为第二裸片的裸片标识，以第一裸片中的功能模块访问第三裸片中的功能模块为例，第二裸片接收到第二访问请求，确定第二访问请求不是本裸片的访问请求，第二裸片的跨裸片接口处的第二译码结点不对第二访问请求携带的第一地址信息进行译码，即第二译码结点透传第二访问请求。第二访问请求汇聚到总线上发送至第二裸片与第三裸片的跨裸片接口，第三裸片确定裸片标识为第三裸片的裸片标识，第三裸片的跨裸片接口处的译码结点对第二访问请求携带的第一地址信息进行译码，得到第二访问请求访问的第三裸片的功能模块的模块标识。
由此，如图12所示，图12为本申请实施例提供的另一种第二裸片的访问请求处理流程图。其中，第二裸片的跨裸片接口处接收到第二访问请求，第二访问请求携带第二裸片的芯片标识和第二裸片的裸片标识，即第二访问请求携带sktid和dieid。第二裸片进行sktid和dieid匹配，若sktid和dieid为非本芯片本裸片，则将第二访问请求进行透传，即将第二访问请求通过总线传输至第二裸片和其他裸片的跨裸片接口处。其中，非本芯片本裸片包括非本芯片非本裸片的情况、本芯片非本裸片的情况。若sktid和dieid为本芯片本裸片，第二译码结点基于第一地址信息进行地址匹配，译码得到第二访问请求访问的第二裸片的功能模块的模块标识。
可选的，第二裸片包括多个功能模块，第二裸片配置有第二地址空间信息，第二地址空间信息包括第二裸片中每个功能模块的地址空间信息和除第二裸片外的其他裸片的地址空间信息。第二裸片中每个功能模块的地址空间信息包括第二裸片中每个功能模块的基地址和第二裸片中每个功能模块的地址空间大小，其他裸片的地址空间信息包括其他裸片的基地址和其他裸片的地址空间大小。
示例性的，第二裸片可以包括第二译码结点，第二译码结点配置有第二地址空间信息。其中，第二译码结点也可以通过硬件实现，例如，第二译码结点可以是一组多输入多输出的逻辑电路。假设第一裸片包括第一译码结点，第二裸片包括第二译码结点。其中，第一译码结点或第二译码结点可以是功能模块和总线之间的译码结点，第一译码结点或第二译码结点也可以是总线和跨裸片接口之间的译码结点。在一个示例中，如图13所示，图13为本申请实施例提供的一种第一译码结点和第二译码结点的地址空间配置示意图。其中，每一段地址空间都对应于一个译码窗口。共用的地址空间为存储因芯片系统的配置要求而各裸片共用的功能模块的地址空间，即第一译码结点和第二译码结点均配置有共用的地址空间。第一译码结点处还配置有第一裸片的功能模块A的地址空间和第一裸片的功能模块B的地址空间等，以及第二裸片的地址空间。第二译码结点处还配置有第二裸片的功能模块C的地址空间和第二裸片的功能模块D的地址空间等，以及第一裸片的地址空间。
可以看出，第一译码结点和第二译码结点处均只配置本裸片的各个功能模块的地址空间和其他裸片的地址空间，而不配置其他裸片中的功能模块的地址空间，可以减少译码结点的配置信息，减少译码结点所占用的电路面积。
总的来说，应用于图6中所示的芯片系统，其中，第一裸片为DIE1，第二裸片为DIE0。以功能模块D请求访问功能模块A为例，功能模块D发出第一访问请求，并携带功能模块A的第一地址信息。DIE1会先判断该第一访问请求是否为访问DIE1中的功能模块的请求。由于该第一访问请求是访问DIE0中的功能模块A，所以第一译码结点处可以基于该第一地址信息译码得到DIE0的裸片标识，第一译码结点将第二访问请求通过DIE1中的总线发送至DIE0与DIE1的跨裸片接口处，此时第二访问请求携带功能模块A的第一地址信息和DIE0的裸片标识。DIE0确定第二访问请求携带的 裸片标识为DIE0的裸片标识，第二译码结点处根据第一地址信息进行译码，得到DIE0中的功能模块A的模块标识，由此，DIE0中通过DIE0中的总线将第二访问请求发送至功能模块A，功能模块A接收到第二访问请求后，回复响应或数据，由此完成功能模块D访问功能模块A的流程。
另外，若功能模块A请求访问功能模块D，第三译码结点和第一译码结点做相同的处理，第四译码结点和第二译码结点做相同的处理，在此不再赘述。
由此，本申请实施例提供的译码方法通过分级译码，减少了译码结点的配置信息，降低了译码的复杂度。另外，第一裸片和第二裸片等裸片在设计时，预留有限的窗口用于跨裸片互联即可，不需要关注与跨裸片接口互联的裸片内部的拓扑接口，简化了多裸片互联的设计需求，实现任意多裸片互联结构下译码的灵活扩展。且对于不同的互联的裸片，也无需设计不同的译码原则，保障裸片共用的可行性。
可以理解的是，为了实现上述功能，电子设备包含了执行各个功能相应的硬件和/或软件模块。结合本文中所公开的实施例描述的各示例的算法步骤，本申请能够以硬件或硬件和计算机软件的结合形式来实现。某个功能究竟以硬件还是计算机软件驱动硬件的方式来执行，取决于技术方案的特定应用和设计约束条件。本领域技术人员可以结合实施例对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
本实施例可以根据上述方法示例对电子设备进行功能模块的划分，例如，可以对应各个功能划分各个功能模块，也可以将两个或两个以上的功能集成在一个处理模块中。上述集成的模块可以采用硬件的形式实现。需要说明的是，本实施例中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。
在一个示例中，电子设备可以包括第一裸片和第二裸片。
在采用对应各个功能划分各个功能模块的情况下，图14示出了上述实施例中涉及的第一裸片1400的一种可能的组成示意图，如图14所示，该第一裸片1400可以包括：确定单元1401和第一译码单元1402。
其中，确定单元1401可以用于第一裸片1400执行上述步骤701等，和/或用于本文所描述的技术的其他过程。
第一译码单元1402可以用于支持第一裸片1400执行上述步骤702和步骤703等，和/或用于本文所描述的技术的其他过程。
在采用对应各个功能划分各个功能模块的情况下，图15示出了上述实施例中涉及的第二裸片1500的一种可能的组成示意图，如图15所示，该第二裸片1500可以包括：接收单元1501、第二译码单元1502和传输单元1503。
其中，接收单元1501可以用于第二裸片1500执行上述步骤1001等，和/或用于本文所描述的技术的其他过程。
第二译码单元1502可以用于支持第二裸片1500执行上述步骤1002等，和/或用于本文所描述的技术的其他过程。
传输单元1503可以用于支持第二裸片1500执行上述步骤1003等，和/或用于本文所描述的技术的其他过程。
需要说明的是，上述方法实施例涉及的各步骤的所有相关内容均可以援引到对应功能模块的功能描述，在此不再赘述。
本实施例提供的第一裸片1400和第二裸片1500，用于执行上述译码方法，因此可以达到与上述实现方法相同的效果。
在采用集成的单元的情况下，电子设备可以包括处理模块、存储模块和通信模块。其中，处理模块可以用于对电子设备的动作进行控制管理，例如，可以用于支持电子设备执行上述确定单元1401和第一译码单元1402执行的步骤。也可以用于支持电子设备执行上述接收单元1501和第二译码单元1502执行的步骤。存储模块可以用于支持电子设备存储程序代码和数据等。通信模块，可以用于支持电子设备与其他设备的通信，例如与无线接入设备的通信。
其中，处理模块可以是处理器或控制器。其可以实现或执行结合本申请公开内容所描述的各种示例性的逻辑方框，模块和电路。处理器也可以是实现计算功能的组合，例如包含一个或多个微处理器组合，数字信号处理(digital signal processing，DSP)和微处理器的组合等等。存储模块可以是存储器。通信模块具体可以为射频电路、蓝牙芯片、Wi-Fi芯片等与其他电子设备交互的设备。
在一个实施例中，当处理模块为处理器，存储模块为存储器时，本实施例所涉及的电子设备可以为具有图6所示结构的芯片系统。
本申请实施例还提供一种电子设备，包括一个或多个处理器以及一个或多个存储器。该一个或多个存储器与一个或多个处理器耦合，一个或多个存储器用于存储计算机程序代码，计算机程序代码包括计算机指令，当一个或多个处理器执行计算机指令时，使得电子设备执行上述相关方法步骤实现上述实施例中的译码方法。
本申请的实施例还提供一种计算机存储介质，该计算机存储介质中存储有计算机指令，当该计算机指令在电子设备上运行时，使得电子设备执行上述相关方法步骤实现上述实施例中的译码方法。
本申请的实施例还提供了一种计算机程序产品，当该计算机程序产品在计算机上运行时，使得计算机执行上述相关步骤，以实现上述实施例中电子设备执行的译码方法。
另外，本申请的实施例还提供一种装置，这个装置具体可以是芯片，组件或模块，该装置可包括相连的处理器和存储器；其中，存储器用于存储计算机执行指令，当装置运行时，处理器可执行存储器存储的计算机执行指令，以使芯片执行上述各方法实施例中电子设备执行的译码方法。
其中，本实施例提供的电子设备、计算机存储介质、计算机程序产品或芯片均用于执行上文所提供的对应的方法，因此，其所能达到的有益效果可参考上文所提供的对应的方法中的有益效果，此处不再赘述。
通过以上实施方式的描述，所属领域的技术人员可以了解到，为描述的方便和简洁，仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将装置的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个装置，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是一个物理单元或多个物理单元，即可以位于一个地方，或者也可以分布到多个不同地方。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个可读取存储介质中。基于这样的理解，本申请实施例的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该软件产品存储在一个存储介质中，包括若干指令用以使得一个设备(可以是单片机，芯片等)或处理器(processor)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(read only memory，ROM)、随机存取存储器(random access memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上内容，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种译码方法，其特征在于，所述译码方法应用于第一裸片，所述第一裸片包括多个功能模块，所述第一裸片配置有第一地址空间信息，所述第一地址空间信息包括所述第一裸片中每个功能模块的地址空间信息和除所述第一裸片外的其他裸片的地址空间信息，所述方法包括：
    所述第一裸片根据所述第一地址空间信息和第一访问请求携带的第一地址信息确定所述第一访问请求是否用于访问所述第一裸片；
    若所述第一裸片确定所述第一访问请求不用于访问所述第一裸片，所述第一裸片根据所述第一地址信息译码得到第二裸片的裸片标识，并向所述第二裸片发送第二访问请求，所述第二访问请求包括所述第一地址信息和所述第二裸片的裸片标识，所述第二访问请求用于所述第二裸片进行译码得到所述第一访问请求访问第二裸片的功能模块的模块标识。
  2. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    若所述第一裸片确定所述第一访问请求用于访问所述第一裸片，所述第一裸片根据所述第一地址信息译码得到所述第一访问请求访问所述第一裸片的功能模块的模块标识。
  3. 根据权利要求1或2所述的方法，其特征在于，所述第一裸片中每个功能模块的地址空间信息包括所述第一裸片中每个功能模块的基地址和所述第一裸片中每个功能模块的地址空间大小，所述其他裸片的地址空间信息包括所述其他裸片的基地址和所述其他裸片的地址空间大小。
  4. 根据权利要求1或2所述的方法，其特征在于，所述第一地址信息用于译码得到所述第一访问请求所访问的功能模块对应的芯片标识、裸片标识和模块标识。
  5. 根据权利要求1所述的方法，其特征在于，所述第一裸片根据所述第一地址空间信息和第一访问请求携带的第一地址信息确定所述第一访问请求是否用于访问所述第一裸片包括：
    所述第一裸片确定所述第一地址信息在所述其他裸片的地址空间信息的地址范围内时，所述第一裸片确定所述第一访问请求不用于访问所述第一裸片；
    所述第一裸片确定所述第一地址信息在所述第一裸片中的功能模块的地址空间信息的地址范围内时，所述第一裸片确定所述第一访问请求用于访问所述第一裸片。
  6. 一种译码方法，其特征在于，所述译码方法应用于第二裸片，所述方法包括：
    所述第二裸片接收第一裸片发送的第二访问请求，所述第二访问请求包括第一地址信息和所述第一裸片译码得到的裸片标识；
    所述第二裸片确定所述裸片标识为所述第二裸片的裸片标识时，所述第二裸片根据所述第一地址信息译码得到所述第二访问请求访问的所述第二裸片的功能模块的模块标识。
  7. 根据权利要求6所述的方法，其特征在于，所述方法还包括：
    所述第二裸片确定所述裸片标识不为所述第二裸片的裸片标识时，所述第二裸片将所述第二访问请求传输至第三裸片。
  8. 根据权利要求6或7所述的方法，其特征在于，所述第二裸片包括多个功能模块，所述第二裸片配置有第二地址空间信息，所述第二地址空间信息包括所述第二裸片中每个功能模块的地址空间信息和除所述第二裸片外的其他裸片的地址空间信息。
  9. 根据权利要求8所述的方法，其特征在于，所述第二裸片中每个功能模块的地址空间信息包括所述第二裸片中每个功能模块的基地址和所述第二裸片中每个功能模块的地址空间大小，所述其他裸片的地址空间信息包括所述其他裸片的基地址和所述其他裸片的地址空间大小。
  10. 一种第一裸片，其特征在于，所述第一裸片包括多个功能模块，所述第一裸片配置有第一地址空间信息，所述第一地址空间信息包括所述第一裸片中每个功能模块的地址空间信息和除所述第一裸片外的其他裸片的地址空间信息，所述第一裸片还包括：
    确定单元，用于根据所述第一地址空间信息和第一访问请求携带的第一地址信息确定所述第一访问请求是否用于访问所述第一裸片；
    第一译码单元，用于若所述第一裸片确定所述第一访问请求不用于访问所述第一裸片，根据所述第一地址信息译码得到第二裸片的裸片标识，并向所述第二裸片发送第二访问请求，所述第二访问请求包括所述第一地址信息和所述第二裸片的裸片标识，所述第二访问请求用于所述第二裸片进行译码得到所述第一访问请求访问第二裸片的功能模块的模块标识。
  11. 根据权利要求10所述的第一裸片，其特征在于，所述第一译码单元还用于，若所述第一裸片确定所述第一访问请求用于访问所述第一裸片，所述第一裸片根据所述第一地址信息译码得到所述 第一访问请求访问所述第一裸片的功能模块的模块标识。
  12. 根据权利要求10或11所述的第一裸片，其特征在于，所述第一裸片中每个功能模块的地址空间信息包括所述第一裸片中每个功能模块的基地址和所述第一裸片中每个功能模块的地址空间大小，所述其他裸片的地址空间信息包括所述其他裸片的基地址和所述其他裸片的地址空间大小。
  13. 根据权利要求10或11所述的第一裸片，其特征在于，所述第一地址信息用于译码得到所述第一访问请求所访问的功能模块对应的芯片标识、裸片标识和模块标识。
  14. 根据权利要求10所述的第一裸片，其特征在于，所述确定单元还用于，所述第一裸片确定所述第一地址信息在所述其他裸片的地址空间信息的地址范围内时，确定所述第一访问请求不用于访问所述第一裸片；
    所述第一裸片确定所述第一地址信息在所述第一裸片中的功能模块的地址空间信息的地址范围内时，确定所述第一访问请求用于访问所述第一裸片。
  15. 一种第二裸片，其特征在于，所述第二裸片包括：
    接收单元，用于接收第一裸片发送的第二访问请求，所述第二访问请求包括第一地址信息和所述第一裸片译码得到的裸片标识；
    第二译码单元，用于所述第二裸片确定所述裸片标识为所述第二裸片的裸片标识时，根据所述第一地址信息译码得到所述第二访问请求访问的所述第二裸片的功能模块的模块标识。
  16. 根据权利要求15所述的第二裸片，其特征在于，所述第二裸片还包括：
    传输单元，用于所述第二裸片确定所述裸片标识不为所述第二裸片的裸片标识时，将所述第二访问请求传输至第三裸片。
  17. 根据权利要求15或16所述的第二裸片，其特征在于，所述第二裸片包括多个功能模块，所述第二裸片配置有第二地址空间信息，所述第二地址空间信息包括所述第二裸片中每个功能模块的地址空间信息和除所述第二裸片外的其他裸片的地址空间信息。
  18. 根据权利要求17所述的第二裸片，其特征在于，所述第二裸片中每个功能模块的地址空间信息包括所述第二裸片中每个功能模块的基地址和所述第二裸片中每个功能模块的地址空间大小，所述其他裸片的地址空间信息包括所述其他裸片的基地址和所述其他裸片的地址空间大小。
  19. 一种计算机可读存储介质，其特征在于，包括计算机指令，当计算机指令在电子设备上运行时，使得电子设备执行上述权利要求1-9中的任一项所述的方法。
  20. 一种计算机程序产品，其特征在于，当计算机程序产品在计算机或处理器上运行时，使得所述计算机或所述处理器执行上述权利要求1-9中的任一项所述的方法。
PCT/CN2024/074317 2023-01-31 2024-01-26 一种译码方法、第一裸片和第二裸片 WO2024160156A1 (zh)

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