WO2024159658A1 - 存储器电路以及存储器版图 - Google Patents

存储器电路以及存储器版图 Download PDF

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Publication number
WO2024159658A1
WO2024159658A1 PCT/CN2023/095112 CN2023095112W WO2024159658A1 WO 2024159658 A1 WO2024159658 A1 WO 2024159658A1 CN 2023095112 W CN2023095112 W CN 2023095112W WO 2024159658 A1 WO2024159658 A1 WO 2024159658A1
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Prior art keywords
transistor
group
transistor group
local data
conductive portion
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PCT/CN2023/095112
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English (en)
French (fr)
Inventor
巴杭天
罗怡菲
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits

Definitions

  • the disclosed embodiments relate to the field of semiconductor technology, and in particular to a memory circuit and a memory layout.
  • DRAM Dynamic Random Access Memory
  • the circuit design and layout design of memory are essential design links for realizing integrated circuit manufacturing. It is not only related to whether the function of the integrated circuit is correct, but also greatly affects the performance, cost and power consumption of the integrated circuit.
  • the current circuit structure and layout layout of memory need to be improved.
  • an embodiment of the present disclosure provides a memory circuit, including: an amplification module, the amplification module including a plurality of amplification units with the same components, each amplification unit being connected in series between a corresponding group of local data lines and complementary local data lines to amplify the voltage difference between the local data lines and the complementary local data lines; each amplification unit including: a first transistor, a second transistor and a third transistor, wherein the source of the first transistor is used to receive a power supply voltage, the gate of the first transistor is used to receive a readout control signal, the drain of the first transistor is respectively connected to the source of the second transistor and the source of the third transistor, the drain of the second transistor is connected to the local data line, the drain of the third transistor is connected to the complementary local data line, the drain of the second transistor is connected to the gate of the third transistor, and the drain of the third transistor is connected to the gate of the second transistor.
  • a memory layout including: an amplification module, the amplification module including a plurality of amplification units with the same components, each amplification unit being connected in series between a corresponding group of local data lines and complementary local data lines to amplify the voltage difference between the local data lines and the complementary local data lines; each amplification unit including: a first transistor, a second transistor and a third transistor, wherein the drain of the first transistor is connected to the source of the second transistor and the source of the third transistor respectively; two first transistors form a first transistor group, and the plurality of first transistor groups are arranged along a first direction; the second transistor and the third transistor connected to the first transistor form a second transistor group, and the first transistor group is arranged along a first direction; A second transistor group is arranged on both sides of the two opposite directions, and along the second direction, among the two first transistors of the first transistor group, one first transistor is connected to the second transistor and the third transistor in the second transistor group on the adjacent side, and the other first transistor
  • two first transistors in the first transistor group have a common first active region
  • one second transistor and one third transistor in the second transistor group have a common second active region
  • a second active region corresponding to one second transistor group and a second active region corresponding to another second transistor group are aligned with each other in the second direction.
  • the second active region includes a first drain region, a common source region, and a second drain region arranged in sequence, wherein the first drain region is the drain of the second transistor, the second drain region is the drain of the third transistor, and the common source region is the source shared by the second transistor and the third transistor; the memory layout also includes: multiple first routing lines, a first routing line is used to connect the drain of the first transistor and an adjacent common source region.
  • the second transistors of one second transistor group are aligned with the second transistors of the other second transistor group in the second direction
  • the third transistors of one second transistor group are aligned with the third transistors of the other second transistor group in the second direction.
  • it also includes: multiple first conductive parts, the first conductive part is located between the second transistor group and the first transistor group, and the first conductive part is electrically connected to the gate of the adjacent second transistor, or the first conductive part is electrically connected to the gate of the adjacent third transistor.
  • it also includes: a second conductive portion electrically connected to the gate of the first transistor, the second conductive portion extending along the first direction, and a portion of the second conductive portion is at least located between the first conductive portion and the first transistor group; along the second direction, the length of the first conductive portion away from the side of the adjacent second transistor group to the adjacent second transistor group is a first length, and the length of the second conductive portion away from the side of the adjacent first transistor group to the adjacent first transistor group is a second length, and the first length is greater than the second length.
  • it also includes: a third conductive portion, the third conductive portion is located on a side of the second transistor group away from the first transistor group, and the third conductive portion is connected to a gate of the adjacent second transistor group that is not connected to the first conductive portion.
  • the memory layout further includes: a switch control area, the switch control area includes an amplification module, along the second direction, the amplification module has a first side and a second side opposite to each other, and the length from the first side to the edge of the adjacent switch control area is The length is the same as the length from the second side to the edge of the adjacent switch control area.
  • FIG1 is a schematic diagram of a partial equivalent circuit structure of a memory circuit
  • FIG2 is a schematic diagram of a partial circuit structure of an amplification module in the related art
  • FIG3 is a schematic diagram of a partial circuit structure of an amplification module provided by an embodiment of the present disclosure
  • FIG4 is a schematic diagram of the structure of a memory layout provided by an embodiment of the present disclosure.
  • FIG5 is a schematic diagram of the structure of a first transistor group provided by an embodiment of the present disclosure.
  • FIG6 is a schematic structural diagram of a second transistor group provided by an embodiment of the present disclosure.
  • FIG7 is a schematic diagram of the structure of another memory layout provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of the structure of another memory layout provided by an embodiment of the present disclosure.
  • FIG. 1 is a schematic diagram of a partial equivalent circuit structure of a memory circuit.
  • the memory includes a plurality of memory arrays, each memory array includes a plurality of memory cells, and the memory cell may be a 1T1C (1 transistor 1 capacitance) structure consisting of a switch transistor and a unit capacitor.
  • the memory may further include a sense amplifier 10, an input/output circuit 11, an amplification module 12, a precharge unit 14, and a local amplifier 13.
  • the amplification module 12 may also be referred to as an intermediate amplification module.
  • One of the source or drain in the switching transistor is connected to the unit capacitor, and the other is connected to the bit line BL/complementary bit line BLB.
  • the word line WL is connected to the gate of the switching transistor and is used to select the gate of the corresponding switching transistor to be turned on, so that the unit capacitor is connected to the bit line BL/complementary bit line BLB, thereby realizing the writing of the electrical signal in the bit line BL/complementary bit line BLB into the unit capacitor, or realizing the reading of the electrical signal in the unit capacitor into the bit line BL/complementary bit line BLB.
  • the sense amplifier 10 is connected between the bit line BL and the complementary bit line BLB.
  • the sense amplifier 10 is used to amplify the bit line The voltage difference between BL and the complementary bit line BLB.
  • the input/output circuit 11 includes: an input/output transistor, one of the source or the drain of the input/output transistor is connected to the bit line BL/complementary bit line BLB, and the other is connected to the local data line LIO/complementary local data line LIOB, and the gate of the input/output transistor is used to receive the column selection signal CSL, and according to the column selection signal CSL, select and turn on the input/output transistor corresponding to the column selection signal CSL, so that the bit line BL/complementary bit line BLB is connected to the local data line LIO/complementary local data line LIOB, thereby realizing data transmission between the bit line BL/complementary bit line BLB and the local data line LIO/complementary local data line LIOB.
  • the local data line LIO is connected to the global data line Yio through the local amplifier 13, so as to realize data transmission between the local data line LIO and the global data line Yio
  • the complementary local data line LIOB is connected to the complementary global data line YioN through the local amplifier 13, so as to realize data transmission between the complementary local data line LIOB and the complementary global data line YioN.
  • the precharge unit 14 is connected in series between the local data line LIO and the complementary local data line LIOB to precharge the local data line LIO and the complementary local data line LIOB to an intermediate potential.
  • the memory circuit includes multiple groups of local data lines LIO and complementary local data lines LIOB.
  • the signals on the local data lines LIO and the complementary local data lines LIOB may cause certain losses due to interference between lines and other reasons, thereby causing signal distortion and affecting the performance of the memory.
  • the amplification module 12 is connected in series between the local data lines LIO and the complementary local data lines LIOB, and is used to amplify the voltage difference between the local data lines LIO and the complementary local data lines LIOB to compensate for the losses caused during the signal transmission process, thereby improving the stability of the memory circuit system.
  • FIG. 2 is a schematic diagram of a partial circuit structure of an amplification module in the related art.
  • the amplification module 12 includes a plurality of first transistors m1, a plurality of second transistors m2, and a plurality of third transistors m3, wherein the first transistors m1, the second transistors m2, and the third transistors m3 are all PMOS (Positive channel Metal Oxide Semiconductor) tubes.
  • the second transistors m2 and the third transistors m3 form a transistor group 15, wherein the source of the first transistor m1 is used to receive the power supply voltage VCC, and the gate of the first transistor m1 is used to receive the readout control signal RdEnN.
  • the drain of the second transistor m2 is connected to the corresponding local data line LIO
  • the drain of the third transistor m3 is connected to the corresponding complementary local data line LIOB
  • the drain of the second transistor m2 is connected to the gate of the third transistor m3
  • the drain of the third transistor m3 is connected to the gate of the second transistor m2.
  • the number of the first transistors m1 is different from the number of the transistor groups 15, that is, the number of the first transistors m1 may be less than or greater than the number of the transistor groups 15.
  • the amplification module 12 may include 4 first transistors m1, 8 second transistors m2, and 8 third transistors m3, that is, the amplification module 12 includes 4 first transistors m1 and 8 transistor groups 15. Since the transistor group 15 composed of the second transistors m2 and the third transistors m3 is not in a one-to-one correspondence with the first transistors m1, a wire is usually used to lead out the drain of at least one first transistor m1 or to connect the drains of multiple parallel first transistors m1, and then divide the multiple transistor groups 15 into The first transistor m1 is connected to the lead-out line of the first transistor separately, which is equivalent to multiple transistors 15 sharing the same first transistor m1 or sharing a transistor group composed of multiple first transistors m1. In this way, not only can the one-to-one control of the first transistor m1 over the transistor group 15 not be achieved, but it is also not conducive to the symmetrical arrangement of the first transistor m1 and the transistor group 15 in the memory layout.
  • the embodiments of the present disclosure provide a memory circuit and a memory layout, wherein the amplification module in the memory circuit includes a plurality of amplification units with the same components, the memory includes a plurality of groups of local data lines and complementary local data lines, each group of local data lines and complementary local data lines are connected in series with a corresponding group of amplification units, each amplification unit includes a first transistor, a second transistor and a third transistor, the transistors in different amplification units are independent of each other, that is, they are not shared, if the second transistor and the third transistor in the same amplification unit are defined as a transistor group, the first transistor is used to transmit a voltage signal to the source of the second transistor and the source of the third transistor respectively, that is, a one-to-one control of a first transistor to a corresponding transistor group is realized, which is conducive to improving the accuracy of controlling the memory circuit.
  • the two second transistor groups are symmetrically distributed on both sides of the first transistor group, which is conducive to improving the symmetry of the memory layout.
  • a first transistor in the first transistor group is connected to the second transistor and the third transistor located on one side of the first transistor group, and another first transistor in the first transistor group is connected to the second transistor and the third transistor located on the other side of the first transistor group, so that the two connecting lines between the first transistor group and the second transistor groups on both sides extend toward the opposite sides away from the first transistor group, which is beneficial to further improve the symmetry of the memory layout, and thus is beneficial to improving the performance of the memory.
  • Fig. 3 is a schematic diagram of a partial circuit structure of an amplification module provided in an embodiment of the present disclosure. It should be noted that Fig. 3 omits multiple groups of local data lines and complementary local data lines, and only illustrates one group of local data lines and complementary local data lines.
  • an embodiment of the present disclosure provides a memory circuit, including: an amplification module 12, the amplification module 12 includes a plurality of amplification units 20 with the same components, each amplification unit 20 is connected in series between a corresponding set of local data lines LIO and complementary local data lines LIOB to amplify the voltage difference between the local data lines LIO and the complementary local data lines LIOB.
  • the signal transmitted by the local data line LIO or the complementary local data line LIOB may be lost to a certain extent, causing the signal transmitted by the local data line LIO or the complementary local data line LIOB to be distorted.
  • the signal distortion may reduce the performance of the memory and even cause erroneous data to be read.
  • the amplification module 12 is used to amplify the voltage difference between the local data line LIO and the complementary local data line LIOB to Make up for the loss caused in the signal transmission process, thereby improving the stability of the memory circuit system.
  • the number of amplification units 20 in the amplification module 12 is determined by the number of groups of local data lines LIO and complementary local data lines LIOB.
  • the memory circuit may include 8 groups of local data lines LIO and complementary local data lines LIOB, and accordingly, the amplification module 12 includes 8 amplification units 20.
  • each amplifying unit 20 includes: a first transistor M1, a second transistor M2 and a third transistor M3, and the first transistor M1, the second transistor M2 and the third transistor M3 are all PMOS tubes.
  • the number of the first transistor M1 is the same as the number of the second transistor M2 and the number of the third transistor M3.
  • the source of the first transistor M1 is used to receive the power supply voltage VCC
  • the gate of the first transistor M1 is used to receive the readout control signal RdEnN
  • the drain of the first transistor M1 is connected to the source of the second transistor M2 and the source of the third transistor M3 respectively.
  • a first transistor M1 in the amplifying module 12 transmits the power supply voltage VCC to a transistor group 16, that is, the one-to-one control of the first transistor M1 to the transistor group 16 is realized, which is conducive to improving the accuracy of controlling the memory circuit.
  • the drain of the second transistor M2 is connected to the corresponding local data line LIO
  • the drain of the third transistor M3 is connected to the corresponding complementary local data line LIOB
  • the drain of the second transistor M2 is connected to the gate of the third transistor M3
  • the drain of the third transistor M3 is connected to the gate of the second transistor M2.
  • the gate of the third transistor M3 connected to the local data line LIO receives the high-level signal
  • the third transistor M3 is turned off
  • the gate of the second transistor M2 connected to the complementary local data line LIOB receives the low-level signal
  • the second transistor M2 is turned on
  • the power supply voltage VCC is transmitted to the local data line LIO
  • the high-level signal transmitted by the local data line LIO is amplified through positive feedback.
  • the amplification module 12 includes a plurality of amplification units 20 with the same components.
  • the first transistor M1 in the amplification unit 20 performs one-to-one control on the transistor group 16, thereby enabling the amplification unit 20 to amplify a corresponding group of local data lines LIO and complementary local data lines LIOB, which is beneficial to improving the accuracy of controlling the memory circuit.
  • the embodiments of the present disclosure further provide a memory layout, which can be applied to the memory circuit provided in the above embodiments.
  • the memory layout provided in the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the parts that are the same as or corresponding to the above embodiments can refer to the above embodiments and will not be repeated below.
  • FIG. 4 is a schematic diagram of the structure of a memory layout according to an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of the structure of a first transistor group according to an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of the structure of a second transistor group according to an embodiment of the present disclosure
  • 7 is a schematic diagram of the structure of another memory layout provided by an embodiment of the present disclosure
  • FIG. 8 is a schematic diagram of the structure of another memory layout provided by an embodiment of the present disclosure.
  • the memory layout includes: an amplification module 12, the amplification module 12 includes a plurality of amplification units 20 with the same components, each amplification unit 20 is connected in series between a corresponding set of local data lines LIO and complementary local data lines LIOB to amplify the voltage difference between the local data lines LIO and the complementary local data lines LIOB; each amplification unit 20 includes: a first transistor M1, a second transistor M2 and a third transistor M3, wherein the drain of the first transistor M1 is connected to the source of the second transistor M2 and the source of the third transistor M3 respectively.
  • the amplification module 12 is used to amplify the voltage difference between the local data line LIO and the complementary local data line LIOB to compensate for the loss caused by the signal transmission process, thereby ensuring the stability of the memory circuit system.
  • the connection relationship between the amplification unit 20 and the local data line LIO and the complementary local data line LIOB, and the connection relationship between the first transistor M1, the second transistor M2, and the third transistor M3 in the amplification unit 20 can refer to the above-mentioned embodiment and Figures 1 and 3.
  • two mutually independent first transistors M1 form a first transistor group 100 , and a plurality of first transistor groups 100 are arranged along a first direction Y.
  • the first direction Y may be an extending direction of a bit line in a memory layout.
  • the second transistor M2 and the third transistor M3 connected to the first transistor M1 form a second transistor group 200, and a second transistor group 200 is provided on both opposite sides of the first transistor group 100 along the second direction X, and along the second direction X, of the two first transistors M1 of the first transistor group 100, one first transistor M1 is connected to the second transistor M2 and the third transistor M3 in the second transistor group 200 on the adjacent side, and the other first transistor M1 is connected to the second transistor M2 and the third transistor M3 in the second transistor group 200 on the adjacent other side, and the second direction X is perpendicular to the first direction Y.
  • the two second transistor groups 200 are symmetrically distributed on both sides of the first transistor group 100, which is conducive to improving the symmetry of the memory layout.
  • the second transistor M2 is directed in the opposite direction toward the third transistor M3, and the two connecting lines between the first transistor group 100 and the second transistor groups 200 on both sides extend toward opposite sides away from the first transistor group 100, which is beneficial to further improve the symmetry of the memory layout, and thus help improve the performance of the memory.
  • the two second transistor groups 200 located on opposite sides of the first transistor group 100 are two second transistor groups 200 corresponding to the first transistor group 100 , and the distances from the first transistor group 100 to the corresponding two second transistor groups 200 are the same.
  • the two first transistors M1 in the first transistor group 100 have a common first active region 110.
  • the size of the first transistor M1 can be maximized within a limited space, which is beneficial to improving the performance of the memory and improving the connection between the two first transistors M1 in the same first transistor group 100.
  • the space waste of the spacing area is beneficial to improve the utilization efficiency of the layout.
  • the active areas 121 of the two first transistors M1 in the first transistor group 100 are disposed separately from each other.
  • the two first transistors M1 in the first transistor group 100 have a common first active region 110, and the first active region 110 includes a common source region 131 and a drain region 130 which is spaced apart from the common source region 131 and is located on both sides of the common source region 131, wherein the drain region 130 is the drain of the first transistor M1, and the common source region 131 is the source shared by the two first transistors M1.
  • a second transistor M2 and a third transistor M3 in the second transistor group 200 have a common second active area 210.
  • the size of the second transistor M2 and the size of the third transistor M3 can be maximized within a limited space, which is beneficial to improving the performance of the memory, and is beneficial to improving the waste of space in the interval area between the second transistor M2 and the third transistor M3 in the same second transistor group 200, which is beneficial to improving the utilization efficiency of the layout.
  • the active area 221 of the second transistor M2 and the active area 231 of the third transistor M3 are arranged separately from each other.
  • the gates 120 of the two first transistors M1 of the first transistor group 100 are arranged at intervals along the first direction Y on the first active area 110
  • the gates 220 of the second transistor M2 and the gates 230 of the third transistor M3 of the second transistor group 200 are arranged at intervals along the first direction Y on the second active area 210
  • the gates 120 of the first transistor M1, the gates 220 of the second transistor M2, and the gates 230 of the third transistor M3 all extend along the second direction X.
  • the second active area 210 corresponding to one second transistor group 200 and the second active area 210 corresponding to the other second transistor group 200 are aligned with each other in the second direction X. That is, in the two second transistor groups 200 located on both sides of the first transistor group 100, the direction in which one second transistor group 200 points to the other second transistor group 200 is parallel to the second direction X.
  • the direction in which one second transistor group 200 points to the other second transistor group 200 may also be different from the second direction X, that is, the two second transistor groups 200 are symmetrically distributed diagonally.
  • the second active region 210 includes a first drain region I, a common source region II, and a second drain region III arranged in sequence, wherein the first drain region I is the drain of the second transistor M2, the second drain region III is the drain of the third transistor M3, and the common source region II is the source shared by the second transistor M2 and the third transistor M3; the memory layout also includes: a plurality of first wirings 101, a first wiring 101 is used to connect the drain of the first transistor M1 and an adjacent common source region II.
  • the two first wirings 101 derived from the first transistor group 100 extend to opposite sides of the first transistor group 100, that is, the two first wirings 101 derived from the first transistor group 100 are also symmetrically distributed, which is conducive to improving the symmetry of the memory layout, and thus is conducive to improving the performance of the memory.
  • the first wiring 101 is a wire located in the first conductive layer.
  • the first conductive layer is located in the first crystal.
  • the first wiring 101 is connected to the drain of the first transistor M1 through a conductive plug, and is connected to the common source region II through a conductive plug.
  • the second transistor M2 of one second transistor group 200 is aligned with the second transistor M2 of the other second transistor group 200 in the second direction X
  • the third transistor M3 of one second transistor group 200 is aligned with the third transistor M3 of the other second transistor group 200 in the second direction X.
  • the second transistor M2 of one second transistor group 200 is symmetrically distributed with the second transistor M2 of the other second transistor group 200 with A-A1 as the symmetry axis, and A-A1 may be an extension line of a line connecting the center points of different first transistor groups 100 arranged along the first direction Y.
  • the second transistor M2 of one second transistor group 200 and the third transistor M3 of the other second transistor group 200 are aligned with each other in the second direction X. That is, in the two second transistor groups 200 located on opposite sides of the first transistor group 100, the two second transistors M2 in different second transistor groups 200 are symmetrically distributed diagonally.
  • the memory layout further includes: a plurality of first conductive portions 111, the first conductive portion 111 is located between the second transistor group 200 and the first transistor group 100, and the first conductive portion 111 is electrically connected to the gate 220 of the adjacent second transistor M2, or the first conductive portion 111 is electrically connected to the gate 230 of the adjacent third transistor M3.
  • FIG7 illustrates the electrical connection between the first conductive portion 111 and the gate 230 of the adjacent third transistor M3 as an example.
  • the two second transistor groups 200 corresponding to the first transistor group 100 are symmetrically distributed, the two first conductive portions 111 located on both sides of the first transistor M1 are also symmetrically distributed, which is conducive to improving the symmetry of the memory layout, and thus is conducive to improving the performance of the memory.
  • the memory layout further includes: a second conductive portion 112 electrically connected to the gate 120 of the first transistor M1, the second conductive portion 112 extending along the first direction Y, and a portion of the second conductive portion 112 at least located between the first conductive portion 111 and the first transistor group 100; along the second direction X, the length from the side of the first conductive portion 111 away from the adjacent second transistor group 200 to the adjacent second transistor group 200 is a first length L1, and the length from the side of the second conductive portion 112 away from the adjacent first transistor group 100 to the adjacent first transistor group 100 is a second length L2, and the first length L1 is greater than the second length L2.
  • first transistor group 100 and the second transistor group 200 Due to the limited space between the first transistor group 100 and the second transistor group 200, setting the second conductive portion 112 at a position closer to the first transistor group 100 is conducive to setting the first conductive portion 111 at a position farther from the second transistor group 200, thereby reducing the impact caused by the first conductive portion 111 being too close to the gate 220 of the second transistor M2, and improving device performance. Furthermore, the first conductive portion 111 and the second conductive portion 112 are both disposed between the first transistor group 100 and the second transistor group 200 , which is beneficial to improving the utilization rate of the layout.
  • an end portion of the second conductive portion 112 has a bending portion 114 connected to the second conductive portion 112 .
  • the bending portion 114 increases the size of the second conductive portion 112.
  • the second conductive portion 112 with the bending portion 114 allows the conductive plug to be set on the bending portion 114 and the second conductive portion 112. Compared with only setting the conductive plug on the second conductive portion 112, it is beneficial to increase the size of the conductive plug, and further help reduce the on-resistance of the conductive plug, thereby improving the performance of the memory.
  • the second transistor group 200 has a first redundant gate 301 disposed on the substrate on both sides along the first direction Y, and the first redundant gate 301 is used to balance the weight distribution in the region.
  • the material of the first redundant gate 301 is the same as the material of the gate 220 of the second transistor M2 and the gate 230 of the third transistor M3, both of which are polysilicon, so as to balance the weight distribution of polysilicon in the entire region including the two second transistor groups 200 adjacent to each other; in addition, the first redundant gate 301 is disposed at the edge position of the first direction Y during the process, which can also improve the accuracy of the gate position of the second transistor M2 and the third transistor M3, and reduce the influence of the optical proximity effect.
  • the gate 230 of the third transistor M3 is connected to the first conductive part 111 on one side along the second direction X, so that the first conductive part 111 is disposed at a position far away from the second transistor group 200, which is conducive to avoiding the first conductive part 111 from being too close to the gate 220 of the second transistor M2, thereby reducing the influence of the first conductive part 111 on the gate 220 of the second transistor M2, that is, reducing the signal crosstalk. It can be understood that the redundant gate 301 is not connected to the power signal.
  • the first transistor group 100 has a second redundant gate 300 disposed on the substrate on both sides along the first direction Y, and the second redundant gate 300 is used to balance the weight distribution in the region.
  • the material of the second redundant gate 300 is the same as that of the gate 120 of the first transistor M1, both of which are polysilicon, so as to balance the weight distribution of polysilicon in the entire region including the two first transistor groups 100 adjacent to each other; in addition, the second redundant gate 300 is disposed at the edge position in the first direction Y during the process, which can also improve the accuracy of the position of the gate 120 of the first transistor M1 and reduce the influence of the optical proximity effect.
  • the second redundant gate 300 has a second conductive portion 112 on one side along the second direction X. Since the second conductive portion 112 is disposed at a position close to the first transistor group 100, in order to prevent the second conductive portion 112 from being too close to the second redundant gate 300, the size of part of the second redundant gate 300 may be shortened along the second direction X, and one end of part of the second redundant gate 300 having the second conductive portion 112 on one side along the second direction X adjacent to the second conductive portion 112 may be disposed at a state far from the second conductive portion 112, so as to help prevent the second redundant gate 300 from affecting the second conductive portion 112. In some embodiments, in the second direction X, the distance between the second redundant gate 300 and the second conductive portion 112 is equal to the first length, or equal to the difference between the first length and the second length.
  • the memory layout further includes: a third conductive portion 113, the third conductive portion 113 is located on a side of the second transistor group 200 away from the first transistor group 100, and the third conductive portion 113 is connected to the gate of the adjacent second transistor group 200 that is not connected to the first conductive portion 111.
  • the two second transistor groups 200 corresponding to the first transistor group 100 are symmetrically distributed on both sides of the first transistor group 100, the two third conductive portions 113 located on both sides of the first transistor M1 are also symmetrically distributed on both sides of the first transistor group 100, which is conducive to improving the symmetry of the memory layout, and further conducive to improving the performance of the memory.
  • the memory layout further includes: a switch control area, the switch control area includes an amplifying module 12, and along the second direction X, the amplifying module 12 has a first side and a second side opposite to each other, and the length from the first side to the edge of the adjacent switch control area is the same as the length from the second side to the edge of the adjacent switch control area.
  • the remaining switch control areas on both sides of the amplifying module 12 are also symmetrically distributed, which is conducive to improving the symmetry of the memory layout, and thus is conducive to improving the performance of the memory.
  • the two second transistor groups are symmetrically distributed on both sides of the first transistor group, which is conducive to improving the symmetry of the memory layout.
  • one first transistor in the first transistor group is connected to the second transistor and the third transistor located on one side of the first transistor group, and another first transistor in the first transistor group is connected to the second transistor and the third transistor located on the other side of the first transistor group, so that the two connecting lines between the first transistor group and the second transistor groups on both sides extend toward the opposite sides away from the first transistor group, which is conducive to further improving the symmetry of the memory layout, and thus is conducive to improving the performance of the memory.

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Abstract

公开了一种存储器电路以及存储器版图。该存储器版图包括：包括多个放大单元的放大模块。每一放大单元包括：第一晶体管、第二晶体管以及第三晶体管。两个第一晶体管组成一个第一晶体管组。与第一晶体管相连接的第二晶体管和第三晶体管组成一个第二晶体管组，第一晶体管组沿第二方向上的相对两侧均设置有一第二晶体管组，且沿第二方向上，第一晶体管组的两个第一晶体管中，一个第一晶体管与相邻一侧的第二晶体管组内的第二晶体管和第三晶体管相连接，另一个第一晶体管与相邻另一侧的第二晶体管组内的第二晶体管和第三晶体管相连接。

Description

存储器电路以及存储器版图
交叉引用
本公开要求于2023年02月02日递交的名称为“存储器电路以及存储器版图”、申请号为202310115188.3的中国专利申请的优先权，其通过引用被全部并入本公开。
技术领域
本公开实施例涉半导体技术领域，特别涉及一种存储器电路以及存储器版图。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)通过向存储单元的电容器中存储电荷以完成对存储器的数据写入操作，通过读取存储单元的电容器中的电荷以完成对存储器的数据读出操作。
存储器的电路设计以及存储器的版图设计是实现集成电路制造所必不可少的设计环节，它不仅关系到集成电路的功能是否正确，而且也会极大程度地影响集成电路的性能、成本以及功耗。目前的存储器的电路结构以及存储器的版图布局有待改进。
发明内容
本公开实施例一方面提供一种存储器电路，包括：放大模块，放大模块包括多个元件相同的放大单元，每一放大单元串接于对应的一组本地数据线和互补本地数据线之间，以放大本地数据线和互补本地数据线之间的电压差；每一放大单元包括：第一晶体管、第二晶体管以及第三晶体管，其中，第一晶体管的源极用于接收供电电压，第一晶体管的栅极用于接收读出控制信号，第一晶体管的漏极分别与第二晶体管的源极以及第三晶体管的源极相连接，第二晶体管的漏极与本地数据线相连接，第三晶体管的漏极与互补本地数据线相连接，且第二晶体管的漏极与第三晶体管的栅极相连接，第三晶体管的漏极与第二晶体管的栅极相连接。
本公开实施例另一方面提供一种存储器版图，包括：放大模块，放大模块包括多个元件相同的放大单元，每一放大单元串接于对应的一组本地数据线和互补本地数据线之间，以放大本地数据线和互补本地数据线之间的电压差；每一放大单元包括：第一晶体管、第二晶体管以及第三晶体管，其中，第一晶体管的漏极分别与第二晶体管的源极以及第三晶体管的源极相连接；两个第一晶体管组成一个第一晶体管组，多个第一晶体管组沿第一方向排布；与第一晶体管相连接的第二晶体管和第三晶体管组成一个第二晶体管组，第一晶体管组沿第 二方向上的相对两侧均设置有一第二晶体管组，且沿第二方向上，第一晶体管组的两个第一晶体管中，一个第一晶体管与相邻一侧的第二晶体管组内的第二晶体管和第三晶体管相连接，另一个第一晶体管与相邻另一侧的第二晶体管组内的第二晶体管和第三晶体管相连接，第二方向垂直于第一方向。
在一些实施例中，第一晶体管组中的两个第一晶体管具有一共用的第一有源区，第二晶体管组中的一个第二晶体管和一个第三晶体管具有一共用的第二有源区。
在一些实施例中，沿第二方向上，位于第一晶体管组相对两侧的两个第二晶体管组中，一个第二晶体管组所对应的第二有源区与另一个第二晶体管组所对应的第二有源区在第二方向上相互对齐。
在一些实施例中，第二有源区包括依次间隔排布的第一漏区、共源区以及第二漏区，其中，第一漏区为第二晶体管的漏极，第二漏区为第三晶体管的漏极，共源区为第二晶体管和第三晶体管共用的源极；存储器版图还包括：多个第一走线，一第一走线用于连接第一晶体管的漏极和一相邻的共源区。
在一些实施例中，沿第二方向上，位于第一晶体管组相对两侧的两个第二晶体管组中，一个第二晶体管组的第二晶体管与另一个第二晶体管组的第二晶体管在第二方向上相互对齐，一个第二晶体管组的第三晶体管与另一个第二晶体管组的第三晶体管在第二方向上相互对齐。
在一些实施例中，还包括：多个第一导电部，第一导电部位于第二晶体管组与第一晶体管组之间，且第一导电部与相邻的第二晶体管的栅极电连接，或者第一导电部与相邻的第三晶体管的栅极电连接。
在一些实施例中，还包括：与第一晶体管的栅极电连接的第二导电部，第二导电部沿第一方向延伸，且部分第二导电部至少位于第一导电部与第一晶体管组之间；沿第二方向上，第一导电部远离邻近的第二晶体管组的一侧至邻近的第二晶体管组的长度为第一长度，第二导电部远离邻近的第一晶体管组的一侧至邻近的第一晶体管组的长度为第二长度，第一长度大于第二长度。
在一些实施例中，还包括：第三导电部，第三导电部位于第二晶体管组的远离第一晶体管组的一侧，且第三导电部与相邻的第二晶体管组中未与第一导电部相连接的栅极相连接。
在一些实施例中，存储器版图还包括：开关控制区，开关控制区包括放大模块，沿第二方向上，放大模块具有相对的第一侧和第二侧，第一侧至相邻的开关控制区边缘的长度 与第二侧至相邻的开关控制区边缘的长度相同。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制；为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一种存储器电路的部分等效电路结构示意图；
图2为相关技术中一种放大模块的部分电路结构示意图；
图3为本公开一实施例提供的一种放大模块的部分电路结构示意图；
图4为本公开一实施例提供的一种存储器版图的结构示意图；
图5为本公开一实施例提供的一种第一晶体管组的结构示意图；
图6为本公开一实施例提供的一种第二晶体管组的结构示意图；
图7为本公开一实施例提供的另一种存储器版图的结构示意图；
图8为本公开一实施例提供的另一种存储器版图的结构示意图。
具体实施方式
由背景技术可知，目前存储器的电路结构以及存储器的版图布局有待改进。
图1为一种存储器电路的部分等效电路结构示意图。
存储器包括多个存储阵列，每个存储阵列中都包含多个存储单元，存储单元可以是一开关晶体管和一单元电容器构成的1T1C(1transistor 1capacitance)结构。此外，参考图1，存储器还可以包括感测放大器10、输入/输出电路11、放大模块12、预充电单元14以及本地放大器13。放大模块12也可以被称之为中间放大模块。
开关晶体管中源极或漏极其中一者连接单元电容器，另一者连接位线BL/互补位线BLB，字线WL连接开关晶体管的栅极，用于选择导通相应开关晶体管的栅极，使单元电容器与位线BL/互补位线BLB连接，从而实现将位线BL/互补位线BLB中的电信号写入单元电容器中，或实现将单元电容器中的电信号读出到位线BL/互补位线BLB中。
感测放大器10连接在位线BL和互补位线BLB之间，感测放大器10用于放大位线 BL和互补位线BLB之间的电压差。
输入/输出电路11包括：输入/输出晶体管，输入/输出晶体管源极或漏极其中一者连接位线BL/互补位线BLB，另一者连接本地数据线LIO/互补本地数据线LIOB，输入/输出晶体管的栅极用于接收列选择信号CSL，并根据列选择信号CSL，选择导通与列选择信号CSL相应的输入/输出晶体管，以使位线BL/互补位线BLB与本地数据线LIO/互补本地数据线LIOB连接，从而实现位线BL/互补位线BLB与本地数据线LIO/互补本地数据线LIOB的数据传递。
本地数据线LIO通过本地放大器13连接全局数据线Yio，从而实现本地数据线LIO与全局数据线Yio之间的数据传输，互补本地数据线LIOB通过本地放大器13连接互补全局数据线YioN，以实现互补本地数据线LIOB与互补全局数据线YioN之间的数据传输。
预充电单元14串接于本地数据线LIO和互补本地数据线LIOB之间，以使本地数据线LIO和互补本地数据线LIOB预充电至中间电位。
存储器电路包括多组本地数据线LIO以及互补本地数据线LIOB，本地数据线LIO以及互补本地数据线LIOB上的信号在传输过程中，可能由于线路之间的干扰等原因造成一定的损耗，进而使得信号失真，影响存储器的性能，放大模块12串接于本地数据线LIO和互补本地数据线LIOB之间，用于对本地数据线LIO以及互补本地数据线LIOB之间的电压差进行放大，以弥补信号传输过程中造成的损耗，进而提高存储器电路系统的稳定性。
图2为相关技术中一种放大模块的部分电路结构示意图。
参考图1和图2，相关技术中，放大模块12包括多个第一晶体管m1、多个第二晶体管m2以及多个第三晶体管m3，第一晶体管m1、第二晶体管m2以及第三晶体管m3均为PMOS(Positive channel Metal Oxide Semiconductor，P沟道金属氧化物半导体)管。第二晶体管m2和第三晶体管m3组成一个晶体管组15，第一晶体管m1的源极用于接收供电电压VCC，第一晶体管m1的栅极用于接收读出控制信号RdEnN，晶体管组15中，第二晶体管m2的漏极与相应的本地数据线LIO相连接，第三晶体管m3的漏极与相应的互补本地数据线LIOB相连接，且第二晶体管m2的漏极与第三晶体管m3的栅极相连接，第三晶体管m3的漏极与第二晶体管m2的栅极相连接。其中，第一晶体管m1的数量和晶体管组15的数量不同，即第一晶体管m1的数量可以小于或大于晶体管组15的数量，例如，放大模块12可以包括4个第一晶体管m1、8个第二晶体管m2以及8个第三晶体管m3，即放大模块12包括4个第一晶体管m1和8个晶体管组15，由于第二晶体管m2与第三晶体管m3组成的晶体管组15与第一晶体管m1并非一一对应的关系，所以通常利用一条导线引出至少一个第一晶体管m1的漏极或者将多个并联的第一晶体管m1的漏极相连接，再将多个晶体管组15分 别与第一晶体管的引出线相连接，相当于多个晶体管15共用同一第一晶体管m1或者说共用多个第一晶体管m1构成的晶体管组。如此，不仅无法实现第一晶体管m1对晶体管组15的一对一控制，也不利于第一晶体管m1与晶体管组15在存储器的版图布局中实现对称排布。
为解决上述问题，本公开实施例提供了一种存储器电路以及存储器版图，存储器电路中的放大模块包括多个元件相同的放大单元，存储器包括多组本地数据线和互补本地数据线，每一组本地数据线和互补本地数据线之间均串接有对应的一组放大单元，每个放大单元中均包括第一晶体管、第二晶体管以及第三晶体管，不同放大单元中的晶体管相互独立，即不共用，若定义同一放大单元内的第二晶体管和第三晶体管为一晶体管组，利用第一晶体管分别向第二晶体管的源极以及第三晶体管的源极传输电压信号，即实现一个第一晶体管对相应的一个晶体管组的一对一控制，有利于提高控制存储器电路的精确性。存储器版图中，使两个第二晶体管组对称分布在第一晶体管组的两侧，有利于提高存储器版图布局的对称性。此外，第一晶体管组中的一个第一晶体管与位于第一晶体管组一侧的第二晶体管和第三晶体管相连接，第一晶体管组中的另一个第一晶体管与位于第一晶体管组另一侧的第二晶体管和第三晶体管相连接，使得第一晶体管组与两侧的第二晶体管组之间的两条连线分别朝远离第一晶体管组的相对两侧延伸，有利于进一步提高存储器版图布局的对称性，进而有利于提升存储器的性能。
下面将结合附图对本公开各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开实施例而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开实施例所要求保护的技术方案。
图3为本公开一实施例提供的一种放大模块的部分电路结构示意图。需要说明的是，图3对多组本地数据线与互补本地数据线进行了省略，仅对一组本地数据线与互补本地数据线进行了图示。
参考图1和图3，本公开实施例一方面提供一种存储器电路，包括：放大模块12，放大模块12包括多个元件相同的放大单元20，每一放大单元20串接于对应的一组本地数据线LIO和互补本地数据线LIOB之间，以放大本地数据线LIO和互补本地数据线LIOB之间的电压差。
存储器电路中，由于噪声等信号干扰因素的存在，可能导致本地数据线LIO或者互补本地数据线LIOB所传输的信号产生一定的损耗，使得本地数据线LIO或者互补本地数据线LIOB所传输的信号失真，信号失真可能降低存储器的性能，甚至导致读出错误的数据，放大模块12用于对本地数据线LIO以及互补本地数据线LIOB之间的电压差进行放大，以 弥补信号传输规程中造成的损耗，进而提高存储器电路系统的稳定性。
放大模块12中放大单元20的数量由成组的本地数据线LIO以及互补本地数据线LIOB的数量所决定，在一个例子中，存储器电路可以包括8组本地数据线LIO以及互补本地数据线LIOB，则相应的，放大模块12包括8个放大单元20。
参考图3，每一放大单元20包括：第一晶体管M1、第二晶体管M2以及第三晶体管M3，第一晶体管M1、第二晶体管M2以及第三晶体管M3均为PMOS管。放大模块12中，第一晶体管M1的数量与第二晶体管M2的数量以及第三晶体管M3的数量均相同。第一晶体管M1的源极用于接收供电电压VCC，第一晶体管M1的栅极用于接收读出控制信号RdEnN，第一晶体管M1的漏极分别与第二晶体管M2的源极以及第三晶体管M3的源极相连接。若定义放大单元20内的第二晶体管M2和第三晶体管M3组成一个晶体管组16，读出控制信号有效时，放大模块12中的一个第一晶体管M1向一个晶体管组16传输供电电压VCC，即实现第一晶体管M1对晶体管组16的一对一控制，有利于提高控制存储器电路的精确性。
继续参考图3，第二晶体管M2的漏极与相应的本地数据线LIO相连接，第三晶体管M3的漏极与相应的互补本地数据线LIOB相连接，且第二晶体管M2的漏极与第三晶体管M3的栅极相连接，第三晶体管M3的漏极与第二晶体管M2的栅极相连接。当第一晶体管M1的栅极接收到的读出控制信号有效时，第一晶体管M1导通，将供电电压VCC传输至第二晶体管M2的源极以及第三晶体管M3的源极，若本地数据线LIO传输高电平信号，互补本地数据线LIOB传输低电平信号，与本地数据线LIO相连接的第三晶体管M3的栅极接收到高电平信号，第三晶体管M3截止，与互补本地数据线LIOB相连接的第二晶体管M2的栅极接收到低电平信号，第二晶体管M2导通，并将供电电压VCC传输至本地数据线LIO，通过正反馈对本地数据线LIO所传输的高电平信号进行放大。
上述实施例提供的存储器电路中，放大模块12包括多个元件相同的放大单元20，放大单元20中的第一晶体管M1对晶体管组16进行一对一控制，进而实现放大单元20对相应的一组本地数据线LIO以及互补本地数据线LIOB进行放大，有利于提高控制存储器电路的精确性。
本公开实施例另一方面还提供一种存储器版图，存储器版图可以应用于上述实施例提供的存储器电路，下面将结合附图对本公开实施例提供存储器版图进行详细说明，需要说明的是，与前述实施例相同或相应的部分可以参考前述实施例，以下将不做赘述。
图4为本公开一实施例提供的一种存储器版图的结构示意图；图5为本公开一实施例提供的一种第一晶体管组的结构示意图；图6为本公开一实施例提供的一种第二晶体管组 的结构示意图；图7为本公开一实施例提供的另一种存储器版图的结构示意图；图8为本公开一实施例提供的另一种存储器版图的结构示意图。
参考图1、图3以及图4，存储器版图包括：放大模块12，放大模块12包括多个元件相同的放大单元20，每一放大单元20串接于对应的一组本地数据线LIO和互补本地数据线LIOB之间，以放大本地数据线LIO和互补本地数据线LIOB之间的电压差；每一放大单元20包括：第一晶体管M1、第二晶体管M2以及第三晶体管M3，其中，第一晶体管M1的漏极分别与第二晶体管M2的源极以及第三晶体管M3的源极相连接。
放大模块12用于对本地数据线LIO以及互补本地数据线LIOB之间的电压差进行放大，以弥补信号传输规程中造成的损耗，进而保证提高存储器电路系统的稳定性。放大模块12中，放大单元20与本地数据线LIO以及互补本地数据线LIOB的连接关系、放大单元20中第一晶体管M1、第二晶体管M2以及第三晶体管M3的连接关系可以参考前述实施例以及图1和图3。
参考图4，存储器版图中，两个相互独立的第一晶体管M1组成一个第一晶体管组100，多个第一晶体管组100沿第一方向Y排布。
在一些实施例中，第一方向Y可以为存储器版图中位线的延伸方向。
参考图3和图4，与第一晶体管M1相连接的第二晶体管M2和第三晶体管M3组成一个第二晶体管组200，第一晶体管组100沿第二方向X上的相对两侧均设置有一第二晶体管组200，且沿第二方向X上，第一晶体管组100的两个第一晶体管M1中，一个第一晶体管M1与相邻一侧的第二晶体管组200内的第二晶体管M2和第三晶体管M3相连接，另一个第一晶体管M1与相邻另一侧的第二晶体管组200内的第二晶体管M2和第三晶体管M3相连接，第二方向X垂直于第一方向Y。如此，两个第二晶体管组200对称分布在第一晶体管组100的两侧，有利于提高存储器版图布局的对称性。此外，位于第一晶体管组100的相对两侧的不同第二晶体管组200中，第二晶体管M2朝向第三晶体管M3的方向相反，第一晶体管组100与两侧的第二晶体管组200之间的两条连线分别朝远离第一晶体管组100的相对两侧延伸，有利于进一步提高存储器版图布局的对称性，进而有利于提升存储器的性能。
需要说明的是，沿第二方向上，位于第一晶体管组100相对两侧的两个第二晶体管组200为第一晶体管组100所对应的两个第二晶体管组200，第一晶体管组100至所对应的两个第二晶体管组200距离均相同。
在一些实施例中，参考图4，第一晶体管组100中的两个第一晶体管M1具有一共用的第一有源区110。如此，可以在有限的空间内，使第一晶体管M1的尺寸最大化，有利于提升存储器的性能，并且，有利于改善同一第一晶体管组100中，两个第一晶体管M1之间 的间隔区域对空间的浪费，有利于提升版图的利用效率。在另一些实施例中，参考图5，第一晶体管组100中的两个第一晶体管M1的有源区121相互分立设置。
参考图4，第一晶体管组100中的两个第一晶体管M1具有一共用的第一有源区110，第一有源区110包括共源区131以及与共源区131间隔排布且位于共源区131两侧的漏区130，其中，漏区130为第一晶体管M1的漏极，共源区131为两个第一晶体管M1共用的源极。
在一些实施例中，参考图4，第二晶体管组200中的一个第二晶体管M2和一个第三晶体管M3具有一共用的第二有源区210。如此，可以在有限的空间内，使第二晶体管M2的尺寸以及第三晶体管M3的尺寸最大化，有利于提升存储器的性能，并且，有利于改善同一第二晶体管组200中，第二晶体管M2与第三晶体管M3之间的间隔区域对空间的浪费，有利于提升版图的利用效率。在另一些实施例中，参考图6，第二晶体管组200中，第二晶体管M2的有源区221和第三晶体管M3的有源区231相互分立设置。
在一些实施例中，参考图4，第一晶体管组100的两个第一晶体管M1的栅极120在第一有源区110上沿第一方向Y间隔排布，第二晶体管组200的第二晶体管M2的栅极220和第三晶体管M3的栅极230在第二有源区210上沿第一方向Y间隔排布，且第一晶体管M1的栅极120、第二晶体管M2的栅极220以及第三晶体管M3的栅极230均沿第二方向X延伸。
在一些实施例中，参考图4，沿第二方向X上，位于第一晶体管组100相对两侧的两个第二晶体管组200中，一个第二晶体管组200所对应的第二有源区210与另一个第二晶体管组200所对应的第二有源区210在第二方向X上相互对齐。即位于第一晶体管组100两侧的两个第二晶体管组200中，一个第二晶体管组200指向另一个第二晶体管组200的方向平行于第二方向X。可以理解的是，在另一些实施例中，位于第一晶体管组100两侧的两个第二晶体管组200中，一个第二晶体管组200指向另一个第二晶体管组200的方向也可以与第二方向X不同，即两个第二晶体管组200呈角对角对称分布。
参考图7，在一些实施例中，第二有源区210包括依次间隔排布的第一漏区I、共源区II以及第二漏区III，其中，第一漏区I为第二晶体管M2的漏极，第二漏区III为第三晶体管M3的漏极，共源区II为第二晶体管M2和第三晶体管M3共用的源极；存储器版图还包括：多个第一走线101，一第一走线101用于连接第一晶体管M1的漏极和一相邻的共源区II。如此，由第一晶体管组100引出的两条第一走线101分别向第一晶体管组100的相对两侧延伸，即第一晶体管组100引出的两条第一走线101也呈对称分布，有利于提升存储器版图布局的对称性，进而有利于提升存储器的性能。
需要说明的是，第一走线101为位于第一导电层的导线，第一导电层位于第一晶体 管组以及第二晶体管组的上方，且第一走线101通过导电插塞与第一晶体管M1的漏极相连接，以及通过导电插塞与共源区II连接。
在一些实施例中，参考图7，沿第二方向X上，位于第一晶体管组100相对两侧的两个第二晶体管组200中，一个第二晶体管组200的第二晶体管M2与另一个第二晶体管组200的第二晶体管M2在第二方向X上相互对齐，一个第二晶体管组200的第三晶体管M3与另一个第二晶体管组200的第三晶体管M3在第二方向X上相互对齐。即位于第一晶体管组100相对两侧的两个第二晶体管组200中，一个第二晶体管组200的第二晶体管M2与另一个第二晶体管组200的第二晶体管M2以A-A1为对称轴对称分布，A-A1可以是沿第一方向Y排布的不同第一晶体管组100的中心点连线的延长线。
在一些实施例中，参考图4，沿第二方向X上，位于第一晶体管组100相对两侧的两个第二晶体管组200中，一个第二晶体管组200的第二晶体管M2与另一个第二晶体管组200的第三晶体管M3在第二方向X上相互对齐。即位于第一晶体管组100相对两侧的两个第二晶体管组200中，不同第二晶体管组200中的两个第二晶体管M2呈角对角对称分布。
在一些实施例中，参考图7，存储器版图还包括：多个第一导电部111，第一导电部111位于第二晶体管组200与第一晶体管组100之间，且第一导电部111与相邻的第二晶体管M2的栅极220电连接，或者第一导电部111与相邻的第三晶体管M3的栅极230电连接。需要说明的是，图7以第一导电部111与相邻的第三晶体管M3的栅极230电连接为例进行了图示。可以理解的是，由于与第一晶体管组100相对应的两个第二晶体管组200呈对称分布，因此，位于第一晶体管M1两侧的两个第一导电部111也呈对称分布，有利于提升存储器版图布局的对称性，进而有利于提升存储器的性能。
在一些实施例中，参考图7，存储器版图还包括：与第一晶体管M1的栅极120电连接的第二导电部112，第二导电部112沿第一方向Y延伸，且部分第二导电部112至少位于第一导电部111与第一晶体管组100之间；沿第二方向X上，第一导电部111远离邻近的第二晶体管组200的一侧至邻近的第二晶体管组200的长度为第一长度L1，第二导电部112远离邻近的第一晶体管组100的一侧至邻近的第一晶体管组100的长度为第二长度L2，第一长度L1大于第二长度L2。由于第一晶体管组100和第二晶体管组200之间的空间有限，将第二导电部112设置在距离第一晶体管组100较近的位置，有利于实现将第一导电部111设置在距离第二晶体管组200较远的位置，从而减弱因第一导电部111和第二晶体管M2的栅极220过近所造成的影响，提升器件性能。并且，将第一导电部111和第二导电部112均设置在第一晶体管组100和第二晶体管组200之间，有利于提升版图的利用率。
在一些实施例中，第二导电部112的端部具有与第二导电部112相连接的弯折部114。 弯折部114增大了第二导电部112的尺寸，具有弯折部114的第二导电部112使得导电插塞可以设置在弯折部114以及第二导电部112上，相较于仅在第二导电部112上设置导电插塞，有利于增大导电插塞的尺寸，进而有利于降低导电插塞的导通电阻，提升存储器的性能。
在一些实施例中，参考图8，第二晶体管组200沿第一方向Y的两侧具有设置在衬底上的第一冗余栅极301，第一冗余栅极301用于平衡区域内的重量分布。示例性的，第一冗余栅极301的材料与第二晶体管M2的栅极220以及第三晶体管M3的栅极230的材料相同，均为多晶硅，从而平衡包含上下相邻两个第二晶体管组200在内的整个区域的多晶硅的重量分布；此外，在工艺过程中在第一方向Y的边缘位置设置第一冗余栅极301，还可以提升第二晶体管M2和第三晶体管M3的栅极位置的准确度，减弱光学邻近效应的影响。在一些实施例中，第三晶体管M3的栅极230沿第二方向X的一侧连接有第一导电部111，使第一导电部111设置在距离第二晶体管组200较远的位置，有利于避免第一导电部111距离第二晶体管M2的栅极220过近，进而有利于减小第一导电部111对第二晶体管M2的栅极220造成的影响，即减弱信号串扰。可以理解的是，冗余栅极301不连接电源信号。
在一些实施例中，参考图8，第一晶体管组100沿第一方向Y的两侧具有设置在衬底上的第二冗余栅极300，第二冗余栅极300用于平衡区域内的重量分布。示例性的，第二冗余栅极300的材料与第一晶体管M1的栅极120的材料相同，均为多晶硅，从而平衡包含上下相邻两个第一晶体管组100在内的整个区域的多晶硅的重量分布；此外，在工艺过程中在第一方向Y的边缘位置设置第二冗余栅极300，还可以提升第一晶体管M1的栅极120的位置的准确度，减弱光学邻近效应的影响。在一些实施例中，第二冗余栅极300沿第二方向X的一侧具有第二导电部112，由于第二导电部112设置在距离第一晶体管组100较近的位置，因此，为了避免第二导电部112距离第二冗余栅极300过近，沿第二方向X上，可以缩短部分第二冗余栅极300的尺寸，将沿第二方向X的一侧具有第二导电部112的部分第二冗余栅极300邻近第二导电部112的一端设置为距离第二导电部112较远的状态，如此，有利于避免第二冗余栅极300对第二导电部112造成影响。在一些实施例中，在第二方向X上，第二冗余栅极300与第二导电部112的距离等于上述第一长度，或者等于第一长度与第二长度的差值。
在一些实施例中，参考图7或图8，存储器版图还包括：第三导电部113，第三导电部113位于第二晶体管组200的远离第一晶体管组100的一侧，且第三导电部113与相邻的第二晶体管组200中未与第一导电部111相连接的栅极相连接。可以理解的是，由于与第一晶体管组100相对应的两个第二晶体管组200对称分布在第一晶体管组100的两侧，因此，位于第一晶体管M1两侧的两个第三导电部113也对称分布在第一晶体管组100的两侧，有利于提升存储器版图布局的对称性，进而有利于提升存储器的性能。
在一些实施例中，存储器版图还包括：开关控制区，开关控制区包括放大模块12，沿第二方向X上，放大模块12具有相对的第一侧和第二侧，第一侧至相邻的开关控制区边缘的长度与第二侧至相邻的开关控制区边缘的长度相同。如此，沿第二方向X上，放大模块12两侧剩余的开关控制区也呈对称分布，有利于提高存储器版图布局的对称性，进而有利于提升存储器的性能。
上述实施例提供的存储器版图中，使两个第二晶体管组对称分布在第一晶体管组的两侧，有利于提高存储器版图布局的对称性。此外，第一晶体管组中的一个第一晶体管与位于第一晶体管组一侧的第二晶体管和第三晶体管相连接，第一晶体管组中的另一个第一晶体管与位于第一晶体管组另一侧的第二晶体管和第三晶体管相连接，使得第一晶体管组与两侧的第二晶体管组之间的两条连线分别朝远离第一晶体管组的相对两侧延伸，有利于进一步提高存储器版图布局的对称性，进而有利于提升存储器的性能。
本领域的普通技术人员可以理解，上述各实施方式是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开的精神和范围。任何本领域技术人员，在不脱离本公开的精神和范围内，均可作各自变动与修改，因此本公开的保护范围应当以权利要求限定的范围为准。

Claims (10)

  1. 一种存储器电路，包括：
    放大模块(12)，所述放大模块(12)包括多个元件相同的放大单元(20)，每一所述放大单元(20)串接于对应的一组本地数据线(LIO)和互补本地数据线(LIOB)之间，以放大所述本地数据线(LIO)和所述互补本地数据线(LIOB)之间的电压差；
    每一所述放大单元(20)包括：第一晶体管(M1)、第二晶体管(M2)以及第三晶体管(M3)，其中，所述第一晶体管(M1)的源极用于接收供电电压(VCC)，所述第一晶体管(M1)的栅极用于接收读出控制信号(RdEnN)，所述第一晶体管(M1)的漏极分别与所述第二晶体管(M2)的源极以及所述第三晶体管(M3)的源极相连接，所述第二晶体管(M2)的漏极与所述本地数据线(LIO)相连接，所述第三晶体管(M3)的漏极与所述互补本地数据线(LIOB)相连接，且所述第二晶体管(M2)的漏极与所述第三晶体管(M3)的栅极相连接，所述第三晶体管(M3)的漏极与所述第二晶体管(M2)的栅极相连接。
  2. 一种存储器版图，包括：
    放大模块(12)，所述放大模块(12)包括多个元件相同的放大单元(20)，每一所述放大单元(20)串接于对应的一组本地数据线(LIO)和互补本地数据线(LIOB)之间，以放大所述本地数据线(LIO)和所述互补本地数据线(LIOB)之间的电压差；
    每一所述放大单元(20)包括：第一晶体管(M1)、第二晶体管(M2)以及第三晶体管(M3)，其中，所述第一晶体管(M1)的漏极分别与所述第二晶体管(M2)的源极以及所述第三晶体管(M3)的源极相连接；
    两个所述第一晶体管(M1)组成一个第一晶体管组(100)，多个所述第一晶体管组(100)沿第一方向(Y)排布；与所述第一晶体管(M1)相连接的所述第二晶体管(M2)和所述第三晶体管(M3)组成一个第二晶体管组(200)，所述第一晶体管组(100)沿第二方向(X)上的相对两侧均设置有一所述第二晶体管组(200)，且沿第二方向(X)上，所述第一晶体管组(100)的两个所述第一晶体管(M1)中，一个所述第一晶体管(M1)与相邻一侧的所述第二晶体管组(200)内的所述第二晶体管(M2)和所述第三晶体管(M3)相连接，另一个所述第一晶体管(M1)与相邻另一侧的所述第二晶体管组(200)内的所述第二晶体管(M2)和所述第三晶体管(M3)相连接，所述第二方向(X)垂直于所述第一方向(Y)。
  3. 根据权利要求2所述存储器版图，其中，所述第一晶体管组(100)中的两个所述第一晶 体管(M1)具有一共用的第一有源区(110)，所述第二晶体管组(200)中的一个所述第二晶体管(M2)和一个所述第三晶体管(M3)具有一共用的第二有源区(210)。
  4. 根据权利要求3所述存储器版图，其中，沿所述第二方向(X)上，位于所述第一晶体管组(100)相对两侧的两个所述第二晶体管组(200)中，一个所述第二晶体管组(200)所对应的所述第二有源区(210)与另一个所述第二晶体管组(200)所对应的所述第二有源区(210)在所述第二方向(X)上相互对齐。
  5. 根据权利要求3所述存储器版图，其中，所述第二有源区(210)包括依次间隔排布的第一漏区(I)、共源区(II)以及第二漏区(III)，其中，所述第一漏区(I)为所述第二晶体管(M2)的漏极，所述第二漏区(III)为所述第三晶体管(M3)的漏极，所述共源区(II)为所述第二晶体管(M2)和所述第三晶体管(M3)共用的源极；
    所述存储器版图还包括：多个第一走线(101)，一所述第一走线(101)用于连接所述第一晶体管(M1)的漏极和一相邻的所述共源区(II)。
  6. 根据权利要求2所述存储器版图，其中，沿所述第二方向(X)上，位于所述第一晶体管组(100)相对两侧的两个所述第二晶体管组(200)中，一个所述第二晶体管组(200)的所述第二晶体管(M2)与另一个所述第二晶体管组(200)的所述第二晶体管(M2)在所述第二方向(X)上相互对齐，一个所述第二晶体管组(200)的所述第三晶体管(M3)与另一个所述第二晶体管组(200)的所述第三晶体管(M3)在所述第二方向(X)上相互对齐。
  7. 根据权利要求2所述存储器版图，其中，还包括：多个第一导电部(111)，所述第一导电部(111)位于所述第二晶体管组(200)与所述第一晶体管组(100)之间，且所述第一导电部(111)与相邻的所述第二晶体管(M2)的栅极(220)电连接，或者所述第一导电部(111)与相邻的所述第三晶体管(M3)的栅极(230)电连接。
  8. 根据权利要求7所述存储器版图，其中，还包括：与所述第一晶体管(M1)的栅极(120)电连接的第二导电部(112)，所述第二导电部(112)沿所述第一方向(Y)延伸，且部分所述第二导电部(112)至少位于所述第一导电部(111)与所述第一晶体管组(100)之间；
    沿所述第二方向(X)上，所述第一导电部(111)远离邻近的所述第二晶体管组(200)的一侧至邻近的所述第二晶体管组(200)的长度为第一长度(L1)，所述第二导电部(112)远离邻近的所述第一晶体管组(100)的一侧至邻近的所述第一晶体管组(100)的长度为第二长度(L2)，所述第一长度(L1)大于所述第二长度(L2)。
  9. 根据权利要求7所述存储器版图，其中，还包括：第三导电部(113)，所述第三导电部(113)位于所述第二晶体管组(200)的远离所述第一晶体管组(100)的一侧，且所述第三导电部(113)与相邻的所述第二晶体管组(200)中未与所述第一导电部(111)相连接的栅极相连接。
  10. 根据权利要求2所述存储器版图，其中，所述存储器版图还包括：开关控制区，所述开关控制区包括所述放大模块(12)，沿所述第二方向(X)上，所述放大模块(12)具有相对的第一侧和第二侧，所述第一侧至相邻的所述开关控制区边缘的长度与所述第二侧至相邻的所述开关控制区边缘的长度相同。
PCT/CN2023/095112 2023-02-02 2023-05-18 存储器电路以及存储器版图 Ceased WO2024159658A1 (zh)

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CN115482843A (zh) * 2021-05-31 2022-12-16 长鑫存储技术有限公司 存储器结构和存储器版图
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