WO2024157122A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2024157122A1
WO2024157122A1 PCT/IB2024/050467 IB2024050467W WO2024157122A1 WO 2024157122 A1 WO2024157122 A1 WO 2024157122A1 IB 2024050467 W IB2024050467 W IB 2024050467W WO 2024157122 A1 WO2024157122 A1 WO 2024157122A1
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Prior art keywords
layer
insulating layer
light
conductive layer
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2024/050467
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English (en)
French (fr)
Japanese (ja)
Inventor
島行徳
神長正美
肥塚純一
松本裕功
中田昌孝
小嶋加奈子
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to CN202480006459.4A priority Critical patent/CN120476684A/zh
Priority to JP2024572519A priority patent/JPWO2024157122A1/ja
Priority to KR1020257022511A priority patent/KR20250138721A/ko
Publication of WO2024157122A1 publication Critical patent/WO2024157122A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6728—Vertical TFTs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/025—Manufacture or treatment of FETs having insulated gates [IGFET] of vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0318—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] of vertical TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6736—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes characterised by the shape of gate insulators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • One aspect of the present invention relates to a semiconductor device and a manufacturing method thereof.
  • One aspect of the present invention relates to a transistor and a manufacturing method thereof.
  • One aspect of the present invention relates to a display device including a semiconductor device.
  • one embodiment of the present invention is not limited to the above technical field.
  • Examples of technical fields of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input/output devices, driving methods thereof, and manufacturing methods thereof.
  • a semiconductor device refers to any device that can function by utilizing semiconductor characteristics.
  • High-definition display panels mainly use light-emitting elements such as organic electroluminescence (EL) elements or light-emitting diodes (LEDs).
  • EL organic electroluminescence
  • LEDs light-emitting diodes
  • Patent Document 1 discloses a high-definition display device that uses an organic EL device (also called an organic EL element).
  • An object of one embodiment of the present invention is to provide a transistor that can be miniaturized. Another object is to provide a transistor with good electrical characteristics. Another object is to provide a transistor that can pass a large current. Another object is to provide a transistor with an extremely short channel length. Another object is to provide a transistor with reduced parasitic capacitance. Another object is to provide a transistor that occupies a small area. Another object is to provide a display device that can be easily made high-definition. Another object is to provide a highly reliable transistor, semiconductor device, and display device.
  • An object of one embodiment of the present invention is to provide a semiconductor device, a display device, a memory device, or an electronic device having a novel structure.
  • An object of one embodiment of the present invention is to alleviate at least one of the problems of the prior art.
  • One aspect of the present invention is a semiconductor device having a transistor and a first insulating layer.
  • the transistor has a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a second insulating layer.
  • the first insulating layer is located on the first conductive layer and has a first opening.
  • the second conductive layer is located on the first insulating layer.
  • the semiconductor layer has a portion in contact with the first conductive layer, a portion in contact with the second conductive layer, and a portion in contact with a side surface of the first insulating layer inside the first opening.
  • the second insulating layer covers the semiconductor layer in the first opening.
  • the third conductive layer covers the second insulating layer in the first opening.
  • the semiconductor device also has a portion where the first conductive layer and the third conductive layer do not overlap each other and where the first conductive layer and the semiconductor layer do not overlap each other in a region overlapping the first opening.
  • Another aspect of the present invention is a semiconductor device having a transistor, a base insulating layer, and a first insulating layer.
  • the transistor has a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a second insulating layer.
  • the first insulating layer is located on the first conductive layer and has a first opening.
  • the first conductive layer is located on the base insulating layer and has a second opening.
  • the second opening is located inside the first opening in a planar view.
  • the second conductive layer is located on the first insulating layer.
  • the semiconductor layer has a portion in contact with the first conductive layer, a portion in contact with the second conductive layer, and a portion in contact with a side surface of the first insulating layer inside the first opening, and has a third opening located inside the first opening in a planar view.
  • the second insulating layer has a portion covering the semiconductor layer in the first opening and a portion in contact with the base insulating layer at a position overlapping the second opening and the third opening.
  • the third conductive layer covers the second insulating layer within the first opening.
  • the second opening is smaller than the third opening and is located inside the third opening in a plan view. Furthermore, it is preferable that the second insulating layer contacts the upper surface of the first conductive layer and the side surface of the first conductive layer at the second opening.
  • the third opening is smaller than the second opening and is located inside the second opening in a plan view. Furthermore, it is preferable that the semiconductor layer contacts the top surface of the first conductive layer, the side surface of the first conductive layer in the second opening, and the underlying insulating layer.
  • One aspect of the present invention is a semiconductor device having a transistor and a first insulating layer.
  • the transistor has a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a second insulating layer.
  • the first insulating layer is located on the first conductive layer and has a first opening.
  • the second conductive layer is located on the first insulating layer.
  • the semiconductor layer has a portion in contact with the first conductive layer, a portion in contact with the second conductive layer, and a portion in contact with a side surface of the first insulating layer inside the first opening.
  • the second insulating layer covers the semiconductor layer in the first opening.
  • the third conductive layer covers the second insulating layer in the first opening, and has a second opening located inside the first opening in a plan view.
  • the third conductive layer has a portion that overlaps with the second conductive layer via the third insulating layer.
  • the fourth conductive layer is electrically connected to the third conductive layer and has a function as wiring.
  • the angle between the side surface of the first insulating layer at the first opening and the bottom surface of the first insulating layer is 75 degrees or more and 90 degrees or less.
  • the semiconductor layer contains a metal oxide
  • the first insulating layer is a first insulating film, a second insulating film, and a third insulating film stacked in this order
  • the first insulating film and the third insulating film contain a nitride
  • the second insulating film contains an oxide.
  • the first insulating film and the third insulating film contain silicon nitride
  • the second insulating film contains silicon oxide.
  • a transistor that can be miniaturized can be provided. Or a transistor with good electrical characteristics can be provided. Or a transistor that can pass a large current can be provided. Or a transistor with an extremely short channel length can be provided. Or a transistor with reduced parasitic capacitance can be provided. Or a transistor that occupies a small area can be provided. Or a display device that can be easily made high-definition can be provided. Or a highly reliable transistor, semiconductor device, and display device can be provided.
  • the present invention it is possible to provide a semiconductor device, a display device, a memory device, or an electronic device having a novel configuration. According to one aspect of the present invention, it is possible to at least alleviate at least one of the problems of the prior art.
  • 1A and 1B show an example of the configuration of a semiconductor device.
  • 2A to 2C show examples of the configuration of a semiconductor device.
  • 3A and 3B show examples of the configuration of a semiconductor device.
  • 4A and 4B show examples of the configuration of a semiconductor device.
  • 5A to 5C show examples of the configuration of a semiconductor device.
  • FIG. 6 shows an example of the configuration of a semiconductor device.
  • 7A to 7C show examples of the configuration of a semiconductor device.
  • 8A to 8D are diagrams illustrating a method for manufacturing a semiconductor device.
  • 9A and 9B show examples of the configuration of a semiconductor device.
  • 10A to 10C show examples of the configuration of a semiconductor device.
  • 11A and 11B show configuration examples of a semiconductor device.
  • FIG. 12 shows an example of the configuration of a semiconductor device.
  • 13A to 13C show examples of the configuration of a semiconductor device.
  • 14A and 14B show configuration examples of a semiconductor device.
  • FIG. 15 shows an example of the configuration of a display device.
  • FIG. 16 shows an example of the configuration of a display device.
  • FIG. 17 shows an example of the configuration of a display device.
  • FIG. 18 shows an example of the configuration of a display device.
  • FIG. 19 shows an example of the configuration of a display device.
  • 20A to 20F are diagrams illustrating a method for manufacturing a display device.
  • 21A to 21D show configuration examples of electronic devices.
  • 22A to 22F show configuration examples of electronic devices.
  • 23A to 23G show configuration examples of electronic devices.
  • a transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage, and switching operations that control conduction or non-conduction.
  • transistor includes IGFETs (Insulated Gate Field Effect Transistors) and thin film transistors (TFTs).
  • source and drain may be interchangeable when transistors of different polarity are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms “source” and “drain” can be used interchangeably.
  • the top surface shape of a certain component refers to the contour shape of the component when viewed from a planar view.
  • a planar view refers to a view from the normal direction of the surface on which the component is formed, or the surface of the support (e.g., substrate) on which the component is formed.
  • the top surface shapes roughly match means that at least a portion of the contours of the stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where a portion of the mask pattern is the same. However, strictly speaking, there are also cases where the contours do not overlap, and the upper layer is located inside the lower layer, or outside the lower layer, and in these cases, it may also be said that "the top surface shapes roughly match.”
  • film and “layer” are interchangeable.
  • insulating layer may be interchangeable with the term “insulating film.”
  • a display panel which is one aspect of a display device, has the function of displaying (outputting) images, etc. on a display surface. Therefore, a display panel is one aspect of an output device.
  • a display panel having a connector such as an FPC (Flexible Printed Circuit) or TCP (Tape Carrier Package) attached to the substrate, or an IC mounted on the substrate using a method such as COG (Chip On Glass), may be referred to as a display panel module, display module, or simply a display panel.
  • a touch panel which is one aspect of a display device, has a function of displaying images, etc. on a display surface, and a function as a touch sensor that detects when a detectable object, such as a finger or stylus, touches, presses, or approaches the display surface. Therefore, a touch panel is one aspect of an input/output device.
  • a touch panel can also be called, for example, a display panel (or display device) with a touch sensor or a display panel (or display device) with a touch sensor function.
  • a touch panel can also have a configuration that includes a display panel and a touch sensor panel. Alternatively, the touch panel can have a touch sensor function inside or on the surface of the display panel.
  • a touch panel substrate on which a connector or IC is mounted may be referred to as a touch panel module, display module, or simply a touch panel.
  • a transistor according to one embodiment of the present invention has a semiconductor layer, a gate insulating layer, a gate electrode, a first electrode, and a second electrode.
  • the first electrode functions as one of a source electrode and a drain electrode, and the second electrode functions as the other.
  • the second electrode is provided above the first electrode.
  • An insulating layer that functions as a spacer is provided between the first electrode and the second electrode.
  • the spacer has an opening that reaches the first electrode, and the semiconductor layer is provided in contact with the first electrode, the second electrode, and the sidewall (also called the side surface) within the opening of the insulating layer.
  • a gate insulating layer and a gate electrode are provided to cover the semiconductor layer.
  • the source electrode and the drain electrode are located at different heights, so the current flowing through the semiconductor layer flows in the height direction.
  • the channel length direction has a height (vertical) component
  • the transistor of one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, etc. Since the transistor can have two or more of the source electrode, semiconductor layer, and drain electrode stacked, it can occupy a significantly smaller area than a so-called planar type transistor (which can also be called a lateral transistor, LFET (Lateral FET), etc.) in which the semiconductor layer is arranged on a flat surface.
  • planar type transistor which can also be called a lateral transistor, LFET (Lateral FET), etc.
  • the area occupied by the transistors can be reduced compared to display devices that use conventional horizontal transistors, making it possible to reduce the size of pixels, increase the functionality of pixels, and improve the aperture ratio. This makes it possible to realize display devices with higher resolution, higher reliability, and lower power consumption than conventional devices.
  • the capacitance between the source electrode and the gate electrode or between the drain electrode and the gate electrode is small because this allows the transistor to perform switching at a high speed. Therefore, we focused on the capacitance between the gate electrode and the first electrode at the bottom of the opening in the insulating layer that functions as a spacer.
  • One aspect of the present invention is a configuration in which a region where the gate electrode and the first electrode do not overlap is provided at the bottom of the opening in the insulating layer.
  • capacitance may be formed not only between the first electrode and the gate electrode, but also between the semiconductor layer and the gate electrode. For this reason, a region where the gate electrode and the semiconductor layer do not overlap is provided at the bottom of the opening in the insulating layer.
  • the first electrode has a second opening located inside an opening (first opening) in the insulating layer that functions as a spacer in a plan view.
  • the semiconductor layer has a third opening located inside the first opening in a plan view.
  • the second opening and the third opening have a mutually overlapping portion.
  • the portion of the first opening where the second opening and the third opening overlap is a portion where the gate electrode does not overlap with either the first electrode or the semiconductor layer. Therefore, the capacitance between the gate electrode and the first electrode can be reduced compared to a case where the second opening and the third opening are not provided.
  • FIG. 1A and 1B are schematic perspective views of a transistor 10.
  • arrows X, Y, and Z are used to indicate directions.
  • Fig. 1A is a perspective view including a cross section of the transistor 10 cut along the X-Z plane
  • Fig. 1B is a perspective view including a cross section of the transistor 10 cut along the Y-Z plane.
  • FIG. 2A shows a plan view of transistor 10
  • FIGS. 2B and 2C show schematic cross-sectional views corresponding to the cut lines A1-A2 and B1-B2 in FIG. 2A, respectively. Note that some components (such as insulating layers) are omitted in FIG. 2A.
  • the transistor 10 is provided on an insulating layer 11 provided on a substrate (not shown).
  • the insulating layer 11 functions as a base insulating layer.
  • the transistor 10 has a semiconductor layer 21, an insulating layer 22 partly functioning as a gate insulating layer, a conductive layer 23 partly functioning as a gate electrode, a conductive layer 24 partly functioning as one of a source electrode and a drain electrode, and a conductive layer 25 partly functioning as the other.
  • a conductive layer 24 is provided on the insulating layer 11, and an insulating layer 41 is provided on the conductive layer 24.
  • a conductive layer 25 is provided on the insulating layer 41.
  • the insulating layer 41 has an opening 20a that reaches the conductive layer 24.
  • the conductive layer 24 has an opening 20b. The opening 20b is located inside the opening 20a in a plan view.
  • the semiconductor layer 21 has a portion in contact with the top surface of the conductive layer 25, a portion in contact with the side surface of the conductive layer 25, a portion in contact with the side surface (also called the inner wall or side wall) of the insulating layer 41 in the opening 20a, and a portion in contact with the top surface of the conductive layer 24.
  • the semiconductor layer 21 has an opening 20c.
  • the opening 20c is located inside the opening 20a in a plan view. Here, the case is shown where the top surface shapes of the openings 20b and 20c are roughly the same.
  • the insulating layer 22 is provided to cover the insulating layer 41, the conductive layer 25, the semiconductor layer 21, the conductive layer 24, and the insulating layer 11.
  • the part of the insulating layer 22 located inside the opening 20a is provided along the top surface of the semiconductor layer 21.
  • the parts of the insulating layer 22 located inside the openings 20c and 20b contact the side surface (also called the inner wall or side wall) of the conductive layer 24 and the top surface of the insulating layer 11.
  • the conductive layer 23 is provided to cover the insulating layer 22. At this time, since the conductive layer 24 and the semiconductor layer 21 have openings 20b and 20c located inside the opening 20a, respectively, it is possible to provide a portion inside the opening 20a where the conductive layer 23 does not overlap with either the conductive layer 24 or the semiconductor layer 21. This makes it possible to reduce the capacitance (also called parasitic capacitance) between the conductive layer 23 and the conductive layer 24.
  • the channel length of the transistor 10 can be precisely controlled by the thickness of the insulating layer 41, so that the variation in the channel length can be made extremely small compared to planar type transistors. Furthermore, by making the insulating layer 41 thinner, a transistor with an extremely short channel length can be manufactured. For example, a transistor with a channel length of 2 ⁇ m or less, 1 ⁇ m or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less, and 5 nm or more, 7 nm or more, or 10 nm or more can be manufactured.
  • a transistor with an extremely short channel length that could not be realized with conventional exposure equipment for mass production of flat panel displays (for example, a minimum line width of about 2 ⁇ m or 1.5 ⁇ m) can be realized.
  • a transistor with a channel length of less than 10 nm can be realized without using an extremely expensive exposure equipment used in cutting-edge LSI technology.
  • Various semiconductor materials can be used for the semiconductor layer 21, but it is particularly preferable to use an oxide semiconductor containing a metal oxide.
  • an oxide semiconductor formed under appropriate conditions a transistor that combines a high on-current and an extremely low off-current can be realized at low cost.
  • the conductive layers 24 and 25 are each configured so that the semiconductor layer 21 is in contact with the upper surface. Therefore, if an oxide semiconductor is used for the semiconductor layer 21, the exposed surfaces of the conductive layers 24 and 25 may be oxidized due to the heat applied during or after the film formation process of the semiconductor film that becomes the semiconductor layer 21, forming an insulating oxide film between the conductive layers 24 and 25 and increasing the contact resistance. Therefore, it is preferable to use an oxide conductor containing a conductive oxide for at least the uppermost part of the conductive layers 24 and 25. This makes it possible to prevent an increase in contact resistance due to oxidation of the surfaces of the conductive layers 24 and 25.
  • the conductive layers 24 and 25 may also be called oxide layers, metal oxide layers, or oxide conductor layers.
  • a part of the conductive layer 24 can be used as one of the source wiring and the drain wiring.
  • a part of the conductive layer 25 can be used as the other of the source wiring and the drain wiring.
  • the electrical resistance is low.
  • one or both of the conductive layers 24 and 25 have a stacked structure including a layer of the highly conductive material, and that the above-mentioned oxide conductor is used at least in the uppermost portion.
  • the transistor 10 is provided at the intersection of the conductive layer 23 that functions as a gate wiring and the conductive layer 24 that functions as a source wiring or drain wiring.
  • the conductive layer 23 has a portion at the bottom of the opening 20a that does not overlap with either the conductive layer 24 or the semiconductor layer 21, and therefore the parasitic capacitance is significantly reduced compared to a case where such a portion is not provided (for example, when neither the opening 20b nor the opening 20c is provided). Since the parasitic capacitance between the gate wiring and the source wiring or the drain wiring is small, for example, when applied to a display device, the frame frequency can be increased and the resolution can be improved.
  • the insulating layer 41 functions as an interlayer insulating layer (spacer) that insulates the conductive layer 24 from the conductive layer 25.
  • a laminated film of insulating layer 41a, insulating layer 41b, and insulating layer 41c is used as the insulating layer 41.
  • the semiconductor layer 21 is provided in contact with the inner wall of the opening 20a of the insulating layer 41b. It is preferable to use an oxide insulating film for the insulating layer 41b. In particular, it is preferable to use an oxide insulating film that releases oxygen when heated. It is also preferable to have a structure in which the insulating layer 41b is sandwiched between insulating layers 41a and 41c that have barrier properties against oxygen. This makes it possible to confine the oxygen contained in the insulating layer 41b to the area surrounded by the insulating layer 41a, the insulating layer 41c, and the semiconductor layer 21, and prevents the oxygen in the insulating layer 41b from being released and reduced during the process, so that oxygen can be supplied to the semiconductor layer 21 more efficiently.
  • the portion of the semiconductor layer 21 that contacts the insulating layer 41b is a region in which oxygen vacancies are reduced, and can be considered an i-type region.
  • the portion that does not contact the insulating layer 41b is an n-type region that contains a large number of carriers.
  • the portion of the semiconductor layer 21 that contacts the insulating layer 41b can be called the channel formation region, and the region outside of that can be called the low resistance region (also called the source region or drain region).
  • Figure 3A shows a schematic cross-sectional view similar to Figure 2B.
  • the channel length L of the transistor 10 can be said to be the length of the portion of the semiconductor layer 21 that is in contact with the insulating layer 41 on the path that connects the portion of the semiconductor layer 21 that is in contact with the conductive layer 24 and the portion of the semiconductor layer 21 that is in contact with the conductive layer 25, as shown in FIG. 3A.
  • the angle ( ⁇ ) of the sidewall of the opening 20a in the insulating layer 41 is 90 degrees
  • the channel length L is equal to the thickness of the insulating layer 41.
  • ⁇ By making ⁇ smaller (or larger) than 90 degrees, the channel length L can be made larger than the thickness of the insulating layer 41.
  • the channel region of the semiconductor layer 21 is herein defined as the portion in contact with the insulating layer 41, it may be replaced by the portion in contact with the insulating layer 41b.
  • the diameter of opening 20a is R1
  • the diameter of opening 20b is R2
  • the diameter of opening 20c is R3.
  • the diameter of the opening in each layer can be the diameter at the bottom end of the layer.
  • the diameter R3 of opening 20c is larger than the diameter R2 of opening 20b.
  • the diameter of the opening in a certain layer is not limited to the diameter at the bottom end of the layer, and the diameter at the top end or center of the layer may be used, or it may be the average value or median value.
  • openings 20b and 20c are located inside opening 20a, their diameters R2 and R3 are smaller than the diameter R1 of opening 20a.
  • the diameters R2 and R3 of openings 20b and 20c are each independently 50% or more of the diameter R1 of opening 20a, preferably 60% or more, more preferably 70% or more, even more preferably 80% or more, and even more preferably 90% or more, and less than 100%.
  • the channel width W of the transistor 10 depends on the shape of the opening 20a.
  • FIG. 3B is a plan view of the cut surface taken along the cutting line C1-C2 in FIG. 3A at the height where the insulating layer 41b is provided, as viewed from the Z direction.
  • the contour of the opening 20a is a circle with a diameter R
  • the angle ⁇ of the sidewall of the opening 20a in the insulating layer 41b deviates from 90 degrees, the circumference of the opening 20a differs depending on the height.
  • the circumference at the height where the diameter of the opening 20a is smallest (here, the lower end) can be regarded as the channel width W.
  • the circumference at the height of the upper end of the opening 20a may also be regarded as the channel width W.
  • the shape of the opening 20a in a plan view can typically be a circle.
  • the shape of the opening 20a is not limited to a circle and can be a variety of shapes.
  • it can be an ellipse, a rectangle with rounded corners, etc.
  • It can also be a regular polygon such as an equilateral triangle, square, or regular pentagon, or a polygon other than a regular polygon.
  • the channel width can be increased by making it a concave polygon, such as a star-shaped polygon, which is a polygon with at least one interior angle exceeding 180 degrees.
  • Other shapes that can be used include an ellipse, a polygon with rounded corners, and a closed curve that combines straight lines and curves.
  • openings 20b and 20c may be of any shape as long as they are positioned inside opening 20a. However, if openings 20b and 20c have a shape similar to or close to the shape of opening 20a, the difference in area between opening 20a and opening 20b or opening 20c can be reduced, and as a result, the area of opening 20a itself can be reduced, which is preferable.
  • the semiconductor layer 21 and the insulating layer 22 are formed along the inner wall of the opening 20a of the insulating layer 41b, so depending on the film formation method, the thickness of this portion may be thin.
  • films formed on surfaces inclined or perpendicular to the substrate surface tend to be thinner than films formed on surfaces parallel to the substrate surface.
  • film formation methods such as atomic layer deposition (ALD) or thermal CVD can form a film of uniform thickness regardless of the angle of the surface on which it is formed.
  • the angle ⁇ of the sidewall of the opening 20a of the insulating layer 41b is 75 degrees or more, 80 degrees or more, or 85 degrees or more, it is preferable to form the semiconductor layer 21 and the insulating layer 22 using the ALD method.
  • an insulating substrate for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria stabilized zirconia substrate), a resin substrate, etc.
  • a semiconductor substrate for example, a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or gallium nitride, etc. are available.
  • a semiconductor substrate having an insulating region inside the aforementioned semiconductor substrate for example, an SOI (Silicon On Insulator) substrate, etc. are available.
  • the conductive substrate there is a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc. are available.
  • a substrate having a metal nitride, a substrate having a metal oxide, etc. can be used.
  • a substrate in which a conductive layer or a semiconductor layer is provided on an insulating substrate a substrate in which a conductive layer or an insulating layer is provided on a semiconductor substrate, and a substrate in which a semiconductor layer or an insulating layer is provided on a conductive substrate, etc. are available.
  • a substrate provided with elements may be used.
  • the elements provided on the substrate include a capacitor element, a resistor element, a switch element (including a transistor), a light-emitting element, a memory element, and the like.
  • the semiconductor layer 21 preferably includes a metal oxide (oxide semiconductor).
  • metal oxides that can be used in the semiconductor layer 21 include In oxide, Ga oxide, and Zn oxide.
  • the metal oxide preferably contains at least In or Zn.
  • the metal oxide preferably contains two or three elements selected from In, element M, and Zn.
  • the element M is a metal element or semimetal element with a high bond energy with oxygen, for example, a metal element or semimetal element with a bond energy with oxygen higher than that of indium.
  • element M include Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb.
  • the element M contained in the metal oxide is preferably one or more of the above elements, and is preferably one or more of Al, Ga, Y, and Sn, and more preferably Ga.
  • a metal oxide having In, M, and Zn may be referred to as an In-M-Zn oxide.
  • metal elements and metalloid elements may be collectively referred to as "metal elements", and "metalloid elements" described in this specification may include metalloid elements.
  • the metal oxide is an In-M-Zn oxide
  • the atomic ratio of In in the In-M-Zn oxide is equal to or greater than the atomic ratio of M.
  • the term "close composition" includes a range of ⁇ 30% of the desired atomic ratio.
  • the atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of M.
  • the semiconductor layer 21 may be made of, for example, In oxide, In-Zn oxide, In-Ga oxide, In-Sn oxide, In-Ti oxide, In-Ga-Al oxide, In-Ga-Sn oxide, In-Ga-Zn oxide, In-Sn-Zn oxide, In-Al-Zn oxide, In-Ti-Zn oxide, In-Ga-Sn-Zn oxide, In-Ga-Al-Zn oxide, etc.
  • Ga-Zn oxide may also be used.
  • a material that does not contain Zn, such as indium oxide, is preferred because it increases the affinity with the LSI manufacturing process.
  • a material that contains Zn is preferred because it is easy to increase the crystallinity.
  • the metal oxide may contain one or more metal elements with a large periodic number.
  • the field effect mobility of the transistor may be increased.
  • metal elements with a large periodic number include metal elements belonging to the fifth period and metal elements belonging to the sixth period. Specific examples of such metal elements include Y, Zr, Ag, Cd, Sn, Sb, Ba, Pb, Bi, La, Ce, Pr, Nd, Pm, Sm, and Eu. La, Ce, Pr, Nd, Pm, Sm, and Eu are called light rare earth elements.
  • the metal oxide may also contain one or more nonmetallic elements.
  • the field effect mobility of the transistor may be increased.
  • nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.
  • the metal oxide can be formed preferably by sputtering or atomic layer deposition (ALD). In particular, it is preferable to form the metal oxide film by ALD, which has excellent coating properties.
  • ALD atomic layer deposition
  • the composition of the metal oxide film may differ from the composition of the target. In particular, the zinc content in the metal oxide film may decrease to about 50% compared to the target.
  • the content of a certain metal element in a metal oxide refers to the ratio of the number of atoms of that element to the total number of atoms of the metal element contained in the metal oxide.
  • the content of metal element X can be expressed as Ax /( Ax + Ay + Az ).
  • metal element X when the ratio of the numbers of atoms of metal element X, metal element Y, and metal element Z in the metal oxide (atomic ratio) is expressed as Bx :By: Bz , the content of metal element X can be expressed as Bx /( Bx + By + Bz ).
  • a transistor with high reliability when a positive bias is applied can be obtained.
  • a transistor with a small amount of variation in threshold voltage in a PBTS (Positive Bias Temperature Stress) test can be obtained.
  • the Ga content it is possible to produce a transistor with high reliability against light.
  • NBTIS Near Bias Temperature Illumination Stress
  • a metal oxide in which the atomic ratio of Ga is equal to or greater than the atomic ratio of In has a larger band gap, and it is possible to reduce the amount of variation in threshold voltage in NBTIS testing of a transistor.
  • the metal oxide becomes highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed. This suppresses fluctuations in the electrical characteristics of the transistor, and increases reliability.
  • the semiconductor layer 21 may have a laminated structure having two or more metal oxide layers.
  • the two or more metal oxide layers of the semiconductor layer 21 may have the same or approximately the same composition.
  • the same sputtering target can be used to form the semiconductor layer, thereby reducing manufacturing costs.
  • a laminated structure in which two or more oxide semiconductor layers with different compositions are laminated may also be used.
  • the ALD method it is also possible to form a metal oxide layer whose composition continuously varies in the thickness direction. This not only widens the range of design options compared to the case where a film with a fixed composition is used, but also prevents the generation of interface states between two layers with different compositions, thereby improving electrical characteristics and reliability.
  • the semiconductor layer 21 has a two-layer structure
  • a material with higher mobility (high conductivity) for the second layer i.e., the side closer to the gate electrode, than for the first layer.
  • This makes it possible to create a normally-off transistor with a large on-current.
  • a material with higher mobility than for the second layer may be used for the first layer, i.e., the side in contact with the source electrode and drain electrode. This makes it possible to reduce the contact resistance between the semiconductor layer 21 and the source electrode or drain electrode, thereby reducing parasitic resistance and making it possible to create a transistor with a large on-current.
  • the semiconductor layer 21 has a three-layer structure, it is preferable to use a material for the second layer that has a higher mobility than the first and third layers. This makes it possible to realize a transistor with a high on-current and high reliability.
  • the difference in the mobility and conductivity described above can be expressed, for example, by the content of indium.
  • an element other than indium that contributes to improving conductivity also affects the mobility and conductivity.
  • the semiconductor layer 21 is preferably a crystalline metal oxide layer.
  • a metal oxide layer having a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, a nano-crystalline (nc: nano-crystal) structure, or the like can be used.
  • CAAC c-axis aligned crystal
  • nc nano-crystalline
  • the defect level density in the semiconductor layer 21 can be reduced, and a highly reliable semiconductor device can be realized.
  • OS transistors have extremely high field-effect mobility compared to transistors using amorphous silicon.
  • OS transistors have an extremely small source-drain leakage current in an off state (hereinafter also referred to as off-current), and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time.
  • off-current extremely small source-drain leakage current in an off state
  • the use of OS transistors can reduce the power consumption of a semiconductor device.
  • the semiconductor device can be applied to, for example, a display device.
  • a display device In order to increase the light emission luminance of a light-emitting device included in a pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Since an OS transistor has a higher withstand voltage between the source and drain than a transistor using silicon (hereinafter, referred to as a Si transistor), a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor included in the pixel circuit, it is possible to increase the amount of current flowing through the light-emitting device and increase the light emission luminance of the light-emitting device.
  • an OS transistor When the transistor operates in the saturation region, an OS transistor can reduce the change in source-drain current in response to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the amount of current flowing through the light-emitting device can be precisely controlled. This makes it possible to increase the gradation in the pixel circuit. Furthermore, even if the electrical characteristics (e.g., resistance) of the light-emitting device fluctuate or there is variation in the electrical characteristics, a stable current can flow.
  • the electrical characteristics e.g., resistance
  • OS transistors have small variations in electrical characteristics due to radiation exposure, i.e., they have high resistance to radiation, and therefore can be suitably used in environments where radiation may be present. It can also be said that OS transistors have high reliability against radiation.
  • OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors.
  • OS transistors can also be suitably used in semiconductor devices used in outer space.
  • radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).
  • the semiconductor material that can be used for the semiconductor layer 21 is not limited to oxide semiconductors.
  • a semiconductor made of a single element or a compound semiconductor can be used.
  • semiconductors made of a single element include silicon (including single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon) and germanium.
  • compound semiconductors include gallium arsenide and silicon germanium.
  • compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors. These semiconductor materials may contain impurities as dopants.
  • the semiconductor layer 21 may have a layered material that functions as a semiconductor.
  • a layered material is a general term for a group of materials that have a layered crystal structure.
  • a layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds.
  • a layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity.
  • Examples of the layered material include graphene, silicene, and chalcogenides.
  • Chalcogenides are compounds containing chalcogen (an element belonging to Group 16).
  • Examples of the chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.
  • transition metal chalcogenides that can be used as the semiconductor layer of a transistor include molybdenum sulfide (representatively MoS 2 ), molybdenum selenide (representatively MoSe 2 ), molybdenum tellurium (representatively MoTe 2 ), tungsten sulfide (representatively WS 2 ), tungsten selenide (representatively WSe 2 ), tungsten tellurium (representatively WTe 2 ), hafnium sulfide (representatively HfS 2 ), hafnium selenide (representatively HfSe 2 ), zirconium sulfide (representatively ZrS 2 ), zirconium selenide (representatively ZrSe 2 ), and the like.
  • the crystallinity of the semiconductor material used for the semiconductor layer 21 is not particularly limited, and any of an amorphous semiconductor, a single crystalline semiconductor, and a semiconductor having crystallinity other than single crystal (a polycrystalline semiconductor, a microcrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used.
  • the use of a crystalline semiconductor is preferable because it can suppress deterioration of the transistor characteristics.
  • the insulating layer 22 functions as a gate insulating layer of a transistor and can also be used as a dielectric layer of a capacitance element.
  • an oxide semiconductor is used for the semiconductor layer 21, it is preferable to use an oxide insulating film for at least the film of the insulating layer 22 that is in contact with the semiconductor layer 21.
  • silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga-Zn oxide can be used.
  • a nitride insulating film such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide can also be used as the insulating layer 22.
  • the insulating layer 22 may have a stacked structure, and may be a stacked structure having, for example, one or more oxide insulating films and one or more nitride insulating films.
  • oxynitride refers to a material that contains more oxygen than nitrogen.
  • Nitrogen oxide refers to a material that contains more nitrogen than oxygen.
  • the insulating layer 22 is preferably made of a high-k insulating material, and preferably has a laminated structure of a high dielectric constant (high-k) material and a material with a higher dielectric strength than the high-k material.
  • the insulating layer 22 can be made of an insulating film (also called ZAZ) in which zirconium oxide, aluminum oxide, and zirconium oxide are laminated in this order.
  • an insulating film also called ZAZA in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are laminated in this order can be used.
  • an insulating film in which hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide are laminated in this order can be used.
  • an insulating film with a relatively high dielectric strength, such as aluminum oxide, in a laminated state the dielectric strength is improved and electrostatic breakdown of the capacitance element can be suppressed.
  • a material exhibiting ferroelectricity may be used as the insulating layer 22.
  • materials exhibiting ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and HfZrO x (x is a real number greater than 0).
  • the conductive layer 24 and the conductive layer 25 are in contact with the semiconductor layer 21.
  • an oxide semiconductor is used as the semiconductor layer 21
  • a metal that is easily oxidized such as aluminum
  • an insulating oxide e.g., aluminum oxide
  • conductive layer 24 and conductive layer 25 it is preferable to use, for example, titanium, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. These are preferable because they are conductive materials that are difficult to oxidize, or materials that maintain their conductivity even when oxidized.
  • conductive oxides such as indium oxide, zinc oxide, In-Sn oxide, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide, and Ga-Zn oxide can be used.
  • Conductive oxides containing indium are particularly preferred because of their high conductivity.
  • oxide materials such as In-Ga-Zn oxide that can be applied to the semiconductor layer 21 can also be used as a conductive layer by increasing the carrier concentration.
  • the conductive layers 24 and 25 may be a single-layer structure of the conductive oxide film, a three-layer structure in which a titanium nitride film, a tungsten film, and a titanium nitride film are laminated in this order, a two-layer structure in which a ruthenium film or a ruthenium oxide film is laminated on tungsten, a two-layer structure in which a ruthenium film or a ruthenium oxide film is laminated on the conductive oxide film, or a two-layer structure in which the conductive oxide film is laminated on a ruthenium film or a ruthenium oxide film.
  • ruthenium is a material that is difficult to etch, so when used, the thinner the better, and it is preferable to use a thickness of, for example, 0.1 nm to 2 nm.
  • the conductive layer 23 functions as a gate electrode, and various conductive materials can be used.
  • a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the metal element. It is also possible to use a nitride of the above metal or alloy, or an oxide of the above metal or alloy.
  • tantalum nitride titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc.
  • a semiconductor with high electrical conductivity such as polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide.
  • nitrides and oxides that can be used for the conductive layers 24 and 25 may be applied to the conductive layer 23.
  • conductive layers 23, 24, and 25 also function as wiring, it is preferable to use a low-resistance conductive material in a laminated state.
  • the low-resistance conductive material that can be used for conductive layer 23 described above can also be used for the lower layer of conductive layer 24 and conductive layer 25.
  • the insulating layer 41b can be used as an interlayer insulating film.
  • a deposition method such as a sputtering method or a plasma CVD method.
  • a film with an extremely low hydrogen content can be obtained. Therefore, the supply of hydrogen to the semiconductor layer 21 can be suppressed, and the electrical characteristics of the transistor 10 can be stabilized.
  • the insulating layer 41b is in contact with the channel formation region of the semiconductor layer 21, it is preferable to use an oxide insulating film. In particular, it is preferable to use an oxide insulating film that releases oxygen when heated.
  • the oxide insulating film that can be used for the gate insulating layer can be used as the insulating layer 41b.
  • the insulating layer 41b functions as an interlayer insulating layer, it is preferable to use a film formation method that allows film formation at a high film formation rate compared to other insulating layers.
  • a TEOS Tetra-Ethyl-Ortho-Silicate, chemical formula: Si( OC2H5 ) 4
  • plasma CVD may be used as the insulating layer 41. This can improve productivity.
  • the insulating layers 41a and 41c are preferably made of a film through which hydrogen does not easily diffuse. By sandwiching the insulating layer 41b between the insulating layers 41a and 41c through which hydrogen does not easily diffuse, it is possible to prevent hydrogen from entering the insulating layer 41b that contacts the semiconductor layer 21 from the outside.
  • silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used as the insulating layer 41a and the insulating layer 41c.
  • silicon nitride and silicon nitride oxide have the characteristics of releasing little impurities (e.g., water and hydrogen) from themselves and being difficult for oxygen and hydrogen to permeate, and therefore can be suitably used as the insulating layer 41a and the insulating layer 41c.
  • the insulating layer 11 functions as an interlayer insulating layer.
  • an insulating material that can be used for the insulating layer 41b or an insulating material that can be used for the insulating layer 41a and the insulating layer 41c can be appropriately used.
  • ⁇ Variation 1> 4A is a schematic cross-sectional view of a transistor 10a exemplified below.
  • the transistor 10a differs from the transistor 10 described above mainly in that the shape of the semiconductor layer 21 is different.
  • the ends of the semiconductor layer 21 and the conductive layer 25 roughly coincide.
  • the conductive layer 25 and the semiconductor layer 21 can be processed in the same process, simplifying the process.
  • the conductive layer 25 is covered by the semiconductor layer 21, it is possible to prevent the conductive layer 25 from being damaged and its conductivity from decreasing during processes such as the etching process of the semiconductor layer 21 and the film formation process of the insulating layer 22.
  • a transistor 10b shown in FIG. 4B differs from the transistor 10 described above mainly in that the configurations of the conductive layer 24 and the semiconductor layer 21 are different.
  • the end of conductive layer 24 has a portion that protrudes further than the end of semiconductor layer 21.
  • the upper surface of conductive layer 24 has a portion that contacts semiconductor layer 21 and a portion that contacts insulating layer 22.
  • diameter R2 of opening 20b is smaller than diameter R3 of opening 20c.
  • the transistor 10c shown in FIG. 5A differs from the transistor 10 described above mainly in that the shape of the conductive layer 24 is different.
  • the conductive layer 24 is thinner at the portion that overlaps the opening 20a than at the portion that overlaps the insulating layer 41. For example, this shape may result if part of the conductive layer 24 is etched and thinned when the opening 20a is formed.
  • the transistor 10d shown in FIG. 5B is an example in which the conductive layer 24 is also etched when the opening 20a is formed. At this time, the semiconductor layer 21 is in contact with the side surface of the conductive layer 24.
  • the step in the opening 20a is reduced, and the occurrence of poor coverage of the insulating layer 22 can be more effectively suppressed.
  • a transistor 10e shown in FIG. 5C is an example in which the semiconductor layer 21 is provided to cover the end portion of the conductive layer 24 within the opening 20a.
  • opening 20c is located inside opening 20b in a plan view. Therefore, diameter R3 of opening 20c is smaller than diameter R2 of opening 20b.
  • This configuration also reduces the step in the opening 20a, making it possible to more effectively prevent poor coverage of the insulating layer 22.
  • FIG. 6 shows a cross section of a transistor 15, which can be formed on the same surface and through the same process as the transistor 10, alongside the transistor 10.
  • Transistor 15 is a transistor in which openings 20b and 20c are not provided in conductive layer 24 and semiconductor layer 21.
  • Transistor 15 has semiconductor layer 21, insulating layer 22, conductive layer 23, conductive layer 24, and conductive layer 25.
  • insulating layer 22 contacts semiconductor layer 21 inside opening 20a, but does not contact conductive layer 24 or insulating layer 11.
  • the diameter of opening 20a provided in insulating layer 41 of transistor 15 can be made smaller than that of transistor 10.
  • transistor 15 can be made smaller than transistor 10.
  • transistor 10 can be used for a transistor that requires a small parasitic capacitance
  • transistor 15 can be used for a transistor that requires a small occupying area, and so on, depending on the requirements.
  • the transistor 10f shown in FIG. 7A differs from the transistor 10 and others described above mainly in that the ends of each layer are processed roughly vertically.
  • the conductive layer 24 is embedded in the insulating layer 44.
  • the insulating layer 41 is provided to cover the conductive layer 24 and the insulating layer 44.
  • the conductive layer 25 is embedded in the insulating layer 45.
  • the insulating layer 22 is provided to cover the insulating layer 45, the conductive layer 25, the semiconductor layer 21, etc.
  • the insulating layer 44 and the conductive layer 24 are planarized so that their upper surfaces are roughly the same height, and the insulating layer 45 and the conductive layer 25 are planarized so that their upper surfaces are roughly the same height.
  • Insulating layers 41a, 41b, and 41c have a generally vertical cross section. That is, the angle ⁇ of the sidewall of opening 20a in insulating layer 41 is generally 90 degrees. In addition, because the end of semiconductor layer 21 and the end of conductive layer 24 generally coincide within opening 20a, the diameter of opening 20c and the outline of opening 20b generally coincide.
  • the semiconductor layer 21, insulating layer 22, and conductive layer 23 are provided along the roughly vertical inner wall of the opening 20a in the insulating layer 41, so they are preferably formed using a film formation method with high coverage such as the ALD method.
  • the transistor 10g shown in FIG. 7B is an example in which the conductive layer 23 is provided so as to fill the opening 20a.
  • An insulating layer 42 is provided on insulating layer 22, and an opening 20d is provided in insulating layer 42, overlapping opening 20a and reaching insulating layer 22.
  • Conductive layer 23 is provided so as to fill opening 20d and opening 20a.
  • the upper surfaces of conductive layer 23 and insulating layer 42 are flattened, and a conductive layer 32 is provided on insulating layer 42, contacting the upper surface of conductive layer 23.
  • Conductive layer 32 functions as a gate wiring.
  • the transistor 10h shown in FIG. 7C is an example in which an insulating layer 22 is provided along the inner wall of the opening 20d.
  • the opening 20d is provided so as to reach the semiconductor layer 21, and an insulating layer 22 is provided to cover the sidewall of the opening 20d and the semiconductor layer 21.
  • a conductive layer 23 is provided so as to fill the opening 20d and the opening 20a.
  • transistors with such a configuration By using the configuration shown in Figures 7A to 7C, it is possible to realize extremely fine transistors. For example, by forming transistors with such a configuration on a semiconductor substrate such as a silicon wafer, it is possible to realize a display panel with a resolution of 3000 ppi or even 5000 ppi.
  • the thin films (insulating films, semiconductor films, conductive films, etc.) that constitute the semiconductor device can be formed using sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), atomic layer deposition (ALD), etc.
  • CVD methods include plasma enhanced chemical vapor deposition (PECVD) and thermal CVD.
  • PECVD plasma enhanced chemical vapor deposition
  • thermal CVD metal organic chemical vapor deposition
  • thin films that make up semiconductor devices can be formed by methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and knife coating.
  • Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrodes in a pulsed manner.
  • RF sputtering is mainly used when depositing insulating films
  • DC sputtering is mainly used when depositing metal conductive films.
  • Pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, and carbides using the reactive sputtering method.
  • CVD methods can be classified into plasma CVD (PECVD) which uses plasma, thermal CVD (TCVD: Thermal CVD) which uses heat, and photo CVD (Photo CVD) which uses light. They can also be further divided into metal CVD (MCVD: Metal CVD) and metal organic CVD (MOCVD: Metal CVD) depending on the source gas used.
  • PECVD plasma CVD
  • TCVD Thermal CVD
  • Photo CVD Photo CVD
  • MCVD Metal CVD
  • MOCVD Metal CVD
  • the plasma CVD method can produce high-quality films at relatively low temperatures.
  • the thermal CVD method does not use plasma, it is possible to reduce plasma damage to the workpiece.
  • the thermal CVD method does not cause plasma damage during film formation, it is possible to produce films with fewer defects.
  • the ALD method can be a thermal ALD method in which the reaction between the precursor and reactant is carried out using only thermal energy, or a PEALD method in which a plasma-excited reactant is used.
  • CVD and ALD are film formation methods that are less affected by the shape of the workpiece and have good step coverage.
  • ALD has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surfaces of openings with high aspect ratios.
  • CVD has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as CVD, which has a faster film formation speed.
  • the CVD method allows the deposition of a film of any composition by varying the flow rate ratio of the raw material gases.
  • the CVD method allows the deposition of a film whose composition changes continuously by changing the flow rate ratio of the raw material gases while the film is being deposited.
  • the time required for deposition can be shortened compared to deposition using multiple deposition chambers, since no time is required for transportation or pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.
  • a film of any composition can be formed by simultaneously introducing multiple different types of precursors. Alternatively, when multiple different types of precursors are introduced, a film of any composition can be formed by controlling the number of cycles of each precursor. Also, as with the CVD method, a film with a continuously changing composition can be formed.
  • the thin film that constitutes the semiconductor device when processing the thin film that constitutes the semiconductor device, it can be processed using a photolithography method or the like.
  • the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method, or the like.
  • island-shaped thin films may be directly formed using a film formation method that uses a shielding mask such as a metal mask.
  • the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these.
  • ultraviolet light, KrF laser light, ArF laser light, etc. can also be used.
  • Exposure can also be performed by immersion exposure technology.
  • Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure.
  • Electron beams can also be used instead of light used for exposure. Extreme ultraviolet light, X-rays, or electron beams are preferable because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.
  • Methods such as dry etching, wet etching, and sandblasting can be used to etch thin films.
  • Figures 8A to 8D are perspective views of each step in the manufacturing process of a semiconductor device, which will be described below.
  • a substrate (not shown) is prepared, and an insulating layer 11 is formed on the substrate.
  • a substrate having at least a heat resistance sufficient to withstand subsequent heat treatments can be used.
  • a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, an organic resin substrate, or the like can be used.
  • semiconductor substrates such as single crystal semiconductor substrates made of silicon or silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium and gallium nitride, and SOI substrates can be used.
  • the insulating layer 11 may be an inorganic insulating film such as a silicon oxide film or a silicon oxynitride film.
  • the insulating layer 11 may be formed by a method such as sputtering, CVD, MBE, PLD, or ALD. If the surface on which the insulating layer 11 is to be formed is not flat, a planarization process may be performed after the insulating layer 11 is formed so that the upper surface of the insulating layer 11 is flat.
  • a conductive film is formed on the insulating layer 11
  • a resist mask is formed on the conductive film, and unnecessary portions of the conductive film are removed by etching to form the conductive layer 24.
  • the conductive film that becomes the conductive layer 24 can be formed using a film formation method such as sputtering, CVD, or ALD.
  • insulating layers 41a, 41b, and 41c are formed on the conductive layer 24 and the insulating layer 11.
  • the insulating layers 41a, 41b, and 41c may be formed by appropriately using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • insulating layers 41a and 41c are made of insulating materials having different compositions or constituent elements from insulating layer 41b.
  • insulating layers 41a, 41b, and 41c affect the channel length of the transistor, it is important to prevent variation in the thicknesses of insulating layers 41a, 41b, and 41c.
  • the insulating layer 41b is a film that will later come into contact with the semiconductor layer 21, it is preferable to use an oxide film that contains a large amount of oxygen to the extent that oxygen is released by heating and has a small hydrogen content.
  • the insulating layer 41b can be formed by a film formation method such as a PECVD method, a sputtering method, or an ALD method, but it is particularly preferable to form the insulating layer 41b by a sputtering method.
  • a gas containing oxygen and not a gas containing hydrogen as a film formation gas it is possible to form an insulating layer 41b that has an extremely small hydrogen content and contains excess oxygen.
  • oxygen can be supplied from the insulating layer 41b to the channel formation region of the semiconductor layer 21, thereby reducing oxygen deficiencies.
  • the conductive film is formed on the insulating layer 41c, and unnecessary portions are removed by etching to form the conductive layer 25 (FIG. 8A).
  • the conductive film may be formed by a film forming method such as sputtering, CVD, MBE, PLD, or ALD.
  • an opening 20a is formed in the conductive layer 25, the insulating layer 41c, the insulating layer 41b, and the insulating layer 41a, reaching the conductive layer 24 ( Figure 8B).
  • the conductive layer 25 may be used as a hard mask.
  • an opening is first formed in the conductive layer 25 using a resist mask.
  • the insulating layer 41c, the insulating layer 41b, and the insulating layer 41a are sequentially etched using the conductive layer 25 as a mask to form the opening 20a.
  • the resist mask may be removed after etching the conductive layer 25, or may be removed during etching of the insulating layer 41c, the insulating layer 41b, and the insulating layer 41a, or may be removed after the opening 20a is formed.
  • the conductive layer 25, the insulating layer 41c, the insulating layer 41b, and the insulating layer 41a can be etched by dry etching to form the fine opening 20a.
  • this is not limited to this, and wet etching and dry etching may be combined, or processing may be performed by wet etching.
  • the sidewalls of the opening 20a may be formed nearly perpendicular to the top surface of the conductive layer 24, since this reduces the area of the opening 20a. With this configuration, a transistor with a small occupancy area can be fabricated.
  • the sidewalls of the opening 20a may be tapered. By forming the sidewalls in a tapered shape, the coverage of the film formed inside the opening 20a can be improved.
  • the maximum width of the opening 20a (maximum diameter when the opening 20a is circular in plan view) is preferably as fine as possible.
  • the maximum width of the opening 20a is 2 ⁇ m or less, 1 ⁇ m or less, 500 nm or less, 300 nm or less, 150 nm or less, 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, or 20 nm or less, and is preferably 5 nm or more.
  • a lithography method using short-wavelength light such as EUV light or an electron beam.
  • the heat treatment may be performed at 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower.
  • the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • the oxygen gas may be about 20%.
  • the heat treatment may be performed under reduced pressure.
  • the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.
  • impurities such as water and hydrogen contained in the insulating layer 41 and the like can be reduced before the formation of the oxide semiconductor film that becomes the semiconductor layer.
  • the gas used in the heat treatment is preferably highly purified.
  • the amount of moisture contained in the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less.
  • a semiconductor film that will become the semiconductor layer 21 is formed, covering the conductive layer 25, the insulating layer 41c, the opening 20a, etc. After that, unnecessary parts of the semiconductor film are removed by etching to form the semiconductor layer 21. Note that at this stage, it is not necessary to form the opening 20c in the semiconductor layer 21.
  • openings 20b and 20c using the same resist mask. This allows the ends of semiconductor layer 21 and conductive layer 24 to roughly coincide.
  • openings 20b and 20c are not limited to this, and they can be formed separately using different resist masks. Also, openings 20c and 20b can be formed simultaneously when processing the semiconductor layer 21. Also, opening 20b can be formed before the semiconductor film is formed, and opening 20c can be formed separately after the semiconductor film is formed. Also, opening 20b can be formed simultaneously when opening 20a is formed.
  • an oxide semiconductor film can be used as the semiconductor film.
  • the oxide semiconductor film can be formed by appropriately using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the oxide semiconductor film is preferably formed in contact with the bottom and sidewall of the opening 20a having a large aspect ratio. Therefore, the oxide semiconductor film is preferably formed by a film formation method with good coverage, and more preferably by a CVD method or an ALD method.
  • the oxide semiconductor film can be formed by forming an In-Ga-Zn oxide film by the ALD method. Note that when the opening 20a has a tapered shape, the oxide semiconductor film can be formed by the sputtering method.
  • the microwave treatment refers to a treatment using an apparatus having a power source that generates high-density plasma using microwaves, for example.
  • oxygen gas By performing microwave treatment in an atmosphere containing oxygen, oxygen gas can be turned into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be made to act.
  • Oxygen acting on an oxide semiconductor can take various forms, such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (also called O radicals, which are atoms, molecules, or ions with an unpaired electron).
  • the oxygen acting on an oxide semiconductor can take any one or more of the above forms, and oxygen radicals are particularly preferred.
  • the temperature at which the substrate is heated may be 100°C or higher and 650°C or lower, preferably 200°C or higher and 600°C or lower, and more preferably 300°C or higher and 450°C or lower.
  • the carbon concentration in the oxide semiconductor film measured by SIMS can be set to less than 1 ⁇ 10 atoms/cm 3 , preferably less than 1 ⁇ 10 atoms/cm 3 , further preferably less than 1 ⁇ 10 atoms/cm 3 .
  • the microwave treatment may be performed on an insulating film, more specifically, a silicon oxide film, located near the oxide semiconductor film, in an atmosphere containing oxygen.
  • a silicon oxide film located near the oxide semiconductor film
  • the microwave treatment may be performed on the insulating layer 22 to be formed later in an atmosphere containing oxygen.
  • the deposition method of each layer may be the same or different.
  • the lower layer of the oxide semiconductor film may be deposited by a sputtering method
  • the upper layer of the oxide semiconductor film may be deposited by an ALD method.
  • An oxide semiconductor film deposited by a sputtering method is likely to have crystallinity. Therefore, by providing a crystalline oxide semiconductor film as the lower layer of the oxide semiconductor film, the crystallinity of the upper layer of the oxide semiconductor film can be improved.
  • the portions overlapping with these can be blocked by the upper layer of the oxide semiconductor film deposited by an ALD method, which has good coverage.
  • the semiconductor film is preferably formed by a sputtering method using a metal oxide target, for example.
  • the semiconductor film is preferably a dense film with as few defects as possible. It is also preferable that the semiconductor film is a high-purity film in which impurities such as hydrogen and water are reduced as much as possible. In particular, it is preferable to use a crystalline metal oxide film as the semiconductor film.
  • oxygen gas when forming the metal oxide film, oxygen gas may be mixed with an inert gas (e.g., helium gas, argon gas, xenon gas, etc.).
  • an inert gas e.g., helium gas, argon gas, xenon gas, etc.
  • the higher the ratio of oxygen gas to the total deposition gas when forming the metal oxide film hereinafter also referred to as the oxygen flow ratio
  • the lower the oxygen flow ratio the lower the crystallinity of the metal oxide film, and a transistor with increased on-current can be obtained.
  • the deposition conditions for the metal oxide film are a substrate temperature between room temperature and 250°C, preferably between room temperature and 200°C, and more preferably between room temperature and 140°C.
  • a substrate temperature between room temperature and less than 140°C is preferable because it increases productivity.
  • the crystallinity can be reduced.
  • a film formation method such as thermal ALD (Atomic Layer Deposition) or PEALD (Plasma Enhanced ALD).
  • thermal ALD Atomic Layer Deposition
  • PEALD Pasma Enhanced ALD
  • the thermal ALD method is preferable because it shows extremely high step coverage.
  • the PEALD method is also preferable because it shows high step coverage and allows low-temperature film formation.
  • a film can be formed by the ALD method using a precursor containing the constituent metal element and an oxidizing agent.
  • three precursors can be used: a precursor containing indium, a precursor containing gallium, and a precursor containing zinc.
  • two precursors can be used: a precursor containing indium, and a precursor containing gallium and zinc.
  • Indium-containing precursors that can be used include triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, and (3-(dimethylamino)propyl)dimethylindium.
  • precursors containing gallium trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamido)gallium, gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, diethylchlorogallium, gallium(III) chloride, etc. can be used.
  • dimethylzinc, diethylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), zinc chloride, etc. can be used as precursors containing zinc.
  • ozone oxygen, water, etc. can be used as an oxidizing agent.
  • Methods for controlling the composition of the resulting film include adjusting the flow ratio of the raw material gases, the time for which the raw material gases are flowed, the order in which the raw material gases are flowed, etc. By adjusting these, it is also possible to deposit a film whose composition changes continuously. It is also possible to deposit two or more films with different compositions in succession.
  • the heat treatment may be performed in a temperature range in which the oxide semiconductor film does not become polycrystallized, and may be performed at 250° C. to 650° C., preferably 400° C. to 600° C.
  • the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • the heat treatment may be performed under reduced pressure.
  • the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the oxygen that has been desorbed after the heat treatment in the nitrogen gas or inert gas atmosphere.
  • the gas used in the heat treatment is preferably highly purified.
  • the amount of moisture contained in the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less.
  • the insulating layer 22 is formed by covering the semiconductor layer 21, the conductive layer 25, the insulating layer 41c, the conductive layer 24, the insulating layer 11, etc.
  • the insulating layer 22 can be formed by a method such as sputtering, CVD, MBE, PLD, or ALD, as appropriate.
  • the insulating layer 22 is provided on the side surface of the semiconductor layer 21 in the opening 20a with a thickness as uniform as possible. For this reason, it is particularly preferable to form the insulating layer 22 by the ALD method, which is a film formation method with extremely excellent coverage. If the side wall of the opening 20a has a tapered shape, the insulating layer 22 can be formed using a film formation method such as a sputtering method.
  • the transistor 10 can be manufactured.
  • This embodiment can be implemented by combining at least a portion of it with other embodiments described in this specification.
  • One embodiment of the present invention has a structure in which the capacitance between the gate electrode and the first electrode at the bottom of an opening (first opening) in an insulating layer functioning as a spacer is reduced.
  • a structure in which the capacitance is reduced by providing an opening in the first electrode and the semiconductor layer located at the bottom is described.
  • a structure example in which the structure is partially different from that in embodiment 1 is described. Note that in the following, a description of parts that overlap with the above may be omitted.
  • the gate electrode has an opening located inside an opening (first opening) in the insulating layer that functions as a spacer in a plan view. This makes it possible to provide a portion where the gate electrode does not overlap with either the first electrode or the semiconductor layer, even if one or both of the semiconductor layer and the first electrode do not have an opening. This makes it possible to reduce the capacitance between the gate electrode and the first electrode.
  • FIG. 9A and 9B are schematic perspective views of a transistor 50.
  • Fig. 9A is a perspective view including a cross section cut along the X-Z plane
  • Fig. 9B is a perspective view including a cross section cut along the Y-Z plane.
  • FIG. 10A shows a plan view of transistor 50
  • FIGS. 10B and 10C show schematic cross-sectional views corresponding to the cut lines A1-A2 and B1-B2 in FIG. 10A, respectively.
  • transistor 50 is provided in opening 20a in insulating layer 41 and its surroundings, and has semiconductor layer 21, insulating layer 22, conductive layer 23, conductive layer 24, and conductive layer 25.
  • the conductive layer 24 is provided on the insulating layer 11.
  • the insulating layer 41 is provided to cover the conductive layer 24, and has an opening that reaches the conductive layer 24.
  • the conductive layer 25 is provided on the insulating layer 41.
  • the semiconductor layer 21 has a portion that contacts the upper surface of the conductive layer 25, the upper surface of the conductive layer 24, and the side surface of the insulating layer 41.
  • the insulating layer 22 is provided to cover the semiconductor layer 21, and the conductive layer 23 is provided to cover the insulating layer 22.
  • the conductive layer 23 has an opening 20e that reaches the insulating layer 22.
  • the opening 20e is located inside the opening 20a.
  • the shape of the opening 20a in the insulating layer 41 and the shape of the opening 20e in the conductive layer 23 are both circular.
  • Fig. 11A is a cross-sectional view of transistor 50 similar to Fig. 10B, and Fig. 11B is a plan view of the cut surface when cut along cut line C1-C2 located at the height where insulating layer 41b in Fig. 11A is provided, as viewed from the Z direction.
  • the diameter R4 of the opening 20e in the conductive layer 23 is set to R4.
  • the diameter R4 of the opening 20e is smaller than the diameter R1 of the opening 20a.
  • the larger R4 is, the greater the area of the portion where the conductive layer 23 does not overlap with the conductive layer 24 and the semiconductor layer 21, and the greater the effect of reducing the parasitic capacitance.
  • the diameter R4 of the opening 20e is preferably 50% or more of the diameter R1 of the opening 20a, preferably 60% or more, more preferably 70% or more, even more preferably 80% or more, and even more preferably 90% or more, but less than 100%.
  • opening 20e may be of any shape as long as it is positioned inside opening 20a. However, it is preferable to make the shape of opening 20e similar to or close to the shape of opening 20a, since this reduces the difference in area between openings 20a and 20e.
  • FIG. 12 is a cross-sectional view of a case where a transistor 50 and the transistor 15 described in Embodiment 1 are fabricated on the same surface.
  • the opening 20a can be processed with the minimum processing dimensions. Therefore, the area occupied by the transistor 15 can be made smaller than that of the transistor 50.
  • the diameters of the openings 20a of the transistors 15 and 50 can be changed as appropriate depending on the design.
  • the transistor 15, which can reduce the area occupied, and the transistor 50, which can reduce the parasitic capacitance, can be used depending on the application.
  • Transistor 50 and transistor 15 can be made differently without increasing the number of processes by using different mask patterns for processing each layer, such as conductive layer 23 and opening 20a.
  • FIG. 13A shows an example of the configuration of a transistor 50a having a structure suitable for miniaturization by applying an LSI process.
  • Transistor 50a differs from transistor 50 in that the ends of each layer are processed to be roughly vertical.
  • conductive layer 24 is embedded in insulating layer 44
  • conductive layer 25 is embedded in insulating layer 45, and each is flattened so that the height of the top surface is the same.
  • the semiconductor layer 21, the insulating layer 22, and the conductive layer 23 are each formed using a film formation method with high coverage.
  • Transistor 50b shown in FIG. 13B is an example having an insulating layer 42 on insulating layer 22.
  • the conductive layer 23 has a portion that is provided along the sidewall of opening 20d in insulating layer 42.
  • Transistor 50c shown in FIG. 13C differs from transistor 50b in the position of insulating layer 22. Insulating layer 22 and conductive layer 23 have portions that are provided along the sidewall of opening 20d in insulating layer 42.
  • the conductive layer 23 may have a shape that fills the opening 20a.
  • forming the conductive layer 23 as a thin film is preferable because it makes it easier to process the conductive layer 23 to form the opening 20e.
  • Transistor 50d shown in FIG. 14A is an example having a conductive layer 32 that functions as a gate wiring.
  • An insulating layer 46 is provided covering the insulating layer 22 and the conductive layer 23, and a conductive layer 32 is provided on the insulating layer 46.
  • the upper surface of the insulating layer 46 is flattened so that it is at the same height as the upper surface of the conductive layer 23.
  • the conductive layer 32 is provided in contact with the upper surface of the conductive layer 23 exposed from the insulating layer 46.
  • the insulating layer 46 is also embedded inside the opening 20a.
  • Transistor 50e shown in FIG. 14B is an example in which an insulating layer 46 and a conductive layer 32 are further applied to transistor 50b shown in FIG. 13B.
  • An insulating layer 46 is provided so as to fill opening 20d.
  • an insulating layer 46 and a conductive layer 32 can also be applied to the transistor 50c shown in FIG. 13C.
  • This embodiment can be implemented by combining at least a portion of it with other embodiments described in this specification.
  • the display device of this embodiment can be a high-resolution display device or a large display device. Therefore, the display device of this embodiment can be used in electronic devices with relatively large screens, such as television devices, desktop or notebook personal computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as in the display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.
  • electronic devices with relatively large screens such as television devices, desktop or notebook personal computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as in the display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.
  • the display device of this embodiment can be a high-definition display device. Therefore, the display device of this embodiment can be used, for example, in the display section of a wristwatch-type or bracelet-type information terminal (wearable device), as well as in the display section of a wearable device that can be worn on the head, such as a head-mounted display (HMD) or other VR device, and a glasses-type AR device.
  • a wearable device such as a head-mounted display (HMD) or other VR device, and a glasses-type AR device.
  • HMD head-mounted display
  • AR device glasses-type AR device
  • the semiconductor device can be used in a display device or a module having the display device.
  • the module having the display device include a module in which a connector such as a flexible printed circuit (hereinafter, referred to as FPC) or a TCP (Tape Carrier Package) is attached to the display device, and a module in which an integrated circuit (IC) is mounted by a COG (Chip On Glass) method or a COF (Chip On Film) method, etc.
  • FPC flexible printed circuit
  • TCP Tape Carrier Package
  • Figure 15 shows a perspective view of the display device 100A.
  • Display device 100A has a configuration in which substrate 152 and substrate 151 are bonded together.
  • substrate 152 is indicated by a dashed line.
  • the display device 100A has a display unit 162, a connection unit 140, a circuit unit 164, wiring 165, etc.
  • FIG. 15 shows an example in which an IC 173 and an FPC 172 are mounted on the display device 100A. Therefore, the configuration shown in FIG. 15 can also be said to be a display module having the display device 100A, an IC, and an FPC.
  • connection portion 140 is provided on the outside of the display portion 162.
  • the connection portion 140 can be provided along one side or multiple sides of the display portion 162. There may be one or multiple connection portions 140.
  • FIG. 15 shows an example in which the connection portion 140 is provided so as to surround the four sides of the display portion 162.
  • the connection portion 140 electrically connects the common electrode of the display element and the conductive layer, and can supply a potential to the common electrode.
  • the circuit portion 164 has, for example, a scanning line driver circuit (also called a gate driver).
  • the circuit portion 164 may also have both a scanning line driver circuit and a signal line driver circuit (also called a source driver).
  • the wiring 165 has a function of supplying signals and power to the display unit 162 and the circuit unit 164.
  • the signals and power are input to the wiring 165 from the outside via the FPC 172, or are input to the wiring 165 from the IC 173.
  • FIG. 15 shows an example in which an IC 173 is provided on a substrate 151 by a COG method, a COF method, or the like.
  • an IC having one or both of a scanning line driver circuit and a signal line driver circuit can be used as the IC 173.
  • the display device 100A and the display module may be configured without an IC.
  • the IC may be mounted on an FPC by a COF method, or the like.
  • the semiconductor device of one embodiment of the present invention can be applied to, for example, one or both of the display portion 162 and the circuit portion 164 of the display device 100A.
  • the semiconductor device of one embodiment of the present invention can also be applied to the IC 173.
  • the semiconductor device of one embodiment of the present invention when the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-definition display device can be obtained. Furthermore, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, and a display device with a narrow frame can be obtained. Furthermore, since the semiconductor device of one embodiment of the present invention has good electrical characteristics, the reliability of the display device can be improved by using it in a display device.
  • a driver circuit of a display device e.g., one or both of a gate line driver circuit and a source line driver circuit
  • the display unit 162 is an area in the display device 100A that displays an image, and has a number of periodically arranged pixels 210.
  • FIG. 15 shows an enlarged view of one pixel 210.
  • pixel arrangements there are no particular limitations on the pixel arrangement in the display device of this embodiment, and various methods can be applied. Examples of pixel arrangements include a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a Pentile arrangement.
  • the pixel 210 shown in FIG. 15 has a subpixel 210R that emits red light, a subpixel 210G that emits green light, and a subpixel 210B that emits blue light.
  • Various elements can be used as the display element, including, for example, liquid crystal elements and light-emitting elements.
  • display elements using shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) elements, microcapsule-type, electrophoresis-type, electrowetting-type, or electronic liquid powder (registered trademark)-type can also be used.
  • QLED Quantum-dot LED
  • a light source and color conversion technology using quantum dot materials may also be used.
  • liquid crystal elements include transmissive liquid crystal elements, reflective liquid crystal elements, and semi-transmissive liquid crystal elements.
  • Light-emitting elements include, for example, self-emitting light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), and semiconductor lasers. As LEDs, for example, mini LEDs and micro LEDs can be used.
  • LEDs Light Emitting Diodes
  • OLEDs Organic LEDs
  • semiconductor lasers As LEDs, for example, mini LEDs and micro LEDs can be used.
  • Light-emitting materials that light-emitting elements have include, for example, materials that emit fluorescence (fluorescent materials), materials that emit phosphorescence (phosphorescent materials), materials that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) materials), and inorganic compounds (quantum dot materials, etc.).
  • fluorescent materials materials that emit fluorescence
  • phosphorescent materials materials that emit phosphorescence
  • TADF thermally activated delayed fluorescence
  • inorganic compounds quantum dot materials, etc.
  • the light-emitting element can emit light of infrared, red, green, blue, cyan, magenta, yellow, or white.
  • the color purity can be increased by providing the light-emitting element with a microcavity structure.
  • the display device of one embodiment of the present invention may be a top-emission type that emits light in the direction opposite to the substrate on which the light-emitting element is formed, a bottom-emission type that emits light toward the substrate on which the light-emitting element is formed, or a dual-emission type that emits light to both sides.
  • FIG. 16 shows an example of a cross section of the display device 100A when a portion of the area including the FPC 172, a portion of the circuit section 164, a portion of the display section 162, a portion of the connection section 140, and a portion of the area including the end portion are cut away.
  • the display device 100A shown in FIG. 16 has transistors 205D, 205R, 205G, 205B, light-emitting elements 130R, 130G, and 130B between substrate 151 and substrate 152.
  • Light-emitting element 130R is a display element included in sub-pixel 210R that emits red light
  • light-emitting element 130G is a display element included in sub-pixel 210G that emits green light
  • light-emitting element 130B is a display element included in sub-pixel 210B that emits blue light.
  • the display device 100A uses an SBS structure.
  • the SBS structure allows the material and configuration to be optimized for each light-emitting element, which increases the freedom of material and configuration selection and makes it easier to improve brightness and reliability.
  • the display device 100A is also a top emission type.
  • transistors and the like can be arranged so as to overlap the light emitting region of the light emitting element, so the aperture ratio of the pixel can be increased compared to a bottom emission type.
  • Transistors 205D, 205R, 205G, and 205B are all formed on substrate 151. These transistors can be fabricated using the same process.
  • transistors according to one embodiment of the present invention in which an oxide semiconductor is used as the semiconductor and parasitic capacitance is reduced are used as the transistors 205D, 205R, 205G, and 205B.
  • the transistors 205R, 205G, and 205B function as driving transistors for controlling a current flowing through a light-emitting element.
  • the transistor 205D provided in the circuit portion 164 is a transistor that constitutes part of the driving circuit.
  • each of the transistors 205D, 205R, 205G, and 205B includes a conductive layer 104 that functions as a gate, an insulating layer 106 that functions as a gate insulating layer, a conductive layer 109 that functions as one of a source electrode or a drain electrode, a conductive layer 107 that functions as the other, a semiconductor layer 108, and an insulating layer 110.
  • the conductive layer 109 and the conductive layer 107 are in contact with the semiconductor layer 108.
  • a conductive layer 112a that is in contact with the conductive layer 107 and a conductive layer 112b that is in contact with the conductive layer 109 are provided.
  • the conductive layer 112a and the conductive layer 112b each include a conductive material that has a lower resistance than the conductive layer 107 and the conductive layer 109, and function as wiring.
  • the same hatching pattern is applied to multiple layers obtained by processing the same film.
  • the display device 100A includes transistors of one embodiment of the present invention in both the display portion 162 and the circuit portion 164.
  • the pixel size can be reduced, leading to higher resolution.
  • the area occupied by the circuit portion 164 can be reduced, leading to a narrower frame.
  • the load on wiring can be reduced, leading to a display device capable of high-speed operation, a large display device, or a display device with high resolution (with a large number of pixels).
  • the description of the previous embodiment can be referred to.
  • the transistors included in the display device of this embodiment are not limited to the transistors of one embodiment of the present invention.
  • the display device may include a combination of a transistor of one embodiment of the present invention and a transistor having another structure.
  • the display device of this embodiment may have, for example, one or more of a planar transistor, a staggered transistor, and an inverted staggered transistor.
  • the transistors of the display device of this embodiment may be either a top-gate type or a bottom-gate type.
  • a gate may be provided above and below a semiconductor layer in which a channel is formed.
  • the display device of this embodiment may have a transistor (Si transistor) using silicon in the channel formation region.
  • silicon examples include single crystal silicon, polycrystalline silicon, and amorphous silicon.
  • a transistor having LTPS in the semiconductor layer (hereinafter also referred to as an LTPS transistor) can be used.
  • LTPS transistors have high field effect mobility and good frequency characteristics.
  • a transistor having amorphous silicon in the semiconductor layer has excellent productivity because it can be uniformly formed on a large-area glass substrate.
  • the display device of this embodiment may also have a transistor (OS transistor) that uses an oxide semiconductor (OS) such as In-Ga-Zn oxide (also referred to as IGZO) in the channel formation region.
  • OS oxide semiconductor
  • IGZO In-Ga-Zn oxide
  • the display device may have a mixture of a transistor that uses silicon as the semiconductor in which the channel is formed and a transistor that uses an oxide semiconductor.
  • the transistors in the circuit unit 164 and the transistors in the display unit 162 may have the same structure or different structures.
  • the transistors in the circuit unit 164 may all have the same structure or may be of two or more types.
  • the transistors in the display unit 162 may all have the same structure or may be of two or more types.
  • All of the transistors in the display portion 162 may be OS transistors, all of the transistors in the display portion 162 may be Si transistors, or some of the transistors in the display portion 162 may be OS transistors and the rest may be Si transistors.
  • LTPS transistors and OS transistors are used in the display unit 162 to realize a display device with low power consumption and high driving capability.
  • a configuration in which LTPS transistors and OS transistors are combined is sometimes called LTPO.
  • a more suitable example is a configuration in which OS transistors are used as transistors that function as switches for controlling conduction/non-conduction between wirings, and LTPS transistors are used as transistors for controlling current.
  • one of the transistors in the display unit 162 functions as a transistor for controlling the current flowing through the light-emitting element and can also be called a driving transistor.
  • One of the source and drain of the driving transistor is electrically connected to the pixel electrode of the light-emitting element.
  • the other transistor in the display unit 162 functions as a switch for controlling pixel selection/non-selection and can also be called a selection transistor.
  • the gate of the selection transistor is electrically connected to a gate line, and one of the source and drain is electrically connected to a source line (signal line). It is preferable to use an OS transistor as the selection transistor. This makes it possible to maintain the gradation of the pixel even if the frame frequency is significantly reduced (for example, 1 fps or less), and therefore power consumption can be reduced by stopping the driver when displaying a still image.
  • An insulating layer 218 is provided to cover transistors 205D, 205R, 205G, and 205B, and an insulating layer 235 is provided on insulating layer 218.
  • the insulating layer 218 preferably functions as a protective layer for the transistor.
  • the insulating layer 218 is preferably made of a material that is difficult for impurities such as water and hydrogen to diffuse into. This allows the insulating layer 218 to function as a barrier layer. With this configuration, it is possible to effectively prevent impurities from diffusing from the outside into the transistor, and the reliability of the display device can be improved.
  • the insulating layer 218 preferably has one or more inorganic insulating films.
  • inorganic insulating films include oxide insulating films, nitride insulating films, oxynitride insulating films, and nitride oxide insulating films. Specific examples of these inorganic insulating films are as described above.
  • the insulating layer 235 preferably functions as a planarizing layer, and is preferably an organic insulating film.
  • Materials that can be used for the organic insulating film include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins.
  • the insulating layer 235 may also have a laminated structure of an organic insulating film and an inorganic insulating film.
  • the outermost layer of the insulating layer 235 preferably functions as an etching protection layer. This makes it possible to prevent the formation of recesses in the insulating layer 235 when processing the pixel electrodes 111R, 111G, 111B, etc. Alternatively, recesses may be provided in the insulating layer 235 when processing the pixel electrodes 111R, 111G, 111B, etc.
  • Light emitting elements 130R, 130G, and 130B are provided on insulating layer 235.
  • the light-emitting element 130R has a pixel electrode 111R on the insulating layer 235, an EL layer 113R on the pixel electrode 111R, and a common electrode 115 on the EL layer 113R.
  • the light-emitting element 130R shown in FIG. 16 emits red light (R).
  • the EL layer 113R has a light-emitting layer that emits red light.
  • the light-emitting element 130G has a pixel electrode 111G, an EL layer 113G, and a common electrode 115.
  • the light-emitting element 130G emits green light (G)
  • the EL layer 113G has a light-emitting layer that emits green light.
  • the light-emitting element 130B has a pixel electrode 111B, an EL layer 113B, and a common electrode 115.
  • the light-emitting element 130B emits blue light (B)
  • the EL layer 113B has a light-emitting layer that emits blue light.
  • EL layers 113R, 113G, and 113B are all shown as having the same thickness, but this is not limited to the above.
  • EL layers 113R, 113G, and 113B may each have a different film thickness.
  • the pixel electrode 111R is electrically connected to the conductive layer 112b of the transistor 205R through openings provided in the insulating layer 106, the insulating layer 218, and the insulating layer 235.
  • the pixel electrode 111G is electrically connected to the conductive layer 112b of the transistor 205G
  • the pixel electrode 111B is electrically connected to the conductive layer 112b of the transistor 205B.
  • the ends of each of the pixel electrodes 111R, 111G, and 111B are covered with an insulating layer 237.
  • the insulating layer 237 functions as a partition (also called a bank or spacer).
  • the insulating layer 237 can be provided in a single layer structure or a stacked structure using one or both of an inorganic insulating material and an organic insulating material.
  • the material that can be used for the insulating layer 218 and the material that can be used for the insulating layer 235 can be applied to the insulating layer 237.
  • the insulating layer 237 can electrically insulate the pixel electrode and the common electrode. Furthermore, the insulating layer 237 can electrically insulate adjacent light-emitting elements from each other.
  • the common electrode 115 is a continuous film that is provided in common to the light-emitting elements 130R, 130G, and 130B.
  • the common electrode 115 that is shared by the multiple light-emitting elements is electrically connected to a conductive layer 123 provided in the connection portion 140.
  • a conductive layer 123 it is preferable to use a conductive layer formed from the same material and in the same process as the pixel electrodes 111R, 111G, and 111B.
  • a conductive film that transmits visible light is used for the electrode from which light is extracted, between the pixel electrode and the common electrode. It is preferable to use a conductive film that reflects visible light for the electrode from which light is not extracted.
  • a conductive film that transmits visible light may also be used for the electrode on the side from which light is not extracted.
  • the light emitted from the EL layer may be reflected by the reflective layer and extracted from the display device.
  • metals, alloys, electrically conductive compounds, and mixtures thereof can be appropriately used.
  • the material include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, and alloys containing these in appropriate combinations.
  • Examples of the material include indium tin oxide (In-Sn oxide, also called ITO), In-Si-Sn oxide (also called ITSO), indium zinc oxide (In-Zn oxide), and In-W-Zn oxide.
  • Examples of the material include alloys containing aluminum (aluminum alloys), such as an alloy of aluminum, nickel, and lanthanum (Al-Ni-La), and alloys containing silver, such as an alloy of silver and magnesium (Mg-Ag), and an alloy of silver, palladium, and copper (Ag-Pd-Cu, also called APC).
  • Such materials include elements belonging to Group 1 or 2 of the periodic table (e.g., lithium, cesium, calcium, and strontium) that are not listed above, rare earth metals such as europium and ytterbium, and alloys containing appropriate combinations of these, graphene, etc.
  • the light-emitting element preferably has a micro-optical resonator (microcavity) structure. Therefore, one of the pair of electrodes of the light-emitting element is preferably an electrode that is transparent and reflective to visible light (semi-transparent and semi-reflective electrode), and the other is preferably an electrode that is reflective to visible light (reflective electrode).
  • the light-emitting element have a microcavity structure, the light emitted from the light-emitting layer can be resonated between both electrodes, thereby intensifying the light emitted from the light-emitting element.
  • the light transmittance of the transparent electrode is 40% or more.
  • the visible light reflectance of the semi-transmissive/semi-reflective electrode is 10% or more and 95% or less, preferably 30% or more and 80% or less.
  • the visible light reflectance of the reflective electrode is 40% or more and 100% or less, preferably 70% or more and 100% or less.
  • the resistivity of these electrodes is preferably 1 ⁇ 10 ⁇ 2 ⁇ cm or less.
  • the EL layers 113R, 113G, and 113B are each provided in an island shape.
  • the ends of adjacent EL layers 113R and 113G overlap, the ends of adjacent EL layers 113G and 113B overlap, and the ends of adjacent EL layers 113R and 113B overlap.
  • the ends of adjacent EL layers may overlap as shown in FIG. 16, but this is not limited to this. In other words, adjacent EL layers may not overlap and may be separated from each other.
  • the EL layers 113R, 113G, and 113B each have at least a light-emitting layer.
  • the light-emitting layer has one or more types of light-emitting materials.
  • a material that emits light of a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red is appropriately used.
  • a material that emits near-infrared light can also be used as the light-emitting material.
  • Light-emitting materials include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.
  • the light-emitting layer may have one or more organic compounds (host materials, assist materials, etc.) in addition to the light-emitting substance (guest material).
  • the one or more organic compounds one or both of a substance with high hole transport properties (hole transport material) and a substance with high electron transport properties (electron transport material) can be used.
  • a bipolar substance a substance with high electron transport properties and hole transport properties, also called a bipolar material
  • TADF material may be used as the one or more organic compounds.
  • the light-emitting layer preferably has, for example, a phosphorescent material and a hole-transporting material and an electron-transporting material, which are a combination that easily forms an exciplex.
  • ExTET Exciplex-Triple Energy Transfer
  • the energy transfer becomes smooth and light emission can be efficiently obtained.
  • the EL layer may have one or more of a layer containing a substance with high hole injection properties (hole injection layer), a layer containing a material with hole transport properties (hole transport layer), a layer containing a substance with high electron blocking properties (electron blocking layer), a layer containing a substance with high electron injection properties (electron injection layer), a layer containing a material with electron transport properties (electron transport layer), and a layer containing a substance with high hole blocking properties (hole blocking layer).
  • the EL layer may contain one or both of a bipolar material and a TADF material.
  • Eigen elements can be made of either low molecular weight compounds or high molecular weight compounds, and may contain inorganic compounds.
  • the layers constituting the luminescent element can be formed by deposition methods (including vacuum deposition methods), transfer methods, printing methods, inkjet methods, coating methods, etc.
  • the light-emitting element may have a single structure (a structure having only one light-emitting unit) or a tandem structure (a structure having multiple light-emitting units).
  • the light-emitting unit has at least one light-emitting layer.
  • the tandem structure is a structure in which multiple light-emitting units are connected in series via a charge-generating layer. When a voltage is applied between a pair of electrodes, the charge-generating layer has the function of injecting electrons into one of the two light-emitting units and injecting holes into the other.
  • the tandem structure makes it possible to obtain a light-emitting element capable of emitting light with high brightness. Furthermore, compared to a single structure, the tandem structure can reduce the current required to obtain the same brightness, thereby improving reliability.
  • the tandem structure may also be called a stack structure.
  • EL layer 113R has a structure having multiple light-emitting units that emit red light
  • EL layer 113G has a structure having multiple light-emitting units that emit green light
  • EL layer 113B has a structure having multiple light-emitting units that emit blue light.
  • a protective layer 131 is provided on the light-emitting elements 130R, 130G, and 130B.
  • the protective layer 131 and the substrate 152 are bonded via an adhesive layer 142.
  • the substrate 152 is provided with a light-shielding layer 117.
  • a solid sealing structure or a hollow sealing structure can be applied to seal the light-emitting elements.
  • the space between the substrates 152 and 151 is filled with an adhesive layer 142, and a solid sealing structure is applied.
  • the space may be filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure may be applied.
  • the adhesive layer 142 may be provided so as not to overlap with the light-emitting elements.
  • the space may also be filled with a resin different from the adhesive layer 142 provided in a frame shape.
  • the protective layer 131 is provided at least on the display unit 162, and is preferably provided so as to cover the entire display unit 162. By providing the protective layer 131 on the light-emitting elements 130R, 130G, and 130B, the reliability of the light-emitting elements can be improved.
  • the protective layer 131 is preferably provided so as to cover not only the display unit 162, but also the connection unit 140 and the circuit unit 164. In addition, the protective layer 131 is preferably provided up to the end of the display device 100A.
  • the connection unit 204 there are portions where the protective layer 131 is not provided in order to electrically connect the FPC 172 and the conductive layer 166.
  • the protective layer 131 may have a single layer structure or a laminated structure of two or more layers.
  • the conductivity of the protective layer 131 does not matter.
  • At least one of an insulating film, a semiconductor film, and a conductive film can be used as the protective layer 131.
  • the protective layer 131 has an inorganic film, which can prevent oxidation of the common electrode 115, suppress impurities (such as moisture and oxygen) from entering the light-emitting element, and suppress deterioration of the light-emitting element, thereby improving the reliability of the display device.
  • the protective layer 131 can be, for example, an inorganic insulating film such as an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Specific examples of these inorganic insulating films are as described above.
  • the protective layer 131 preferably has a nitride insulating film or a nitride oxide insulating film, and more preferably has a nitride insulating film.
  • the protective layer 131 may also be an inorganic film containing ITO, In-Zn oxide, Ga-Zn oxide, Al-Zn oxide, IGZO, or the like.
  • the inorganic film preferably has a high resistance, and more specifically, preferably has a higher resistance than the common electrode 115.
  • the inorganic film may further contain nitrogen.
  • the protective layer 131 has high transparency to visible light.
  • ITO, IGZO, and aluminum oxide are preferable because they are inorganic materials that have high transparency to visible light.
  • the protective layer 131 may be, for example, a laminated structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film, or a laminated structure of an aluminum oxide film and an IGZO film on the aluminum oxide film. By using this laminated structure, it is possible to prevent impurities (water, oxygen, etc.) from entering the EL layer side.
  • the protective layer 131 may have an organic film.
  • the protective layer 131 may have both an organic film and an inorganic film.
  • organic films that can be used for the protective layer 131 include the organic insulating film that can be used for the insulating layer 235.
  • connection portion 204 is provided in an area of the substrate 151 where the substrate 152 does not overlap.
  • the wiring 165 is electrically connected to the FPC 172 via the conductive layer 166 and the connection layer 242.
  • the wiring 165 is an example of a single-layer structure of a conductive layer obtained by processing the same conductive film as the conductive layer 112b.
  • the conductive layer 166 is an example of a single-layer structure of a conductive layer obtained by processing the same conductive film as the pixel electrodes 111R, 111G, and 111B.
  • the conductive layer 166 is exposed on the top surface of the connection portion 204. This allows the connection portion 204 and the FPC 172 to be electrically connected via the connection layer 242.
  • the display device 100A is a top emission type. Light emitted by the light emitting elements is emitted towards the substrate 152. It is preferable to use a material that is highly transparent to visible light for the substrate 152.
  • the pixel electrodes 111R, 111G, and 111B contain a material that reflects visible light, and the counter electrode (common electrode 115) contains a material that transmits visible light.
  • the light-shielding layer 117 can be provided between adjacent light-emitting elements, in the connection section 140, in the circuit section 164, etc.
  • a colored layer such as a color filter may be provided on the surface of substrate 152 facing substrate 151 or on protective layer 131.
  • a color filter By providing a color filter over the light-emitting element, the color purity of the light emitted from the pixel can be increased.
  • various optical members can be arranged on the outside of the substrate 152 (the surface opposite to the substrate 151).
  • the optical members include a polarizing plate, a retardation plate, a light diffusion layer (such as a diffusion film), an anti-reflection layer, and a light collecting film.
  • a surface protection layer such as an antistatic film that suppresses the adhesion of dust, a water-repellent film that makes it difficult for dirt to adhere, a hard coat film that suppresses the occurrence of scratches due to use, and an impact absorbing layer may be arranged on the outside of the substrate 152.
  • a glass layer or a silica layer As the surface protection layer, it is possible to suppress the occurrence of surface contamination and scratches, which is preferable.
  • DLC diamond-like carbon
  • AlO x aluminum oxide
  • a polyester-based material As the surface protection layer.
  • a polycarbonate-based material may be used as the surface protection layer.
  • a material with a high hardness for the surface protection layer it is preferable to use a material with a high hardness for the surface protection layer.
  • the substrates 151 and 152 may each be made of glass, quartz, ceramics, sapphire, resin, metal, alloy, semiconductor, or the like.
  • the substrate on the side from which light from the light-emitting element is extracted is made of a material that transmits the light. If a flexible material is used for the substrates 151 and 152, the flexibility of the display device can be increased, and a flexible display can be realized.
  • a polarizing plate may also be used for at least one of the substrates 151 and 152.
  • the substrates 151 and 152 may each be made of polyester resins such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc. At least one of the substrates 151 and 152 may be made of glass having a thickness sufficient to provide flexibility.
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • polyacrylonitrile resin acrylic resin
  • polyimide resin polymethyl methacrylate resin
  • a substrate with high optical isotropy has low birefringence (it can also be said that the amount of birefringence is small).
  • films with high optical isotropy include triacetyl cellulose (TAC, also known as cellulose triacetate) film, cycloolefin polymer (COP) film, cycloolefin copolymer (COC) film, and acrylic film.
  • curing adhesives such as photo-curing adhesives such as ultraviolet curing adhesives, reactive curing adhesives, heat curing adhesives, and anaerobic adhesives.
  • photo-curing adhesives such as ultraviolet curing adhesives, reactive curing adhesives, heat curing adhesives, and anaerobic adhesives.
  • These adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin.
  • materials with low moisture permeability such as epoxy resin are preferable.
  • Two-part mixed resins may also be used.
  • Adhesive sheets, etc. may also be used.
  • connection layer 242 may be an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), or the like.
  • Display device 100B The display device 100B shown in FIG. 17 is a display device of a bottom emission type in that it uses a light emitting element having an EL layer 113 common to the subpixels of each color and a colored layer (such as a color filter).
  • the main differences from the display device 100A are as follows. In the following description of the display device, the description of the same parts as those of the display device described above may be omitted.
  • Light emitted by the light-emitting element is emitted toward the substrate 151. It is preferable to use a material that is highly transparent to visible light for the substrate 151. On the other hand, the translucency of the material used for the substrate 152 does not matter.
  • the display device 100B shown in FIG. 17 has transistors 205D, 205R, 205G, and 205B (not shown), light-emitting elements 130R, 130G, and 130B, a colored layer 132R that transmits red light, a colored layer 132G that transmits green light, and a colored layer 132B that transmits blue light between substrates 151 and 152.
  • the light-emitting element 130R has a pixel electrode 111R, an EL layer 113 on the pixel electrode 111R, and a common electrode 115 on the EL layer 113.
  • the light emitted by the light-emitting element 130R is extracted as red light to the outside of the display device 100B via the colored layer 132R.
  • the light-emitting element 130G has a pixel electrode 111G, an EL layer 113 on the pixel electrode 111G, and a common electrode 115 on the EL layer 113.
  • the light emitted by the light-emitting element 130G is extracted as green light to the outside of the display device 100B via the colored layer 132G.
  • the light-emitting element 130B has a pixel electrode 111B, an EL layer 113 on the pixel electrode 111B, and a common electrode 115 on the EL layer 113.
  • the light emitted by the light-emitting element 130B is extracted as blue light to the outside of the display device 100B via the colored layer 132B.
  • Light-emitting elements 130R, 130G, and 130B each share an EL layer 113 and a common electrode 115.
  • a configuration in which a common EL layer 113 is provided for the subpixels of each color can reduce the number of manufacturing steps compared to a configuration in which a different EL layer is provided for each subpixel of each color.
  • the light-emitting elements 130R, 130G, and 130B shown in FIG. 17 emit white light.
  • the white light emitted by the light-emitting elements 130R, 130G, and 130B passes through the colored layers 132R, 132G, and 132B to obtain light of the desired color.
  • FIG. 17 shows an example in which the light-shielding layer 117 is provided on the substrate 151, the insulating layer 153 is provided on the light-shielding layer 117, and the transistors 205D, 205R, 205G, and 205B (not shown) are provided on the insulating layer 153.
  • the colored layers 132R, 132G, and 132B are provided on the insulating layer 218, and the insulating layer 235 is provided on the colored layers 132R, 132G, and 132B.
  • the pixel electrodes 111R, 111G, and 111B are each made of a material that is highly transparent to visible light. It is preferable to use a material that reflects visible light for the common electrode 115. In a bottom-emission display device, a low-resistance metal or the like can be used for the common electrode 115, so that voltage drops caused by the resistance of the common electrode 115 can be suppressed, and high display quality can be achieved.
  • the transistor of one embodiment of the present invention can be miniaturized and its occupation area can be reduced, so that in a display device with a bottom emission structure, the pixel aperture ratio can be increased or the pixel size can be reduced.
  • light-emitting elements 130R, 130G, and 130B When a microcavity is applied to light-emitting elements 130R, 130G, and 130B, they each emit light in which the light of a specific wavelength is intensified from the white light emitted by EL layer 113.
  • a light-emitting element has a microcavity applied in this way, if an EL layer that emits white light is applied, it will be called a light-emitting element that emits white light.
  • a light-emitting element that emits white light preferably includes two or more light-emitting layers.
  • light-emitting layers can be selected such that the emission colors of the two light-emitting layers are complementary to each other. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary to each other, a configuration can be obtained in which the light-emitting element as a whole emits white light.
  • the emission colors of the three or more light-emitting layers can be combined to obtain a configuration in which the light-emitting element as a whole emits white light.
  • the EL layer 113 preferably has, for example, a light-emitting layer having a light-emitting material that emits blue light, and a light-emitting layer having a light-emitting material that emits visible light with a longer wavelength than blue.
  • the EL layer 113 preferably has, for example, a light-emitting layer that emits yellow light, and a light-emitting layer that emits blue light.
  • the EL layer 113 preferably has, for example, a light-emitting layer that emits red light, a light-emitting layer that emits green light, and a light-emitting layer that emits blue light.
  • a tandem structure For light-emitting elements that emit white light, it is preferable to use a tandem structure. Specifically, a two-stage tandem structure having a light-emitting unit that emits yellow light and a light-emitting unit that emits blue light, a two-stage tandem structure having a light-emitting unit that emits red and green light and a light-emitting unit that emits blue light, a three-stage tandem structure having, in this order, a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green or green light, and a light-emitting unit that emits blue light, or a three-stage tandem structure having, in this order, a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green or green light, and red light, and a light-emitting unit that emits blue light, etc.
  • the number of layers and the order of colors of the light-emitting units can be, from the anode side, a two-layer structure of B and Y, a two-layer structure of B and light-emitting unit X, a three-layer structure of B, Y, and B, or a three-layer structure of B, X, and B.
  • the number of layers and the order of colors of the light-emitting layers in light-emitting unit X can be, from the anode side, a two-layer structure of R and Y, a two-layer structure of R and G, a two-layer structure of G and R, a three-layer structure of G, R, and G, or a three-layer structure of R, G, and R.
  • another layer may be provided between the two light-emitting layers.
  • the light-emitting elements 130R, 130G, and 130B shown in FIG. 17 may be configured to emit blue light.
  • the EL layer 113 has one or more light-emitting layers that emit blue light.
  • the blue light emitted by the light-emitting element 130B can be extracted.
  • a color conversion layer is provided between the light-emitting element 130R or the light-emitting element 130G and the substrate 151, so that the blue light emitted by the light-emitting element 130R or the light-emitting element 130G can be converted into light with a longer wavelength, and red or green light can be extracted.
  • a portion of the light emitted by the light-emitting element may pass through the color conversion layer without being converted.
  • the display device 100C shown in Fig. 18 is an example of a display device to which an MML (metal maskless) structure is applied.
  • the display device 100C has a light-emitting element manufactured without using a fine metal mask.
  • the layered structure from the substrate 151 to the insulating layer 235 and the layered structure from the protective layer 131 to the substrate 152 are similar to those of the display device 100A, and therefore descriptions thereof will be omitted.
  • light emitting elements 130R, 130G, and 130B are provided on insulating layer 235.
  • the light-emitting element 130R has a conductive layer 124R on the insulating layer 235, a conductive layer 126R on the conductive layer 124R, a layer 133R on the conductive layer 126R, a common layer 114 on the layer 133R, and a common electrode 115 on the common layer 114.
  • the light-emitting element 130R shown in FIG. 18 emits red light (R).
  • the layer 133R has a light-emitting layer that emits red light.
  • the layer 133R and the common layer 114 can be collectively referred to as an EL layer.
  • one or both of the conductive layer 124R and the conductive layer 126R can be referred to as a pixel electrode.
  • light-emitting element 130G has conductive layer 124G on insulating layer 235, conductive layer 126G on conductive layer 124G, layer 133G on conductive layer 126G, common layer 114 on layer 133G, and common electrode 115 on common layer 114.
  • Light-emitting element 130G shown in FIG. 18 emits green light (G).
  • Layer 133G has a light-emitting layer that emits green light.
  • light-emitting element 130B has conductive layer 124B on insulating layer 235, conductive layer 126B on conductive layer 124B, layer 133B on conductive layer 126B, common layer 114 on layer 133B, and common electrode 115 on common layer 114.
  • Light-emitting element 130B shown in FIG. 18 emits blue light (B).
  • Layer 133B has a light-emitting layer that emits blue light.
  • layers provided in an island shape for each light-emitting element are indicated as layer 133B, layer 133G, or layer 133R, and a layer shared by a plurality of light-emitting elements is indicated as common layer 114.
  • layers 133R, 133G, and 133B may be referred to as island-shaped EL layers or EL layers formed in an island shape, without including common layer 114.
  • Layer 133R, layer 133G, and layer 133B are separated from each other.
  • the EL layer in an island shape for each light-emitting element, it is possible to suppress leakage current between adjacent light-emitting elements. This makes it possible to prevent crosstalk caused by unintended light emission, and to realize a display device with extremely high contrast.
  • layers 133R, 133G, and 133B are all shown to have the same film thickness, but this is not limited to this. Each of layers 133R, 133G, and 133B may have a different film thickness.
  • the conductive layer 124R is electrically connected to the conductive layer 112b of the transistor 205R through openings provided in the insulating layer 106, the insulating layer 218, and the insulating layer 235.
  • the conductive layer 124G is electrically connected to the conductive layer 112b of the transistor 205G
  • the conductive layer 124B is electrically connected to the conductive layer 112b of the transistor 205B.
  • the conductive layers 124R, 124G, and 124B are formed to cover the openings provided in the insulating layer 235.
  • Layer 128 is embedded in the recesses of the conductive layers 124R, 124G, and 124B, respectively.
  • Layer 128 has the function of planarizing the recesses of conductive layers 124R, 124G, and 124B.
  • Conductive layers 126R, 126G, and 126B that are electrically connected to conductive layers 124R, 124G, and 124B are provided on conductive layers 124R, 124G, and 124B and layer 128. Therefore, the regions that overlap with the recesses of conductive layers 124R, 124G, and 124B can also be used as light-emitting regions, and the aperture ratio of the pixel can be increased. It is preferable to use a conductive layer that functions as a reflective electrode for conductive layer 124R and conductive layer 126R.
  • Layer 128 may be an insulating layer or a conductive layer.
  • Various inorganic insulating materials, organic insulating materials, and conductive materials can be used as appropriate for layer 128.
  • layer 128 is preferably formed using an insulating material, and is particularly preferably formed using an organic insulating material.
  • the organic insulating material that can be used for insulating layer 237 described above can be used for layer 128.
  • FIG. 18 shows an example in which the top surface of layer 128 has a flat portion, but the shape of layer 128 is not particularly limited.
  • the top surface of layer 128 can have at least one of a convex curved surface, a concave curved surface, and a flat surface.
  • the height of the upper surface of layer 128 and the height of the upper surface of conductive layer 124R may be the same or approximately the same, or may be different from each other.
  • the height of the upper surface of layer 128 may be lower or higher than the height of the upper surface of conductive layer 124R.
  • the end of the conductive layer 126R may be aligned with the end of the conductive layer 124R, or may cover the side of the end of the conductive layer 124R.
  • the ends of the conductive layer 124R and the conductive layer 126R preferably have a tapered shape.
  • the ends of the conductive layer 124R and the conductive layer 126R preferably have a tapered shape with a taper angle of less than 90°.
  • the layer 133R provided along the side of the pixel electrode has an inclined portion.
  • the conductive layers 124G, 126G and the conductive layers 124B, 126B are similar to the conductive layers 124R, 126R, so detailed description will be omitted.
  • conductive layer 126R The upper and side surfaces of conductive layer 126R are covered by layer 133R. Similarly, the upper and side surfaces of conductive layer 126G are covered by layer 133G, and the upper and side surfaces of conductive layer 126B are covered by layer 133B. Therefore, the entire area in which conductive layers 126R, 126G, and 126B are provided can be used as the light-emitting area of light-emitting elements 130R, 130G, and 130B, thereby increasing the aperture ratio of the pixel.
  • a portion of the top surface and the side surfaces of layers 133R, 133G, and 133B are covered with insulating layers 125 and 127.
  • a common layer 114 is provided on layers 133R, 133G, 133B, and insulating layers 125 and 127, and a common electrode 115 is provided on common layer 114.
  • Common layer 114 and common electrode 115 are each a continuous film provided in common to multiple light-emitting elements.
  • the insulating layer 237 shown in FIG. 16 and the like is not provided between the conductive layer 126R and the layer 133R.
  • the display device 100C does not have an insulating layer (also called a partition, bank, spacer, etc.) that contacts the pixel electrode and covers the upper end of the pixel electrode. Therefore, the distance between adjacent light-emitting elements can be made extremely narrow. This makes it possible to provide a high-definition or high-resolution display device.
  • a mask for forming the insulating layer is not required, which reduces the manufacturing cost of the display device.
  • each of the layers 133R, 133G, and 133B has a light-emitting layer.
  • Each of the layers 133R, 133G, and 133B preferably has a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the light-emitting layer.
  • each of the layers 133R, 133G, and 133B preferably has a light-emitting layer and a carrier block layer (hole block layer or electron block layer) on the light-emitting layer.
  • each of the layers 133R, 133G, and 133B preferably has a light-emitting layer, a carrier block layer on the light-emitting layer, and a carrier transport layer on the carrier block layer. Since the surfaces of the layers 133R, 133G, and 133B are exposed during the manufacturing process of the display device, by providing one or both of the carrier transport layer and the carrier block layer on the light-emitting layer, it is possible to suppress exposure of the light-emitting layer to the outermost surface and reduce damage to the light-emitting layer. This can improve the reliability of the light-emitting element.
  • the common layer 114 has, for example, an electron injection layer or a hole injection layer.
  • the common layer 114 may have an electron transport layer and an electron injection layer stacked together, or a hole transport layer and a hole injection layer stacked together.
  • the common layer 114 is shared by the light emitting elements 130R, 130G, and 130B.
  • Insulating layer 125 covers the sides of layers 133R, 133G, and 133B via insulating layer 125.
  • the side surfaces (and even parts of the top surfaces) of layers 133R, 133G, and 133B are covered with at least one of insulating layers 125 and 127, which prevents the common layer 114 (or common electrode 115) from coming into contact with the pixel electrodes and the side surfaces of layers 133R, 133G, and 133B, thereby preventing short circuits in the light-emitting elements. This improves the reliability of the light-emitting elements.
  • the insulating layer 125 contacts the side surfaces of the layers 133R, 133G, and 133B. By configuring the insulating layer 125 to contact the layers 133R, 133G, and 133B, peeling of the layers 133R, 133G, and 133B can be prevented, and the reliability of the light-emitting element can be improved.
  • the insulating layer 127 is provided on the insulating layer 125 so as to fill the recesses in the insulating layer 125. It is preferable that the insulating layer 127 covers at least a portion of the side surface of the insulating layer 125.
  • the gap between adjacent island-shaped layers can be filled, reducing the large unevenness of the surface on which layers (such as the carrier injection layer and the common electrode) are formed on the island-shaped layers, making it possible to make the surface flatter. This improves the coverage of the carrier injection layer, the common electrode, etc.
  • the common layer 114 and the common electrode 115 are provided on the layers 133R, 133G, and 133B, the insulating layer 125, and the insulating layer 127. Before the insulating layer 125 and the insulating layer 127 are provided, there is a step between the region where the pixel electrode and the island-shaped EL layer are provided and the region (region between the light-emitting elements) where the pixel electrode and the island-shaped EL layer are not provided. In the display device of one embodiment of the present invention, the step can be flattened by having the insulating layer 125 and the insulating layer 127, and the coverage of the common layer 114 and the common electrode 115 can be improved. Therefore, poor connection due to step disconnection can be suppressed. In addition, the step can be suppressed from locally thinning the common electrode 115 and increasing the electrical resistance.
  • the upper surface of the insulating layer 127 preferably has a highly flat shape.
  • the upper surface of the insulating layer 127 may have at least one of a flat surface, a convex curved surface, and a concave curved surface.
  • the upper surface of the insulating layer 127 preferably has a smooth convex curved shape with high flatness.
  • the insulating layer 125 can be an insulating layer having an inorganic material.
  • an inorganic insulating film such as an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film can be used for the insulating layer 125. Specific examples of these inorganic insulating films are as described above.
  • the insulating layer 125 may have a single layer structure or a laminated structure. In particular, aluminum oxide is preferable because it has a high selectivity with respect to the EL layer in etching and has a function of protecting the EL layer in the formation of the insulating layer 127.
  • the insulating layer 125 may have a laminated structure of a film formed by the ALD method and a film formed by the sputtering method.
  • the insulating layer 125 may have a laminated structure of, for example, an aluminum oxide film formed by the ALD method and a silicon nitride film formed by the sputtering method.
  • the insulating layer 125 preferably has a function as a barrier insulating layer against at least one of water and oxygen.
  • the insulating layer 125 preferably has a function of suppressing the diffusion of at least one of water and oxygen.
  • the insulating layer 125 preferably has a function of capturing or fixing (also called gettering) at least one of water and oxygen.
  • a barrier insulating layer refers to an insulating layer that has barrier properties.
  • barrier properties refer to a function of suppressing the diffusion of the corresponding substance (also called low permeability), or a function of capturing or fixing the corresponding substance (also called gettering).
  • the insulating layer 125 has a function as a barrier insulating layer or a gettering function, which makes it possible to suppress the intrusion of impurities (typically at least one of water and oxygen) that may diffuse from the outside into each light-emitting element. This configuration makes it possible to provide a highly reliable light-emitting element and further a highly reliable display device.
  • impurities typically at least one of water and oxygen
  • the insulating layer 125 has a low impurity concentration. This can prevent impurities from entering the EL layer from the insulating layer 125 and causing deterioration of the EL layer.
  • the impurity concentration in the insulating layer 125 it is possible to improve the barrier properties against at least one of water and oxygen.
  • the insulating layer 125 has a sufficiently low hydrogen concentration or a sufficiently low carbon concentration, and preferably both.
  • the insulating layer 127 provided on the insulating layer 125 has the function of flattening the unevenness of the insulating layer 125 formed between adjacent light-emitting elements. In other words, the presence of the insulating layer 127 has the effect of improving the flatness of the surface on which the common electrode 115 is formed.
  • an insulating layer containing an organic material can be suitably used.
  • the organic material it is preferable to use a photosensitive organic resin, for example, a photosensitive resin composition containing an acrylic resin.
  • acrylic resin does not only refer to polymethacrylic acid ester or methacrylic resin, but may refer to acrylic polymers in a broad sense.
  • the insulating layer 127 may be made of acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenol resin, or precursors of these resins. Also, the insulating layer 127 may be made of organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin. Also, a photoresist may be used as the photosensitive organic resin. Either a positive-type material or a negative-type material may be used as the photosensitive organic resin.
  • PVA polyvinyl alcohol
  • a photoresist may be used as the photosensitive organic resin. Either a positive-type material or a negative-type material may be used as the photosensitive organic resin.
  • the insulating layer 127 may be made of a material that absorbs visible light. By having the insulating layer 127 absorb the light emitted from the light-emitting element, it is possible to suppress leakage of light from the light-emitting element to an adjacent light-emitting element through the insulating layer 127 (stray light). This can improve the display quality of the display device. In addition, since the display quality can be improved without using a polarizing plate in the display device, it is possible to reduce the weight and thickness of the display device.
  • Materials that absorb visible light include materials containing pigments such as black, materials containing dyes, resin materials with light absorbing properties (such as polyimide), and resin materials that can be used in color filters (color filter materials).
  • resin materials that can be used in color filters color filter materials.
  • by mixing three or more colors of color filter materials it is possible to create a resin layer that is black or close to black.
  • Display device 100D In the above, an example in which a light emitting element is used as a display element has been shown, but hereinafter, a liquid crystal display device in which a liquid crystal element is used as a display element will be described.
  • the liquid crystal element of the display device can be of various configurations. Typically, a transmissive liquid crystal element using the VA (Vertical Alignment) mode, FFS (Fringe Field Switching) mode, or IPS (In-Plane Switching) mode can be used. In addition to transmissive liquid crystal elements, reflective or semi-transmissive liquid crystal elements may also be used. It is preferable that the display device is a normally black liquid crystal display device.
  • the VA mode can be MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, ASV (Advanced Super View) mode, etc.
  • the liquid crystal element may be one that employs various modes.
  • various modes For example, in addition to the VA mode, FFS mode, and IPS mode, it may be possible to use liquid crystal elements that employ TN (Twisted Nematic) mode, ASM (Axially Symmetrically Aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, ECB (Electrically Controlled Birefringence) mode, guest-host mode, etc.
  • TN Transmission Nematic
  • ASM Analy Symmetrically Aligned Micro-cell
  • OCB Optically Compensated Birefringence
  • FLC Fluorroelectric Liquid Crystal
  • AFLC AntiFerroelectric Liquid Crystal
  • ECB Electrodefringence
  • the liquid crystal display device is a display device that controls the transmission or non-transmission of light by utilizing the optical modulation action of polarized light and liquid crystal.
  • the optical modulation action of liquid crystal is controlled by an electric field (including a horizontal electric field, a vertical electric field, or an oblique electric field) applied to the liquid crystal.
  • Examples of liquid crystals that can be used in liquid crystal elements include thermotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, polymer dispersed liquid crystals (PDLC: Polymer Dispersed Liquid Crystal), polymer network liquid crystals (PNLC: Polymer Network Liquid Crystal), ferroelectric liquid crystals, and antiferroelectric liquid crystals.
  • liquid crystal materials exhibit cholesteric phases, smectic phases, cubic phases, chiral nematic phases, isotropic phases, and the like, depending on the conditions.
  • liquid crystal material either positive or negative liquid crystals may be used as the liquid crystal material, and the most suitable liquid crystal material may be used depending on the mode or design to be applied.
  • the display device 100D shown in FIG. 19 is an FFS mode liquid crystal display device.
  • Substrate 151 and substrate 152 are bonded together by adhesive layer 144.
  • Liquid crystal 262 is sealed in the area surrounded by substrate 151, substrate 152, and adhesive layer 144.
  • Polarizing plate 260a is located on the outer surface of substrate 152
  • polarizing plate 260b is located on the outer surface of substrate 151.
  • a backlight can be provided outside polarizing plate 260a or polarizing plate 260b.
  • Transistors 205D, 205R, 205G, and 205B (not shown), a connection portion 204, a spacer 224, and the like are provided on the substrate 151.
  • the transistor 205D is provided in the circuit portion 164, and the transistors 205R and 205G are provided in the display portion 162.
  • the conductive layer 112b of the transistors 205R and 205G is electrically connected to the pixel electrode 111 of the liquid crystal element 60.
  • the substrate 152 is provided with colored layers 132R and 132G, a light-shielding layer 117, an insulating layer 225, etc.
  • Transistors 205D, 205R, and 205G each have a conductive layer 112a, a conductive layer 112b, a semiconductor layer 108, a conductive layer 107, a conductive layer 109, an insulating layer 106, a conductive layer 104, and the like.
  • the conductive layer 112a functions as one of a source electrode and a drain electrode, and the conductive layer 112b functions as the other.
  • the conductive layer 107 functions as one of a source electrode and a drain electrode, and the conductive layer 109 functions as the other.
  • the conductive layer 104 functions as a gate electrode.
  • a part of the insulating layer 106 functions as a gate insulating layer.
  • transistors 205D, 205R, and 205G are covered with insulating layer 218.
  • Insulating layer 218 functions as a protective layer for transistors 205D, 205R, and 205G.
  • the subpixels of the display unit 162 each have a transistor, a liquid crystal element 60, and a colored layer.
  • a subpixel that emits red light has a transistor 205R, a liquid crystal element 60, and a colored layer 132R that transmits red light.
  • a subpixel that emits green light has a transistor 205G, a liquid crystal element 60, and a colored layer 132G that transmits green light.
  • a subpixel that emits blue light similarly has a transistor, a liquid crystal element 60, and a colored layer that transmits blue light.
  • the liquid crystal element 60 has a common electrode 115, a pixel electrode 111, and liquid crystal 262.
  • the common electrode 115 is provided on an insulating layer 218, and an insulating layer 214 is provided on the common electrode 115.
  • the pixel electrode 111 is provided on the insulating layer 214.
  • the pixel electrode 111 and the common electrode 115 transmit visible light.
  • the liquid crystal element 60 can be a transmissive liquid crystal element.
  • the orientation of the liquid crystal 262 can be controlled by the voltage applied between the pixel electrode 111 and the common electrode 115, and the optical modulation of the light can be controlled.
  • the intensity of the light emitted through the polarizing plate 260a can be controlled.
  • the colored layer absorbs light other than a specific wavelength range of the incident light, so that the extracted light is, for example, red light.
  • a linear polarizing plate may be used as the polarizing plate 260a, but a circular polarizing plate may also be used.
  • a circular polarizing plate for example, a laminate of a linear polarizing plate and a quarter-wave retardation plate may be used.
  • polarizer 260a When a circular polarizer is used as polarizer 260a, a circular polarizer may also be used as polarizer 260b, or a normal linear polarizer may be used.
  • the desired contrast can be achieved by adjusting the cell gap, orientation, drive voltage, etc. of the liquid crystal element used in liquid crystal element 60 according to the type of polarizer used for polarizers 260a and 260b.
  • connection portion 204 is provided in a region close to the end of the substrate 151.
  • the wiring 165 is electrically connected to the FPC 172 via the conductive layer 166 and the connection layer 242.
  • the wiring 165 is connected to the wiring 165 through an opening provided in the insulating layer 110.
  • the wiring 165 is formed from the same material and in the same process as the conductive layer 112a and the conductive layer 107, and the conductive layer 166 is formed from the same material and in the same process as the conductive layer 112b.
  • the pixel electrode 111 has a comb-like shape or a shape with slits in a plan view.
  • the pixel electrode 111 is disposed so as to overlap the common electrode 115. In the area overlapping the colored layer, there is a portion on the common electrode 115 where the pixel electrode 111 is not disposed.
  • both the pixel electrode 111 and the common electrode 115 may have a comb-like upper surface shape.
  • the pixel electrode 111 and the common electrode 115 are configured to partially overlap. This allows the capacitance between the pixel electrode 111 and the common electrode 115 to be used as a storage capacitance, eliminating the need to provide a separate capacitive element and increasing the aperture ratio of the display device.
  • an insulating layer 225 is provided to cover the colored layers 132R, 132G and the light-shielding layer 117.
  • the insulating layer 225 functions as an overcoat that prevents the components contained in the colored layers 132R, 132G, etc. from diffusing into the liquid crystal 262.
  • the insulating layer 225 may also function as a planarizing film.
  • the insulating layer 225 can be formed using an organic resin that is translucent.
  • an alignment film for controlling the alignment of the liquid crystal 262 may be provided on the surfaces of the pixel electrode 111, the insulating layer 214, the insulating layer 225, etc. that come into contact with the liquid crystal 262.
  • FIG. 20 shows cross-sectional views of three light-emitting elements and a connection part 140 of a display part 162 in each process.
  • Light-emitting elements can be fabricated using vacuum processes such as deposition, and solution processes such as spin coating and inkjet printing.
  • deposition methods include physical deposition (PVD) methods such as sputtering, ion plating, ion beam deposition, molecular beam deposition, and vacuum deposition, and chemical deposition (CVD).
  • PVD physical deposition
  • CVD chemical deposition
  • the functional layers included in the EL layer can be formed by deposition (vacuum deposition, etc.), coating methods (dip coating, die coating, bar coating, spin coating, spray coating, etc.), printing methods (inkjet printing, screen (screen printing), offset (lithographic printing), flexo (letterpress printing), gravure, microcontact, etc.), etc.
  • the island-like layer (layer including the light-emitting layer) produced by the method for producing a display device described below is not formed using a fine metal mask, but is formed by depositing the light-emitting layer over one surface and then processing it using photolithography. This makes it possible to realize a high-definition display device or a display device with a high aperture ratio, which has been difficult to achieve until now. Furthermore, since the light-emitting layers can be produced separately for each color, it is possible to realize a display device that is extremely vivid, has high contrast, and has high display quality. Furthermore, by providing a sacrificial layer on the light-emitting layer, damage to the light-emitting layer during the production process of the display device can be reduced, and the reliability of the light-emitting element can be increased.
  • a display device is composed of three types of light-emitting elements, one that emits blue light, one that emits green light, and one that emits red light
  • three types of island-shaped light-emitting layers can be formed by repeating the deposition of the light-emitting layer and processing by photolithography three times.
  • pixel electrodes 111R, 111G, and 111B and a conductive layer 123 are formed on a substrate 151 on which transistors 205R, 205G, and 205B (not shown) are provided (FIG. 20A).
  • the conductive film that becomes the pixel electrodes can be formed by, for example, sputtering or vacuum deposition. After forming a resist mask on the conductive film by a photolithography process, the conductive film can be processed to form pixel electrodes 111R, 111G, and 111B and conductive layer 123. The conductive film can be processed by one or both of wet etching and dry etching.
  • Film 133Bf (later layer 133B) includes a light-emitting layer that emits blue light.
  • an example is shown in which an island-shaped EL layer for a light-emitting element that emits blue light is first formed, and then an island-shaped EL layer for a light-emitting element that emits light of another color is formed.
  • the pixel electrodes of the light-emitting elements of the colors formed second or later may be damaged by the previous process. This may result in the driving voltage of the light-emitting elements of the colors formed second or later being higher.
  • an island-shaped EL layer of a light-emitting element that emits light with the shortest wavelength e.g., a blue light-emitting element.
  • the island-shaped EL layers in the order of blue, green, and red, or blue, red, and green.
  • the state of the interface between the pixel electrode and the EL layer in the blue light-emitting element can be kept good, and the drive voltage of the blue light-emitting element can be prevented from increasing. It also extends the life of the blue light-emitting element and improves its reliability. Furthermore, since the red and green light-emitting elements are less affected by increases in drive voltage compared to the blue light-emitting element, the drive voltage can be reduced and reliability can be improved for the entire display device.
  • the order in which the island-shaped EL layers are fabricated is not limited to the above, and may be, for example, red, green, and blue.
  • film 133Bf is not formed on conductive layer 123.
  • film 133Bf can be formed only in desired areas.
  • a light-emitting element can be manufactured through a relatively simple process.
  • the heat resistance temperature of the compounds contained in film 133Bf is preferably 100°C or higher and 180°C or lower, more preferably 120°C or higher and 180°C or lower, and more preferably 140°C or higher and 180°C or lower. This can improve the reliability of the light-emitting element.
  • the upper limit of the temperature allowed in the manufacturing process of the display device can be increased. This can broaden the range of choices for materials and formation methods used in the display device, making it possible to improve yield and reliability.
  • the heat resistance temperature can be, for example, any one of the glass transition point, softening point, melting point, thermal decomposition temperature, and 5% weight loss temperature, preferably the lowest temperature among these.
  • the film 133Bf can be formed, for example, by a deposition method, specifically a vacuum deposition method.
  • the film 133Bf may also be formed by a transfer method, a printing method, an inkjet method, a coating method, or other methods.
  • a sacrificial layer 118B is formed on the film 133Bf and on the conductive layer 123 (FIG. 20A).
  • a resist mask is formed by a photolithography process on the film that will become the sacrificial layer 118B, the film can be processed to form the sacrificial layer 118B.
  • the sacrificial layer 118B is preferably provided so as to cover the ends of each of the pixel electrodes 111R, 111G, and 111B. This means that the ends of the layer 133B formed in a later process will be located outside the ends of the pixel electrode 111B. This makes it possible to use the entire upper surface of the pixel electrode 111B as a light-emitting region, thereby increasing the aperture ratio of the pixel. In addition, since the ends of the layer 133B may be damaged in a process after the formation of the layer 133B, it is preferable that they are located outside the ends of the pixel electrode 111B, that is, are not used as a light-emitting region. This makes it possible to suppress variation in the characteristics of the light-emitting element and increase reliability.
  • layer 133B covers the top and side surfaces of pixel electrode 111B, each process after the formation of layer 133B can be performed without pixel electrode 111B being exposed. If the end of pixel electrode 111B is exposed, corrosion may occur during an etching process or the like. By suppressing corrosion of pixel electrode 111B, the yield and characteristics of the light-emitting element can be improved.
  • the sacrificial layer 118B is also preferable to provide at a position that overlaps the conductive layer 123. This makes it possible to prevent the conductive layer 123 from being damaged during the manufacturing process of the display device.
  • a film that is highly resistant to the processing conditions of the film 133Bf specifically, a film that can increase the etching selectivity with respect to the film 133Bf, is used.
  • the sacrificial layer 118B is formed at a temperature lower than the heat resistance temperature of each compound contained in the film 133Bf.
  • the substrate temperature when forming the sacrificial layer 118B is typically 200°C or less, preferably 150°C or less, more preferably 120°C or less, more preferably 100°C or less, and even more preferably 80°C or less.
  • the deposition temperature of sacrificial layer 118B can be made high, which is preferable.
  • the substrate temperature when forming sacrificial layer 118B can be set to 100°C or higher, 120°C or higher, or 140°C or higher.
  • the higher the deposition temperature the denser the inorganic insulating film can be and the higher the barrier properties can be. Therefore, by depositing the sacrificial layer at such a temperature, damage to film 133Bf can be further reduced, and the reliability of the light-emitting element can be improved.
  • each of the other layers e.g., insulating film 125f
  • film 133Bf the deposition temperature of each of the other layers (e.g., insulating film 125f) formed on film 133Bf.
  • the sacrificial layer 118B can be formed by, for example, sputtering, ALD (including thermal ALD and PEALD), CVD, or vacuum deposition. It may also be formed by using the wet film formation method described above.
  • the sacrificial layer 118B (if the sacrificial layer 118B has a laminated structure, the layer provided in contact with the film 133Bf) is preferably formed using a formation method that causes less damage to the film 133Bf. For example, it is preferable to use the ALD method or the vacuum deposition method rather than the sputtering method.
  • the sacrificial layer 118B can be processed by wet etching or dry etching. It is preferable to process the sacrificial layer 118B by anisotropic etching.
  • the wet etching method By using the wet etching method, damage to the film 133Bf during processing of the sacrificial layer 118B can be reduced compared to when using the dry etching method.
  • a developer When using the wet etching method, it is preferable to use, for example, a developer, a tetramethylammonium hydroxide (TMAH) aqueous solution, dilute hydrofluoric acid, oxalic acid, phosphoric acid, acetic acid, nitric acid, or a mixed solution containing two or more of these.
  • TMAH tetramethylammonium hydroxide
  • a mixed acid-based chemical solution containing water, phosphoric acid, dilute hydrofluoric acid, and nitric acid may be used.
  • the chemical solution used in the wet etching process may be alkaline or acidic.
  • the sacrificial layer 118B may be, for example, one or more of a metal film, an alloy film, a metal oxide film, a semiconductor film, an inorganic insulating film, and an organic insulating film.
  • the sacrificial layer 118B can be made of metal materials such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, titanium, aluminum, yttrium, zirconium, and tantalum, or alloy materials containing such metal materials.
  • the sacrificial layer 118B can be made of metal oxides such as In-Ga-Zn oxide, indium oxide, In-Zn oxide, In-Sn oxide, indium titanium oxide (In-Ti oxide), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide), and indium tin oxide containing silicon.
  • metal oxides such as In-Ga-Zn oxide, indium oxide, In-Zn oxide, In-Sn oxide, indium titanium oxide (In-Ti oxide), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide), and indium tin oxide containing silicon.
  • element M (wherein M is one or more elements selected from aluminum, silicon, boron, yttrium, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium) may be used in place of the above gallium.
  • semiconductor materials such as silicon or germanium can be used as materials that have high compatibility with semiconductor manufacturing processes.
  • oxides or nitrides of the above semiconductor materials can be used.
  • non-metallic materials such as carbon, or compounds thereof can be used.
  • metals such as titanium, tantalum, tungsten, chromium, and aluminum, or alloys containing one or more of these, can be used.
  • oxides containing the above metals, such as titanium oxide or chromium oxide, or nitrides such as titanium nitride, chromium nitride, or tantalum nitride can be used.
  • various inorganic insulating films that can be used for the protective layer 131 can be used as the sacrificial layer 118B.
  • oxide insulating films are preferable because they have higher adhesion to the film 133Bf than nitride insulating films.
  • inorganic insulating materials such as aluminum oxide, hafnium oxide, and silicon oxide can be used for the sacrificial layer 118B.
  • an aluminum oxide film can be formed as the sacrificial layer 118B using the ALD method. Using the ALD method is preferable because it can reduce damage to the base (particularly the film 133Bf).
  • the sacrificial layer 118B can be a laminated structure of an inorganic insulating film (e.g., an aluminum oxide film) formed using the ALD method and an inorganic film (e.g., an In-Ga-Zn oxide film, a silicon film, or a tungsten film) formed using the sputtering method.
  • an inorganic insulating film e.g., an aluminum oxide film
  • an inorganic film e.g., an In-Ga-Zn oxide film, a silicon film, or a tungsten film
  • the same inorganic insulating film can be used for both the sacrificial layer 118B and the insulating layer 125 to be formed later.
  • an aluminum oxide film formed by ALD can be used for both the sacrificial layer 118B and the insulating layer 125.
  • the same film-forming conditions can be applied to the sacrificial layer 118B and the insulating layer 125, or different film-forming conditions can be applied to each of them.
  • the sacrificial layer 118B can be an insulating layer with high barrier properties against at least one of water and oxygen.
  • the sacrificial layer 118B is a layer that is removed in most or all in a later process, it is preferable that it is easy to process. Therefore, it is preferable to form the sacrificial layer 118B under conditions where the substrate temperature during film formation is lower than that of the insulating layer 125.
  • an organic material may be used for the sacrificial layer 118B.
  • the organic material may be a material that is soluble in a solvent that is chemically stable with respect to at least the film located at the top of the film 133Bf.
  • a material that dissolves in water or alcohol is preferably used.
  • the sacrificial layer 118B may be made of an organic resin such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, alcohol-soluble polyamide resin, or a fluororesin such as a perfluoropolymer.
  • PVA polyvinyl alcohol
  • polyvinyl butyral polyvinylpyrrolidone
  • polyethylene glycol polyglycerin
  • pullulan polyethylene glycol
  • polyglycerin polyglycerin
  • pullulan polyethylene glycol
  • pullulan polyglycerin
  • water-soluble cellulose water-soluble cellulose
  • alcohol-soluble polyamide resin or a fluororesin such as a perfluoropolymer.
  • the sacrificial layer 118B can be a laminated structure of an organic film (e.g., a PVA film) formed using either a vapor deposition method or the above-mentioned wet film formation method, and an inorganic film (e.g., a silicon nitride film) formed using a sputtering method.
  • an organic film e.g., a PVA film
  • an inorganic film e.g., a silicon nitride film
  • a portion of the sacrificial film may remain as a sacrificial layer.
  • the film 133Bf is processed using the sacrificial layer 118B as a hard mask to form the layer 133B ( Figure 20B).
  • a laminated structure of layer 133B and sacrificial layer 118B remains on pixel electrode 111B.
  • Pixel electrodes 111R and 111G are exposed.
  • sacrificial layer 118B remains on conductive layer 123 in the region corresponding to connection portion 140.
  • the film 133Bf is preferably processed by anisotropic etching.
  • anisotropic dry etching is preferable.
  • wet etching may be used.
  • the process of forming film 133Bf, the process of forming sacrificial layer 118B, and the process of forming layer 133B are repeated at least twice, changing the light-emitting material, to form a layered structure of layer 133R and sacrificial layer 118R on pixel electrode 111R, and a layered structure of layer 133G and sacrificial layer 118G on pixel electrode 111G (FIG. 20C).
  • layer 133R is formed to include a light-emitting layer that emits red light
  • layer 133G is formed to include a light-emitting layer that emits green light.
  • the materials that can be used for sacrificial layer 118B can be applied to sacrificial layers 118R and 118G, and both may be the same material or different materials.
  • the side surfaces of layers 133B, 133G, and 133R are perpendicular or approximately perpendicular to the surface on which they are formed.
  • the angle between the surface on which they are formed and these side surfaces is 60 degrees or more and 90 degrees or less.
  • the distance between two adjacent layers of layers 133B, 133G, and 133R formed using photolithography can be narrowed to 8 ⁇ m or less, 5 ⁇ m or less, 3 ⁇ m or less, 2 ⁇ m or less, or 1 ⁇ m or less.
  • the distance can be defined as, for example, the distance between two adjacent opposing ends of layers 133B, 133G, and 133R. In this way, by narrowing the distance between the island-shaped EL layers, a display device with high definition and a large aperture ratio can be provided.
  • insulating film 125f which will later become insulating layer 125, is formed to cover the pixel electrode, layer 133B, layer 133G, layer 133R, sacrificial layer 118B, sacrificial layer 118G, and sacrificial layer 118R, and insulating layer 127 is formed on insulating film 125f ( Figure 20D).
  • the insulating film 125f it is preferable to form an insulating film having a thickness of 3 nm or more, 5 nm or more, or 10 nm or more, and 200 nm or less, 150 nm or less, 100 nm or less, or 50 nm or less.
  • the insulating film 125f is preferably formed, for example, by the ALD method.
  • the ALD method is preferable because it can reduce film formation damage and can form a film with high coating properties.
  • As the insulating film 125f it is preferable to form an aluminum oxide film, for example, by the ALD method.
  • the insulating film 125f may be formed using a sputtering method, a CVD method, or a plasma CVD method, which have a faster film formation speed than the ALD method. This allows a highly reliable display device to be manufactured with high productivity.
  • the insulating film that becomes the insulating layer 127 is preferably formed by the above-mentioned wet film formation method (e.g., spin coating) using, for example, a photosensitive resin composition containing an acrylic resin.
  • a heat treatment also called pre-baking
  • visible light or ultraviolet light is irradiated to a part of the insulating film to expose the part.
  • development is performed to remove the exposed area of the insulating film.
  • a heat treatment also called post-baking
  • the insulating layer 127 shown in FIG. 20D can be formed.
  • the shape of the insulating layer 127 is not limited to the shape shown in FIG. 20D.
  • the upper surface of the insulating layer 127 can have one or more of a convex curved surface, a concave curved surface, and a flat surface.
  • the insulating layer 127 may cover the side surface of at least one end of the insulating layer 125, the sacrificial layer 118B, the sacrificial layer 118G, and the sacrificial layer 118R.
  • an etching process is performed using the insulating layer 127 as a mask to remove the insulating film 125f and parts of the sacrificial layers 118B, 118G, and 118R.
  • openings are formed in the sacrificial layers 118B, 118G, and 118R, respectively, and the top surfaces of the layers 133G, 133G, and 133R, and the conductive layer 123 are exposed.
  • parts of the sacrificial layers 118B, 118G, and 118R may remain in positions overlapping the insulating layer 127 and the insulating layer 125 (see sacrificial layers 119B, 119G, and 119R).
  • the etching process can be performed by dry etching or wet etching. If the insulating film 125f is formed using the same material as the sacrificial layers 118B, 118G, and 118R, this is preferable because the etching process can be performed in one go.
  • insulating layer 127 As described above, by providing insulating layer 127, insulating layer 125, sacrificial layer 118B, sacrificial layer 118G, and sacrificial layer 118R, it is possible to prevent connection failures caused by disconnected portions of common layer 114 and common electrode 115 between each light-emitting element, and increases in electrical resistance caused by locally thin portions of the film thickness. This allows the display device of one embodiment of the present invention to improve display quality.
  • the common layer 114 and the common electrode 115 are formed in this order on the insulating layer 127, the layer 133B, the layer 133G, and the layer 133R ( Figure 20F).
  • the common layer 114 can be formed by a method such as a deposition method (including a vacuum deposition method), a transfer method, a printing method, an inkjet method, or a coating method.
  • the common electrode 115 can be formed by, for example, sputtering or vacuum deposition. Alternatively, a film formed by deposition and a film formed by sputtering can be laminated together.
  • the island-shaped layers 133B, 133G, and 133R are not formed using a fine metal mask, but are formed by forming a film on one surface and then processing it, so that the island-shaped layers can be formed with a uniform thickness.
  • This makes it possible to realize a high-definition display device or a display device with a high aperture ratio.
  • the layers 133B, 133G, and 133R can be prevented from contacting each other in adjacent subpixels. Therefore, it is possible to prevent leakage current from occurring between the subpixels. This makes it possible to prevent crosstalk caused by unintended light emission, and to realize a display device with extremely high contrast.
  • the display device of one embodiment of the present invention can achieve both high definition and high display quality.
  • This embodiment can be implemented by combining at least a portion of it with other embodiments described in this specification.
  • the electronic device of this embodiment has a display device of one embodiment of the present invention in a display portion.
  • the display device of one embodiment of the present invention can easily achieve high definition and high resolution. Therefore, it can be used in the display portion of various electronic devices.
  • the semiconductor device of one embodiment of the present invention can also be applied to portions other than the display portion of an electronic device.
  • portions other than the display portion of an electronic device For example, by using the semiconductor device of one embodiment of the present invention in a control portion of an electronic device, it is possible to reduce power consumption, which is preferable.
  • Electronic devices include, for example, electronic devices with relatively large screens such as television sets, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.
  • the display device of one embodiment of the present invention can be used favorably in electronic devices having a relatively small display area because it is possible to increase the resolution.
  • electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), as well as wearable devices that can be worn on the head, such as VR devices such as head-mounted displays, glasses-type AR devices, and MR devices.
  • the display device of one embodiment of the present invention preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels).
  • an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels).
  • HD 1280 x 720 pixels
  • FHD (1920 x 1080 pixels
  • WQHD 2560 x 1440 pixels
  • WQXGA 2560 x 1600 pixels
  • 4K 3840 x 2160 pixels
  • 8K 8K
  • the pixel density (resolution) of the display device of one embodiment of the present invention is preferably 100 ppi or more, preferably 300 ppi or more, more preferably 500 ppi or more, more preferably 1000 ppi or more, more preferably 2000 ppi or more, more preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 7000 ppi or more.
  • the display device can support various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.
  • the electronic device of this embodiment may have a sensor (including the function of sensing, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • a sensor including the function of sensing, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • the electronic device of this embodiment can have various functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, etc., a function to execute various software (programs), a wireless communication function, a function to read out programs or data recorded on a recording medium, etc.
  • a function to display various information still images, videos, text images, etc.
  • a touch panel function a function to display a calendar, date or time, etc.
  • a function to execute various software (programs) a wireless communication function
  • a function to read out programs or data recorded on a recording medium etc.
  • FIG. 21A to 21D An example of a wearable device that can be worn on the head will be described using Figures 21A to 21D.
  • These wearable devices have at least one of the following functions: a function to display AR content, a function to display VR content, a function to display SR content, and a function to display MR content.
  • a function to display AR content a function to display AR content
  • VR content a function to display VR content
  • SR content a function to display SR content
  • MR content a function to display MR content
  • Electronic device 700A shown in FIG. 21A and electronic device 700B shown in FIG. 21B each have a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.
  • a display device can be applied to the display panel 751. Therefore, the electronic device can display images with extremely high resolution.
  • Electronic device 700A and electronic device 700B can each project an image displayed on display panel 751 onto display area 756 of optical member 753. Because optical member 753 is translucent, the user can see the image displayed in the display area superimposed on the transmitted image visible through optical member 753. Therefore, electronic device 700A and electronic device 700B are each electronic devices capable of AR display.
  • Electronic device 700A and electronic device 700B may be provided with a camera capable of capturing an image of the front as an imaging unit. Furthermore, electronic device 700A and electronic device 700B may each be provided with an acceleration sensor such as a gyro sensor, thereby detecting the orientation of the user's head and displaying an image corresponding to that orientation in display area 756.
  • an acceleration sensor such as a gyro sensor
  • the communication unit has a wireless communication device, and can supply video signals and the like via the wireless communication device.
  • a connector can be provided to which a cable through which a video signal and power supply potential can be connected.
  • Electronic device 700A and electronic device 700B are provided with batteries and can be charged wirelessly and/or wired.
  • the housing 721 may be provided with a touch sensor module.
  • the touch sensor module has a function of detecting that the outer surface of the housing 721 is touched.
  • the touch sensor module can detect a tap operation or a slide operation by the user and execute various processes. For example, a tap operation can execute processes such as pausing or resuming a video, and a slide operation can execute processes such as fast-forwarding or rewinding. Furthermore, by providing a touch sensor module on each of the two housings 721, the range of operations can be expanded.
  • touch sensors can be used as the touch sensor module.
  • various types can be adopted, such as the capacitance type, resistive film type, infrared type, electromagnetic induction type, surface acoustic wave type, and optical type.
  • a photoelectric conversion element When using an optical touch sensor, a photoelectric conversion element can be used as the light receiving element.
  • the active layer of the photoelectric conversion element can be made of either or both of an inorganic semiconductor and an organic semiconductor.
  • Electronic device 800A shown in FIG. 21C and electronic device 800B shown in FIG. 21D each have a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.
  • a display device can be applied to the display portion 820. Therefore, the electronic device can display images with extremely high resolution. This allows the user to feel a high sense of immersion.
  • the display unit 820 is provided inside the housing 821 at a position that can be seen through the lens 832. In addition, by displaying different images on the pair of display units 820, it is also possible to perform a three-dimensional display using parallax.
  • the electronic device 800A and the electronic device 800B can each be considered electronic devices for VR.
  • a user wearing the electronic device 800A or the electronic device 800B can view the image displayed on the display unit 820 through the lens 832.
  • Electric device 800A and electronic device 800B each preferably have a mechanism that can adjust the left-right positions of lens 832 and display unit 820 so that they are optimally positioned according to the position of the user's eyes. Also, it is preferable that they have a mechanism that adjusts the focus by changing the distance between lens 832 and display unit 820.
  • the attachment unit 823 allows the user to attach the electronic device 800A or electronic device 800B to the head. Note that in FIG. 21C and other figures, the attachment unit 823 is shaped like the temples of glasses, but is not limited to this. The attachment unit 823 only needs to be wearable by the user, and may be shaped like a helmet or band, for example.
  • the imaging unit 825 has a function of acquiring external information.
  • the data acquired by the imaging unit 825 can be output to the display unit 820.
  • An image sensor can be used for the imaging unit 825.
  • multiple cameras may be provided to support multiple angles of view, such as telephoto and wide angle.
  • a distance measuring sensor capable of measuring the distance to an object
  • the imaging unit 825 is one aspect of the detection unit.
  • the detection unit for example, an image sensor or a distance image sensor such as a LIDAR (Light Detection and Ranging) can be used.
  • LIDAR Light Detection and Ranging
  • the electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone.
  • a configuration having the vibration mechanism can be applied to one or more of the display unit 820, the housing 821, and the wearing unit 823. This makes it possible to enjoy video and audio simply by wearing the electronic device 800A without the need for separate audio equipment such as headphones, earphones, or speakers.
  • Each of electronic devices 800A and 800B may have an input terminal.
  • the input terminal can be connected to a cable that supplies a video signal from a video output device or the like, and power for charging a battery provided within the electronic device.
  • the electronic device of one embodiment of the present invention may have a function of wireless communication with the earphone 750.
  • the earphone 750 has a communication unit (not shown) and has a wireless communication function.
  • the earphone 750 can receive information (e.g., audio data) from the electronic device through the wireless communication function.
  • the electronic device 700A shown in FIG. 21A has a function of transmitting information to the earphone 750 through the wireless communication function.
  • the electronic device 800A shown in FIG. 21C has a function of transmitting information to the earphone 750 through the wireless communication function.
  • the electronic device may have an earphone unit.
  • the electronic device 700B shown in FIG. 21B has an earphone unit 727.
  • the earphone unit 727 and the control unit may be configured to be connected to each other by wire.
  • a portion of the wiring connecting the earphone unit 727 and the control unit may be disposed inside the housing 721 or the attachment unit 723.
  • electronic device 800B shown in FIG. 21D has earphone unit 827.
  • earphone unit 827 and control unit 824 can be configured to be connected to each other by wire.
  • Part of the wiring connecting earphone unit 827 and control unit 824 may be disposed inside housing 821 or mounting unit 823.
  • earphone unit 827 and mounting unit 823 may have magnets. This allows earphone unit 827 to be fixed to mounting unit 823 by magnetic force, which is preferable as it makes storage easier.
  • the electronic device may have an audio output terminal to which earphones or headphones can be connected.
  • the electronic device may also have one or both of an audio input terminal and an audio input mechanism.
  • a sound collection device such as a microphone can be used as the audio input mechanism.
  • the electronic device may be endowed with the functionality of a so-called headset.
  • both glasses-type devices such as electronic device 700A and electronic device 700B
  • goggle-type devices such as electronic device 800A and electronic device 800B
  • the electronic device of one embodiment of the present invention can transmit information to the earphones via wire or wirelessly.
  • the electronic device 6500 shown in FIG. 22A is a portable information terminal that can be used as a smartphone.
  • the electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and the like.
  • the display portion 6502 has a touch panel function.
  • the display device of one embodiment of the present invention can be applied to the display portion 6502.
  • FIG. 22B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.
  • a translucent protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.
  • the display panel 6511, the optical member 6512, and the touch sensor panel 6513 are fixed to the protective member 6510 by an adhesive layer (not shown).
  • a part of the display panel 6511 is folded back in the area outside the display unit 6502, and the FPC 6515 is connected to the folded back part.
  • An IC 6516 is mounted on the FPC 6515.
  • the FPC 6515 is connected to a terminal provided on a printed circuit board 6517.
  • the flexible display of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized.
  • the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted thereon while keeping the thickness of the electronic device small.
  • a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.
  • FIG. 22C shows an example of a television device.
  • a display unit 7000 is built into a housing 7101.
  • the housing 7101 is supported by a stand 7103.
  • a display device can be applied to the display portion 7000.
  • the television device 7100 shown in FIG. 22C can be operated using operation switches provided on the housing 7101 and a separate remote control 7111.
  • the display unit 7000 may be provided with a touch sensor, and the television device 7100 may be operated by touching the display unit 7000 with a finger or the like.
  • the remote control 7111 may have a display unit that displays information output from the remote control 7111.
  • the channel and volume can be operated using operation keys or a touch panel provided on the remote control 7111, and the image displayed on the display unit 7000 can be operated.
  • the television device 7100 is configured to include a receiver and a modem.
  • the receiver can receive general television broadcasts.
  • by connecting to a wired or wireless communication network via the modem it is also possible to carry out one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.
  • FIG. 22D shows an example of a notebook personal computer.
  • the notebook personal computer 7200 has a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, etc.
  • the display unit 7000 is incorporated in the housing 7211.
  • a display device can be applied to the display portion 7000.
  • Figures 22E and 22F show an example of digital signage.
  • the digital signage 7300 shown in FIG. 22E has a housing 7301, a display unit 7000, and a speaker 7303. It can also have LED lamps, operation keys (including a power switch or an operation switch), connection terminals, various sensors, a microphone, etc.
  • FIG. 22F shows digital signage 7400 attached to a cylindrical pole 7401.
  • Digital signage 7400 has a display unit 7000 that is provided along the curved surface of pole 7401.
  • a display device according to one embodiment of the present invention can be applied to the display portion 7000.
  • the larger the display unit 7000 the more information can be provided at one time. Also, the larger the display unit 7000, the more easily it catches people's attention, which can increase the advertising effectiveness of an advertisement, for example.
  • a touch panel By applying a touch panel to the display unit 7000, not only can images or videos be displayed on the display unit 7000, but the user can also intuitively operate it, which is preferable. Furthermore, when used to provide information such as route information or traffic information, the intuitive operation can improve usability.
  • the digital signage 7300 or the digital signage 7400 can be linked via wireless communication with an information terminal 7311 or an information terminal 7411 such as a smartphone carried by a user.
  • advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411.
  • the display on the display unit 7000 can be switched by operating the information terminal 7311 or the information terminal 7411.
  • the digital signage 7300 or the digital signage 7400 can also be made to run a game using the screen of the information terminal 7311 or the information terminal 7411 as an operating means (controller). This allows an unspecified number of users to participate in and enjoy the game at the same time.
  • the electronic device shown in Figures 23A to 23G has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function to sense, detect, or measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light), a microphone 9008, etc.
  • a display device of one embodiment of the present invention can be applied to the display portion 9001.
  • the electronic devices shown in Figures 23A to 23G have various functions. For example, they can have a function of displaying various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function of displaying a calendar, date or time, etc., a function of controlling processing by various software (programs), a wireless communication function, a function of reading and processing programs or data recorded on a recording medium, etc.
  • the functions of the electronic devices are not limited to these, and they can have various functions.
  • the electronic devices may have multiple display units.
  • the electronic devices may have a function of providing a camera or the like to capture still images or videos and store them on a recording medium (external or built into the camera), a function of displaying the captured images on the display unit, etc.
  • FIG. 23A is a perspective view showing a mobile information terminal 9101.
  • the mobile information terminal 9101 can be used as a smartphone, for example.
  • the mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like.
  • the mobile information terminal 9101 can display text and image information on multiple surfaces.
  • FIG. 23A shows an example in which three icons 9050 are displayed.
  • Information 9051 shown in a dashed rectangle can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming e-mail, SNS, telephone calls, etc., the title of e-mail or SNS, the sender's name, the date and time, the remaining battery level, and radio wave strength.
  • an icon 9050 or the like may be displayed at the position where the information 9051 is displayed.
  • Figure 23B is a perspective view showing a mobile information terminal 9102.
  • the mobile information terminal 9102 has a function of displaying information on three or more sides of the display unit 9001.
  • information 9052, information 9053, and information 9054 are each displayed on different sides.
  • a user can check information 9053 displayed in a position that can be observed from above the mobile information terminal 9102 while the mobile information terminal 9102 is stored in a breast pocket of clothes. The user can check the display without taking the mobile information terminal 9102 out of the pocket and decide, for example, whether or not to answer a call.
  • FIG. 23C is a perspective view showing a tablet terminal 9103.
  • the tablet terminal 9103 is capable of executing various applications such as mobile phone calls, e-mail, text browsing and creation, music playback, Internet communication, and computer games, for example.
  • the tablet terminal 9103 has a display unit 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front side of the housing 9000, operation keys 9005 as operation buttons on the left side of the housing 9000, and a connection terminal 9006 on the bottom.
  • FIG. 23D is a perspective view showing a wristwatch-type mobile information terminal 9200.
  • the mobile information terminal 9200 can be used, for example, as a smart watch (registered trademark).
  • the display surface of the display unit 9001 is curved, and display can be performed along the curved display surface.
  • the mobile information terminal 9200 can also make hands-free calls by communicating with, for example, a headset capable of wireless communication.
  • the mobile information terminal 9200 can also transmit data to and from other information terminals and charge itself via a connection terminal 9006. Charging may be performed by wireless power supply.
  • FIG. 23E to 23G are perspective views showing a foldable mobile information terminal 9201.
  • FIG. 23E is a perspective view of the mobile information terminal 9201 in an unfolded state
  • FIG. 23G is a perspective view of the mobile information terminal 9201 in a folded state
  • FIG. 23F is a perspective view of a state in the middle of changing from one of FIG. 23E and FIG. 23G to the other.
  • the mobile information terminal 9201 has excellent portability when folded, and has excellent display visibility due to a seamless wide display area when unfolded.
  • the display unit 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by hinges 9055.
  • the display unit 9001 can be bent with a radius of curvature of 0.1 mm or more and 150 mm or less.
  • This embodiment can be implemented by combining at least a portion of it with other embodiments described in this specification.

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Cited By (2)

* Cited by examiner, † Cited by third party
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WO2026069098A1 (ja) * 2024-09-27 2026-04-02 株式会社半導体エネルギー研究所 半導体装置、及び半導体装置の作製方法
WO2026078504A1 (ja) * 2024-10-10 2026-04-16 株式会社半導体エネルギー研究所 半導体装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59181668A (ja) * 1983-03-31 1984-10-16 Fujitsu Ltd 半導体装置
US20060017104A1 (en) * 2004-07-22 2006-01-26 Jae-Man Yoon Semiconductor device having a channel pattern and method of manufacturing the same
JP2017168764A (ja) * 2016-03-18 2017-09-21 株式会社ジャパンディスプレイ 半導体装置
WO2018203181A1 (ja) * 2017-05-01 2018-11-08 株式会社半導体エネルギー研究所 半導体装置
US20210391430A1 (en) * 2020-06-15 2021-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and manufacturing method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110544436B (zh) 2014-09-12 2021-12-07 株式会社半导体能源研究所 显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59181668A (ja) * 1983-03-31 1984-10-16 Fujitsu Ltd 半導体装置
US20060017104A1 (en) * 2004-07-22 2006-01-26 Jae-Man Yoon Semiconductor device having a channel pattern and method of manufacturing the same
JP2017168764A (ja) * 2016-03-18 2017-09-21 株式会社ジャパンディスプレイ 半導体装置
WO2018203181A1 (ja) * 2017-05-01 2018-11-08 株式会社半導体エネルギー研究所 半導体装置
US20210391430A1 (en) * 2020-06-15 2021-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2026069098A1 (ja) * 2024-09-27 2026-04-02 株式会社半導体エネルギー研究所 半導体装置、及び半導体装置の作製方法
WO2026078504A1 (ja) * 2024-10-10 2026-04-16 株式会社半導体エネルギー研究所 半導体装置

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