WO2024149573A1

WO2024149573A1 - Analog-to-digital converter with shared comparator readout

Info

Publication number: WO2024149573A1
Application number: PCT/EP2023/086367
Authority: WO
Inventors: Pieter De Wit; Adi Xhakoni; Ali Fekri
Original assignee: Ams Sensors Belgium Bvba
Priority date: 2023-01-13
Filing date: 2023-12-18
Publication date: 2024-07-18

Abstract

The present technology relates an analog-to-digital converter, ADC (100), comprising : a comparator (110) comprising a first comparator branch (110A) and second comparator branch (HOB), the first comparator branch (110A) comprising a plurality of stages (112A), each of the stages (112A) being configured to be sequentially connected to the second comparator branch (HOB), each stage (112A) comprising: a first input transistor (114A), and a capacitor (116A), a first terminal of the capacitor (116A) being configured to be directly connected to a pixel array (12), a second terminal of the capacitor (116A) being configured to be connected to a gate electrode of the first input transistor (H4A), wherein the second comparator branch (HOB) comprises a second input transistor (114B), a reference voltage (Vref) being connectable to the gate electrode of the second input transistor (114B), and a source region of the second input transistor (114B) is configured to be sequentially connected to a source region of the first input transistor (114A) of each of the stages (112A) so as to connect the second comparator branch (HOB) to a respective stage (112A).

Description

ANALOG-TO-DIGITAL CONVERTER WITH SHARED COMPARATOR READOUT [0001] An analog-to-digital converter (ADC) is a system that converts an analog signal, such as a sound picked up by a mi- crophone or light entering a digital camera, into a digital signal. More specifically, the ADC converts an analog input voltage or current to a digital number representing the magni- tude of the voltage or current, which may then be read and processed by a microcontroller. In this context, several ADCs with different ADC architectures are known and used as inte- grated circuits (ICs) in different systems. [0002] For example, an image sensor such as a CMOS image sen- sor (CIS) usually comprises an array of pixels and applies an ADC with a counter-ramp ADC architecture to read out the volt- ages of the pixels. Specifically, the array of pixels is ex- posed to radiation during an exposure period and, subsequent- ly, the signal value or pixel signal of each pixel is read from the array and converted by the ADC into a digital signal. [0003] In such image sensors, the pixels and readout circuitry often introduce random noise in the image, an unwanted side- product of image capture. For example, in a typical CIS, the readout occurs during two modes or phases. These two readout modes or phases correspond to two different signal levels typ- ically called the "reset" level and the actual "signal" level. By subtracting these two signal levels, any common mode noise, as well as some low frequency noise (1/f noise), between them can be eliminated. This is called correlated double sampling (CDS). For low noise image capture, CDS is widely used. [0004] These two signal levels are subsequently converted us- ing the ADC with a counter-ramp architecture. In such an ADC architecture, the signal level and a linearly sloping ramp signal are applied to a comparator and a counter starts count- ing at the start of the conversion mode or phase. At the crossing point of these two signals, the comparator toggles and the value of the counter is latched into a memory. The larger the voltage range of the input signal, the longer the conversion takes. [0005] In conventional image sensors, the reset level can show a large variation, e.g., due to variations of the pixel tran- sistors. A large variation in the reset level will require a longer ramping phase to convert the reset level. This will in- crease the conversion time of the ADC and reduce the frame rate of the image sensor. [0006] In addition, in view of decreasing pixel and readout pitches in a CIS, the ADC is commonly shared over several col- umns of the pixel array. When a shared ADC architecture is used, combined with analog CDS, then a sample and hold (S&H) stage is usually applied in front of the ADC. The S&H stage increases noise and needs to be fairly large (typically >1pF). Moreover, it is required per column, thereby limiting the ef- fectiveness of the ADC sharing approach. [0007] In view of the above, it is an object of the present invention to provide an improved ADC applicable for small pix- el and readout pitches, which provides small row noise and power consumption. SUMMARY [0008] According to embodiments, an analog-to-digital convert- er (ADC) comprises a comparator comprising a first comparator branch and second comparator branch, the first comparator branch comprising a plurality of stages, each of the stages being configured to be sequentially connected to the second comparator branch, each stage comprising: a first input tran- sistor, and a capacitor, a first terminal of the capacitor be- ing configured to be directly connected to a pixel array, a second terminal of the capacitor being configured to be con- nected to a gate electrode of the first input transistor, wherein the second comparator branch comprises a second input transistor, a reference voltage being connectable to the gate electrode of the second input transistor, and a source region of the second input transistor is configured to be sequential- ly connected to a source region of the first input transistor of each of the stages so as to connect the second comparator branch to a respective stage. [0009] In other words, the above ADC architecture comprises circuitries divided into a column specific circuitry (e.g., the stages including capacitors and first input transistors) and a column shared- circuitry (e.g., the second comparator branch including the second input transistor). Said concept enables to share area and minimizes the power consumption. For example, the stages are operated sequentially during a conver- sion, where only one stage is placed per shared readout in a readout path. This provides more flexibility to the circuit design, e.g., it enables a very compact analog readout. Fur- thermore, the sequential conversions reduce the power consump- tion per pixel column and minimize the effects of row noise. In addition, there is no need for a sample and hold stage and/or a PGA. [0010] The first terminal of the capacitor of each of the stages may be connected to an output of a corresponding column of the pixel array. Thus, corresponding pixel signals from the pixel array may be input into the ADC for conversion. [0011] The ADC may further comprise a column specific memory assigned to each column of the pixel array. This memory may store respective converted pixel signal values. [0012] The ADC may be operable in a calibration mode and a comparison mode. In the calibration mode, the gate electrode of the second input transistor may be connected to the refer- ence voltage. In the comparison mode, the gate electrode of the second input transistor may be connected to a ramp volt- age. The comparison mode may comprise a reset comparison mode and a signal comparison mode. [0013] In addition, further readout modes may be possible. For example, special readout schemes may be applied including a larger number of readouts per pixel (e.g., a reference HDR readout). [0014] In the calibration mode, the capacitor of the stage connected to the second comparator branch may store a charge corresponding to a pixel offset level of the column corre- sponding to the stage. This charge may be converted and used to account for a pixel offset noise. [0015] In the reset comparison mode, the ADC may convert a calibration value corresponding to the charge stored on the capacitor into a digital reset value. It may further store the digital reset value in the column specific memory sequentially for each of the stages. Specifically, the reset procedure may be performed directly for each column on a corresponding reset signal. This may alleviate the need for a sampling circuit. [0016] In the signal comparison mode, the ADC may convert an input signal of the column corresponding to the stage connect- ed to the second branch into a digital signal value. In great- er detail, the digital signal value may be based on the stored digital reset value. The digital signal value also may be stored in the column specific memory sequentially for each of the stages. [0017] More specifically, in the signal comparison mode, the digital signal value may be based on a difference between the converted input signal and the digital reset value. This may allow to remove the pixel offset level from each converted in- put signal as well as the ADC offset. For example, it may re- duce pixel and ADC 1/f noise. [0018] Moreover, the source region of the second input tran- sistor 114B may be connected to a source region of the first input transistor of each of the stages in a random order. That is, sequentially connecting the second input transistor to a source region of the first input transistor of each one of the plurality of stages comprises a random connection sequence. This may further minimize patterns in a corresponding output image. [0019] According to embodiments an ADC comprises: a comparator comprising a first comparator branch and second comparator branch, the first comparator branch comprising a plurality of first stages, the second comparator branch comprising a plu- rality of second stages, each of the first stages being con- figured to be connected to a corresponding one of the second stages, each first stage comprising: a first input transistor, and a capacitor, a first terminal of the capacitor being con- figured to be directly connected to a pixel array, a second terminal of the capacitor being configured to be connected to a gate electrode of the first input transistor, each second stage comprising: a second input transistor, a reference volt- age being connectable to the gate electrode of the second in- put transistor, wherein the ADC is operable in a calibration mode, a reset comparison mode, and a signal comparison mode, wherein in the calibration mode, source regions of the second input transistors are connected to source regions of corre- sponding ones of the first input transistors, and in the reset comparison mode and in the signal comparison mode, the source region of a selected one of the second input transistors is configured to be sequentially connected to the source regions of the first input transistors. [0020] This ADC architecture has similar effects as described for the first ADC configuration above. The difference with re- gard to the first ADC is that in this ADC, in the calibration mode, all of the first stages are connected to respective sec- ond stages. That is, the CDS process is performed parallel not sequentially. Thus, the CDS process is combined into a single phase for all columns. That allows to further reduce the row time for a readout process. [0021] In addition, the ADC may comprise a bias transistor. The source regions of the second input transistors may be con- nected to a drain region of the bias transistor. Furthermore, the source regions of the first input transistors also may be connected to the drain region of the bias transistor. [0022] According to embodiments, a bias current during the calibration mode may correspond to the bias current during the reset comparison mode and signal comparison mode. [0023] According to embodiments, each of the stages of the first comparator branch may comprise circuit elements compris- ing a second storage element. [0024] More specifically, the circuit elements may comprise a further input transistor. The second storage element may be a further capacitor connected to the further input transistor. [0025] In other words, each stage may have a mirrored counter- part. For example, the capacitor of a corresponding stage may preserve the pixel offset level as described above while the capacitor of its mirrored counterpart may be used to initiate a further readout of the next row. This results in a row time reduction and a higher framerate. An area overhead is thereby limited only to an input stage of the ADC. [0026] According to embodiments, the ADC may also be used in combination with a programmable gain amplifier (PGA). For ex- ample, the ADC may further comprise a PGA and a second capaci- tor that is shared between the stages of the first comparator branch of the ADC. A first terminal of the second capacitor may be sequentially connected to an output of each of the stages of the first comparator branch. And a second terminal of the second capacitor may be connected to an output the PGA. [0027] According to still further embodiments, the ADC may further comprise a bandwidth limitation (BW lim) circuit. The BW lim circuit may be sequentially connected to a predefined number of stages of the first comparator branch. Said circuit may further improve the performance of the ADC. [0028] According to still further embodiments, an ADC compris- es a group of comparators, an input terminal of each of the comparators being configured to be connected to a pixel group, the ADC further comprising a bandwidth limitation (BW lim) circuit, an output terminal of each of the comparators being configured to be sequentially connected to the BW lim circuit. Similar to the ADC architectures described above, also this configuration allows to reduce the area of the ADC, since only the part referring to the operational transconductance ampli- fier (OTA) and a feedforward cap of the ADC is non-shared while all remaining area hungry circuitry is shared. [0029] According to still further embodiments, the ADC com- prises a comparator, an input terminal of the comparator being connected to capacitors connected to a pixel group. There may be an ADC architecture where only the capacitors are column specific. [0030] In detail, the capacitors may be connected to the pixel group via a plurality of columns. That is, the capacitors may be column specific. The comparator may be shared between the plurality of columns. [0031] A pixel group may thereby correspond to one column, or to several columns. [0032] According to embodiments, an image sensor comprises a pixel array comprising a plurality of pixels arranged in rows and columns, an ADC according to any one of the ADCs described above, which is connected to the pixel array, and control cir- cuity configured to generate control signals for controlling a read out and resetting of the pixels. BRIEF DESCRIPTION OF THE DRAWINGS [0033] The accompanying drawings are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate the embodiments of the present inven- tion and together with the description serve to explain the principles. Other embodiments of the invention and many of the intended advantages will be readily appreciated, as they be- come better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numbers desig- nate corresponding similar parts. Fig. 1 is a schematic diagram illustrating an image sensor ac- cording to embodiments. Fig. 2 is a schematic diagram illustrating an ADC according to embodiments. Fig. 3A is a schematic diagram illustrating components of an ADC according to embodiments. Fig. 3B is a schematic diagram illustrating operation modes of the ADC according to embodiments. Fig. 4A is a schematic diagram illustrating components of an ADC according to embodiments. Fig. 4B is a schematic diagram illustrating operation modes of the ADC according to embodiments. Fig. 4C is a schematic diagram illustrating operation modes of the ADC according to embodiments. Fig. 5A is a schematic diagram illustrating an ADC according to further embodiments. Fig. 5B is a schematic diagram illustrating an input of a com- parator of the ADC according to the further embodiments. Fig. 5C is a schematic diagram illustrating components of the ADC according to the further embodiments. Fig. 5D is a schematic diagram illustrating operation modes of the ADC according to the further embodiments. Fig. 6A is a schematic diagram illustrating an ADC according to still further embodiments. Fig. 6B is a schematic diagram illustrating components of the ADC according to the still further embodiments. Fig. 7 is a schematic diagram illustrating components of an ADC according to yet further embodiments. Fig. 8 is a schematic diagram illustrating components of an ADC according to yet further embodiments. Fig. 9 is a schematic diagram illustrating components of an ADC according to yet embodiments. DETAILED DESCRIPTION [0034] In the following detailed description reference is made to the accompanying drawings, which form a part hereof and in which are illustrated by way of illustration specific embodi- ments in which the invention may be practiced. In this regard, directional terminology such as "top", "bottom", "front", "back", "over", "on", "above", "leading", "trailing" etc. is used with reference to the orientation of the Figures being described. Since components of embodiments of the invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope defined by the claims. [0035] The description of the embodiments is not limiting. In particular, elements of the embodiments described hereinafter may be combined with elements of different embodiments. [0036] As employed in this specification, the terms “coupled” and/or “electrically coupled” are not meant to mean that the elements must be directly coupled together - intervening ele- ments may be provided between the “coupled” or “electrically coupled” elements. The term “electrically connected” intends to describe a low-ohmic electric connection between the ele- ments electrically connected together. [0037] As used herein, the terms “having”, “containing”, “in- cluding”, “comprising” and the like are open ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles “a”, “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates other- wise. [0038] Fig. 1 is a schematic diagram illustrating an image sensor 10 according to embodiments. The image sensor 10 com- prises a pixel array 12 comprising a plurality of pixels 14 organized in a structure with one or more pixel groups (e.g., pixel columns Col[0], …, Col[N]) to form the image sensor 10. The grouping can be made column Col[0], …, Col[N] by column Col[0], …, Col[N], row Row[0], …, Row[N] by row Row[0], …, Row[N] or according to other criteria (e.g., to form sub- arrays). In the following, reference is made to pixels 14 ar- ranged in corresponding rows Row[0], … Row [N] and columns Col[0], …, Col[N] and the term "column" will be used as an ex- ample implementation of a "group" (of pixels 14). Hence the terms pixel group and pixel column and the terms group input and column input may be appreciated as being understood as be- ing exchangeable insofar as "group" is a generalization of a "column." [0039] In addition, the sensor 10 comprises an analog-to- digital converter (ADC) 100, 200, 300, 400 which is connected to the pixel array 12 and converts pixel signals in form of voltages (e.g., input voltages V_in) into a digital representa- tion. The image sensor 10 also comprises control circuitry 16 illustrated in a simplified manner in Fig. 1. The control cir- cuitry 16 may for example cause individual pixels 14 in a se- lected row Row[0], … Row[N] to be read out through the columns Col[0], …, Col[N], which provide the pixel signals to the ADC 100, 200, 300, 400 for conversion. In this context, the con- trol circuitry 16 may generate control signals such as row signals for respective rows Row[0], … Row [N] and column reset signals S_RST for respective columns Col[0], …, Col[N]. The re- set signals S_RST enable resetting respective pixels 14 to their initial state after a read out takes place (e.g., for clearing remaining signals of a last operation). However, the image sensor 10 shown in Fig. 1 is not limited to these circuitry elements and may include additional components and/or arrange- ments. Furthermore, the terms input signals and pixel signals may be used interchangeably. [0040] Common ADC architectures used for such an image sensor are based on a shared ADC and a column specific sample and hold circuitry (S&H). Such a configuration, however, implies a high readout noise due to very small sample and hold capaci- tors within the circuitry. This limits the effectiveness of the ADC sharing approach. Moreover, a comparator of the ADC is shared over all columns Col[0], …, Col[N], which increases the gain and offset effects associated with corresponding input transistors of the comparator. To address these issues, the present invention provides an improved configuration for an ADC with a shared comparator readout as explained in the fol- lowing. [0041] Fig. 2 is a schematic diagram of an ADC 100, 200 ac- cording to embodiments. The ADC 100, 200 is illustrated in a simplified manner in Fig. 2 and may comprise a comparator 110, 210, capacitors 116, 216, switches S2A, S1A, a counter circuit CT for deriving digital values, a buffer BUF, and a memory Mem[0], …, Mem[N] for storing these values. However, the ADC architecture is not limited to these elements and additional circuitry such as an analog column circuitry ACC may be pre- sent. The comparator 110, 210 may be comprised in an analog part P1 of the ADC 100, 200, while the counter circuit CT, the buffer BUF, and the memory Mem[0], …, Mem[N] may be included in a digital part P2 of the ADC 100, 200. Specific details re- garding the components of the ADC 100, 200 are shown in Figs. 3A and 4A described further below. [0042] For example, a pixel signal corresponding to a selected column Col[0], …, Col[N] and a linearly sloping ramp signal V_ramp may be applied to the comparator 110, 210 during a specif- ic operation mode of the ADC 100, 200 (which will be explained later on). The counter circuit CT may then start counting and stores a corresponding counter value in the buffer BUF. At the crossing point of these two signals, the comparator 110, 210 may toggle and the value of the counter circuit CT may be latched into the memory Mem[0], …, Mem[N] associated with the selected column Col[0], …, Col[N]. It is noted that various counter schemes may be applied in the ADC 100, 200. That is, the ADC architecture described in the present application may be independent of the counter approach used. [0043] As explained in detail in the following, the comparator 110, 210 of the ADC 100, 200 may be divided into column spe- cific and column shared circuitry. [0044] Fig. 3A is a schematic diagram illustrating components of the ADC 100 according to embodiments in more detail. The ADC 100 comprises the comparator 110 including a first compar- ator branch 110A and a second comparator branch 110B. The first comparator branch 110A comprises a plurality of stages 112A, which are indicated by dashed rectangles in Fig. 3A. Each of the stages 112A is configured to be sequentially con- nected to the second comparator branch 110B. In greater de- tail, each stage 112B may be associated with a corresponding column Col[0], …, Col[N] of the pixel array 12. That is, each of the stages 112A may comprise circuitry that is column spe- cific. Or stated differently, the first comparator branch 110A including the stages 112A represents a part or block of the ADC 100 that may be column-local. According to configurations, the full readout (i.e., converting the signals corresponding to the full set of columns Col[0], …, Col[N]) may comprise of multiple parallel ADC instances 100, which may each be con- nected to a subset of the columns Col[0], …, Col[N]. [0045] Each stage 112A comprises a first input transistor 114A and a capacitor 116A. A first terminal of the capacitor 116A is directly connected to the pixel array 12, or more specifi- cally, to a corresponding column Col[0], …, Col[N] of the pix- el array 12, which connects a corresponding stage 112A to a corresponding pixel 14. A second terminal of the capacitor 116A is connected to a gate electrode of the first input tran- sistor 114A. Each stage 112A may further comprise a feedback switch S1A, which, when closed, puts the corresponding stage 112A into a feedback loop for calibrating the capacitor 116A when it is connected to the second comparator branch 110B. The calibration procedure will be described in detail with refer- ence to Fig. 3B. Furthermore, each stage 112A may also include a selection switch S2A, which, when closed, connects a corre- sponding stage 112A to an output of the ADC 100. [0046] The second comparator branch 110B comprises a second input transistor 114B. A reference voltage V_ref is connectable to the gate electrode of the second input transistor 114B. The gate electrode may also be connectable to a ramp voltage V_ramp. The voltages V_ref, V_ramp may be selected depending on specific operation modes of the ADC 100, which also will be explained in detail with reference to Fig. 3B. [0047] In addition, a source region of the second input tran- sistor 114B is configured to be sequentially connected to a source region of the first input transistor 114A of each of the stages 112A so as to connect the second comparator branch 110B to a respective stage 112A of the first comparator branch 110A. [0048] This configuration avoids large amounts of row noise, since input signals (pixel signals) of each of the columns Col[0], …, Col[N] are converted sequentially. For example, when the pixel signals pertaining to the pixels 14 of a se- lected row Row[0], …, Row[N] are read out via the columns Col[0], …, Col[N] and converted one after the other by the comparator 110 (i.e., by the respective stages 112A connected consecutively to the second comparator branch 110B), the dif- ferent noise contributions of the reference voltage V_ref and the ramp voltage V_ramp across the various columns Col[0], …, Col[N] allow reducing a visual row noise. This differs from performing a parallel readout and conversion done in common ADC architectures, which result in a large row noise. [0049] According to embodiments, the source region of the sec- ond input transistor 114B may be configured to be connected in a random order to a source region of the first input transis- tor 114A of each of the stages 112A. That is the “sequential connection” may comprise various connection sequences includ- ing the random order. Randomizing a conversion sequence for the pixel signals and the corresponding columns Col[0], …, Col[N] may further minimize patterns in a corresponding output image. The selection of the columns Col[0], …, Col[N] may thereby be controlled by the control circuitry 16. [0050] As described above, the first terminal of the capacitor 116A of each of the stages 110A may be connected to an output of a corresponding column Col[0], …, Col[N] of the pixel array 12. In detail, the columns Col[0], …, Col[N] may directly con- nect the first terminals of the capacitors 116A to correspond- ing pixels 14 and provide respective input signals (pixel sig- nals) to the stages 110A. [0051] The output of the stages 110A may be connected to the digital part P2 of the ADC 100 as shown in Fig. 2. More spe- cifically, the conversion of the input signals (pixel signals) into corresponding digital representations for each stage 112A takes place in the digital part P2 of the ADC 100. [0052] In this regard, the ADC 100 may further comprise a col- umn specific memory Mem[0], …, Mem[N] assigned to each column Col[0], …, Col[N] of the image sensor 10 (not shown in Fig. 3A). Each consecutive stage 112A may comprise such a memory Mem[0], …, Mem[N] as illustrated in Fig. 2. The column specif- ic memory Mem[0], …, Mem[N] may be used to store digital reset values RST__conv and digital signal values SIG__conv resulting from converting input signals (pixel signals) of the columns Col[0], …, Col[N] via the ADC 100 as explained later on. [0053] Each of the stages 112A of the first comparator branch 110A may thus comprise column specific circuitry elements com- prising the capacitor 116A, the first input transistor 114A, and the column specific memory Mem[0], …, Mem[N]. The remain- ing part of the ADC 100 may be column-shared. This may refer to the remainder of the comparator 110 circuit elements as shown in Fig. 3A including the second comparator branch 110B and the digital part P2 of the ADC 100 such as the counter circuit CT shown in Fig. 2 (except the memory Mem[0], …, Mem[N]). This division of the comparator circuit 110, 110A, 110B into column specific and column-shared parts may allow to save area and energy. For example, each one of the stages 112A is placed only once per shared readout (i.e., connected to the second comparator branch 110B), which may result in a higher equivalent column pitch that is available for implementation. This provides more flexibility to the circuit design. Moreo- ver, the sequential conversion of the input signals, which is described in the following, may reduce an equivalent power consumption per pixel column Col[0], …, Col[N]. [0054] The ADC 100 may be operable in a calibration mode M_cal1 and a comparison mode M_comp1, which have been referred to above as operation modes of the ADC 100. The calibration mode M_cal1 comprises an analog correlated double sampling (CDS) process that is performed for each column Col[0], …, Col[N] sequen- tially. In the analog CDS process, pixel-specific offsets are removed before corresponding signals are applied to the input of the first input transistor 116A (e.g., by storing a pixel- specific voltage level on the capacitor 116A as explained in detail in the following paragraphs). The comparison mode M_comp1 may further comprise a digital CDS, in which a full A/D con- version is performed on both the RST and the SIG level, allow- ing to fully compensate the common noise and offset contribu- tions in both readouts. In general, CDS is a noise reduction technique in which a reference voltage of a pixel (i.e., the pixel’s voltage after it is reset) is subtracted from a signal voltage of the pixel (i.e., the pixel’s voltage at the end of integration, which corresponds to the pixel signal or input signal described above), to cancel thermal noise associated with a capacitance of the sensor 10. [0055] In greater detail, in the calibration mode M_cal1, each column Col[0], …, Col[N] receives sequentially a reset signal S_RST. This reset signal S_RST causes a corresponding pixel 14 to be reset to an initial state. Thereafter, a calibration of the first capacitor 116A to a pixel offset level takes place for each of the stages 112A. The duration of the calibration mode M_cal1 may thereby correspond to the summed time period in which the reset signal S_RST is set for each of the columns Col[0], …, Col[N]. [0056] To accomplish the calibration, the gate electrode of the second input transistor 114B may be connected to the ref- erence voltage V_ref. Furthermore, the feedback switch S1A for a selected one of the stages 112A may be closed such that the selected stage 112A of the first comparator branch 110A and the second comparator branch 110B are put into a feedback loop. In addition, the second terminal of the capacitor 116A of a selected one of the stages 112A may be connected to the reference voltage V_ref, e.g., via a further switch S3A as shown in Fig. 3A. During the calibration mode M_cal1, the capacitor 116A of the stage 112A connected to the second comparator branch 110B may store a charge corresponding to a pixel offset level of the column Col[0], …, Col[N] corresponding to the stage 112A. [0057] More specifically, closing the feedback switch S1A may allow to charge the capacitor 116A of a selected one of the stages 112A with a voltage corresponding to a difference be- tween the reference voltage V_ref and the voltage level provided from a corresponding pixel 14. For example, during the cali- bration mode M_cal1, a reset level voltage is provided as the voltage level from the pixel 14, which is input into a corre- sponding column Col[0], …, Col[N]. The voltage difference is stored on the capacitor 116A and is referred to in the follow- ing as the pixel offset level. This value is then converted, in the comparison mode M_comp1, into a digital reset value RST__conv for each stage 112A consecutively. [0058] Fig. 3B is a schematic diagram illustrating the opera- tion modes M_cal1, M_comp1 of the ADC 100 according to embodiments. As can be seen in Fig. 3B, in the calibration mode M_cal1, the respective columns Col[0], …, Col[N] (and correspondingly the stages 112A) are selected one after the other after a reset signal settling phase RST_set. The reference voltage V_ref applied to the first and second input transistors 114A, 114B is shown in the lower part of Fig. 3B. In this way, the capacitor 116A of each stage 110A may be calibrated to the respective pixel offset value associated with a corresponding row Row[0], …, Row[N]. This value may correspond to the pixel’s 14 voltage of the pixel 14 after it is reset (i.e., the difference between the reference voltage V_ref and the reset level voltage as de- scribed above). It is noted that while Fig. 3B shows an as- cending order of sequentially selected columns Col[0], …, Col[N] (respectively stages 112A), i.e., starting from [0] to [N], this is not limiting. Also a different (sequential) or- dering of the columns Col[0], …, Col[N] may be possible, for example by randomizing the column order [0], …, [N]. [0059] In view of the above, the calibration of the capacitors 116A of the comparator 110 may be performed directly on corre- sponding column reset signals S_RST. This may avoid the need for a sampling circuit, which further improves charge sharing is- sues and requires less area. [0060] In the comparison mode M_comp1, the gate electrode of the second input transistor 114B may be connected to the ramp voltage V_ramp. The comparison mode M_comp1 may comprise a reset comparison mode M_res1 and a signal comparison mode M_sig1 de- scribed in the following. [0061] In the reset comparison mode M_res1 the calibration value corresponding to the charge stored on the capacitor 114A is converted into a digital reset value RST__conv and stored in the column specific memory Mem[0], …, Mem[N] sequentially for each of the stages 112A. For example, the ramp voltage V_ramp for de- riving the digital reset value RST__conv is illustrated at the lower part of Fig. 3B in combination with the associated reset comparison mode M_res1. As is apparent from Fig. 3B, each of the columns Col[0], …, Col[N], and thus, the stages 112A, are se- lected successively and connected to the second comparator branch 110B. The derived digital reset value RST__conv is indi- cated in the bottom part of Fig. 3B. [0062] In the signal comparison mode M_sig1, an input signal (pixel signal) of the column Col[0], …, Col[N] corresponding to the stage 112A connected to the second branch 110B may be converted into a digital signal value SIG__conv. For example, the converted input signal may be further processed using the stored digital reset value RST__conv, which results in the digi- tal signal value SIG__conv. In other words, the digital signal value SIG__conv may be based on the stored digital reset value RST__conv. The digital signal value SIG__conv may also be stored in the column specific memory Mem[0], …, Mem[N] sequentially for each of the stages 112A. [0063] In greater detail, at the beginning of the signal com- parison mode M_sig1, the input signals (pixel signals) of each column Col[0], …, Col[N] may settle before the conversion into the respective digital signal value SIG__conv is performed. This is reflected in Fig. 3B by SIG_set and the corresponding con- stant voltage at the lower part of Fig. 3B associated with this phase. [0064] The digital signal value SIG__conv that is stored in the column specific memory Mem[0], …, Mem[N] may be based on a difference between the converted input signal and the digital reset value RST__conv. By this subtraction the pixel dependent offset may be removed from each converted input signal (pixel signal), which refers to the digital CDS process described above. [0065] According to further embodiments, it is also possible to store the digital reset value RST__conv and the converted in- put signal value into two independent memory elements (not shown in Fig. 3A). A subtraction of both values may then be done in a later digital data postprocessing process. [0066] The ADC 100 may further comprise a bias transistor 118, whose drain region is connected to the source region of the second input transistor 114B. Furthermore, the source regions of the first input transistors 114A of each stage 110A may al- so be configured to be sequentially connected to the drain re- gion of the bias transistor 118. A bias current I_bias for the ADC 100 shown in Fig. 3B may be the same for each mode M_cal1, M_res1, M_sig1. [0067] As described above, the source region of the second in- put transistor 114B may be connected to a source region of the first input transistor 114A of each of the stages 112A in a random order. It is noted that the term “sequential” as used in this application comprises different connection sequences and is not limited to random or consecutive orders. [0068] To summarize, the ADC 100 according to embodiments as described with reference to Figs. 3A and 3B may provide a com- pact analog readout circuit including an analog CDS part to remove pixel offsets. In addition, due to the minimal attenua- tion at the input of the comparator 110 there is little random noise. Furthermore, there is no need of a sample and hold cir- cuit, which results in low area consumption and avoids a sam- pling noise. Column-column or block-block effects (regarding a gain and/or offset) may be minimized as the main contributor to gain and offset variations of the comparator 110 (e.g., the first input transistor 114A) is fully column-local. That is, there only may be a random column-column offset and gain vari- ation. In addition, the calibration of the comparator 110 may be done directly on the column reset signal S_RST, which avoids the need for a sampling circuit and reduces area and/or charge sharing issues. The ADC 100 provides an optimized row noise as the plurality of pixels columns Col[0], …, Col[N] is converted sequentially. In greater detail, the varying noise contribu- tions of V_ref, V_ramp across the different pixel columns Col[0], …, Col[N] reduce a visual row noise appearance. The randomiza- tion of a conversion sequence may further minimize patterns in a resulting image. The ADC 100 may also provide an improved power efficiency of common bias blocks. There may be a low time fraction in which bias blocks are active and a low number of noise-sensitive analog reference levels (V_ref, V_ramp only). The ADC 100 may further be suitable for a small pixel pitch due to the maximum reduction of column specific circuitry. [0069] Fig. 4A is a schematic diagram illustrating components of an ADC 200 according to further embodiments. The ADC 200 comprises a comparator 210 comprising a first comparator branch 210A and second comparator branch 210B. The first com- parator branch 210A comprises a plurality of first stages 212A. The second comparator branch 210B comprises a plurality of second stages 212B. The first and second stages 212A, 212B are indicated by dashed rectangles in Fig. 4A. Similar to the ADC 100 shown in Fig. 3A, each one of the first stages 212A may be associated with a corresponding column Col[0], …, Col[N] of the pixel array 14. Furthermore, each of the first stages 212A is configured to be connected to a corresponding one of the second stages 212B. [0070] As described with reference to Fig. 3A, each first stage 212A comprises a first input transistor 214A and a ca- pacitor 216A. A first terminal of the capacitor 216A is di- rectly connected to the pixel array 12, or more specifically, to a corresponding column Col[0], …, Col[N] of the pixel array 12. A second terminal of the capacitor 216A is connected to a gate electrode of the first input transistor 214A. Similar to the stages 112A of the ADC 100, each one of the first stages 212A of the ADC 200 comprises a feedback switch S1A, which, when closed, puts a corresponding first stage 212A connected to a corresponding second stage 212B into a feedback loop for calibrating the capacitor 216A of the corresponding first stage 212A. Furthermore, each first stage 212A may also in- clude a selection switch S2A, which, when closed, connects a corresponding first stage 212A to an output of the ADC 200. [0071] Each second stage 212B comprises a second input tran- sistor 214B. A reference voltage V_ref is connectable to the gate electrode of the second input transistor 214B. The gate electrode may also be connectable to a ramp voltage V_ramp. The voltages V_ref, V_ramp may be selected depending on specific opera- tion modes of the ADC 200. For example, the ADC 200 is opera- ble in a calibration mode M_cal2, a reset comparison mode M_res2, and a signal comparison mode M_sig2. [0072] In the calibration mode M_cal2, source regions of the sec- ond input transistors 214 are connected to source regions of corresponding ones of the first input transistors 214A. As de- scribed above with regard to the ADC 100, in the calibration mode M_cal2, an analog CDS process is performed for each one of the first stages 212A. That is, the capacitors 216A of the first stages 212A may be calibrated to a pixel offset level. [0073] The difference with respect to the calibration mode M_cal1 performed in the ADC 100 illustrated in Fig. 3A is that in the calibration mode M_cal2 of the ADC 200, each source region of the first input transistor 214A is connected to a respective one of the second input transistors 214B in parallel and not se- quentially. This is further indicated in Fig. 4B, which illus- trates the operation modes of the ADC 200 according to embodi- ments. As can be seen, in the calibration mode M_cal2, all of the first stages 212A are selected and connected to the second stages 212B and to their associated columns Col[0], …, Col[N]. It is noted that the initial settling phases RST_set and SIG_set have been omitted in Figs. 4B and 4C for simplicity, but they may be present similar as shown in Fig. 3B. [0074] Furthermore, in the reset comparison mode M_res2 and in the signal comparison mode M_sig2, the source region of a select- ed one of the second input transistors 214B is configured to be sequentially connected to a selected one of the source re- gions of the first input transistors 214A. More specifically, during the modes M_res2 and M_sig2 only the selected second stage 212B is sequentially connected to a selected one of the first stages 212A. Fig. 4B shows an ascending order. However, a dif- ferent (sequential) read out of the columns Col[0], …, Col[N] may be possible, for example by randomizing the column order [0], …, [N]. [0075] The effects of this ADC configuration are similar to the one of the ADC 100 discussed above. In addition, the ADC 200 enables to further reduce the row time as a column- sequential CDS operation is combined into a single phase for all columns Col[0], …, Col[N]. In other words, the conversion is still performed sequentially, only the CDS procedure is done for all first stages 212A at the same time. [0076] The ADC 200 may further comprise a bias transistor 218 as shown in Fig. 4A. The source regions of the second input transistors 214B and the source regions of the first input transistors 214A may both be connected to a drain region of the bias transistor 218. [0077] Fig. 4B shows in the lower part the applied bias cur- rent I_bias in each respective mode M_cal2, M_res2, M_sig2. As can be seen from Fig. 4B, the bias current I_bias may be increased dur- ing the calibration mode M_cal2 (e.g., by N times, according to the number of columns Col[0], …, Col[N]) and may be the same for the remaining modes M_res2, M_sig2. [0078] According to further embodiments, it is also possible that the bias current I_bias during the configuration mode M_cal2 may correspond to the bias current I_bias during the reset com- parison mode M_res2 and signal comparison mode M_sig2. This is il- lustrated in Fig. 4C. In other words, it is possible that the amount of the bias current I_bias does not change and remains the same for all modes M_cal2, M_res2, M_sig2. [0079] Fig. 5A is a schematic diagram illustrating the ADC 100, 200 according to further embodiments. The ADC 100, 200 may, in addition to the configurations shown in Figs. 2, 3A, and 4A, comprise further circuit elements such as second stor- age elements represented by capacitors 116’, 216’ in Fig. 5A. The timing and/or circuit variations described previously may also be applied to this scheme. [0080] Fig. 5B is a schematic diagram illustrating an input of the comparator 110, 210 of the ADC 100, 200 for a selected column Col[i] of the plurality of columns Col[0], …, Col[N]. As can be seen, the capacitor 116’, 216’ may be connected in parallel to the capacitor 116, 216. Furthermore, the capacitor 116’, 216’ may be connected to an input of a comparator stage 112A’, 212A’ which is shown in more detail in Fig. 5C for the ADC 100. Specifically, the capacitor 116’ may be connected to a further input transistor 114’ of an additional first compar- ator branch 112A’. [0081] In other words, each stage 112A, 212A may have a mir- rored stage 112A’, 212A’. This is indicated in Fig. 5C for the ADC 100, which illustrates the mirrored stage 112A’ (i.e., the mirrored counterpart of the stage 112A of Fig. 3A) according to the further embodiments. The original stages 112A, 212A are as described with reference to Figs. 3A to 4C. In this regard, also the memory Mem[0], …, Mem[N] may be duplicated (not shown in Figs. 5A and 5C). [0082] Comparing this embodiment to the previous embodiments, it is apparent that the previous embodiments use comparator input stages 110A, 210A and N memory elements Mem[0], …, Mem[N] for N pixel columns Col[0], …, Col[N]. This embodiment may use 2*N comparator input stages 110A, 110A’ and 2*N memory elements Mem[0], …, Mem[N] for N columns Col[0], …, Col[N]. [0083] Consequently, for a given pixel pitch, the layout size of a readout implementation according to this scheme may be larger compared to the previous embodiments (the allowed readout width = pixel pitch * N remains unchanged, but may comprise e a larger number of circuit elements, i.e., 2*N in- put stages 110A, 210A, and memory elements Mem[0], …, Mem[N] versus N input stages 112A, 212A and memory elements Mem[0], …, Mem[N] as previously), but at the advantage of a reduced row readout time (increased speed) due to a pipelined readout described in the following. [0084] Due to the configurations shown in Figs. 5A to 5D, the readout concept shown in Figs. 3A to 4C as explained above may be extended to reduce the readout time by pipelining during a column Col[0], …, Col[N] readout via the mirrored stages 112A’, 212A’. [0085] Typically, a large dead-time exists, in which a column Col[0], …, Col[N] needs to settle to a new value, or in which pixel control signals need to settle to a new value (e.g. a TX pulse). As explained above, a second capacitor 116’, 216’ may be added per column Col[0], …, Col[N] for each of the stages 112A, 212A. The first capacitor 112A, 212A may allow to pre- serve an analog calibration value (e.g., a pixel offset value) matching to a particular pixel row Row[0], …, Row[N]. [0086] The second capacitor 116A’, 216A’ of the mirrored stage 112A’ may then be used to initiate and/or partially readout a second pixel row Row[0], …, Row[N], while not disturbing the readout of the first pixel row Row[0], …, Row[N]. [0087] Fig. 5D is a schematic diagram illustrating operation modes M_cal1, M_res1, M_sig1 of the ADC 100 according to the further embodiments. The first line A1 shows the row readout from the pixel array 16 on the selected column Col[i] for the first two rows Row[0] and Row[1] of the plurality of rows Row[0], …, Row[N] in a simplified representation. The second line A2 in- dicates the selected ADC stages 112A, 112A’ for the respective column Col[i]. The third line A3 outlines the selected opera- tion modes M_cal1, M_res1, M_sig1 for the pixel row Row[0]. And the fourth line shows the operation modes M_cal1, M_res1, M_sig1 for the pixel row Row[1]. This scheme may be continued for the remain- ing rows Row[3], … Row[N]. As can be seen in Fig. 5D, the op- eration modes M_cal1 and M_res1 for the second pixel row Row[1] are carried out before the these modes are finished in the first row Row[0]. It is noted that a similar operation applies to the ADC 200. [0088] In other words, via the mirrored stage 112A’, 212A’ it may be possible to start signal processing already on the next row Row[0], …, Row[N], while signal processing of the first one is not yet finished. This may result in a further row time reduction in the readout process and a higher framerate. In this regard, the configuration shown in Figs. 5A to 5D may be applicable also to different types of pixels 14 (e.g., voltage domain global shutter pixels (V-GS), charge domain global shutter pixels (Q-GS), rolling shutter pixels (RS)). [0089] According to still further embodiments, the ADC 100, 200 may further comprise a programmable gain amplifier (PGA) shared between the columns Col[0], …, Col[N] that controls a gain of the transistor 114B. In this still further embodi- ments, the ADC 100, 200 may have a shared input stage (e.g., N stages 112A used for N pixel columns Col[0], …, Col[N]). The comparator 110, 210 may be included in the PGA, which may be followed by a single analog ADC stage 150, 250. The analog ADC stage 150, 250 may sequentially convert all pixel columns Col[0], …, Col[N]. This is schematically illustrated in Fig. 6A, which presents the PGA including comparators 110, 210. As can be seen in more detail in Fig. 6B, the ADC 100, 200 may also comprise a second capacitor 20 that is shared between the stages 112A, 212A of the first comparator branch 110A of the ADC 100, 200 and serves as a feedback capacitor. In other words, in this scheme, sharing will be fully present inside the PGA. [0090] In greater detail, Fig. 6B is a schematic diagram il- lustrating components of the ADC 100 according to the still further embodiments illustrated in Fig. 6A (similar ones may apply to the ADC 200, which is not shown in Fig. 6B). A first terminal of the second capacitor 20 may be configured to be sequentially connected to an output of each of the stages 112A of the first comparator branch 110A. A second terminal of the second capacitor 20 may be connected to an output the PGA. [0091] Using the PGA in combination with the comparator con- figuration having column specific and column shared circuitry as described above with reference to Figs. 3A to 4C and illus- trated as well in Figs. 6A and 6B allows to save additional area. [0092] Fig. 7 shows a schematic diagram illustrating compo- nents of an ADC 300 according to yet further embodiments. The ADC 300 comprises a group of comparators 310. An input termi- nal of each of the comparators 310 is configured to be con- nected to a pixel group of a pixel array 12. The pixel group may correspond to one pixel column Col[0], …, Col[N], or sev- eral pixel columns Col[0], …, Col[N]. [0093] For example, the input terminal of each comparator 310 may be connected with a corresponding column Col[0], …, Col[N] of the pixel array 12 providing as input signal an input volt- age V_in in addition to a ramp voltage V_ramp. In Fig. 7, four columns and comparators 310 are depicted, but this number may change depending on circuit requirements. The ADC 300 further comprises a bandwidth limitation (BW lim) circuit 50 connected to the group of comparators 310. In greater detail, an output terminal of each of the comparators 310 is configured to be sequentially connected to the BW lim circuit 50. The addition- al blocks shown in Fig. 7 may pertain to further circuits of the ADC 300 such as a black sun protection circuit 60, a kick- back cancellation circuit 70, and a quantizer 80. These cir- cuits 60, 70, 80 may be present depending on specific require- ments. Furthermore, the circuit 50 may be shared over a spe- cific number of columns Col[0], …, Col[N]. The circuit 60 may be shared over a specific number of columns Col[0], …, Col[N]. The circuit 70 may be shared over a specific number of columns Col[0], …, Col[N]. And the circuit 80 may be shared over a specific number of columns Col[0], …, Col[N]. [0094] Each comparator 310 may comprise a capacitor 316 and a corresponding switch S300 to put the comparator 310 into a feedback loop. Similar to the ADC configurations 100, 200 as described above, the capacitors 316 and comparators 310 (i.e., the operational transconductance amplifier circuits (OTAs)) are column specific. The remaining circuits may be shared. The ADC 300 may have similar operation modes as described with reference to Fig. 3B and a detailed description is therefore omitted. [0095] This configuration may allow the use of smaller tran- sistors and provides a better offset. Like the configurations shown in Figs. 3A and 4A, the ADC 300 does not require a sam- ple and hold circuit. In addition, by dividing the area- intensive circuitry as described above, a general space saving is possible. [0096] Fig. 8 shows an ADC 400 according to embodiments, where only capacitors 416 are column specific, i.e., non-shared. The remaining circuit of a comparator 410 (i.e., the operational transconductance amplifier circuit (OTA) may be shared among a plurality of n columns Col[0], …, Col[N]. That is, N columns may share the OTA of the comparator 410. [0097] In detail, according to this configuration, the capaci- tors 416 may be connected to the pixel group 12 via a plurali- ty of columns Col[0] , …, Col[N]. As can be seen in Fig. 8, the capacitors 416 may be column specific, while the compara- tor 410 may be shared between the plurality of columns Col[0] , …, Col[N]. Similar to the configurations shown in Figs. 3A, 4A and 7, the ADC 400 does not require a column-specific sam- ple and hold circuit (which includes a noise drawback due to related kTC-sampling noise). This configuration may thus pro- vide analog-to-digital conversions with high performance (re- duced noise) and low area consumption since column-specific sample and hold stages are not required. [0098] The configuration of Fig. 8 may be applied to the ADC 300 illustrated in Fig. 7. In more detail, e.g., the circuit 50 may be shared by a group of M comparators 410. The circuit 60 may be shared by a group of M comparators 410. The circuit 70 may be shared by a group of M comparators 410. And the cir- cuit 80 may be shared by a group of M comparators 410. Fur- thermore, M×n columns Col[0], …, Col[N] may share circuits 50, 60, 70, and/or 80. [0099] The schemes outlined in Figs. 7 and 8 may be used in several circuit topologies. Specifically, the architecture in Fig 7, has the advantage of further area reduction of the ADC 300 as only the capacitor 316 is non-shared while all the oth- er components of the OTA are shared. [0100] According to yet further embodiments, the ADC 100, 200 described with reference to Figs. 3A to 4C also may comprise a bandwidth limitation (BW lim) circuit (not shown in Figs. 3A and 4A). The BW lim circuit 50 may be configured to be sequen- tially connected to a predefined number of stages 112A, 212A of the first comparator branch 110A. [0101] For example, this scheme is schematically illustrated in Fig. 9 for two stages 112A of ADC 100. In Fig. 9, the first stage 112A may be connected to the second comparator branch 112B. The BW lim circuit 50 may be arranged between the stages 112A. A corresponding output of the stages 112A is provided to the digital part P2 of the ADC 100 (not shown in Fig. 9). [0102] The BW lim circuit 50 according to embodiments may be an analog bandwidth limiting filter, intended to reduce ther- mal noise contributions, such to lower the noise contributions of the full ADCs 100, 200, 300. This bandwidth filter may typ- ically require some larger circuit elements (R, C). Thus, sharing these components may be very beneficial from layout implementation perspective, see for example Fig. 9. [0103] While embodiments of the invention have been described above, it is obvious that further embodiments may be imple- mented. For example, further embodiments may comprise any sub- combination of features recited in the claims or any sub- combination of elements described in the examples given above. Accordingly, this spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

LIST OF REFERENCES 10 image sensor 12 pixel array 14 pixel 16 control circuitry 50 bandwidth limitation circuit 60 sun protection circuit 70 kickback cancellation circuit 80 quantizer 100 ADC 200 ADC 300 ADC 400 ADC 110 comparator 210 comparator 310 comparator 410 comparator 110A first comparator branch 110A’ mirrored first comparator branch 110B second comparator branch 210A first comparator branch 210A’ mirrored first comparator branch 210B second comparator branch 112A stages 112A’ mirrored stages 212A first stages 212A’ mirrored first stages 212B second stages 150 analog ADC stage 250 analog ADC stage S1A feedback switch S2A selection switch S3A selection switch S1A’ mirrored feedback switch S2A’ mirrored selection switch S3A’ mirrored selection switch S300 feedback switch 114A first input transistor 114A’ first mirrored input transistor 214A first input transistor 214A’ first mirrored input transistor 114B second input transistor 214B second input transistor 116A capacitor 116A’ mirrored capacitor 216A capacitor 216A’ mirrored capacitor 316 capacitor 416 capacitor 118 bias transistor 218 bias transistor Col[0], …, Col[N] columns Row[0], …, Row[N] columns Mem[0], …, Mem[N] column specific memory Mem[0]’, …, Mem[N]’ mirrored column specific memory M_cal1 calibration mode M_cal2 calibration mode M_comp1 comparison mode M_res1 reset comparison mode M_res2 reset comparison mode M_sig1 signal comparison mode M_sig2 signal comparison mode RST_set reset signal settling phase SIG_set signal settling phase I_bias bias current S_RST reset signal V_ref reference voltage V_ramp ramp voltage digital reset value SIG__conv digital signal value CT counter circuit P1 analog part of ADC P2 digital part of ADC BUF Buffer

Claims

CLAIMS 1. An analog-to-digital converter, ADC (100), comprising: a comparator (110) comprising a first comparator branch (110A) and second comparator branch (110B), the first comparator branch (110A) comprising a plural- ity of stages (112A), each of the stages (112A) being config- ured to be sequentially connected to the second comparator branch (110B), each stage (112A) comprising: a first input transistor (114A), and a capacitor (116A), a first terminal of the capacitor (116A) being configured to be directly connected to a pixel array (12), a second terminal of the capacitor (116A) being configured to be connected to a gate electrode of the first input transistor (114A), wherein the second comparator branch (110B) comprises a second input transistor (114B), a reference voltage (V_ref) be- ing connectable to the gate electrode of the second input transistor (114B), and a source region of the second input transistor (114B) is configured to be sequentially connected to a source region of the first input transistor (114A) of each of the stages (112A) so as to connect the second comparator branch (110B) to a respective stage (112A).

2. The ADC (100) according to claim 1, wherein the first terminal of the capacitor (116A) of each of the stages (112A) is configured to be connected to an output of a corresponding column (Col[0], …, Col[N]) of the pixel array (12).

3. The ADC (100) according to claim 2, further comprising a column specific memory (Mem[0], …, Mem[N]) assigned to each column (Col[0], …, Col[N]) of the pixel array (12).

4. The ADC (100) according to claim 2 or 3 being operable in a calibration mode (M_cal1) and a comparison mode (M_comp1), wherein in the calibration mode (M_cal1), the gate electrode of the second input transistor (114B) is connected to the refer- ence voltage (V_ref), and in the comparison mode (M_comp1), the gate electrode of the second input transistor (114B) is connected to a ramp voltage (V_ramp), the comparison mode (M_comp1) comprising a reset comparison mode (M_res1) and a signal comparison mode (M_sig1).

5. The ADC (100) according to claim 4, wherein, in the calibration mode (M_cal1), the capacitor (116A) of the stage (112A) connected to the second comparator branch (110B) is configured to store a charge corresponding to a pixel offset level of the column (Col[0], …, Col[N]) corresponding to the stage (112A).

6. The ADC (100) according to claim 5, being configured to, in the reset comparison mode (M_res1), convert a calibration value corresponding to the charge stored on the capacitor (116A) into a digital reset value (RST__conv) and to store the digital reset value (RST__conv) in the column specific memory (Mem[0], …, Mem[N]) sequentially for each of the stages (112A).

7. The ADC (100) according to claim 6, being configured to, in the signal comparison mode (M_sig1), convert an input sig- nal of the column (M_sig1) corresponding to the stage (112A) con- nected to the second branch (110B) into a digital signal value (SIG__conv), the digital signal value (SIG__conv) being based on the stored digital reset value (RST__conv), wherein the digital signal value (SIG__conv) is stored in the column specific memory (Mem[0], …, Mem[N]) sequentially for each of the stages (112A).

8. The ADC (100) according to claim 7, wherein, in the signal comparison mode (M_sig1), the digital signal value (SIG__conv) is based on a difference between the converted input signal and the digital reset value

.

9. The ADC (100) according to any one of the preceding claims, wherein the source region of the second input transistor 114B is configured to be connected to a source region of the first input transistor 114A of each of the stages 112A in a random order.

10. An analog-to-digital converter, ADC (200), comprising: a comparator (210) comprising a first comparator branch (210A) and second comparator branch (210B), the first comparator branch (210A) comprising a plural- ity of first stages (212A), the second comparator branch (210B) comprising a plu- rality of second stages (212B), each of the first stages (212A) being configured to be connected to a corresponding one of the second stages (212B), each first stage (212A) comprising: a first input transistor (214A), and a capacitor (216A), a first terminal of the capacitor (216A) being configured to be directly connected to a pixel array (12), a second terminal of the capacitor (216A) being configured to be connected to a gate electrode of the first input transistor (214A), each second stage (212B) comprising: a second input transistor (214B), a reference voltage (V_ref) being connectable to the gate electrode of the second input transistor (214B), wherein the ADC (200) is operable in a calibration mode (M_cal2), a reset comparison mode (M_res2), and a signal comparison mode (M_sig2), wherein in the calibration mode (M_cal2), source regions of the second input transistors (214B) are connected to source re- gions of corresponding ones of the first input transistors (214A), and in the reset comparison mode (M_res2) and in the signal comparison mode (M_sig2), the source region of a selected one of the second input transistors (214B) is configured to be se- quentially connected to the source regions of the first input transistors (214A).

11. The ADC (200) according to claim 10, further comprising a bias transistor (218), wherein the source regions of the second input transistors (214B) are configured to be connected to a drain region of the bias transistor (218), and wherein the source regions of the first input transistors (214A) are configured to be connected to the drain region of the bias transistor (218).

12. The ADC (200) according to claim 11, wherein a bias current (I_bias) during the calibration mode (M_cal2) corresponds to the bias current (I_bias) during the reset comparison mode (M_res2) and signal comparison mode (M_sig2).

13. The ADC (100, 200) according to any one of the preced- ing claims, wherein each of the stages (112A, 212A) of the first comparator branch (110A, 210A) comprise circuit elements comprising a second storage element.

14. The ADC (100, 200) according to claim 13, wherein the circuit elements comprise a further input transistor (114’, 214’), wherein the second storage element is a further capaci- tor (116’, 216’) connected to the further input transistor (114’, 214’).

15. The ADC (100, 200) according to claims 1 to 11, wherein the ADC (100, 200) further comprises a programmable gain am- plifier, PGA, and a second capacitor (20) that is shared be- tween the stages (112A, 212A) of the first comparator branch (110A, 210A) of the ADC (100, 200), wherein a first terminal of the second capacitor (20) is configured to be sequentially connected to an output of each of the stages (112A, 212A) of the first comparator branch (110A, 210A), and wherein a second terminal of the second capacitor (20) is connected to an out- put the PGA.

16. The ADC (100, 200) according to any of the preceding claims, further comprising a bandwidth limitation, BW lim, circuit, the BW lim circuit being configured to be sequential- ly connected to a predefined number of stages (112A, 212A) of the first comparator branch (110A, 210A).

17. An analog-to-digital converter, ADC (300), comprising a group of comparators (310), an input terminal of each of the comparators (310) being configured to be connected to a pixel group (12) via a plurality of columns (column Col[0], …, Col[N]), the ADC (300) further comprising a bandwidth limita- tion, BW lim, circuit (50), an output terminal of each of the comparators (310) being configured to be sequentially connect- ed to the BW lim circuit (50), wherein each comparator (310) comprises a capacitor (316) and a corresponding switch (S300) to put the comparator (310) into a feedback loop.

18. An analog-to-digital converter, ADC (400), comprising a comparator (410), an input terminal of the comparator (410) being connected to capacitors (416) connected to a pixel group (12), wherein the capacitors (416) are connected to the pixel group (12) via a plurality of columns (Col[0] , …, Col[N]), wherein the capacitors (416) are column specific, and wherein the comparator (410) is shared between the plurality of col- umns (Col[0] , …, Col[N]).

19. The ADC (300, 400) according to claim 17 to 18, wherein a pixel group corresponds to one column Col[0], …, Col[N], or to several columns Col[0], …, Col[N].

20. An image sensor (10) comprising: a pixel array (12) comprising a plurality of pixels (14) arranged in rows (Row[0], …, Row[N]) and columns (Col[0], …, Col[N]); an ADC (100, 200, 300, 400) according to any one of the preceding claims 1 to 18 connected to the pixel array (12); and control circuity (16) configured to generate control signals for controlling a read out and resetting of the pixels (14).