WO2024148657A1

WO2024148657A1 - Write-leveling system and write-leveling method

Info

Publication number: WO2024148657A1
Application number: PCT/CN2023/077267
Authority: WO
Inventors: 黄克琴; 冀康灵
Original assignee: 长鑫存储技术有限公司
Priority date: 2023-01-12
Filing date: 2023-02-20
Publication date: 2024-07-18
Also published as: CN118366514A

Abstract

The present disclosure relates to a write-leveling system and a write-leveling method. The write-leveling system comprises: a controller and a storage chip, wherein the controller is used for providing a clock signal and a data gating signal for the storage chip; a first adjustment time is stored in the storage chip, and the first adjustment time is used for representing a path delay difference between the clock signal and the data gating signal within the storage chip; and on the basis of the first adjustment time, the controller adjusts a sending delay for sending the data gating signal to the storage chip, and continuously adjusts the sending delay until a trigger edge of the clock signal that is received by the storage chip is aligned with a trigger edge of the data gating signal.

Description

Write leveling system and write leveling method

cross reference

The present disclosure claims priority to Chinese patent application number 202310068043.2, filed on January 12, 2023, entitled “Write Leveling System and Write Leveling Method,” which is incorporated herein by reference in its entirety.

Technical Field

The present disclosure relates to the field of semiconductor circuit design, and in particular to a write leveling system and a write leveling method.

Background technique

For Synchronous Dynamic Random Access Memory (SDRAM), SDRAM supports "write-leveling" which allows the memory controller to compensate for the offset.

For the "write leveling function" of the memory, the storage controller repeatedly delays the data enable signal Dqs until it detects the transition of the identification signal from 0 to 1 (the clock signal ck and the data enable signal Dqs obtained by the memory are aligned at the detection point, and the generated identification signal changes from 0 to 1). Once the transition of the identification signal from 0 to 1 is detected, the storage controller locks the delay setting of the data enable signal Dqs. At this time, the memory realizes the alignment of the clock signal ck and the data enable signal Dqs, and completes write leveling.

Summary of the invention

An embodiment of the present disclosure provides a write leveling system, including: a controller and a memory chip; the controller is used to provide a clock signal and a data enable signal to the memory chip; a first adjustment time is stored in the memory chip, and the first adjustment time is used to characterize the path delay difference between the clock signal and the data enable signal inside the memory chip; the controller adjusts the sending delay of the data enable signal to the memory chip based on the first adjustment time, and continues to adjust the sending delay until the trigger edge of the clock signal received by the memory chip and the trigger edge of the data enable signal are aligned.

For example, the write leveling system also includes: when the trigger edge of the clock signal received by the storage chip is aligned with the trigger edge of the data selection signal, the storage chip feeds back an identification signal to the controller; the controller obtains a second adjustment time corresponding to the storage chip based on the identification signal, and the second adjustment time is used to characterize the transmission delay of the data selection signal by the controller when the trigger edge of the clock signal and the trigger edge of the data selection signal are aligned; the controller sends the data selection signal to the storage chip based on the second adjustment time.

For example, the controller acquires the second adjustment time corresponding to the memory chip based on the identification signal, including: when the controller receives the identification signal, based on the transmission delay of the current data selection signal, acquiring the second adjustment time corresponding to the memory chip.

For example, the controller adjusts the sending delay of a data selection signal to a corresponding storage chip based on a first adjustment time, and continuously adjusts the sending delay, including: the controller obtains the first adjustment time stored in the storage chip; the controller adjusts the sending delay of the data selection signal to the storage chip based on the first adjustment time; the controller continuously adjusts the sending delay of the data selection signal.

For example, the storage chip includes: a delay timing unit for storing a first adjustment time; the controller obtains the first adjustment time stored in the storage chip, including: the controller connects to the delay timing unit in the storage chip and obtains the first adjustment time stored in the delay timing unit.

For example, the delay timing unit is set based on redundant registers in the memory chip.

For example, the controller obtains the first adjustment time based on the mode register read command.

For example, the delay timing unit includes: a first processing unit, configured to obtain the path transmission time difference between the data selection signal and the clock signal in the memory chip; a second processing unit, connected to the first processing unit, configured to obtain the first adjustment time based on the path transmission time difference and the period of the data selection signal.

For example, the controller includes: multiple cascaded signal generating units, each level of signal generating unit includes: an AND logic circuit, a first input end is used to receive a write leveling enable signal, and a second input end is used to receive a delay identification signal, the delay identification signal is used to perform different delays on the data selection signal; an OR logic circuit, a first input end is connected to the output end of the AND logic circuit, and the second input end of the OR logic circuit in the first-level signal generating unit is used to receive the data selection signal; a trigger, an input end is connected to the output end of the OR logic circuit, the output end serves as the output end of the signal generating unit, and the clock end is used to receive the data selection signal; the second input end of the OR logic circuit in the non-first-level signal generating unit is connected to the output end of the trigger in the previous-level signal generating unit, and the output end of the trigger in the last-level signal generating unit is used to output the delayed data selection signal.

Another embodiment of the present disclosure also provides a write leveling method, which is applied to the write leveling system provided in the above embodiment, including: obtaining a first adjustment time corresponding to the memory chip, the first adjustment time being used to characterize the path delay difference between the clock signal and the data enable signal inside the memory chip; adjusting the sending delay of the data enable signal to the memory chip based on the first adjustment time, and continuously adjusting the sending delay until the trigger edge of the clock signal received by the memory chip and the trigger edge of the data enable signal are aligned, and simplifying the write leveling operation of the memory on the basis of removing the delay unit set on the transmission path of the data enable signal Dqs.

For example, continuously adjusting the sending delay until the trigger edge of the clock signal received by the memory chip is aligned with the trigger edge of the data selection signal, including: obtaining an identification signal fed back by the memory chip, wherein when the trigger edge of the clock signal received by the memory chip is aligned with the trigger edge of the data selection signal, the memory chip feeds back the identification signal to the controller; based on the identification signal, obtaining a second adjustment time corresponding to the memory chip, the second adjustment time is used to characterize the sending delay of the data selection signal when the trigger edge of the clock signal is aligned with the trigger edge of the data selection signal; and sending the data selection signal to the memory chip based on the second adjustment time.

For example, obtaining a first adjustment time corresponding to the memory chip includes: obtaining the first adjustment time based on a mode register read command received by the memory.

For example, obtaining the first adjustment time corresponding to the storage chip includes: obtaining the first adjustment time stored in the storage chip.

For example, a method for acquiring a first adjustment time stored in a memory chip includes: acquiring a path transmission time difference between a data selection signal and a clock signal in the memory chip; and acquiring the first adjustment time based on the path transmission time difference and a period of the data selection signal.

BRIEF DESCRIPTION OF THE DRAWINGS

One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

FIG1 is a schematic diagram of the system structure of a write leveling system provided by an embodiment of the present disclosure;

2 and 3 are schematic diagrams showing the meaning of the first adjustment time provided in an embodiment of the present disclosure;

FIG4 is a schematic diagram of a flow chart of a write leveling system provided by an embodiment of the present disclosure;

FIG5 is a schematic diagram of the structure of a controller provided by an embodiment of the present disclosure;

6 and 7 are schematic diagrams of the structure of a memory chip provided in an embodiment of the present disclosure;

8 and 9 are flowchart diagrams corresponding to the steps of a write leveling method provided in another embodiment of the present disclosure.

Detailed ways

As can be seen from the background technology, the rising edge of the clock signal ck received by each SDRAM needs to be aligned with the rising edge of the data strobe signal Dqs. The traditional write leveling solution needs to set a delay unit on the transmission path of the data strobe signal Dqs to match the delay difference of the clock signal ck and the data strobe signal Dqs in the transmission path inside the memory. However, the delay setting of the delay unit is The larger the setting, the greater the jitter caused in the write leveling characteristics, thereby increasing the difficulty of write leveling of the memory.

An embodiment of the present disclosure provides a write leveling system, which simplifies the write leveling operation of a memory on the basis of removing a delay unit provided on a transmission path of a data strobe signal Dqs.

It can be understood by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented. The division of the following embodiments is for the convenience of description and should not constitute any limitation on the specific implementation of the present disclosure. The various embodiments can be combined with each other and referenced to each other without contradiction.

FIG. 1 is a schematic diagram of the system structure of the write leveling system provided in the present embodiment, FIG. 2 and FIG. 3 are schematic diagrams of the meaning of the first adjustment time provided in the present embodiment, FIG. 4 is a schematic diagram of the flow of the write leveling system provided in the present embodiment, FIG. 5 is a schematic diagram of the structure of the controller provided in the present embodiment, and FIG. 6 and FIG. 7 are schematic diagrams of the structure of the storage chip provided in the present embodiment. The write leveling system provided in the present embodiment is described in detail below in conjunction with the accompanying drawings, as follows:

A write leveling system includes a controller and a storage chip.

1 , the write leveling system of the system of the present embodiment includes a controller 10 and a plurality of memory chips 20, wherein the controller 10 is used to provide a data selection signal Dqs and a clock signal ck to each memory chip 20; specifically, the data selection signal Dqs is set as “point to point transmission” between the controller 10 and the memory chip 20, and the “point to point transmission” means that the controller 10 directly transmits the data selection signal Dqs to each memory chip 20; the clock signal ck is set as “fly-by” between the controller 10 and the memory chip 20, and the “fly-by” means that the controller 10 provides a clock signal ck, and the clock signal ck is transmitted sequentially between the memory chips 20.

Since the clock signal ck and the data selection signal Dqs are transmitted in different ways, the delay between the clock signal ck and the data selection signal Dqs received by the memory chip 20 is very large. Therefore, it is necessary to delay the data selection signal Dqs sent to each memory chip 20 so that the clock signal ck and the data selection signal Dqs received by the memory chip 20 are aligned.

It should be noted that the write leveling system provided in this embodiment is applicable to volatile memories, such as dynamic random access memories DRAM, synchronous dynamic random access memories SDRAM, various generations of double data rate synchronous dynamic random access memories DDRx SDRAM, various generations of low power double data rate synchronous dynamic random access memories LPDDRx SDRAM, graphic double data rate synchronous dynamic random access memories GDDR SDRAM, thyristor random access memories TRAM, etc., and is also applicable to non-volatile memories, such as phase change random access memories PRAM, magnetic random access memories MRAM, resistive random access memories RRAM, etc.

With respect to the memory chip 20 provided in the present embodiment, referring to FIG2 and FIG3 , a first adjustment time is stored in the memory chip 20, and the first adjustment time is used to characterize the path delay difference between the clock signal ck and the data selection signal Dqs inside the memory chip 20, i.e., the delay difference between the data selection signal Dqs1 and the clock signal ck1 received by the DQ pad of the memory chip 20 and the data selection signal Dqs2 and the clock signal ck2 transmitted to the internal comparator 201, i.e., 丨tdqs2-tdqs1丨-丨tck2-tck1丨.

It should be noted that, referring to Figures 2 and 3, the "DQ pad" mentioned above is the pad 200 of the memory chip 20 for receiving the data selection signal Dqs and the clock signal ck.

Regarding the above-mentioned "path delay difference between the clock signal ck and the data selection signal Dqs inside the memory chip", refer to Figure 3, assuming that the clock signal received by the memory chip 20 is ck1, the data selection signal received by the memory chip 20 is Dqs1, and the time difference between ck1 and Dqs1 is t1; the data selection signal received by the comparator in the memory chip 20 is Dqs2, and the clock signal received by the comparator 201 is ck2; in the process of Dqs1 being transmitted to Dqs2, a new delay t2 is added, and in the process of ck1 being transmitted to ck2, a new delay t3 is added. At this time, the delay difference between ck2 and Dqs2 is t1+丨t2-t3丨.

Generally speaking, the transmission delay of the clock signal ck from the DQ pad to the comparator 201 is greater than that of the data strobe signal The transmission delay of Dqs from the DQ pad to the comparator 201 is t3＞t2, so a delay unit 202 is usually set on the transmission path of the data selection signal Dqs to balance the path delay difference between the clock signal ck and the data selection signal Dqs inside the memory chip 20 based on the delay unit 202, so that 丨t2-t3丨＝0, so that the delay between the clock signal ck received by the comparator 201 and the data selection signal Dqs is the same as the delay between the clock signal ck and the data selection signal Dqs received by the memory chip 20, that is, the data selection signal Dqs and the clock signal ck aligned by the comparator 201 are also aligned at the DQ pad; and the write leveling system provided in this embodiment balances the path delay difference between the clock signal ck and the data selection signal Dqs inside the memory chip 20 through the first adjustment time, so that 丨t2-t3丨＝0, so that the clock signal ck and the data selection signal Dqs received by the DQ pad are directly aligned.

Specifically, referring to Figure 4, the controller 10 obtains a first adjustment time stored in the memory chip 20, and the first adjustment time is used to characterize the path delay difference between the clock signal ck and the data enable signal Dqs inside the memory chip. The controller 10 adjusts the sending delay of the data enable signal Dqs to the memory chip 20 based on the obtained first adjustment time. Then, the controller 10 continuously adjusts the sending delay of the data enable signal Dqs until the trigger edge of the clock signal received by the memory chip and the trigger edge of the data enable signal are aligned.

It should be noted that the “trigger edge” mentioned in the above description, that is, the effective edge, can be a rising edge or a falling edge, specifically, the actual effective edge of the corresponding signal.

The controller 10 continuously adjusts the transmission delay of the data strobe signal dqs until the trigger edge of the clock signal received by the memory chip is aligned with the trigger edge of the data strobe signal, that is, the write-leveling operation of the memory, and further includes:

When the trigger edge of the clock signal ck received by the comparator 201 of the memory chip 20 is aligned with the trigger edge of the data enable signal dqs (that is, when the trigger edge of the clock signal ck received by the DQ pad is aligned with the trigger edge of the data enable signal dqs), the memory chip feeds back an identification signal to the controller 10; it should be noted that, in the present embodiment, the write leveling operation is not divided into chip external alignment and chip internal alignment. Since the controller 10 sends the data enable signal dqs based on the first adjustment time, the clock signal ck and the data enable signal dqs obtained by the memory chip have consistent on-chip path delays. The identification signal can be directly set to represent that the clock signal ck and the data enable signal dqs are aligned at the DQ pad. At this time, the execution result of the Write-leveling operation of the memory can directly align the clock signal ck and the data enable signal dqs at the DQ pad.

It should be noted that the continuous adjustment of the transmission delay of the data selection signal Dqs can be set as follows: setting a step (step value), and then gradually increasing the transmission delay of the data selection signal Dqs based on the set step value until the identification signal fed back by the memory chip 20 is obtained, wherein the identification signal is used to indicate that the trigger edge of the clock signal ck received by the comparator 201 is aligned with the trigger edge of the data selection signal dqs.

As for the identification signal, the identification signal is generated by the comparator 201 inside the memory chip 20. The comparator 201 receives the data selection signal dqs and the clock signal ck, and is used to compare whether the data selection signal dqs and the clock signal ck are aligned. When they are not aligned, the generated identification signal is "0". Due to the step scan, when the identification signal jumps from "0" to "1", it indicates that the data selection signal dqs and the clock signal ck are aligned.

In addition, the controller 10 obtains a second adjustment time corresponding to the memory chip 20 based on the identification signal, and the second adjustment time is used to characterize the transmission delay of the data selection signal dqs by the controller 10 when the trigger edge of the clock signal ck and the trigger edge of the data selection signal dqs are aligned; the controller 10 sends the data selection signal dqs to the memory chip based on the second adjustment time. Specifically, the controller 10 obtains the second adjustment time corresponding to the memory chip 20 based on the identification signal, including: when the controller 10 receives the identification signal, based on the transmission delay of the current data selection signal dqs, obtains the second adjustment time corresponding to the memory chip. In one example, the controller obtains the current step value corresponding to the memory chip 20 based on the indication signal, and obtains the second adjustment time based on the current step value and the first adjustment time, wherein the second adjustment time = current step value + first adjustment time.

When the identification signal completes the transition from "0" to "1", it indicates that the memory Write-leveling operation is completed. The "received identification signal" mentioned above means that the identification signal with the result of "1" is received.

Among them, the controller 10 sends a data enable signal dqs to the memory chip based on the second adjustment time, that is, the memory controller locks the delay setting of the data enable signal Dqs, and the subsequent memory sends the data enable signal dqs to the memory chip based on the second adjustment time, so that the clock signal ck and the data enable signal dqs received by the memory chip 20 are aligned on the DQ pad.

It should be noted that the process of obtaining the second adjustment time mentioned above can be a Write-leveling operation when the chip is powered on, and the chip can also perform a new Write-leveling during the subsequent operation to re-obtain the second adjustment time for re-locking.

For the write leveling system provided in this embodiment, the first adjustment time is used to characterize the path delay difference between the clock signal ck and the data enable signal Dqs inside the memory chip 20. The controller 10 obtains the first adjustment time and sends the data enable signal Dqs to the memory chip 20 based on the first adjustment time delay, so that the data enable signal Dqs and the clock signal ck aligned at the comparator of the memory chip are also aligned at the DQ pad. At this time, the identification signal generated by the comparator in the memory chip can characterize the alignment of the clock signal ck and the data enable signal dqs at the DQ pad, that is, the execution result of the Write-leveling operation of the memory can directly align the clock signal ck and the data enable signal dqs at the DQ pad, so that the write leveling system simplifies the write equalization operation of the memory on the basis of removing the delay unit set on the transmission path of the data enable signal Dqs, and at the same time avoids the jitter caused in the leveling characteristics of the memory due to the setting of the delay unit.

In some embodiments, the controller 10 adjusts the sending delay of the data selection signal dqs to the corresponding memory chip 20 based on the first adjustment time, and continuously adjusts the sending delay, including: the controller 10 obtains the first adjustment time stored in the memory chip 20, the controller 10 adjusts the sending delay of the data selection signal dqs to the memory chip based on the first adjustment time, and the controller 10 continuously adjusts the sending delay of the data selection signal dqs.

For the controller 10 provided in this embodiment, referring to Figure 5, the controller 10 includes: a plurality of cascaded signal generating units 50, each level of signal generating unit 50 includes: an AND logic circuit 501, a first input end for receiving a write leveling enable signal, a second input end for receiving a delay identification signal, the delay identification signal being used to perform different delays on data selection signals of different operating frequencies; an OR logic circuit 502, a first input end connected to the output end of the AND logic circuit 501, a second input end of the OR logic circuit 502 in the first-level signal generating unit 501 is used to receive a data selection signal Dqs; a trigger 503, an input end connected to the output end of the OR logic circuit 502, an output end serving as the output end of the signal generating unit 501, and a clock end serving as the data selection signal Dqs; a second input end of the OR logic circuit in the non-first-level signal generating unit 501 is connected to the output end of the trigger in the previous-level signal generating unit, and the output end of the trigger in the last-level signal generating unit 50 is used as the output end of the controller 10, for outputting the delayed data selection signal dqs.

It should be noted that the multiple signal generating units 50 are only cascaded in structure. In terms of output logic, the multiple signal generating units 50 are not cascaded, but have a selective output relationship.

In addition, for the signal generating unit 50, the first adjustment time is included in the input end of each stage of the AND gate, that is, the first adjustment time is included in the delay identification signal.

Specifically, each level of signal generating unit 50 receives a different delay identification signal. In the example of FIG5 , the delay identification signals received by the cascaded signal generating units 50 are A to N, respectively. Each delay identification signal corresponds to a different time delay. In some embodiments, the delay identification signals are A to N, namely, the number of delay cycles of the first adjustment time at different frequencies. Assume that the time delay corresponding to the delay identification signal A is tA, the time delay corresponding to the time identification signal B is tB, and the time delay corresponding to the time identification signal N is tN. At this time, different delay identification signals or different combinations of delay identification signals are provided to achieve different delays for the data selection signal Dqs, thereby achieving the Write-leveling operation of the memory.

For the trigger 503 , the reset terminal RST of the trigger 503 is also used to receive a reset signal reset, and the reset signal is used to reset the output of the trigger 503 , thereby avoiding erroneous output of the data selection signal Dqs based on the storage value of the trigger 503 .

In some embodiments, referring to Figure 6, the memory chip 20 includes: a delay timing unit 301 for storing a first adjustment time; the memory 10 obtains the first adjustment time of the memory in the memory chip 10, including: the controller 10 connects to the delay timing unit 301 in the memory chip 20, and obtains the first adjustment time stored in the delay timing unit 301.

Specifically, the first adjustment time = (path transmission time difference between the clock signal ck and the data enable signal Dqs inside the memory chip) / period of the data enable signal Dqs; wherein, the path difference between the clock signal ck and the data enable signal Dqs inside the memory chip is obtained based on the cancelled delay unit, and the period of the data enable signal Dqs is obtained based on the parameters of the memory, and the first adjustment time is calculated by the designer based on relevant parameters such as the circuit structure and wiring layout on the path of the clock signal ck and the data enable signal Dqs and is directly stored in the delay timing unit 301.

In some embodiments, the delay timing unit 301 is set based on a redundant register in the memory chip 20, and the redundant register is an unused register in the memory chip 20, for example, it may be an unused mode register. The first adjustment time is stored in the unused mode register in the memory chip 20 to avoid structural adjustments to the memory chip 20, so as to improve the applicability of the write leveling system provided in this embodiment.

In some embodiments, the first adjustment time can also be set to be calculated and obtained based on the processing unit inside the memory chip 20 and then stored in the delay timing unit 301; specifically, referring to Figure 7, the delay timing unit 301 includes: a first processing unit 401, configured to obtain the path transmission time difference between the data selection signal Dqs and the clock signal ck in the memory chip 20, and a second processing unit 402, connected to the first processing unit 401, configured to obtain the first adjustment time based on the path transmission time difference and the period of the data selection signal Dqs.

The path transmission time difference between the data selection signal Dqs and the clock signal ck in the memory chip 20 is obtained based on the delay set by the cancelled delay unit, and the second processing unit 402 can be set as only a calculation unit in actual settings.

In some embodiments, the controller 10 obtains the first adjustment time, including: the controller 10 obtains the first adjustment time based on a mode register read command (Mode Register Read, MRR). Since the memory chip 20 itself executes the MRR command during the startup process, the command is reused to obtain the first adjustment time, for example, stored in a redundant mode register, through the MRR. Thus, the first adjustment time is obtained based on the MRR command, so that the controller 10 does not need to set additional actions to obtain the first adjustment time.

It should be noted that the features disclosed in the write-leveling system provided in the above embodiments can be arbitrarily combined without conflict to obtain a new write-leveling system embodiment.

Another embodiment of the present disclosure provides a write leveling method, which is applied to the write leveling system provided in the above embodiment, and simplifies the write leveling operation of the memory on the basis of removing the delay unit set on the transmission path of the data selection signal Dqs.

FIG8 and FIG9 are flowcharts corresponding to the steps of the write leveling method provided in this embodiment. The write leveling method provided in this embodiment is described in detail below in conjunction with the accompanying drawings, as follows:

Referring to FIG8 , a leveling method is described, including:

Step 701, obtaining a first adjustment time corresponding to a storage chip.

Specifically, the first adjustment time is used to characterize the path delay difference between the clock signal and the data strobe signal inside the memory chip.

2 and 3 , a first adjustment time is stored in the memory chip 20, and the first adjustment time is used to characterize the path delay difference between the clock signal ck and the data selection signal Dqs inside the memory chip 20, that is, the delay difference between the data selection signal Dqs2 and the clock signal ck2 transmitted from the DQ pad of the memory chip 20 to the internal comparator 201, that is, 丨tdqs2-tdqs1丨-丨tck2-tck1丨.

Generally speaking, the transmission delay of the clock signal ck from the DQ pad to the comparator 201 is greater than the transmission delay of the data selection signal Dqs from the DQ pad to the comparator 201, that is, t3＞t2. Therefore, a delay unit 202 is usually set on the transmission path of the data selection signal Dqs to balance the path delay difference between the clock signal ck and the data selection signal Dqs in the memory chip 20 based on the delay unit 202, so that 丨t2-t3丨＝0, so that the clock signal ck received by the comparator 201 and the data selection signal Dqs are equal. The delay between the clock signal ck and the data enable signal Dqs is the same as the delay between the clock signal ck and the data enable signal Dqs received by the memory chip 20, that is, the data enable signal Dqs and the clock signal ck aligned by the comparator 201 are also aligned at the DQ pad; and the write leveling system provided in this embodiment balances the path delay difference between the clock signal ck and the data enable signal Dqs inside the memory chip 20 through the first adjustment time, so that 丨t2-t3丨＝0, thereby making the clock signal ck and the data enable signal Dqs received by the DQ pad directly aligned.

In some embodiments, a method for acquiring a first adjustment time stored in a memory chip includes: acquiring a path transmission time difference between a data selection signal and a clock signal in the memory chip, and acquiring the first adjustment time based on the path transmission time difference and a period of the data selection signal.

Accordingly, in some embodiments, obtaining the first adjustment time corresponding to the memory includes: obtaining the first adjustment time stored in the memory chip.

In one example, the first adjustment time is set based on a redundant register in a memory chip, and the redundant register is an unused register in the memory chip, for example, an unused mode register. The first adjustment time is stored in the unused mode register in the memory chip 20 to avoid structural adjustments to the memory chip 20, so as to improve the applicability of the write leveling system provided in this embodiment.

In some embodiments, obtaining the first adjustment time corresponding to the memory chip includes: obtaining the first adjustment time based on a mode register read command (Mode Register Read, MRR) received by the memory. Since the memory chip 20 itself executes the MRR command during the startup process, the command is reused, and the MRR is used to obtain, for example, the first adjustment time stored in a redundant mode register. The first adjustment time is thus obtained based on the MRR command, so that the controller 10 obtains the first adjustment time without setting additional actions.

Step 702: adjusting a transmission delay of a data strobe signal to a memory chip based on a first adjustment time.

Step 703, continuously adjusting the transmission delay of the data strobe signal until the trigger edge of the clock signal received by the memory chip is aligned with the trigger edge of the data strobe signal.

The first adjustment time is used to characterize the path delay difference between the clock signal ck and the data enable signal Dqs inside the memory chip 20. The controller 10 obtains the first adjustment time and sends the data enable signal Dqs to the memory chip 20 based on the first adjustment time delay, so that the data enable signal Dqs and the clock signal ck aligned at the comparator of the memory chip are also aligned at the DQ pad. At this time, the identification signal generated by the comparator in the memory chip can characterize the alignment of the clock signal ck and the data enable signal dqs at the DQ pad, that is, the execution result of the Write-leveling operation of the memory can directly align the clock signal ck and the data enable signal dqs at the DQ pad, so that the write leveling system simplifies the write equalization operation of the memory on the basis of removing the delay unit set on the transmission path of the data enable signal Dqs, and at the same time avoids the jitter caused in the leveling characteristics of the memory due to the setting of the delay unit.

Referring to FIG. 9 , in some embodiments, step 703 includes:

Step 704: Acquire an identification signal fed back by the storage chip.

Specifically, when the trigger edge of the clock signal received by the memory chip is aligned with the trigger edge of the data strobe signal, the memory chip feeds back an identification signal to the controller.

More specifically, referring to Figure 5, the controller 10 includes: a plurality of cascaded signal generating units 50, each level of the signal generating unit 50 includes: an AND logic circuit 501, a first input end for receiving a write leveling enable signal, a second input end for receiving a delay identification signal, the delay identification signal being used to perform different delays on data selection signals of different operating frequencies; an OR logic circuit 502, a first input end connected to the output end of the AND logic circuit 501, a second input end of the OR logic circuit 502 in the first-level signal generating unit 501 is used to receive a data selection signal Dqs; a trigger 503, an input end connected to the output end of the OR logic circuit 502, an output end serving as the output end of the signal generating unit 501, and a clock end serving as the data selection signal Dqs; a second input end of the OR logic circuit in the non-first-level signal generating unit 501 is connected to the output end of the trigger in the previous-level signal generating unit, and the output end of the trigger in the last-level signal generating unit 50 serves as the output end of the controller 10, for outputting a delayed data selection signal dqs.

When the trigger edge of the clock signal ck received by the comparator 201 of the memory chip 20 is aligned with the trigger edge of the data selection signal dqs (that is, when the trigger edge of the clock signal ck received by the DQ pad is aligned with the trigger edge of the data selection signal dqs), the memory chip feeds back an identification signal to the controller 10; it should be noted that, in the present embodiment, the write leveling operation is not divided into chip external alignment and chip internal alignment. Since the controller 10 sends the data selection signal dqs based on the first adjustment time, the clock signal ck and the data selection signal dqs obtained by the memory chip have the same intra-chip path delay, and the identification signal can be directly set to represent that the clock signal ck and the data selection signal dqs are aligned at the DQ pad. At this time, the execution result of the Write-leveling operation of the memory can directly align the clock signal ck and the data selection signal dqs at the DQ pad.

As for the identification signal, the identification signal is generated by the comparator 201 inside the memory chip 20. The comparator 201 receives the data selection signal dqs and the clock signal ck, and is used to compare whether the data selection signal dqs and the clock signal ck are aligned. If they are not aligned, the generated identification signal is "0". Due to the step scan, when the identification signal jumps from "0" to "1", it indicates that the data selection signal dqs and the clock signal ck are aligned.

Step 705: Acquire a second adjustment time corresponding to the memory chip based on the identification signal.

Specifically, the second adjustment time is used to characterize the transmission delay of the data strobe signal when the trigger edge of the clock signal and the trigger edge of the data strobe signal are aligned.

Step 706: Send a data strobe signal to the memory chip based on the second adjustment time.

The controller sends a data enable signal to the memory chip based on the second adjustment time, that is, the memory controller locks the delay setting of the data enable signal Dqs, and the subsequent memory sends a data enable signal to the memory chip based on the second adjustment time, so that the clock signal and the data enable signal received by the memory chip are aligned at the DQ pad of the memory chip.

It should be noted that the features disclosed in the write-leveling method provided in the above embodiments can be arbitrarily combined without conflict to obtain a new write-leveling method embodiment.

Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present disclosure, and in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present disclosure.

Claims

A write leveling system, characterized by comprising: a controller (10) and a storage chip (20);

The controller (10) is used to provide a clock signal and a data strobe signal to the memory chip (20);

The memory chip (20) stores a first adjustment time, the first adjustment time being used to characterize a path delay difference between the clock signal and the data strobe signal inside the memory chip;

The controller (10) adjusts the transmission delay of the data strobe signal to the memory chip (20) based on the first adjustment time, and continues to adjust the transmission delay until the trigger edge of the clock signal received by the memory chip (20) is aligned with the trigger edge of the data strobe signal.
The write leveling system according to claim 1, further comprising:

When the trigger edge of the clock signal received by the memory chip (20) is aligned with the trigger edge of the data strobe signal, the memory chip (20) feeds back an identification signal to the controller (10);

The controller (10) acquires a second adjustment time corresponding to the memory chip (20) based on the identification signal, wherein the second adjustment time is used to characterize a transmission delay of the data strobe signal by the controller (10) when a trigger edge of the clock signal and a trigger edge of the data strobe signal are aligned;

The controller (10) sends the data strobe signal to the memory chip (20) based on the second adjustment time.
The write leveling system according to claim 2 is characterized in that the controller (10) obtains the second adjustment time corresponding to the memory chip (20) based on the identification signal, including: when the controller (10) receives the identification signal, based on the current transmission delay of the data selection signal, obtaining the second adjustment time corresponding to the memory chip (20).
The write leveling system according to any one of claims 1 to 3, characterized in that the controller (10) adjusts the transmission delay of the data strobe signal to the corresponding memory chip (20) based on the first adjustment time, and continuously adjusts the transmission delay, comprising:

The controller (10) acquires the first adjustment time stored in the storage chip (20);

The controller (10) adjusts the transmission delay of the data strobe signal to the memory chip (20) based on the first adjustment time;

The controller (10) continuously adjusts the transmission delay of the data strobe signal.
The writing leveling system according to any one of claims 1 to 4, characterized in that it comprises:

The storage chip (20) comprises: a delay timing unit, used for storing the first adjustment time;

The controller (10) acquires the first adjustment time stored in the storage chip (20), comprising:

The controller (10) is connected to the delay timing unit (201) in the storage chip (20), and obtains the first adjustment time stored in the delay timing unit (202).
The write leveling system according to claim 5, characterized in that the delay timing unit (201) is set based on a redundant register in the memory chip.
The write leveling system according to any one of claims 1 to 6, characterized in that the controller (10) obtains the first adjustment time based on a mode register read command.
The write leveling system according to claim 5, characterized in that the delay timing unit (201) comprises:

The first processing unit (401) is configured to obtain the data strobe signal and the The path transmission time difference of the clock signal;

The second processing unit (402) is connected to the first processing unit (401) and is configured to obtain the first adjustment time based on the path transmission time difference and the period of the data selection signal.
The write leveling system according to any one of claims 1 to 8, characterized in that the controller (10) comprises:

A plurality of cascaded signal generating units (50), each level of signal generating unit (50) comprising:

An AND logic circuit (501), wherein a first input terminal is used to receive a write leveling enable signal, and a second input terminal is used to receive a delay identification signal, wherein the delay identification signal is used to perform different delays on the data strobe signal;

An OR logic circuit (502), a first input terminal of which is connected to the output terminal of the AND logic circuit, and a second input terminal of the OR logic circuit in the first-stage signal generating unit is used to receive the data selection signal;

A trigger (503), the input end of which is connected to the output end of the OR logic circuit, the output end of which serves as the output end of the signal generating unit, and the clock end of which is used to receive the data selection signal;

The second input end of the OR logic circuit (502) in the non-first-stage signal generating unit (50) is connected to the output end of the trigger (503) in the previous-stage signal generating unit (50), and the output end of the trigger (503) in the last-stage signal generating unit (50) is used to output the delayed data selection signal.
A write leveling method, applied to the write leveling system according to any one of claims 1 to 9, characterized in that it comprises:

Acquire a first adjustment time corresponding to the memory chip, where the first adjustment time is used to characterize a path delay difference between a clock signal and a data strobe signal inside the memory chip;

The transmission delay of the data strobe signal to the memory chip is adjusted based on the first adjustment time, and the transmission delay is continuously adjusted until the trigger edge of the clock signal received by the memory chip is aligned with the trigger edge of the data strobe signal.
The write leveling method according to claim 10, characterized in that the continuously adjusting the sending delay until the trigger edge of the clock signal received by the memory chip is aligned with the trigger edge of the data strobe signal comprises:

Acquire an identification signal fed back by the memory chip, wherein when a trigger edge of the clock signal received by the memory chip is aligned with a trigger edge of the data strobe signal, the memory chip feeds back the identification signal to the controller;

Acquire a second adjustment time corresponding to the memory chip based on the identification signal, wherein the second adjustment time is used to characterize a transmission delay of the data strobe signal when a trigger edge of the clock signal and a trigger edge of the data strobe signal are aligned;

The data strobe signal is sent to the memory chip based on the second adjustment time.
The write leveling method according to claim 10 or 11 is characterized in that obtaining the first adjustment time corresponding to the memory chip comprises: obtaining the first adjustment time based on a mode register read command received by the memory.
The write leveling method according to claim 10 or 11 is characterized in that obtaining the first adjustment time corresponding to the storage chip includes: obtaining the first adjustment time stored in the storage chip.
The write adjustment method according to claim 13, characterized in that the method for acquiring the first adjustment time stored in the storage chip comprises:

Acquire the path transmission time difference between the data strobe signal and the clock signal in the memory chip;

The first adjustment time is acquired based on the path transmission time difference and the period of the data strobe signal.