WO2024140240A1 - Signal generation device, quantum control system, and quantum computer - Google Patents

Abstract

The present application belongs to the technical field of quantum, and discloses a signal generation device, a quantum control system, and a quantum computer, for use in outputting an intermediate frequency signal carrying quantum state coding information. The signal generation device comprises a plurality of waveform parameter generation modules and a digital-to-analog conversion module; each waveform parameter generation module outputs a waveform parameter of an intermediate frequency signal according to first clock information and a frequency control word, wherein a preset phase difference exists between the waveform parameters output by the waveform parameter generation modules; the digital-to-analog conversion module outputs corresponding intermediate frequency signals according to the waveform parameters output by the waveform parameter generation modules, wherein the preset phase difference is determined according to the first clock information of the waveform parameter generation modules and the output frequency for outputting the waveform parameters. The present application improves the frequency and precision of intermediate frequency signals that are output, and further improves the control and reading precision of a quantum processor.

Description

Signal generating device, quantum control system and quantum computer

This application claims priority to the Chinese patent application filed with the Chinese Patent Office on December 30, 2022, with application number 202211741939.4 and application name “Signal Generating Device, Quantum Control System and Quantum Computer”, and the Chinese patent application filed with the Chinese Patent Office on March 13, 2023, with application number 2023102535772 and application name “Signal Generating Device, Quantum Control System and Quantum Computer”, the entire contents of which are incorporated by reference in this application.

Technical Field

The present application relates to the field of electronics, and more specifically, to a signal generating device, a quantum control system and a quantum computer.

Background technique

Quantum computing is a new computing model that follows the laws of quantum mechanics to control basic information units for computing. The basic information unit of classical computing is the classical bit, and the basic information unit of quantum computing is the quantum bit. The classical bit can only be in one state, that is, 0 or 1, but based on the principle of quantum mechanics superposition, the state of the quantum bit can be in a superposition state of multiple possibilities. Therefore, the computing efficiency of quantum computing far exceeds that of classical computing.

The operation process of quantum computing is mainly performed by the quantum processor. The specific operation process includes: first applying a control signal to the quantum bit in the ground state, and then applying a read signal to the quantum bit after the control signal operation to obtain the quantum computing result. Therefore, the frequency of the control signal and the read signal is close to the operating frequency of the quantum processor. The operating frequency of the quantum processor is usually gigahertz, such as 6GHz, so the frequency of the control signal and the read signal is usually between 6GHz-8GHz.

At present, the control signal and the read signal are generally obtained by mixing the intermediate frequency signal and the microwave signal. Therefore, the accuracy of the intermediate frequency signal will have a direct impact on the accuracy of the control signal and the read signal. In the relevant technology, the intermediate frequency signal is usually output by a signal source device such as a signal generator or an arbitrary waveform generator. Due to the accuracy limitation of the signal source device, the output intermediate frequency signal has a low accuracy problem, which in turn affects the accuracy of the control signal and the read signal after mixing, and cannot meet the control and read accuracy requirements required by the quantum processor when performing the calculation process.

Summary of the invention

The purpose of this application is to provide a signal generating device, a quantum control system and a quantum computer, which make up for the shortcomings of the relatively low frequency and accuracy of the intermediate frequency signal output by the signal source device in the prior art, improve the frequency and accuracy of the output intermediate frequency signal, and thus improve the control and reading accuracy of the quantum processor.

The specific technical solution of this application is as follows:

In a first aspect, the present application provides a signal generating device for outputting an intermediate frequency signal carrying quantum state encoding information, the signal generating device comprising a plurality of waveform parameter generating modules and a digital-to-analog conversion module; the waveform parameter generating module outputs the waveform parameters of the intermediate frequency signal according to first clock information and a frequency control word; wherein there is a preset phase difference between the waveform parameters output by each of the waveform parameter generating modules, and the preset phase difference is used to control the waveform parameters to be output in phase order; the digital-to-analog conversion module outputs a corresponding intermediate frequency signal according to the waveform parameters output by each of the waveform parameter generating modules; wherein the preset phase difference is based on the first clock information and the frequency control word of each of the waveform parameter generating modules The output frequency of the output waveform parameters is determined.

Optionally, the signal generating device further comprises a data processing module, which splices the waveform parameters output by each of the waveform parameter generating modules according to an output bit sequence, and sends the spliced waveform parameters to the digital-to-analog conversion module.

Optionally, the waveform parameter generation module includes a phase accumulator unit and a memory unit; the phase accumulator unit is used to accumulate the frequency control word and the current phase value according to the first clock information, and send the phase data obtained by adding the accumulated phase value and the phase control word to the memory unit; the memory unit is used to store the waveform parameters according to the address, and output the waveform parameters of the corresponding address to the data processing module according to the phase data.

Optionally, the data bit width of the phase accumulator unit includes 32 bits.

Optionally, the frequency control word is determined according to the output frequency of the waveform parameter generation module, the data bit width and the first clock information.

Optionally, the preset phase difference is determined as: Among them, Ph is the preset phase difference, N is the data bit width of the phase accumulator unit, fd is the first clock information, and fo is the output frequency of the waveform parameter generation module.

Optionally, the working clocks of the phase accumulator unit and the memory unit are the same as the working clock of the digital-to-analog conversion module.

Optionally, the waveform parameter generation module and the data processing module are both functional modules within the FPGA.

Optionally, one of the FPGAs includes a plurality of the waveform parameter generation modules and at least one of the data processing modules.

Optionally, the sampling rate of the digital-to-analog conversion module is at least 1 GS/s, and the number of the waveform parameter generation modules is at least 2.

Optionally, the sampling rate of the digital-to-analog conversion module is at least 3GS/s, and the number of the waveform parameter generation modules is at least 6.

Optionally, the waveform parameter generation module includes a phase accumulator unit, and the signal generating device also includes: multiple signal parameter generation modules, which are used to generate primary signal parameters according to the input phase control information based on the Cordic algorithm; wherein the phase control information input by different signal parameter generation modules conforms to the specified rules, so that the phase difference between the primary signal parameters output by the multiple signal parameter generation modules is an integer multiple of the specified phase difference; a digital-to-analog conversion module, which is also used to generate the intermediate frequency signal according to the target signal parameters formed by multiple primary signal parameters arranged according to the specified phase difference; wherein the phase accumulator unit has a specified corresponding relationship with the signal parameter generation module, and the phase accumulator unit is used to accumulate the phase control information according to the working clock frequency of the signal parameter generation module, and send the accumulated phase control information to the signal parameter generation module.

Optionally, the frequency of the intermediate frequency signal has a first correlation with the frequency of the control signal and/or the read signal of the quantum processor; wherein the first correlation is used to characterize a first frequency condition satisfied by the frequency of the intermediate frequency signal when the frequency of the control signal and/or the read signal satisfies the accuracy condition of the quantum processor.

Optionally, the number of the signal parameter generating modules has a second correlation with the frequency of the intermediate frequency signal; wherein the second correlation is used to characterize the quantity condition satisfied by the number of the signal parameter generating modules when the frequency of the intermediate frequency signal satisfies the first frequency condition.

Optionally, the phase control information is determined according to the number of the signal parameter generating modules and the working clock frequency, output frequency and data bit width of the signal parameter generating modules.

Optionally, the designated rule includes that the difference between phase control information input by adjacent signal parameter generation modules is a designated phase difference.

Optionally, the signal generating device further includes a data processing module, configured to perform data processing on a plurality of the primary signal parameters to obtain a target signal parameter corresponding to at least one period of the intermediate frequency signal.

Optionally, the working clock of the signal parameter generating module is the same as the working clock of the digital-to-analog conversion module.

In a second aspect, the present application provides a quantum control system, comprising the signal generating device described in the first aspect and A microwave source and a signal mixing device, wherein the signal mixing device is used to mix the intermediate frequency signal output by the signal generating device and the microwave signal output by the microwave source and output a control signal and/or a read signal.

In a third aspect, the present application provides a quantum computer, comprising a quantum control system and a quantum processor as described in the second aspect, wherein the quantum control system outputs a control signal for controlling the quantum processor to perform an operation, and a read signal for measuring the operation result of the quantum processor.

Compared with the prior art, the present application has the following beneficial effects.

The signal generating device of the present application is used to output an intermediate frequency signal carrying quantum state encoding information, and the signal generating device includes a plurality of waveform parameter generating modules and a digital-to-analog conversion module; the waveform parameter generating module outputs the waveform parameters of the intermediate frequency signal according to the first clock information and the frequency control word; wherein, there is a preset phase difference between the waveform parameters output by each of the waveform parameter generating modules, and the preset phase difference is used to control the waveform parameters to be output in phase order; the digital-to-analog conversion module outputs the corresponding intermediate frequency signal according to the waveform parameters output by each of the waveform parameter generating modules; wherein, the preset phase difference is determined according to the first clock information of each of the waveform parameter generating modules and the output frequency of the waveform parameters.

The embodiment of the present application adopts multiple waveform parameter generation modules to output a number of waveform parameters according to a unified first clock information, which can not only ensure the synchronization of the working clock, but also reduce the working frequency of the waveform parameters output by a single waveform parameter generation module, thereby avoiding logic timing violations; in addition, the total number of waveform parameters output by multiple waveform parameter generation modules is matched with the number of points per unit time of the sampling rate of the digital-to-analog conversion module, and a preset phase difference is set between the waveform parameters output by the multiple waveform parameter generation modules, so that the waveform parameters transmitted to the digital-to-analog conversion module are continuous and can cover the waveform parameters within a complete cycle of the intermediate frequency signal, thereby improving the resolution of the waveform parameters and ensuring that the digital-to-analog conversion module outputs a high-precision intermediate frequency signal; the intermediate frequency signal output by the digital-to-analog conversion module can also be adjusted by adjusting the frequency control word and the preset phase difference.

The embodiment of the present application adopts multiple signal parameter generation modules to generate primary signal parameters according to the input phase control information based on the Cordic algorithm, and the phase control information input by different signal parameter generation modules conforms to the specified rules, so that the phase difference between the primary signal parameters output by the multiple signal parameter generation modules is an integer multiple of the specified phase difference, so that the target signal parameters formed by arranging the primary signal parameters according to the specified phase difference can correspond to at least one complete cycle of the target intermediate frequency signal, and the accuracy of the target signal parameters can make the intermediate frequency signal output by the digital-to-analog conversion module according to the target signal parameters meet the accuracy conditions, thereby realizing that the digital-to-analog conversion module outputs the target intermediate frequency signal that meets the accuracy conditions under relatively accurate logical timing.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic structural diagram of a signal generating device provided in an embodiment of the present application;

FIG2 is a schematic structural diagram of a signal generating device provided by another embodiment of the present application;

FIG3 is a schematic diagram of the structure of a waveform parameter generation module provided in yet another embodiment of the present application.

FIG. 4 is a schematic diagram of the structure of a signal generating device provided in yet another embodiment of the present application.

FIG5 is a schematic diagram of the geometric principle of the Cordic algorithm used by the signal parameter generation module provided in an embodiment of the present application.

FIG6 is a schematic diagram of the structure of a signal generating device provided in yet another embodiment of the present application.

FIG. 7 is a schematic diagram of the structure of a signal generating device provided in yet another embodiment of the present application.

FIG8 is a schematic diagram of the structure of a quantum control system provided in an embodiment of the present application.

Detailed ways

In order to more clearly illustrate the technical solutions in the implementation modes of this specification, the drawings required for describing the implementation modes will be briefly introduced below. Obviously, the drawings described below are only some implementation modes of this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

The following detailed description is illustrative only and is not intended to limit the application or use of the embodiments and/or embodiments. In addition, it is not intended to be bound by any explicit or implicit information presented in the previous "background technology" or "invention content" section or "specific implementation" section.

To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, one or more embodiments are now described with reference to the accompanying drawings, wherein similar reference numerals throughout the text are used to refer to similar components. In the following description, for the purpose of explanation, many specific details are set forth in order to provide a more thorough understanding of one or more embodiments. However, it is clear that in various cases, one or more embodiments can be practiced without these specific details, and the various embodiments can be combined and referenced to each other without contradiction.

It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

The control signal and read signal acting on the quantum processor are mainly obtained by mixing the intermediate frequency signal. The intermediate frequency signal carries the quantum state encoding information for controlling the quantum processor and reading the quantum calculation results. Generally speaking, the intermediate frequency signal is an analog signal, and the digital to analog converter (DAC) can output the corresponding analog signal according to the digital signal received at the input end. The digital signal input to the digital to analog converter corresponds to the amplitude of the intermediate frequency signal. In other words, the digital signal corresponds to the waveform parameters of the analog signal. The higher the resolution of the waveform parameters, the higher the resolution of the corresponding intermediate frequency signal.

The digital signal or waveform parameters input to the DAC are usually provided by a Field-Programmable Gate Array (FPGA). For example, the digital signal input to the DAC can be output after running the Cordic algorithm through the FPGA. As an example, the waveform parameters can be output through a Direct Digital Synthesizer (DDS) in the FPGA.

In the field of quantum computing, the control signals and read signals used to control and read quantum processors are usually obtained by processing intermediate frequency signals using frequency mixing technology. Therefore, the signal accuracy of the control signals and read signals directly affects the control and read accuracy of the quantum processor, that is, the resolution of the intermediate frequency signal directly affects the control and read accuracy of the quantum processor. In order to achieve high-precision control of the quantum processor and high-precision reading of the calculation results, the frequency and resolution of the intermediate frequency signal used to obtain the control signal and read signal need to meet certain conditions.

In addition, according to the Nyquist sampling theorem, the sampling rate is twice the output signal frequency, but due to the limited out-of-band suppression characteristics of the image frequency suppression filter, the maximum output signal frequency is generally taken as 0.45 times the sampling rate. In this embodiment, the operating frequency of the quantum processor is usually between 6GHz-8GHz, the frequency of the intermediate frequency signal is usually 200MHz-500MHz, and the resolution of the intermediate frequency signal is not less than 1KHz; that is, the frequency of the analog signal output by the DAC is usually hundreds of megahertz, so the sampling rate of the DAC is not less than 1GS/s. Correspondingly, the operating clock frequency requirement of a single DDS in the FPGA also needs to be consistent with the sampling rate of the DAC to ensure that the number of waveform parameters output by a single DDS per unit time meets the number of sampling points per unit time at the DAC sampling rate. The DDS operating clock frequency in the FPGA in the prior art cannot achieve accurate logic timing at high clock frequencies.

Based on this, as shown in Figure 1, an embodiment of the present application provides a signal generating device for outputting an intermediate frequency signal carrying quantum state encoding information, the signal generating device comprising a plurality of waveform parameter generating modules 1 and a digital-to-analog conversion module 2; the waveform parameter generating module 1 outputs the waveform parameters of the intermediate frequency signal according to the first clock information and the frequency control word; wherein, there is a preset phase difference between the waveform parameters output by each of the waveform parameter generating modules 1, and the preset phase difference is used to control the waveform parameters to be output in phase order; the digital-to-analog conversion module 2 outputs the corresponding intermediate frequency signal according to the waveform parameters output by each of the waveform parameter generating modules 1; wherein, the preset phase difference is determined based on the first clock information of the waveform parameter generating module 1 and the output frequency of the waveform parameters.

Specifically, the waveform parameters include the phase, amplitude, and frequency parameters of the generated waveform. The first clock information is The working clock frequency of the waveform parameters output by the parameter generation module 1, that is, at each moment of the first clock information, each waveform parameter generation module 1 will output the waveform parameters. The working clock synchronization of each waveform parameter generation module 1 can be ensured by the unified first clock information. The frequency control word is the control character of the waveform parameters output by each waveform parameter generation module 1. It can be understood that the waveform parameter generation module 1 has data bit width and data depth parameters for storing multiple waveform parameters, and the number of waveform parameters to be output is determined by the frequency control word. In this embodiment, the waveform parameter generation module 1 can use DDS, and the digital-to-analog conversion module 2 can use DAC. The fc in the figure is the first clock information, which can be provided by the clock source; F is the frequency control word; fd is the working clock frequency of the digital-to-analog conversion module 2, that is, the sampling rate. Among them, the first clock information is determined by the sampling rate of the digital-to-analog conversion module 2 and the number of waveform parameter generation modules 1. Specifically, the first clock information of each waveform parameter generation module 1 is the working clock frequency of the digital-to-analog conversion module 2 divided by the number of waveform parameter generation modules 1, that is, fc=fd/n, n is the number of waveform parameter generation modules 1.

Each waveform parameter generation module 1 is used to output a certain number of waveform parameters of the intermediate frequency signal. Using multiple waveform parameter generation modules 1 to output a number of waveform parameters can reduce the working clock frequency of a single waveform parameter generation module; each waveform parameter generation module 1 not only outputs waveform parameters based on the same first clock information and frequency control word, but also has a preset phase difference between the waveform parameters output by each waveform parameter generation module 1, so that the waveform parameters transmitted to the digital-to-analog conversion module 2 are continuous and cover the waveform parameters of a complete cycle of the intermediate frequency signal. The resolution of the waveform parameters output by the waveform parameter generation module 1 can also be improved to ensure that the digital-to-analog conversion module 2 outputs a high-precision intermediate frequency signal. In addition, the adjustment of the intermediate frequency signal output by the digital-to-analog conversion module can also be achieved by adjusting the frequency control word and the preset phase difference. Among them, the example of the signal generating device including three waveform parameter generation modules 1 can also include other quantities, such as 4, 5, 6, etc. Specifically, the number of waveform parameter generation modules 1 is determined according to the frequency parameters of the intermediate frequency signal; after the frequency parameters of the intermediate frequency signal output by the digital-to-analog conversion module 2 are determined, the sampling rate of the digital-to-analog conversion module 2 can be determined, and the number of corresponding waveform parameter generation modules 1 can also be determined. For example, when the frequency parameter parameter of the intermediate frequency signal is 500MHz, the sampling rate of the digital-to-analog conversion module 2 is selected as 1.2GS/s, and the first clock information of each waveform parameter generation module 1 is determined to be 400MHz, the number of waveform parameter generation modules 1 is 3; similarly, when the first clock information of each waveform parameter generation module 1 adopts 300MHz, the number of waveform parameter generation modules 1 is 4; ensure that the waveform parameters output by multiple waveform parameter generation modules 1 correspond to the 1.2GS/s sampling rate of the digital-to-analog conversion module 2. In addition, the preset phase difference between the waveform parameters output by each waveform parameter generation module 1 is set accordingly to ensure that the waveform parameters transmitted to the digital-to-analog conversion module 2 are continuous and cover the waveform parameters of a complete cycle of the intermediate frequency signal.

As shown in FIG. 2 , as an implementation of an embodiment of the present application, the signal generating device further includes a data processing module 3, which splices the waveform parameters output by each of the waveform parameter generating modules 1 according to the output bit sequence, and sends the spliced waveform parameters to the digital-to-analog conversion module 2. Specifically, the waveform parameter generating modules 1 are sorted according to the output bit sequence, and the waveform parameters output by the waveform parameter generating modules 1 have differences in phase difference and output bit sequence. The waveform parameters are spliced according to the output bit sequence by the data processing module 3 to ensure that the spliced waveform parameters are the amplitude parameters of the required intermediate frequency signal. It should be supplemented that the data processing module 3 is connected to the digital-to-analog conversion module 2 through an interface communication connection with a fixed data format, and the data processing module 3 converts the spliced waveform parameters with a complete periodic waveform into data in a fixed data format and sends them to the digital-to-analog conversion module 2.

In combination with the three waveform parameter generation modules 1 shown in FIG. 2 , the output bit sequence of the waveform parameter generation module 1 is arranged from low to high, and the corresponding waveform parameters are also arranged in a bit sequence from low to high, ensuring that the spliced waveform parameters output by the data processing module 3 are the required amplitude parameters of the intermediate frequency signal, ensuring the signal accuracy of the intermediate frequency signal. In addition, the accuracy of the output intermediate frequency signal can be improved by fine-tuning the frequency control word and the phase difference values preset by several waveform parameter generation modules 1.

As shown in FIG. 3, as an implementation of an embodiment of the present application, the waveform parameter generation module 1 includes a phase accumulator unit 11 and a memory unit 12; the phase accumulator unit 11 is used to accumulate the frequency control word and the current phase value according to the first clock information, and send the phase data obtained by adding the accumulated phase value and the phase control word to the memory unit 12; the memory unit 12 is used to store the waveform parameters of the complete cycle according to the phase in the waveform parameters according to the address, and output the waveform parameters of the corresponding address to the memory unit according to the phase data. Data processing module 3.

Specifically, at each first clock information moment, the phase accumulator unit 11 adds the frequency control word at the input end to the current phase accumulation value to obtain a new phase accumulation value, adds the new phase accumulation value to the phase control word to obtain the accumulated phase data, and sends the phase data to the memory and the input end of the phase accumulator, and continuously accumulates the frequency control word under the control of the first clock information. In addition, the memory unit 12 is used to store the waveform parameters of the complete cycle of the intermediate frequency signal according to the address, wherein the address corresponds to the phase of each waveform parameter; the phase data output by the phase accumulator is used as the address to search the waveform parameter corresponding to the corresponding address in the memory unit 12, and the waveform parameter corresponding to the amplitude of the intermediate frequency signal is output through the memory unit 12. By adjusting the frequency control word, the size of the value accumulated each time by the phase accumulator unit 11 can be adjusted, and then the phase data can be adjusted, and the offset of the address corresponding to the phase data in the memory unit 12 under each clock can be changed to achieve frequency adjustment of the output waveform parameter; matching the signal frequency of the intermediate frequency signal.

As an implementation of an embodiment of the present application, the data bit width of the phase accumulator unit 11 includes 32 bits. Correspondingly, the bit width of the memory unit 12 is 12 bits, the storage waveform parameter depth of the memory unit 12 is 4096, and the working clock is 400MHz. The bit width of the phase accumulator unit 11 is greater than the bit width log ₂ 4096 of the memory unit 12, ensuring that the phase accumulator unit 11 accumulates one cycle and the memory unit 12 also cycles one cycle. The address of the memory unit 12 corresponds to the high bit of the phase accumulator unit 11. Generally, the waveform parameter depth of the memory unit 12 is 2 to 3 bits larger than the data bit width of the waveform parameter, which can save memory RAM resources and achieve higher resolution and better signal-to-noise ratio. Taking the bit width of the phase accumulator unit 11 as an example of 32 bits, the phase accumulator unit 11 accumulates to a maximum value of 2 ³² -1, then the minimum resolution of the output waveform of the signal generating device can be determined as:

Wherein, fc is the working clock frequency of the phase accumulator unit 11, i.e., the first clock information. By calculation, it can be determined that the resolution is 0.09313 Hz, which meets the sampling signal requirements of the digital-to-analog conversion module 2, thereby ensuring the accuracy of the output intermediate frequency signal. Wherein, every time the frequency control word is added or subtracted by one, the frequency changes by 0.09313 Hz. The output frequency of the signal generating device can be accurately adjusted by adjusting the frequency control word and the preset phase difference. In addition, by increasing the data bit width of the phase accumulator unit 11, the accuracy of the intermediate frequency signal output by the digital-to-analog conversion module 2 is improved, and the range of the intermediate frequency signal is increased.

As an implementation method of the embodiment of the present application, the frequency control word is determined according to the output frequency of the waveform parameter generation module 1, the data bit width and the first clock information. The relationship among the output frequency, data bit width and the first clock information of the waveform parameter generation module 1 is as follows:

Among them, F is the frequency control word, fo is the output frequency of the waveform parameter generation module 1, N is the data bit width of the phase accumulator unit 11, and fc is the first clock information. The working clock frequency of the phase accumulator unit 11 is determined according to the sampling rate of the digital-to-analog conversion module 2 and the number of waveform parameter generation modules 1, the data bit width N is determined according to the accuracy of the intermediate frequency signal, and the first clock information fc can be preset. Combined with the above formula, it can be found that the frequency control word of the phase accumulator unit 11 when performing the accumulation calculation can be determined according to the required output frequency fo. By flexibly adjusting the frequency control word, the output frequency of the waveform parameter generation module 1 can be adjusted to match the needs of intermediate frequency signals of different frequencies.

For example, the expected output frequency fo is 300MHz, by calculating F=2 ³² *300/400=3221225472; if fo is 600MHz, by calculating F=2 ³² *300/400=6442450944>2 ³² , at this time the frequency control word is much larger than the maximum value of the data bit width of the phase accumulator unit 11, at this time the frequency control word F=(2 ³² *600/400)%2 ³² =2147483648, it is also possible to calculate the output frequency fo by taking the modulus of the working clock of the waveform parameter generating module 1 according to the above formula: F=(2 ³² *(600%400)/400)=2 ³² *200/400=2147483648. The frequency of the waveform data output by the memory unit 12 is determined by the frequency control word. By adjusting the frequency control word, the time for the phase accumulator unit 11 to accumulate one circle can be controlled, thereby controlling the time for the memory unit 12 to output a complete waveform, that is, the inverse of the frequency. It is found that the frequency control word of the phase accumulator unit 11 during the accumulation calculation can be determined according to the frequency fo output as required. By flexibly adjusting the frequency control word, the frequency of the waveform parameter output by the waveform parameter generating module 1 can be adjusted to match the needs of intermediate frequency signals of different frequencies.

As an implementation method of the embodiment of the present application, the preset phase difference between each waveform parameter generating module 1 is calculated as follows:

Assuming the output frequency fo is 300MHz, the preset phase difference Ph between each waveform parameter generating module 1 is 2 ³² *300/1200=1073741824. Wherein fo is the output frequency, N is the bit width of the phase accumulator unit 11, fd is the working clock (sampling rate) of the digital-to-analog conversion module 2, and Ph is the preset phase difference between each waveform data generating module. The number of waveform parameter generating modules 1 is equal to (fd/fc). Therefore, it can be determined that the working clock fc of each waveform parameter generating module 1 is equal to the working clock fd of the digital-to-analog conversion module 2 divided by the number of waveform parameter generating modules 1.

In combination with the correspondence between the frequency control word and the preset phase difference and the output frequency of the waveform parameter generating module 1, the frequency of the waveform parameter output by the waveform parameter generating module 1 can be adjusted by flexibly adjusting the frequency control word and the preset phase difference to match the needs of intermediate frequency signals of different frequencies. In addition, the accuracy of the intermediate frequency signal output by the digital-to-analog conversion module 2 can also be improved by flexibly adjusting the frequency control word and the preset phase difference.

As an implementation method of the embodiment of the present application, the working clocks of the phase accumulator unit 11 and the memory unit 12 are co-sourced with the working clock of the digital-to-analog conversion module 2. Among them, the working clock frequencies of the phase accumulator unit 11 and the memory unit 12 are multiples of the working clock frequency of the digital-to-analog conversion module 2, and the specific multiples are determined according to the number of waveform parameter generation modules 1. The digital-to-analog conversion module 2 needs to provide a clock signal when working, which is usually provided by a clock source. In addition, the phase accumulator unit 11 and the memory unit 12 also need to provide a clock signal when working, and work with the clock signal provided by the same clock source to ensure that the working clocks of the phase accumulator unit 11, the memory unit 12, and the digital-to-analog conversion module 2 are synchronized, thereby ensuring the accuracy of the waveform parameters output to the digital-to-analog conversion module 2 and the accuracy of the intermediate frequency signal output by the digital-to-analog conversion module 2.

As an implementation method of the embodiment of the present application, the waveform parameter generation module 1 and the data processing module 3 are both functional modules in the FPGA. In this embodiment, the waveform parameter generation module 1 and the data processing module 3 are both functional modules set in the FPGA, wherein the waveform parameter generation module 1 may include a DDS, and the memory unit 12 uses a RAM or ROM memory. Functional modules are set in the FPGA, and the parameters of each functional module are flexibly defined to meet the waveform parameter requirements corresponding to various intermediate frequency signals.

In addition, when setting the functional modules in the FPGA, one FPGA includes multiple waveform parameter generation modules 1 and at least one data processing module 3; multiple waveform parameter generation modules 1 correspond to one data processing module 3. According to the frequency parameter requirements of the intermediate frequency signal, a corresponding number of waveform parameter generation modules 1 are set in the FPGA to output waveform parameters, and a data processing module 3 is used to splice and convert the format of each waveform parameter, and the processed waveform parameters are transmitted to the digital-to-analog conversion module 2. Multiple digital-to-analog conversion modules 2 are connected by instantiating the waveform parameter generation module 1 and the data processing module 3 multiple times inside the FPGA, and the waveform parameters of multiple intermediate frequency signals are output to meet the driving requirements of multiple quantum bits on the quantum processor. It should be noted that the number of waveform parameter generation modules 1, the working clock frequency, and the data bit width set in the FPGA need to be combined with the memory and resource settings of the FPGA.

In specific applications, the intermediate frequency signal is used to read the quantum processor after mixing processing, the sampling rate of the digital-to-analog conversion module 2 includes at least 1GS/s, and the number of the waveform parameter generation modules 1 includes at least 2. The intermediate frequency signal is used to control the quantum processor after mixing processing, the sampling rate of the digital-to-analog conversion module 2 includes at least 3GS/s, and the number of the waveform parameter generation modules 1 includes at least 6. The more the number of parallel waveform parameter generation modules 1 is, the lower the working clock frequency of a single waveform parameter generation module 1 can be, and the requirements of the internal logic timing of the FPGA can be met. When the quantum processor runs quantum computing, the accuracy of the control signal directly affects the fidelity of the logic gates applied to the quantum processor, and the resolution requirements of the intermediate frequency signal are extremely high. The sampling rate of the digital-to-analog conversion module 2 is set to 3GS/s, and the number of the corresponding waveform parameter generation modules 1 in the FPGA includes at least 6, that is, the working clock frequency of each waveform parameter generation module 1 is at least 500MHz. In this embodiment, the sampling rate of the digital-to-analog conversion module 2 is set to 3.2GS/s, the number of waveform parameter generation modules 1 is set to 8, and the working clock frequency of each waveform parameter generation module 1 is 400MHz-1000MHz.

In addition, the requirements for the read signal are lower than those for the control signal, and a sampling rate of 1GS/s or more can be used. In this embodiment, the sampling rate is preferably 1.2GS/s, and the number of waveform parameter generation modules 1 is set to 4, and the working clock frequency of each waveform parameter generation module 1 is at least 300MHz. Using an appropriate number of waveform parameter generation modules 1 can avoid the working clock frequency of the waveform parameter generation module 1 being too high to meet the requirements of the internal logic timing of the FPGA, improve the signal-to-noise ratio, reduce resource consumption, and ensure the performance of the FPGA.

As shown in Figures 1 to 3, as an implementation method of the present application, the preset phase difference is a derivative of the number of the waveform parameter generation modules 1. For example, if the number of waveform parameter generation modules 1 is 3, the preset phase difference between the waveform parameters output by each waveform parameter generation module 1 is 1/3, ensuring that when the first clock information is updated, the phase difference and resolution between the waveform parameters output by each waveform parameter generation module 1 are consistent, ensuring that the waveform parameters transmitted to the digital-to-analog conversion module 2 cover the amplitude of the intermediate frequency signal, and the amplitude is evenly distributed within the period, thereby improving the accuracy and resolution of the intermediate frequency signal.

In some embodiments, in order to make the frequency and resolution of the output intermediate frequency signal meet the conditions, the sampling rate of the corresponding DAC also needs to meet certain conditions. Specifically, the working clock frequency of the functional module used to run the Cordic algorithm in the FPGA needs to match the sampling rate of the DAC. However, in the related art, there is only a single functional module running the Cordic algorithm in the FPGA. In order to make the output digital signal meet the accuracy conditions, the module needs to perform multiple iterative operations, resulting in a large output delay and consuming more computing resources. In addition, due to the limitation of the working clock frequency of the FPGA, it is difficult for the module to achieve a more accurate logic timing when running the output digital signal at a high clock frequency.

Therefore, it is necessary to provide a signal generating device, which can generate primary signal parameters according to the input phase control information based on the Cordic algorithm through multiple signal parameter generating modules, and by inputting phase control information that complies with specified rules into different signal parameter generating modules, the phase difference between the primary signal parameters output by the multiple signal parameter generating modules is an integer multiple of the specified phase difference, and the primary signal parameters output by the multiple signal parameter generating modules are spliced to form a target signal parameter corresponding to the period of the target intermediate frequency signal, and then the target intermediate frequency signal is generated according to the target signal parameter through the digital-to-analog conversion module, so that when the accuracy of the output intermediate frequency signal meets the conditions, the operating frequency of a single signal parameter generating module is reduced to achieve more accurate logic timing.

Please refer to Fig. 4. The signal generating device provided in the embodiment of the present application may further include a plurality of signal parameter generating modules 4.

In this embodiment, multiple signal parameter generating modules 4 are used to generate primary signal parameters based on the Cordic algorithm according to the input phase control information; wherein the phase control information input by different signal parameter generating modules conforms to the specified rules, so that the phase difference between the primary signal parameters output by the multiple signal parameter generating modules is an integer multiple of the specified phase difference.

In this embodiment, the phase control information can be used to indicate the angle at which the initial vector needs to be iteratively rotated at each working clock moment. Specifically, for example, for the first signal parameter generating module, the phase control information can be a single rotation angle. For other signal parameter generating modules except the first signal parameter generating module, the phase control information can be the sum of a single rotation angle and an integer multiple of a specified angle value.

In this embodiment, the primary signal parameters can be used to represent the coordinate parameters of multiple vectors formed by multiple rotations of the initial vector. Specifically, the number of coordinate parameters included in the primary signal parameters can be determined by a single rotation angle.

In this embodiment, the signal parameter generation module 4 can use the Cordic algorithm in a two-dimensional rectangular coordinate system. The specific process of the signal parameter generation module 4 generating primary signal parameters based on the Cordic algorithm according to the input phase control information is as follows.

Please refer to Figure 5. In this embodiment, there is a first initial vector ( _x0 , _y0 ) in the two-dimensional coordinate system, the first initial vector is located on the X axis and _x0 >0, _y0 =0. In some embodiments, the first initial vector may have an angle β with the positive direction of the X axis (not shown in Figure 2), then _x0 >0, _y0 >0.

The first phase control information Ph1 is input to the first signal parameter generating module. Specifically, the first phase control information Ph1 may include a single rotation angle α of the vector. Then, the first initial vector is rotated counterclockwise by an angle α to obtain First vector (x′ ₀ , y′ ₀ ). See Formula 1. The coordinate parameters of the first vector (x′ ₀ , y′ ₀ ) can be expressed by the coordinates of the first initial vector (x ₀ , y ₀ ) and a single rotation angle α.

The second vector can be obtained by rotating the first vector counterclockwise by an angle of α. Similarly, the first initial vector can be iteratively rotated counterclockwise by an angle of α to obtain multiple vectors and corresponding multiple coordinate parameters, and the multiple coordinate parameters are used as the first primary signal parameters. Specifically, for example, if α is 1°, 360 coordinate parameters can be obtained by iteratively rotating the first initial vector. If α is 2°, 180 coordinate parameters can be obtained by iteratively rotating the first initial vector.

The second phase control information Ph2 is input to the second signal parameter generation module. Specifically, the second phase control information Ph2 may include a single rotation angle α and a specified angle value θ. The second signal parameter generation module rotates the first initial vector counterclockwise by an angle θ to obtain a second initial vector (x ₁ , y ₁ ). The second primary signal parameter can be obtained by repeating the above process to iteratively rotate the second initial vector for one circle. The single rotation angle α in the second phase control information and the single rotation angle α in the first phase control information have the same value. The phase difference between the second primary signal parameter and the first primary signal parameter is the phase difference corresponding to the angle θ.

In this embodiment, after generating the primary signal parameters, the single signal parameter generating module 4 can directly send the primary signal parameters to the digital-to-analog conversion module. In some embodiments, after generating the primary signal parameters, the single signal parameter generating module 4 can temporarily store the primary signal parameters in a register, and when the primary signal parameters generated by the multiple signal parameter generating modules 4 form target signal parameters corresponding to at least one cycle of the target intermediate frequency signal, the multiple signal parameter generating modules 4 send the generated multiple primary signal parameters to the digital-to-analog conversion module together.

In this implementation, the working clock frequencies fd of the multiple signal parameter generating modules 4 may be provided by the same clock source to achieve working clock synchronization of the multiple signal parameter generating modules 4 .

In this embodiment, the digital-to-analog conversion module 2 can be used to generate a target intermediate frequency signal according to a target signal parameter formed by a plurality of primary signal parameters arranged according to a specified phase difference. Specifically, after receiving a plurality of primary signal parameters sent by a plurality of signal parameter generation modules 4, the digital-to-analog conversion module can determine the output order of the plurality of primary signal parameters according to the specified phase difference, and arrange the plurality of primary signal parameters according to the output order and the specified phase difference to form a target signal parameter, so that the number of coordinate parameters contained in the target signal parameter matches the sampling rate condition that the digital-to-analog conversion module needs to meet, and then generate a target intermediate frequency signal according to the target signal parameter.

In this embodiment, the digital-to-analog conversion module 2 can generate a target intermediate frequency signal according to target signal parameters formed by multiple primary signal parameters, so that the digital-to-analog conversion module 2 outputs a target intermediate frequency signal that meets accuracy conditions under accurate logical timing.

In some embodiments, the frequency of the target intermediate frequency signal has a first correlation with the frequency of the manipulation signal and/or the read signal of the quantum processor; wherein the first correlation is used to characterize a first frequency condition satisfied by the frequency of the target intermediate frequency signal when the frequency of the manipulation signal and/or the read signal satisfies the accuracy condition of the quantum processor.

When executing the quantum computing operation process, the operating frequency of the quantum processor is usually between 6GHz and 8GHz. In order to realize the manipulation of the quantum bit state and the reading of the quantum bit state after the quantum gate operation, the manipulation signal and the reading signal after the mixing process need to be close to the operating frequency of the quantum processor. When the frequency of the manipulation signal and/or the reading signal reaches the GHz level, the first frequency condition that the frequency of the target intermediate frequency signal needs to meet can be that the frequency is within the range of 200MHz-500MHz, and the resolution of the target intermediate frequency signal is not less than 1KHz.

In this embodiment, since the frequency of the target intermediate frequency signal satisfies the first correlation relationship with the frequency of the manipulation signal and/or the read signal, the manipulation signal and/or the read signal obtained by mixing the target intermediate frequency signal can meet the accuracy condition of the quantum processor.

In some embodiments, the number of the signal parameter generating modules 4 has a second correlation relationship with the frequency of the target intermediate frequency signal; wherein the second correlation relationship is used to characterize the quantity condition satisfied by the number of the signal parameter generating modules 4 when the frequency of the target intermediate frequency signal satisfies the first frequency condition.

In this embodiment, the number of signal parameter generation modules 4 is associated with the frequency of the target intermediate frequency signal through the sampling rate of the DAC. According to the Nyquist sampling theorem, in order to enable the sampled digital signal to retain the information of the original signal before sampling, the sampling rate is twice the output signal frequency. However, due to the limited out-of-band suppression characteristics of the image rejection filter, the maximum output signal frequency is generally taken as 0.45 times the sampling rate. For example, when the frequency of the target intermediate frequency signal output by the DAC is 200MHz-500MHz, the sampling rate of the DAC is not less than 1GS/s.

In this embodiment, the number of signal parameter generating modules 4 is determined according to the sampling rate of the DAC and the working clock frequency of a single signal parameter generating module 4. The working clock frequency of a single signal parameter generating module 4 can be a preset value. Specifically, for example, the frequency of the target intermediate frequency signal is 500MHz, and the sampling rate of the digital-to-analog conversion module is 1.2GS/s. When the working clock frequency of a single signal parameter generating module 4 is 400MHz, the number of signal parameter generating modules 4 is 3; when the working clock frequency of a single signal parameter generating module 4 is 300MHz, the number of signal parameter generating modules 4 is 4. The more the number of signal parameter generating modules 4, the lower the working clock frequency of a single signal parameter generating module 4. Since the working clock frequency of a single signal parameter generating module 4 is limited by the working frequency of the FPGA, a lower working clock frequency can enable the signal parameter generating module 4 to work under a more accurate logic timing. The embodiment of this specification does not specifically limit the number of signal parameter generating modules 4.

Therefore, the sampling rate of the DAC that outputs the target intermediate frequency signal of the target intermediate frequency signal can be determined according to the frequency of the target intermediate frequency signal, and then the number of signal parameter generating modules 4 can be determined according to the sampling rate of the DAC and the working clock frequency of a single signal parameter generating module 4, so as to ensure that multiple signal parameter generating modules 4 operate under relatively accurate logical timing.

In some implementations, the phase control information is determined according to the number of the signal parameter generating modules 4 and the working clock frequency, output frequency and data bit width of the signal parameter generating modules 4 .

In this embodiment, the output frequency of the signal parameter generating module 4 can be used to represent the number of coordinate parameters included in the primary signal parameters output by a single signal parameter generating module 4 per unit time. The output frequency of the signal parameter generating module 4 can be obtained by adjusting the frequency control word. Specifically, the frequency control word can be the rotation angle of the vector corresponding to the coordinate parameter output by the signal parameter generating module 4 at each working clock relative to the vector corresponding to the previous coordinate parameter in the two-dimensional rectangular coordinate system. For example, referring to FIG. 5, the frequency control word can be the rotation angle α of the vector (x′ ₀ , y′ ₀ ) relative to the vector (x ₀ , y ₀ ).

Since the frequency of the target intermediate frequency signal can vary within the range of 200 MHz-500 MHz, the output frequency of the single signal parameter generating module 4 can be adjusted by changing the frequency control word to match intermediate frequency signals of different frequencies.

In this embodiment, the data bit width of the signal parameter generating module 4 can be used to represent the data width transmitted once by the signal parameter generating module 4. The data bit width of the signal parameter generating module 4 can be determined according to the resolution of the intermediate frequency signal.

Please refer to Formula 2. In this implementation, it can be determined according to the working clock frequency, output frequency and data bit width of the signal parameter generation module 4 .

Among them, F is the frequency control word, PW is the data bit width of the signal parameter generation module 4, fo is the output frequency of the signal parameter generation module 4, and fd is the working clock frequency of the signal parameter generation module 4. Among them, the highest bit of PW is the sign bit, and the next highest two bits are integer bits.

In this embodiment, the phase control information may include a frequency control word and an integer multiple of a specified phase difference. Specifically, referring to FIG5 , the specified phase difference may be a rotation angle θ of the vector (x ₁ , y ₁ ) relative to the vector (x ₀ , y ₀ ). Referring to Formula 3, the specified phase difference may be determined according to the operating clock frequency, output frequency and data bit width of the signal parameter generating module 4 and the number of the signal parameter generating modules 4 .

Wherein, ΔPh is the specified phase difference, PW is the data bit width of the signal parameter generation module 4, fo is the output frequency of the signal parameter generation module 4, fd is the working clock frequency of the signal parameter generation module 4, and N is the number of the signal parameter generation modules 4. Wherein, the highest bit of PW is the sign bit, and the next highest two bits are integer bits.

By adjusting the frequency control word and the specified phase difference in the phase control information, the output frequencies of the multiple signal parameter generating modules 4 can be adjusted to match intermediate frequency signals of different frequencies.

In some implementations, the designated rule may include that the difference between the phase control information input by the adjacent signal parameter generation module 4 is a designated phase difference.

Please refer to Fig. 5. In this embodiment, the specified phase difference may be a rotation angle θ of the vector ( _x1 , _y1 ) relative to the vector ( _x0 , _y0 ) and a rotation angle θ of the vector ( _x2 , _y2 ) relative to the vector ( _x1 , _y1 ).

By inputting phase control information whose difference is a specified phase difference into adjacent signal parameter generating modules 4, it can be achieved that the phase difference between the primary signal parameters output by multiple signal parameter generating modules 4 is an integer multiple of the specified phase difference.

In some embodiments, the signal generating device including multiple signal parameter generating modules may also include the data processing module 3 mentioned above, and the data processing module 3 can be used to perform data processing on the multiple primary signal parameters to obtain target signal parameters corresponding to at least one period of the target intermediate frequency signal.

Please refer to Figure 6. In this embodiment, after generating the primary signal parameters, the signal parameter generation module 4 can send the primary signal parameters to the data processing module 3. After receiving the multiple primary signal parameters, the data processing module 3 can perform data processing on the coordinate parameters in the multiple two-dimensional rectangular coordinate systems included in the primary signal parameters according to the data format and data bit width requirements for converting digital signals to analog signals. Specifically, according to Formula 1, the cosine value and tangent value of the rotation angle of the vector corresponding to the coordinate parameters relative to the initial vector can be obtained from the coordinate parameters, but the FPGA cannot directly calculate the sine value, cosine value and tangent value.

Please refer to Formula 4 and Table 1. Table 1 shows the corresponding values of θ _i , tanθ _i , and cosθ _i when tanθ _i = 2 ^-i and i takes values of 0, 1, ..., 6, etc. The data processing module can first perform data conversion on the sine value, cosine value, and tangent value to achieve the rotation angle of the vector corresponding to the coordinate parameter relative to the initial vector by shifting and adding and subtracting.

When the rotation angle θ satisfies When , θ can be expressed in the form of Formula 5, where s _i ∈{-1,1}.

Table 1

θ _i = arctan2 ^-i Formula 4

Referring to Formula 6, the coordinate parameters of the vector (x _k , y _k ) obtained by rotating the initial vector for the kth iteration are:

The data processing module 3 can determine the output order of multiple primary signal parameters according to the specified phase difference. Specifically, the data processing module 3 can use the first primary signal parameter generated by the first signal parameter generating module as a reference, compare the multiple relationship between the phase difference between the multiple primary signal parameters and the first primary signal parameter and the specified phase difference, and determine the output order of the multiple primary signal parameters based on the multiple relationship. For example, the output order of the primary signal parameters can be determined according to the rule of increasing multiples, and the smaller the multiple, the higher the output order of the primary signal parameters; the output order of the primary signal parameters can also be determined according to the rule of decreasing multiples, and the smaller the multiple, the lower the output order of the primary signal parameters.

After determining the output order of the multiple primary signal parameters, the data processing module 3 can perform splicing and data format conversion on the multiple coordinate parameters included in the multiple primary signal parameters according to the specified phase difference and output order to obtain A target signal parameter corresponding to at least one period of the target intermediate frequency signal is obtained, and the target signal parameter is sent to the digital-to-analog conversion module 2.

In this embodiment, the plurality of signal parameter generating modules 4 respectively send the generated primary signal parameters to the same data processing module 3. The data processing module 3 sends the generated target signal parameters to the digital-to-analog conversion module 2 after performing data conversion processing on the plurality of primary signal parameters.

In some implementations, multiple signal parameter generation modules 4 may send the primary signal parameters generated by them to multiple data processing modules 3. Specifically, for example, each signal parameter generation module 4 may send the primary signal parameters to the data processing module 3 corresponding thereto, or every two signal parameter generation modules 4 may send the primary signal parameters to the same data processing module 3. The implementations of this specification do not specifically limit the number of data processing modules 3.

In some embodiments, multiple data processing modules 3 can be used to perform different data processing on the coordinate parameters included in the primary signal parameters. Specifically, for example, a single data processing module 3 can be used to perform preliminary data processing on the coordinate parameters included in the primary signal parameters, convert them into coordinate parameters that meet the format requirements of the digital-to-analog conversion module 2, and then splice the coordinate parameters that meet the format requirements of the digital-to-analog conversion module 2 in multiple primary signal parameters according to the specified phase difference and output order to form target signal parameters, and then send the target signal parameters to the digital-to-analog conversion module 2. The embodiments of this specification do not specifically limit the functions of a single data processing module 3.

Before the primary signal parameters generated by the signal parameter generation module 4 are transmitted to the digital-to-analog conversion module 2, the primary signal parameters are processed by the data processing module 3, so that the target signal parameters received by the digital-to-analog conversion module 2 meet the data bit width and data format requirements of the digital-to-analog conversion module 2, thereby improving the conversion efficiency of the digital-to-analog conversion module 2.

In some embodiments, the signal parameter generation module 4 and the data processing module 3 can be taken as a module group, and the module group can be instantiated multiple times inside the FPGA to form multiple module groups. Each module group is connected to a digital-to-analog conversion module 2 to output multiple intermediate frequency signals to meet the control requirements of multi-bit quantum bits on the quantum processor.

In some embodiments, the signal generating device further includes a phase accumulator unit 11 having a specified corresponding relationship with the signal parameter generating module 4. In some embodiments, the phase accumulator unit 11 can be simply referred to as an accumulator. The accumulator is used to accumulate the phase control information according to the working clock frequency of the signal parameter generating module 4, and send the accumulated phase control information to the signal parameter generating module 4.

Please refer to FIG7 . In this embodiment, the designated corresponding relationship may be a one-to-one correspondence, that is, each signal parameter generating module 4 may have a corresponding phase accumulator unit 11 .

In this embodiment, the phase accumulator unit 11 is used to accumulate the phase control information according to the working clock frequency of the signal parameter generating module 4, and send the accumulated phase control information to the signal parameter generating module 4, which may include: the phase accumulator unit 11 can accumulate a frequency control word to the phase control information based on the previous phase control information in each working clock, and then send the accumulated phase control information to the signal parameter generating module 4, so as to control the signal parameter generating module 4 to change the output according to the accumulated phase control information at each working clock moment. Specifically, the working clock moment can be determined according to the working clock frequency. For example, the working clock frequency is 400MHz, and the working clock is the reciprocal of the working clock frequency, that is, 2.5ns. Take time 0 as the initial working clock moment, and every moment of 2.5ns is the working clock moment.

Please refer to Figure 5. Taking the first signal parameter generation module as an example, the phase control information includes a frequency control word. In a two-dimensional rectangular coordinate system, the vector (x ₀ , y ₀ ) corresponds to the initial working clock moment, and the initial phase control information is a rotation angle α. Then, at the time of 2.5ns, the vector (x ₀ , y ₀ ) rotates counterclockwise by an angle α to obtain a vector (x′ ₀ , y′ ₀ ). The first signal parameter generation module outputs the coordinate parameters of the vector (x′ ₀ , y′ ₀ ). The phase accumulator unit 11 can accumulate a rotation angle α on the basis of the previous phase control information within each working clock, that is, within the period from 2.5ns to 5ns, the phase accumulator unit 11 accumulates a rotation angle α on the basis of the initial phase control information to obtain the first phase control information, and sends the first phase control information to the first signal parameter generating module, so that at the time of 5ns, the control vector (x′ ₀ , y′ ₀ ) is rotated again in the counterclockwise direction by an angle α to obtain the vector (x″ ₀ , y″ ₀ ). A signal parameter generation module outputs the coordinate parameters of the vector (x" ₀ , y" ₀ ). This is deduced in this way, until the vector (x ₀ , y ₀ ) rotates one circle, the number of coordinate parameters output by the first signal parameter generation module is 360°/α.

The phase control information of the input signal parameter generating module 4 is continuously changed through the phase accumulator unit 11, so that the signal parameter generating module 4 generates primary signal parameters according to the received phase control information, which simplifies the process of the signal parameter generating module 4 generating primary signal parameters and reduces the output delay of the signal parameter generating module 4.

In some embodiments, the working clocks of the phase accumulator unit 11 and the signal parameter generating module 4 are the same as the working clock of the digital-to-analog conversion module, so as to achieve working clock synchronization of the signal parameter generating module 4 and the corresponding phase accumulator unit 11, as well as working clock synchronization of multiple signal parameter generating modules 4 and the corresponding multiple phase accumulator units 11 and the digital-to-analog conversion module.

Based on the same application concept, as shown in Figure 8, an embodiment of the present application provides a quantum control system, including any of the above-mentioned signal generating devices, microwave sources, and signal mixing devices, wherein the signal mixing device is used to mix the intermediate frequency signal output by the signal generating device and the microwave signal output by the microwave source and output a control signal and/or a reading signal.

Based on the same application concept, an embodiment of the present application provides a quantum computer, including the above-mentioned quantum control system and quantum processor, wherein the quantum control system outputs a control signal for controlling the quantum processor to perform operations, and a read signal for measuring the operation results of the quantum processor.

The above describes in detail the structure, features and effects of the present application based on the embodiments shown in the drawings. The above is only a preferred embodiment of the present application, but the present application does not limit the scope of implementation to what is shown in the drawings. Any changes made in accordance with the concept of the present application, or modifications to equivalent embodiments with equivalent changes, which still do not exceed the spirit covered by the description and drawings, should be within the protection scope of the present application.

Claims (20)

1. A signal generating device, characterized in that it is used to output an intermediate frequency signal carrying quantum state encoding information, and the signal generating device includes a plurality of waveform parameter generating modules and a digital-to-analog conversion module;

   The waveform parameter generation module outputs the waveform parameters of the intermediate frequency signal according to the first clock information and the frequency control word; wherein the waveform parameters output by each of the waveform parameter generation modules have a preset phase difference, and the preset phase difference is used to control the waveform parameters to be output in phase order;

   The digital-to-analog conversion module outputs a corresponding intermediate frequency signal according to the waveform parameters output by each of the waveform parameter generation modules;

   The preset phase difference is determined according to the first clock information of each waveform parameter generating module and the output frequency of outputting the waveform parameter.
2. The signal generating device according to claim 1 is characterized in that it also includes a data processing module, which splices the waveform parameters output by each of the waveform parameter generating modules according to the output bit sequence, and sends the spliced waveform parameters to the digital-to-analog conversion module.
3. The signal generating device according to claim 2, characterized in that the waveform parameter generating module comprises a phase accumulator unit and a memory unit;

   The phase accumulator unit is used to accumulate the frequency control word and the current phase value according to the first clock information, and send the phase data obtained by adding the accumulated phase value and the phase control word to the memory unit;

   The memory unit is used to store the waveform parameters according to the address, and output the waveform parameters corresponding to the address to the data processing module according to the phase data.
4. The signal generating device according to claim 3 is characterized in that the data bit width of the phase accumulator unit includes 32 bits.
5. The signal generating device according to claim 4 is characterized in that the frequency control word is determined according to the output frequency of the waveform parameter generating module, the data bit width and the first clock information.
6. The signal generating device according to claim 4, characterized in that the preset phase difference is determined as:
   

   Among them, Ph is the preset phase difference, N is the data bit width of the phase accumulator unit, fd is the first clock information, and fo is the output frequency of the waveform parameter generation module.
7. The signal generating device according to claim 3 is characterized in that the working clocks of the phase accumulator unit and the memory unit are co-sourced with the working clock of the digital-to-analog conversion module.
8. The signal generating device according to claim 2 is characterized in that the waveform parameter generating module and the data processing module are both functional modules within the FPGA.
9. The signal generating device according to claim 8 is characterized in that one of the FPGAs includes a plurality of the waveform parameter generating modules and at least one of the data processing modules.
10. The signal generating device according to claim 1 is characterized in that the sampling rate of the digital-to-analog conversion module is at least 1 GS/s, and the number of the waveform parameter generation modules is at least 2.
11. The signal generating device according to claim 1 is characterized in that the sampling rate of the digital-to-analog conversion module is at least 3GS/s, and the number of the waveform parameter generation modules is at least 6.
12. The signal generating device according to claim 1, characterized in that the waveform parameter generating module comprises a phase accumulator unit, and the signal generating device further comprises:

    Multiple signal parameter generation modules, used to generate primary signal parameters according to input phase control information based on Cordic algorithm respectively; wherein the phase control information input by different signal parameter generation modules conforms to a specified rule, so that the phase difference between the primary signal parameters output by the multiple signal parameter generation modules is an integer multiple of the specified phase difference;

    The digital-to-analog conversion module is also used to generate the intermediate frequency signal according to the target signal parameters formed by the multiple primary signal parameters arranged according to the specified phase difference;

    Among them, the phase accumulator unit has a specified corresponding relationship with the signal parameter generation module, and the phase accumulator unit is used to accumulate the phase control information according to the working clock frequency of the signal parameter generation module, and send the accumulated phase control information to the signal parameter generation module.
13. The signal generating device according to claim 12 is characterized in that the frequency of the intermediate frequency signal has a first correlation with the frequency of the control signal and/or the read signal of the quantum processor; wherein the first correlation is used to characterize the first frequency condition satisfied by the frequency of the intermediate frequency signal when the frequency of the control signal and/or the read signal satisfies the accuracy condition of the quantum processor.
14. The signal generating device according to claim 13 is characterized in that the number of the signal parameter generating modules has a second correlation relationship with the frequency of the intermediate frequency signal; wherein the second correlation relationship is used to characterize the quantity condition satisfied by the number of the signal parameter generating modules when the frequency of the intermediate frequency signal satisfies the first frequency condition.
15. The signal generating device according to claim 12 is characterized in that the phase control information is determined according to the number of the signal parameter generating modules and the working clock frequency, output frequency and data bit width of the signal parameter generating modules.
16. The signal generating device according to claim 15 is characterized in that the specified rule includes the difference between the phase control information input by adjacent signal parameter generation modules being the specified phase difference.
17. The signal generating device according to claim 12 is characterized in that it also includes a data processing module for performing data processing on a plurality of the primary signal parameters to obtain a target signal parameter corresponding to at least one period of the intermediate frequency signal.
18. The signal generating device according to claim 12 is characterized in that a working clock of the signal parameter generating module is co-sourced with a working clock of the digital-to-analog conversion module.
19. A quantum control system, characterized in that it comprises the signal generating device, microwave source, and signal mixing device as described in any one of claims 1 to 18, wherein the signal mixing device is used to mix the intermediate frequency signal output by the signal generating device and the microwave signal output by the microwave source and output a control signal and/or a read signal.
20. A quantum computer, characterized in that it includes the quantum control system and quantum processor described in claim 19, wherein the quantum control system outputs a control signal for controlling the quantum processor to perform operations, and a read signal for measuring the operation results of the quantum processor.