WO2024140240A1 - Signal generation device, quantum control system, and quantum computer - Google Patents
Signal generation device, quantum control system, and quantum computer Download PDFInfo
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- Quantum computing is a new computing model that follows the laws of quantum mechanics to control basic information units for computing.
- the basic information unit of classical computing is the classical bit
- the basic information unit of quantum computing is the quantum bit.
- the classical bit can only be in one state, that is, 0 or 1, but based on the principle of quantum mechanics superposition, the state of the quantum bit can be in a superposition state of multiple possibilities. Therefore, the computing efficiency of quantum computing far exceeds that of classical computing.
- the data bit width of the phase accumulator unit includes 32 bits.
- the frequency control word is determined according to the output frequency of the waveform parameter generation module, the data bit width and the first clock information.
- the present application provides a quantum computer, comprising a quantum control system and a quantum processor as described in the second aspect, wherein the quantum control system outputs a control signal for controlling the quantum processor to perform an operation, and a read signal for measuring the operation result of the quantum processor.
- the embodiment of the present application adopts multiple signal parameter generation modules to generate primary signal parameters according to the input phase control information based on the Cordic algorithm, and the phase control information input by different signal parameter generation modules conforms to the specified rules, so that the phase difference between the primary signal parameters output by the multiple signal parameter generation modules is an integer multiple of the specified phase difference, so that the target signal parameters formed by arranging the primary signal parameters according to the specified phase difference can correspond to at least one complete cycle of the target intermediate frequency signal, and the accuracy of the target signal parameters can make the intermediate frequency signal output by the digital-to-analog conversion module according to the target signal parameters meet the accuracy conditions, thereby realizing that the digital-to-analog conversion module outputs the target intermediate frequency signal that meets the accuracy conditions under relatively accurate logical timing.
- FIG2 is a schematic structural diagram of a signal generating device provided by another embodiment of the present application.
- FIG3 is a schematic diagram of the structure of a waveform parameter generation module provided in yet another embodiment of the present application.
- FIG. 4 is a schematic diagram of the structure of a signal generating device provided in yet another embodiment of the present application.
- FIG6 is a schematic diagram of the structure of a signal generating device provided in yet another embodiment of the present application.
- FIG. 7 is a schematic diagram of the structure of a signal generating device provided in yet another embodiment of the present application.
- FIG8 is a schematic diagram of the structure of a quantum control system provided in an embodiment of the present application.
- the output bit sequence of the waveform parameter generation module 1 is arranged from low to high, and the corresponding waveform parameters are also arranged in a bit sequence from low to high, ensuring that the spliced waveform parameters output by the data processing module 3 are the required amplitude parameters of the intermediate frequency signal, ensuring the signal accuracy of the intermediate frequency signal.
- the accuracy of the output intermediate frequency signal can be improved by fine-tuning the frequency control word and the phase difference values preset by several waveform parameter generation modules 1.
- a signal generating device which can generate primary signal parameters according to the input phase control information based on the Cordic algorithm through multiple signal parameter generating modules, and by inputting phase control information that complies with specified rules into different signal parameter generating modules, the phase difference between the primary signal parameters output by the multiple signal parameter generating modules is an integer multiple of the specified phase difference, and the primary signal parameters output by the multiple signal parameter generating modules are spliced to form a target signal parameter corresponding to the period of the target intermediate frequency signal, and then the target intermediate frequency signal is generated according to the target signal parameter through the digital-to-analog conversion module, so that when the accuracy of the output intermediate frequency signal meets the conditions, the operating frequency of a single signal parameter generating module is reduced to achieve more accurate logic timing.
- the single signal parameter generating module 4 can directly send the primary signal parameters to the digital-to-analog conversion module.
- the single signal parameter generating module 4 can temporarily store the primary signal parameters in a register, and when the primary signal parameters generated by the multiple signal parameter generating modules 4 form target signal parameters corresponding to at least one cycle of the target intermediate frequency signal, the multiple signal parameter generating modules 4 send the generated multiple primary signal parameters to the digital-to-analog conversion module together.
- the designated rule may include that the difference between the phase control information input by the adjacent signal parameter generation module 4 is a designated phase difference.
- the signal parameter generation module 4 can send the primary signal parameters to the data processing module 3.
- the data processing module 3 can perform data processing on the coordinate parameters in the multiple two-dimensional rectangular coordinate systems included in the primary signal parameters according to the data format and data bit width requirements for converting digital signals to analog signals. Specifically, according to Formula 1, the cosine value and tangent value of the rotation angle of the vector corresponding to the coordinate parameters relative to the initial vector can be obtained from the coordinate parameters, but the FPGA cannot directly calculate the sine value, cosine value and tangent value.
- the data processing module 3 can determine the output order of multiple primary signal parameters according to the specified phase difference. Specifically, the data processing module 3 can use the first primary signal parameter generated by the first signal parameter generating module as a reference, compare the multiple relationship between the phase difference between the multiple primary signal parameters and the first primary signal parameter and the specified phase difference, and determine the output order of the multiple primary signal parameters based on the multiple relationship. For example, the output order of the primary signal parameters can be determined according to the rule of increasing multiples, and the smaller the multiple, the higher the output order of the primary signal parameters; the output order of the primary signal parameters can also be determined according to the rule of decreasing multiples, and the smaller the multiple, the lower the output order of the primary signal parameters.
- an embodiment of the present application provides a quantum computer, including the above-mentioned quantum control system and quantum processor, wherein the quantum control system outputs a control signal for controlling the quantum processor to perform operations, and a read signal for measuring the operation results of the quantum processor.
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Abstract
The present application belongs to the technical field of quantum, and discloses a signal generation device, a quantum control system, and a quantum computer, for use in outputting an intermediate frequency signal carrying quantum state coding information. The signal generation device comprises a plurality of waveform parameter generation modules and a digital-to-analog conversion module; each waveform parameter generation module outputs a waveform parameter of an intermediate frequency signal according to first clock information and a frequency control word, wherein a preset phase difference exists between the waveform parameters output by the waveform parameter generation modules; the digital-to-analog conversion module outputs corresponding intermediate frequency signals according to the waveform parameters output by the waveform parameter generation modules, wherein the preset phase difference is determined according to the first clock information of the waveform parameter generation modules and the output frequency for outputting the waveform parameters. The present application improves the frequency and precision of intermediate frequency signals that are output, and further improves the control and reading precision of a quantum processor.
Description
本申请要求于2022年12月30日提交中国专利局、申请号为202211741939.4、申请名称为“信号发生装置、量子控制系统及量子计算机”的中国专利申请,以及于2023年3月13日提交中国专利局、申请号为2023102535772、申请名称为“信号发生装置、量子控制系统及量子计算机”的中国专利申请的优先权,其全部内容通过引用结合在本申请中。This application claims priority to the Chinese patent application filed with the Chinese Patent Office on December 30, 2022, with application number 202211741939.4 and application name “Signal Generating Device, Quantum Control System and Quantum Computer”, and the Chinese patent application filed with the Chinese Patent Office on March 13, 2023, with application number 2023102535772 and application name “Signal Generating Device, Quantum Control System and Quantum Computer”, the entire contents of which are incorporated by reference in this application.
本申请涉及电子领域,更为具体地,涉及一种信号发生装置、量子控制系统及量子计算机。The present application relates to the field of electronics, and more specifically, to a signal generating device, a quantum control system and a quantum computer.
量子计算是一种遵循量子力学规律调控基本信息单元进行计算的新型计算模式。经典计算的基本信息单元是经典比特,量子计算的基本信息单元是量子比特,经典比特只能处于一种状态,即0或1,而基于量子力学态叠加原理,量子比特的状态可以处于多种可能性的叠加状态,因而量子计算的计算效率远远超过经典计算的计算效率。Quantum computing is a new computing model that follows the laws of quantum mechanics to control basic information units for computing. The basic information unit of classical computing is the classical bit, and the basic information unit of quantum computing is the quantum bit. The classical bit can only be in one state, that is, 0 or 1, but based on the principle of quantum mechanics superposition, the state of the quantum bit can be in a superposition state of multiple possibilities. Therefore, the computing efficiency of quantum computing far exceeds that of classical computing.
量子计算的运算过程主要由量子处理器执行。具体运算过程包括:先向处于基态的量子比特施加操控信号,再对经操控信号操作后的量子比特施加读取信号以获取量子计算结果。因此,操控信号和读取信号的频率与量子处理器的工作频率较为接近。而量子处理器的工作频率通常为吉赫兹,如6GHz,因此,操控信号和读取信号的频率通常在6GHz-8GHz之间。The operation process of quantum computing is mainly performed by the quantum processor. The specific operation process includes: first applying a control signal to the quantum bit in the ground state, and then applying a read signal to the quantum bit after the control signal operation to obtain the quantum computing result. Therefore, the frequency of the control signal and the read signal is close to the operating frequency of the quantum processor. The operating frequency of the quantum processor is usually gigahertz, such as 6GHz, so the frequency of the control signal and the read signal is usually between 6GHz-8GHz.
目前,一般通过对中频信号和微波信号进行混频处理获得操控信号和读取信号,因此,中频信号的精度会对操控信号和读取信号的精度产生直接影响。在相关技术中,通常采用信号发生器、任意波形发生器等信号源器件输出中频信号,由于信号源器件精度限制,输出的中频信号存在精度较低的问题,进而影响到混频后的操控信号和读取信号的精度,无法满足量子处理器执行运算过程时所需的操控和读取精度要求。At present, the control signal and the read signal are generally obtained by mixing the intermediate frequency signal and the microwave signal. Therefore, the accuracy of the intermediate frequency signal will have a direct impact on the accuracy of the control signal and the read signal. In the relevant technology, the intermediate frequency signal is usually output by a signal source device such as a signal generator or an arbitrary waveform generator. Due to the accuracy limitation of the signal source device, the output intermediate frequency signal has a low accuracy problem, which in turn affects the accuracy of the control signal and the read signal after mixing, and cannot meet the control and read accuracy requirements required by the quantum processor when performing the calculation process.
发明内容Summary of the invention
本申请的目的是提供一种信号发生装置、量子控制系统及量子计算机,弥补了现有技术中信号源器件输出的中频信号的频率和精度均比较低的缺点,提高了输出的中频信号的频率和精度,进而提高了对量子处理器的操控和读取精度。The purpose of this application is to provide a signal generating device, a quantum control system and a quantum computer, which make up for the shortcomings of the relatively low frequency and accuracy of the intermediate frequency signal output by the signal source device in the prior art, improve the frequency and accuracy of the output intermediate frequency signal, and thus improve the control and reading accuracy of the quantum processor.
本申请技术方案具体如下:The specific technical solution of this application is as follows:
第一方面,本申请提供了一种信号发生装置,用于输出携带量子态编码信息的中频信号,所述信号发生装置包括若干个波形参数生成模块和数模转换模块;所述波形参数生成模块依据第一时钟信息和频率控制字输出所述中频信号的波形参数;其中,各所述波形参数生成模块输出的波形参数之间具有预设相位差,所述预设相位差用于控制所述波形参数按照相位次序输出;所述数模转换模块依据各所述波形参数生成模块输出的波形参数输出对应的中频信号;其中,所述预设相位差依据各所述波形参数生成模块的第一时钟信息及
输出所述波形参数的输出频率确定。In a first aspect, the present application provides a signal generating device for outputting an intermediate frequency signal carrying quantum state encoding information, the signal generating device comprising a plurality of waveform parameter generating modules and a digital-to-analog conversion module; the waveform parameter generating module outputs the waveform parameters of the intermediate frequency signal according to first clock information and a frequency control word; wherein there is a preset phase difference between the waveform parameters output by each of the waveform parameter generating modules, and the preset phase difference is used to control the waveform parameters to be output in phase order; the digital-to-analog conversion module outputs a corresponding intermediate frequency signal according to the waveform parameters output by each of the waveform parameter generating modules; wherein the preset phase difference is based on the first clock information and the frequency control word of each of the waveform parameter generating modules The output frequency of the output waveform parameters is determined.
可选地,信号发生装置还包括数据处理模块,所述数据处理模块对各所述波形参数生成模块输出的波形参数按照输出位序进行拼接,并将拼接后的波形参数发送至所述数模转换模块。Optionally, the signal generating device further comprises a data processing module, which splices the waveform parameters output by each of the waveform parameter generating modules according to an output bit sequence, and sends the spliced waveform parameters to the digital-to-analog conversion module.
可选地,所述波形参数生成模块包括相位累加器单元和存储器单元;所述相位累加器单元用于依据所述第一时钟信息将所述频率控制字与当前相位值累加,并将累加后的相位值与相位控制字相加得到的相位数据发送至所述存储器单元;所述存储器单元用于依据地址存储所述波形参数,并根据所述相位数据输出对应地址的波形参数至所述数据处理模块。Optionally, the waveform parameter generation module includes a phase accumulator unit and a memory unit; the phase accumulator unit is used to accumulate the frequency control word and the current phase value according to the first clock information, and send the phase data obtained by adding the accumulated phase value and the phase control word to the memory unit; the memory unit is used to store the waveform parameters according to the address, and output the waveform parameters of the corresponding address to the data processing module according to the phase data.
可选地,所述相位累加器单元的数据位宽包括32位。Optionally, the data bit width of the phase accumulator unit includes 32 bits.
可选地,所述频率控制字依据所述波形参数生成模块的输出频率、所述数据位宽以及所述第一时钟信息确定。Optionally, the frequency control word is determined according to the output frequency of the waveform parameter generation module, the data bit width and the first clock information.
可选地,所述预设相位差确定为:其中,Ph为所述预设相位差,所述N为所述相位累加器单元的数据位宽,fd为所述第一时钟信息,fo为所述波形参数生成模块的输出频率。Optionally, the preset phase difference is determined as: Among them, Ph is the preset phase difference, N is the data bit width of the phase accumulator unit, fd is the first clock information, and fo is the output frequency of the waveform parameter generation module.
可选地,所述相位累加器单元和所述存储器单元的工作时钟与所述数模转换模块的工作时钟同源。Optionally, the working clocks of the phase accumulator unit and the memory unit are the same as the working clock of the digital-to-analog conversion module.
可选地,所述波形参数生成模块、所述数据处理模块均为FPGA内的功能模块。Optionally, the waveform parameter generation module and the data processing module are both functional modules within the FPGA.
可选地,一个所述FPGA内包括多个所述波形参数生成模块和至少一个所述数据处理模块。Optionally, one of the FPGAs includes a plurality of the waveform parameter generation modules and at least one of the data processing modules.
可选地,所述数模转换模块的采样率至少包括1GS/s,所述波形参数生成模块的数量至少包括2个。Optionally, the sampling rate of the digital-to-analog conversion module is at least 1 GS/s, and the number of the waveform parameter generation modules is at least 2.
可选地,所述数模转换模块的采样率至少包括3GS/s,所述波形参数生成模块的数量至少包括6个。Optionally, the sampling rate of the digital-to-analog conversion module is at least 3GS/s, and the number of the waveform parameter generation modules is at least 6.
可选地,所述波形参数生成模块包括相位累加器单元,所述信号发生装置还包括:多个信号参数生成模块,用于分别基于Cordic算法根据输入的相位控制信息生成初级信号参数;其中,不同信号参数生成模块输入的相位控制信息符合指定规则,使得多个信号参数生成模块输出的初级信号参数之间的相位差为指定相位差的整数倍;数模转换模块,还用于根据按照指定相位差排列的多个初级信号参数形成的目标信号参数,以生成所述中频信号;其中,所述相位累加器单元与所述信号参数生成模块具有指定对应关系,所述相位累加器单元用于依据所述信号参数生成模块的工作时钟频率对所述相位控制信息进行累加,并将累加后的相位控制信息发送至所述信号参数生成模块。Optionally, the waveform parameter generation module includes a phase accumulator unit, and the signal generating device also includes: multiple signal parameter generation modules, which are used to generate primary signal parameters according to the input phase control information based on the Cordic algorithm; wherein the phase control information input by different signal parameter generation modules conforms to the specified rules, so that the phase difference between the primary signal parameters output by the multiple signal parameter generation modules is an integer multiple of the specified phase difference; a digital-to-analog conversion module, which is also used to generate the intermediate frequency signal according to the target signal parameters formed by multiple primary signal parameters arranged according to the specified phase difference; wherein the phase accumulator unit has a specified corresponding relationship with the signal parameter generation module, and the phase accumulator unit is used to accumulate the phase control information according to the working clock frequency of the signal parameter generation module, and send the accumulated phase control information to the signal parameter generation module.
可选地,所述中频信号的频率与量子处理器的操控信号和/或读取信号的频率具有第一关联关系;其中,所述第一关联关系用于表征在所述操控信号和/或读取信号的频率满足所述量子处理器的精度条件的情况下,所述中频信号的频率满足的第一频率条件。Optionally, the frequency of the intermediate frequency signal has a first correlation with the frequency of the control signal and/or the read signal of the quantum processor; wherein the first correlation is used to characterize a first frequency condition satisfied by the frequency of the intermediate frequency signal when the frequency of the control signal and/or the read signal satisfies the accuracy condition of the quantum processor.
可选地,所述信号参数生成模块的数量与所述中频信号的频率具有第二关联关系;其中,所述第二关联关系用于表征在所述中频信号的频率满足所述第一频率条件的情况下,所述信号参数生成模块的数量满足的数量条件。Optionally, the number of the signal parameter generating modules has a second correlation with the frequency of the intermediate frequency signal; wherein the second correlation is used to characterize the quantity condition satisfied by the number of the signal parameter generating modules when the frequency of the intermediate frequency signal satisfies the first frequency condition.
可选地,所述相位控制信息依据所述信号参数生成模块的数量以及所述信号参数生成模块的工作时钟频率、输出频率和数据位宽确定。Optionally, the phase control information is determined according to the number of the signal parameter generating modules and the working clock frequency, output frequency and data bit width of the signal parameter generating modules.
可选地,所述指定规则包括相邻信号参数生成模块输入的相位控制信息的差值为指定相位差。Optionally, the designated rule includes that the difference between phase control information input by adjacent signal parameter generation modules is a designated phase difference.
可选地,信号发生装置还包括数据处理模块,用于对多个所述初级信号参数进行数据处理以获取与所述中频信号的至少一个周期对应的目标信号参数。Optionally, the signal generating device further includes a data processing module, configured to perform data processing on a plurality of the primary signal parameters to obtain a target signal parameter corresponding to at least one period of the intermediate frequency signal.
可选地,所述信号参数生成模块的工作时钟与所述数模转换模块的工作时钟同源。Optionally, the working clock of the signal parameter generating module is the same as the working clock of the digital-to-analog conversion module.
第二方面,本申请提供一种量子控制系统,包括第一方面所述的信号发生装置以及
微波源和信号混频装置,所述信号混频装置用于对所述信号发生装置输出的中频信号以及所述微波源输出的微波信号进行混频处理并输出操控信号和/或读取信号。In a second aspect, the present application provides a quantum control system, comprising the signal generating device described in the first aspect and A microwave source and a signal mixing device, wherein the signal mixing device is used to mix the intermediate frequency signal output by the signal generating device and the microwave signal output by the microwave source and output a control signal and/or a read signal.
第三方面,本申请提供一种量子计算机,包括如第二方面所述的量子控制系统以及量子处理器,所述量子控制系统输出用于控制所述量子处理器执行运算的操控信号、以及对所述量子处理器的运算结果进行测量的读取信号。In a third aspect, the present application provides a quantum computer, comprising a quantum control system and a quantum processor as described in the second aspect, wherein the quantum control system outputs a control signal for controlling the quantum processor to perform an operation, and a read signal for measuring the operation result of the quantum processor.
与现有技术相比,本申请具有以下有益效果。Compared with the prior art, the present application has the following beneficial effects.
本申请的信号发生装置用于输出携带量子态编码信息的中频信号,所述信号发生装置包括若干个波形参数生成模块和数模转换模块;所述波形参数生成模块依据第一时钟信息和频率控制字输出所述中频信号的波形参数;其中,各所述波形参数生成模块输出的波形参数之间具有预设相位差,所述预设相位差用于控制所述波形参数按照相位次序输出;所述数模转换模块依据各所述波形参数生成模块输出的波形参数输出对应的中频信号;其中,所述预设相位差依据各所述波形参数生成模块的第一时钟信息及输出所述波形参数的输出频率确定。The signal generating device of the present application is used to output an intermediate frequency signal carrying quantum state encoding information, and the signal generating device includes a plurality of waveform parameter generating modules and a digital-to-analog conversion module; the waveform parameter generating module outputs the waveform parameters of the intermediate frequency signal according to the first clock information and the frequency control word; wherein, there is a preset phase difference between the waveform parameters output by each of the waveform parameter generating modules, and the preset phase difference is used to control the waveform parameters to be output in phase order; the digital-to-analog conversion module outputs the corresponding intermediate frequency signal according to the waveform parameters output by each of the waveform parameter generating modules; wherein, the preset phase difference is determined according to the first clock information of each of the waveform parameter generating modules and the output frequency of the waveform parameters.
本申请实施例采用多个波形参数生成模块按照统一的第一时钟信息输出若干个波形参数,不仅可以确保工作时钟同步,还可以降低单个波形参数生成模块输出波形参数的工作频率,避免逻辑时序违例;此外,采用多个波形参数生成模块输出的波形参数的总数量与数模转换模块采样率单位时间内的点数相匹配,并对多个波形参数生成模块输出的波形参数之间设置预设相位差,使得传输至数模转换模块的波形参数连续,可以覆盖中频信号一个完整周期内的波形参数,进而提高波形参数的分辨率,确保数模转换模块输出高精度的中频信号;还可以通过调节频率控制字和预设相位差实现数模转换模块输出的中频信号的调节。The embodiment of the present application adopts multiple waveform parameter generation modules to output a number of waveform parameters according to a unified first clock information, which can not only ensure the synchronization of the working clock, but also reduce the working frequency of the waveform parameters output by a single waveform parameter generation module, thereby avoiding logic timing violations; in addition, the total number of waveform parameters output by multiple waveform parameter generation modules is matched with the number of points per unit time of the sampling rate of the digital-to-analog conversion module, and a preset phase difference is set between the waveform parameters output by the multiple waveform parameter generation modules, so that the waveform parameters transmitted to the digital-to-analog conversion module are continuous and can cover the waveform parameters within a complete cycle of the intermediate frequency signal, thereby improving the resolution of the waveform parameters and ensuring that the digital-to-analog conversion module outputs a high-precision intermediate frequency signal; the intermediate frequency signal output by the digital-to-analog conversion module can also be adjusted by adjusting the frequency control word and the preset phase difference.
本申请实施例通过采用多个信号参数生成模块分别基于Cordic算法根据输入的相位控制信息生成初级信号参数,且不同信号参数生成模块输入的相位控制信息符合指定规则,使得多个信号参数生成模块输出的初级信号参数之间的相位差为指定相位差的整数倍,从而使得由初级信号参数按照指定相位差排列形成的目标信号参数可以与目标中频信号的至少一个完整周期对应,且目标信号参数的精度可以使得数模转换模块根据目标信号参数输出的中频信号满足精度条件,进而实现了数模转换模块在较为准确的逻辑时序下输出满足精度条件的目标中频信号。The embodiment of the present application adopts multiple signal parameter generation modules to generate primary signal parameters according to the input phase control information based on the Cordic algorithm, and the phase control information input by different signal parameter generation modules conforms to the specified rules, so that the phase difference between the primary signal parameters output by the multiple signal parameter generation modules is an integer multiple of the specified phase difference, so that the target signal parameters formed by arranging the primary signal parameters according to the specified phase difference can correspond to at least one complete cycle of the target intermediate frequency signal, and the accuracy of the target signal parameters can make the intermediate frequency signal output by the digital-to-analog conversion module according to the target signal parameters meet the accuracy conditions, thereby realizing that the digital-to-analog conversion module outputs the target intermediate frequency signal that meets the accuracy conditions under relatively accurate logical timing.
图1为本申请实施例提供的一种信号发生装置的结构示意图;FIG1 is a schematic structural diagram of a signal generating device provided in an embodiment of the present application;
图2为本申请又一实施例提供的一种信号发生装置的结构示意图;FIG2 is a schematic structural diagram of a signal generating device provided by another embodiment of the present application;
图3为本申请又一实施例提供的一种波形参数生成模块的结构示意图。FIG3 is a schematic diagram of the structure of a waveform parameter generation module provided in yet another embodiment of the present application.
图4为本申请又一实施例提供的信号发生装置的结构示意图。FIG. 4 is a schematic diagram of the structure of a signal generating device provided in yet another embodiment of the present application.
图5为本申请实施例提供的信号参数生成模块运用的Cordic算法的几何原理示意图。FIG5 is a schematic diagram of the geometric principle of the Cordic algorithm used by the signal parameter generation module provided in an embodiment of the present application.
图6为本申请又一实施例提供的信号发生装置的结构示意图。FIG6 is a schematic diagram of the structure of a signal generating device provided in yet another embodiment of the present application.
图7为本申请又一实施例提供的信号发生装置的结构示意图。FIG. 7 is a schematic diagram of the structure of a signal generating device provided in yet another embodiment of the present application.
图8为本申请实施例提供的量子控制系统的结构示意图。FIG8 is a schematic diagram of the structure of a quantum control system provided in an embodiment of the present application.
为了更清楚地说明本说明书实施方式中的技术方案,下面将对描述实施方式所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本说明书的一些实施方式,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
In order to more clearly illustrate the technical solutions in the implementation modes of this specification, the drawings required for describing the implementation modes will be briefly introduced below. Obviously, the drawings described below are only some implementation modes of this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
以下详细描述仅是说明性的,并不旨在限制实施例和/或实施例的应用或使用。此外,无意受到前面的“背景技术”或“发明内容”部分或“具体实施方式”部分中呈现的任何明示或暗示信息的约束。The following detailed description is illustrative only and is not intended to limit the application or use of the embodiments and/or embodiments. In addition, it is not intended to be bound by any explicit or implicit information presented in the previous "background technology" or "invention content" section or "specific implementation" section.
为使本申请实施例的目的、技术方案和优点更加清楚,现在参考附图描述一个或多个实施例,其中,贯穿全文相似的附图标记用于指代相似的组件。在下面的描述中,出于解释的目的,阐述了许多具体细节,以便提供对一个或多个实施例的更透彻的理解。然而,很明显,在各种情况下,可以在没有这些具体细节的情况下实践一个或多个实施例,各个实施例在不矛盾的前提下可以相互结合相互引用。To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, one or more embodiments are now described with reference to the accompanying drawings, wherein similar reference numerals throughout the text are used to refer to similar components. In the following description, for the purpose of explanation, many specific details are set forth in order to provide a more thorough understanding of one or more embodiments. However, it is clear that in various cases, one or more embodiments can be practiced without these specific details, and the various embodiments can be combined and referenced to each other without contradiction.
需要说明的是,本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象,而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换,以便这里描述的本申请的实施例能够以除了在这里图示或描述的那些以外的顺序实施。此外,术语“包括”和“具有”以及他们的任何变形,意图在于覆盖不排他的包含,例如,包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元,而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
作用于量子处理器的操控信号和读取信号主要通过对中频信号进行混频处理获得,中频信号携带有对量子处理器进行操控并读取量子计算结果的量子态编码信息。通常而言,中频信号为模拟信号,可以由数模转换器(Digital to analog converter,DAC)根据输入端接收的数字信号输出对应的模拟信号。输入数模转换器的数字信号与中频信号的幅值对应。也就是说,数字信号对应模拟信号的波形参数,波形参数的分辨率越高,对应的中频信号的分辨率也越高。The control signal and read signal acting on the quantum processor are mainly obtained by mixing the intermediate frequency signal. The intermediate frequency signal carries the quantum state encoding information for controlling the quantum processor and reading the quantum calculation results. Generally speaking, the intermediate frequency signal is an analog signal, and the digital to analog converter (DAC) can output the corresponding analog signal according to the digital signal received at the input end. The digital signal input to the digital to analog converter corresponds to the amplitude of the intermediate frequency signal. In other words, the digital signal corresponds to the waveform parameters of the analog signal. The higher the resolution of the waveform parameters, the higher the resolution of the corresponding intermediate frequency signal.
输入DAC的数字信号或波形参数通常由现场可编程逻辑门阵列(Field-Programmable Gate Array,FPGA)提供。例如,输入DAC的数字信号可以通过FPGA运行Cordic算法后输出。作为一个示例,可以通过FPGA内的直接数字频率合成器(Direct Digital Synthesizer,DDS)输出波形参数。The digital signal or waveform parameters input to the DAC are usually provided by a Field-Programmable Gate Array (FPGA). For example, the digital signal input to the DAC can be output after running the Cordic algorithm through the FPGA. As an example, the waveform parameters can be output through a Direct Digital Synthesizer (DDS) in the FPGA.
在量子计算领域中,对量子处理器进行操控和读取的操控信号和读取信号通常采用混频技术对中频信号处理获得。因此,操控信号和读取信号的信号精度直接影响对量子处理器的操控和读取精度,即中频信号的分辨率直接影响对量子处理器的操控和读取精度。为实现对量子处理器的高精度操控和对运算结果的高精度读取,用于获得操控信号和读取信号的中频信号的频率和分辨率需要满足一定条件。In the field of quantum computing, the control signals and read signals used to control and read quantum processors are usually obtained by processing intermediate frequency signals using frequency mixing technology. Therefore, the signal accuracy of the control signals and read signals directly affects the control and read accuracy of the quantum processor, that is, the resolution of the intermediate frequency signal directly affects the control and read accuracy of the quantum processor. In order to achieve high-precision control of the quantum processor and high-precision reading of the calculation results, the frequency and resolution of the intermediate frequency signal used to obtain the control signal and read signal need to meet certain conditions.
此外,根据奈奎斯特采样定理(Nyquist),采样率为输出信号频率的2倍,但限于镜频抑制滤波器的有限的带外抑制特性,一般取最高输出信号频率为采样率的0.45倍。在本实施例中,量子处理器的工作频率通常在6GHz-8GHz之间,中频信号的频率通常采用200MHz-500MHz,中频信号的分辨率不小于1KHz;即DAC输出的模拟信号的频率通常为百兆赫兹,因此DAC的采样率不低于1GS/s。对应的,FPGA中单个DDS工作时钟频率要求也需要与DAC的采样率一致,确保单个DDS单位时间内输出的波形参数的个数满足DAC采样率下单位时间内的采样点数的需求。现有技术中FPGA内的DDS工作时钟频率无法实现高时钟频率下准确的逻辑时序。In addition, according to the Nyquist sampling theorem, the sampling rate is twice the output signal frequency, but due to the limited out-of-band suppression characteristics of the image frequency suppression filter, the maximum output signal frequency is generally taken as 0.45 times the sampling rate. In this embodiment, the operating frequency of the quantum processor is usually between 6GHz-8GHz, the frequency of the intermediate frequency signal is usually 200MHz-500MHz, and the resolution of the intermediate frequency signal is not less than 1KHz; that is, the frequency of the analog signal output by the DAC is usually hundreds of megahertz, so the sampling rate of the DAC is not less than 1GS/s. Correspondingly, the operating clock frequency requirement of a single DDS in the FPGA also needs to be consistent with the sampling rate of the DAC to ensure that the number of waveform parameters output by a single DDS per unit time meets the number of sampling points per unit time at the DAC sampling rate. The DDS operating clock frequency in the FPGA in the prior art cannot achieve accurate logic timing at high clock frequencies.
基于此,如附图1所示,本申请实施例提供一种信号发生装置,用于输出携带量子态编码信息的中频信号,所述信号发生装置包括若干个波形参数生成模块1和数模转换模块2;所述波形参数生成模块1依据第一时钟信息和频率控制字输出所述中频信号的波形参数;其中,各所述波形参数生成模块1输出的波形参数之间具有预设相位差,所述预设相位差用于控制所述波形参数按照相位次序输出;所述数模转换模块2依据各所述波形参数生成模块1输出的波形参数输出对应的中频信号;其中,所述预设相位差依据所述波形参数生成模块1的第一时钟信息及输出所述波形参数的输出频率确定。Based on this, as shown in Figure 1, an embodiment of the present application provides a signal generating device for outputting an intermediate frequency signal carrying quantum state encoding information, the signal generating device comprising a plurality of waveform parameter generating modules 1 and a digital-to-analog conversion module 2; the waveform parameter generating module 1 outputs the waveform parameters of the intermediate frequency signal according to the first clock information and the frequency control word; wherein, there is a preset phase difference between the waveform parameters output by each of the waveform parameter generating modules 1, and the preset phase difference is used to control the waveform parameters to be output in phase order; the digital-to-analog conversion module 2 outputs the corresponding intermediate frequency signal according to the waveform parameters output by each of the waveform parameter generating modules 1; wherein, the preset phase difference is determined based on the first clock information of the waveform parameter generating module 1 and the output frequency of the waveform parameters.
具体的,波形参数包含生成波形的相位、幅值、频率参数,第一时钟信息为各波形
参数生成模块1输出波形参数的工作时钟频率,即每个第一时钟信息的时刻,各波形参数生成模块1均会输出波形参数,通过统一的第一时钟信息可以确保各波形参数生成模块1的工作时钟同步。频率控制字为各波形参数生成模块1输出波形参数的控制字符,可以理解的是,波形参数生成模块1具有数据位宽和数据深度参数,用于存储多个波形参数,通过频率控制字确定需要输出的若干个波形参数。在本实施例中,波形参数生成模块1可以选用DDS,数模转换模块2可以选用DAC。附图中的fc为第一时钟信息,可以由时钟源提供;F为频率控制字;fd为数模转换模块2工作时钟频率,即采样率。其中,第一时钟信息由数模转换模块2的采样率以及波形参数生成模块1的数量确定。具体的,各波形参数生成模块1的第一时钟信息为数模转换模块2的工作时钟频率除以波形参数生成模块1的数量,即fc=fd/n,n为波形参数生成模块1的数量。Specifically, the waveform parameters include the phase, amplitude, and frequency parameters of the generated waveform. The first clock information is The working clock frequency of the waveform parameters output by the parameter generation module 1, that is, at each moment of the first clock information, each waveform parameter generation module 1 will output the waveform parameters. The working clock synchronization of each waveform parameter generation module 1 can be ensured by the unified first clock information. The frequency control word is the control character of the waveform parameters output by each waveform parameter generation module 1. It can be understood that the waveform parameter generation module 1 has data bit width and data depth parameters for storing multiple waveform parameters, and the number of waveform parameters to be output is determined by the frequency control word. In this embodiment, the waveform parameter generation module 1 can use DDS, and the digital-to-analog conversion module 2 can use DAC. The fc in the figure is the first clock information, which can be provided by the clock source; F is the frequency control word; fd is the working clock frequency of the digital-to-analog conversion module 2, that is, the sampling rate. Among them, the first clock information is determined by the sampling rate of the digital-to-analog conversion module 2 and the number of waveform parameter generation modules 1. Specifically, the first clock information of each waveform parameter generation module 1 is the working clock frequency of the digital-to-analog conversion module 2 divided by the number of waveform parameter generation modules 1, that is, fc=fd/n, n is the number of waveform parameter generation modules 1.
每一个波形参数生成模块1均用于输出一定数量的中频信号的波形参数,采用多个波形参数生成模块1输出若干个波形参数,可以降低单个波形参数生成模块的工作时钟频率;各波形参数生成模块1不仅依据相同的第一时钟信息和频率控制字输出波形参数,且各波形参数生成模块1输出的波形参数之间具有预设相位差,使得传输至数模转换模块2的波形参数连续,且覆盖中频信号一个完整周期的波形参数,还可以提高波形参数生成模块1输出波形参数的分辨率,确保数模转换模块2输出高精度的中频信号。此外,还可以通过调节频率控制字和预设相位差实现数模转换模块输出的中频信号的调节。其中,附图1示例的为包括3个波形参数生成模块1的信号发生装置,还可以包括其他数量,例如4个、5个、6个等其他数量。具体的,波形参数生成模块1的数量依据所述中频信号的频率参数确定;数模转换模块2输出的中频信号的频率参数确定后,数模转换模块2的采样率既可以确定了,对应的波形参数生成模块1的数量也可以确定了。例如,中频信号的频参数率参数为500MHz,数模转换模块2的采样率选1.2GS/s,将每个波形参数生成模块1的第一时钟信息确定为400MHz时,则波形参数生成模块1的数量为3个;同理,当每个波形参数生成模块1的第一时钟信息采用300MHz时,则波形参数生成模块1的数量为4个;确保多个波形参数生成模块1输出的波形参数对应数模转换模块2的1.2GS/s采样率。此外,对应设置各波形参数生成模块1输出的波形参数之间的预设相位差,确保传输至数模转换模块2的波形参数连续并覆盖中频信号一个完整周期的波形参数。Each waveform parameter generation module 1 is used to output a certain number of waveform parameters of the intermediate frequency signal. Using multiple waveform parameter generation modules 1 to output a number of waveform parameters can reduce the working clock frequency of a single waveform parameter generation module; each waveform parameter generation module 1 not only outputs waveform parameters based on the same first clock information and frequency control word, but also has a preset phase difference between the waveform parameters output by each waveform parameter generation module 1, so that the waveform parameters transmitted to the digital-to-analog conversion module 2 are continuous and cover the waveform parameters of a complete cycle of the intermediate frequency signal. The resolution of the waveform parameters output by the waveform parameter generation module 1 can also be improved to ensure that the digital-to-analog conversion module 2 outputs a high-precision intermediate frequency signal. In addition, the adjustment of the intermediate frequency signal output by the digital-to-analog conversion module can also be achieved by adjusting the frequency control word and the preset phase difference. Among them, the example of the signal generating device including three waveform parameter generation modules 1 can also include other quantities, such as 4, 5, 6, etc. Specifically, the number of waveform parameter generation modules 1 is determined according to the frequency parameters of the intermediate frequency signal; after the frequency parameters of the intermediate frequency signal output by the digital-to-analog conversion module 2 are determined, the sampling rate of the digital-to-analog conversion module 2 can be determined, and the number of corresponding waveform parameter generation modules 1 can also be determined. For example, when the frequency parameter parameter of the intermediate frequency signal is 500MHz, the sampling rate of the digital-to-analog conversion module 2 is selected as 1.2GS/s, and the first clock information of each waveform parameter generation module 1 is determined to be 400MHz, the number of waveform parameter generation modules 1 is 3; similarly, when the first clock information of each waveform parameter generation module 1 adopts 300MHz, the number of waveform parameter generation modules 1 is 4; ensure that the waveform parameters output by multiple waveform parameter generation modules 1 correspond to the 1.2GS/s sampling rate of the digital-to-analog conversion module 2. In addition, the preset phase difference between the waveform parameters output by each waveform parameter generation module 1 is set accordingly to ensure that the waveform parameters transmitted to the digital-to-analog conversion module 2 are continuous and cover the waveform parameters of a complete cycle of the intermediate frequency signal.
如附图2所示,作为本申请实施例的一种实施方式,所述信号发生装置还包括数据处理模块3,所述数据处理模块3对各所述波形参数生成模块1输出的波形参数按照输出位序进行拼接,并将拼接后的波形参数发送至所述数模转换模块2。具体的,对波形参数生成模块1按照输出位序进行排序,波形参数生成模块1输出的波形参数具有相位差和输出位序的区别,采用数据处理模块3按照输出位序对波形参数进行拼接,确保拼接后的波形参数为需要的中频信号的幅值参数。需要补充的是,数据处理模块3与数模转换模块2之间通过固定数据格式的接口通信连接,数据处理模块3将拼接后的具有完整周期波形的波形参数转换成固定数据格式的数据后发送至数模转换模块2。As shown in FIG. 2 , as an implementation of an embodiment of the present application, the signal generating device further includes a data processing module 3, which splices the waveform parameters output by each of the waveform parameter generating modules 1 according to the output bit sequence, and sends the spliced waveform parameters to the digital-to-analog conversion module 2. Specifically, the waveform parameter generating modules 1 are sorted according to the output bit sequence, and the waveform parameters output by the waveform parameter generating modules 1 have differences in phase difference and output bit sequence. The waveform parameters are spliced according to the output bit sequence by the data processing module 3 to ensure that the spliced waveform parameters are the amplitude parameters of the required intermediate frequency signal. It should be supplemented that the data processing module 3 is connected to the digital-to-analog conversion module 2 through an interface communication connection with a fixed data format, and the data processing module 3 converts the spliced waveform parameters with a complete periodic waveform into data in a fixed data format and sends them to the digital-to-analog conversion module 2.
结合附图2所示的3个波形参数生成模块1,将波形参数生成模块1的输出位序由低到高进行排列,并将对应的波形参数也按照由低到高的位序进行排列,确保数据处理模块3输出的拼接后的波形参数为需要的中频信号的幅值参数,确保中频信号的信号精度。此外,可以通过微调频率控制字和若干个波形参数生成模块1预设的相位差值提高输出的中频信号的精度。In combination with the three waveform parameter generation modules 1 shown in FIG. 2 , the output bit sequence of the waveform parameter generation module 1 is arranged from low to high, and the corresponding waveform parameters are also arranged in a bit sequence from low to high, ensuring that the spliced waveform parameters output by the data processing module 3 are the required amplitude parameters of the intermediate frequency signal, ensuring the signal accuracy of the intermediate frequency signal. In addition, the accuracy of the output intermediate frequency signal can be improved by fine-tuning the frequency control word and the phase difference values preset by several waveform parameter generation modules 1.
如附图3所示,作为本申请实施例的一种实施方式,所述波形参数生成模块1包括相位累加器单元11和存储器单元12;所述相位累加器单元11用于依据所述第一时钟信息将所述频率控制字与当前相位值累加,并将累加后的相位值与相位控制字相加得到的相位数据发送至所述存储器单元12;所述存储器单元12用于依据地址按照波形参数中的相位存储完整周期的波形参数,并根据所述相位数据输出对应地址的波形参数至所述
数据处理模块3。As shown in FIG. 3, as an implementation of an embodiment of the present application, the waveform parameter generation module 1 includes a phase accumulator unit 11 and a memory unit 12; the phase accumulator unit 11 is used to accumulate the frequency control word and the current phase value according to the first clock information, and send the phase data obtained by adding the accumulated phase value and the phase control word to the memory unit 12; the memory unit 12 is used to store the waveform parameters of the complete cycle according to the phase in the waveform parameters according to the address, and output the waveform parameters of the corresponding address to the memory unit according to the phase data. Data processing module 3.
具体的,相位累加器单元11在每个第一时钟信息时刻,相位累加器单元11将输入端的频率控制字与当前的相位累加值相加获得新的相位累加值,新的相位累加值与相位控制字相加获得累加后的相位数据,并将相位数据发送至存储器以及相位累加器的输入端,在第一时钟信息的控制下,不停的对频率控制字进行累加。此外,存储器单元12用于按照地址存储中频信号的完整周期的波形参数,其中,地址对应各波形参数的相位;用相位累加器输出的相位数据作为地址在存储器单元12中通过查找对应地址对应的波形参数,通过存储器单元12输出与中频信号的幅值对应的波形参数。通过调节频率控制字,可以调节相位累加器单元11的每次累加的值的大小,进而调节相位数据,改变存储器单元12中相位数据对应的地址在每个时钟下的偏移量,实现输出波形参数的频率调节;与中频信号的信号频率匹配。Specifically, at each first clock information moment, the phase accumulator unit 11 adds the frequency control word at the input end to the current phase accumulation value to obtain a new phase accumulation value, adds the new phase accumulation value to the phase control word to obtain the accumulated phase data, and sends the phase data to the memory and the input end of the phase accumulator, and continuously accumulates the frequency control word under the control of the first clock information. In addition, the memory unit 12 is used to store the waveform parameters of the complete cycle of the intermediate frequency signal according to the address, wherein the address corresponds to the phase of each waveform parameter; the phase data output by the phase accumulator is used as the address to search the waveform parameter corresponding to the corresponding address in the memory unit 12, and the waveform parameter corresponding to the amplitude of the intermediate frequency signal is output through the memory unit 12. By adjusting the frequency control word, the size of the value accumulated each time by the phase accumulator unit 11 can be adjusted, and then the phase data can be adjusted, and the offset of the address corresponding to the phase data in the memory unit 12 under each clock can be changed to achieve frequency adjustment of the output waveform parameter; matching the signal frequency of the intermediate frequency signal.
作为本申请实施例的一种实施方式,所述相位累加器单元11的数据位宽包括32位。对应的,存储器单元12的位宽12位,存储器单元12的存储波形参数深度为4096个,工作时钟为400MHz。相位累加器单元11位宽大于存储器单元12的位宽log24096,保证相位累加器单元11累加一周,存储器单元12也循环一周,存储器单元12地址对应到相位累加器单元11的高位,一般取存储器单元12的波形参数深度比波形参数的数据位宽大2~3位,即可以节约存储器ram的资源,又可以实现更高的分辨率和较好的信噪比。以相位累加器单元11的位宽32位为例,相位累加器单元11累加到最大值为232-1,则可以确定信号发生装置输出波形的最小分辨率为:
As an implementation of an embodiment of the present application, the data bit width of the phase accumulator unit 11 includes 32 bits. Correspondingly, the bit width of the memory unit 12 is 12 bits, the storage waveform parameter depth of the memory unit 12 is 4096, and the working clock is 400MHz. The bit width of the phase accumulator unit 11 is greater than the bit width log 2 4096 of the memory unit 12, ensuring that the phase accumulator unit 11 accumulates one cycle and the memory unit 12 also cycles one cycle. The address of the memory unit 12 corresponds to the high bit of the phase accumulator unit 11. Generally, the waveform parameter depth of the memory unit 12 is 2 to 3 bits larger than the data bit width of the waveform parameter, which can save memory RAM resources and achieve higher resolution and better signal-to-noise ratio. Taking the bit width of the phase accumulator unit 11 as an example of 32 bits, the phase accumulator unit 11 accumulates to a maximum value of 2 32 -1, then the minimum resolution of the output waveform of the signal generating device can be determined as:
As an implementation of an embodiment of the present application, the data bit width of the phase accumulator unit 11 includes 32 bits. Correspondingly, the bit width of the memory unit 12 is 12 bits, the storage waveform parameter depth of the memory unit 12 is 4096, and the working clock is 400MHz. The bit width of the phase accumulator unit 11 is greater than the bit width log 2 4096 of the memory unit 12, ensuring that the phase accumulator unit 11 accumulates one cycle and the memory unit 12 also cycles one cycle. The address of the memory unit 12 corresponds to the high bit of the phase accumulator unit 11. Generally, the waveform parameter depth of the memory unit 12 is 2 to 3 bits larger than the data bit width of the waveform parameter, which can save memory RAM resources and achieve higher resolution and better signal-to-noise ratio. Taking the bit width of the phase accumulator unit 11 as an example of 32 bits, the phase accumulator unit 11 accumulates to a maximum value of 2 32 -1, then the minimum resolution of the output waveform of the signal generating device can be determined as:
其中,fc为相位累加器单元11的工作时钟频率,即第一时钟信息,通过计算可以确定分辨率为0.09313Hz,满足数模转换模块2的采样信号需求,进而确保输出的中频信号的精度。其中,频率控制字每加一或减一,频率改变0.09313Hz,可以通过调节频率控制字和预设相位差,精确调节信号发生装置的输出频率。此外,还通过增大相位累加器单元11的数据位宽,提高数模转换模块2输出的中频信号的精度,增大中频信号的范围。Wherein, fc is the working clock frequency of the phase accumulator unit 11, i.e., the first clock information. By calculation, it can be determined that the resolution is 0.09313 Hz, which meets the sampling signal requirements of the digital-to-analog conversion module 2, thereby ensuring the accuracy of the output intermediate frequency signal. Wherein, every time the frequency control word is added or subtracted by one, the frequency changes by 0.09313 Hz. The output frequency of the signal generating device can be accurately adjusted by adjusting the frequency control word and the preset phase difference. In addition, by increasing the data bit width of the phase accumulator unit 11, the accuracy of the intermediate frequency signal output by the digital-to-analog conversion module 2 is improved, and the range of the intermediate frequency signal is increased.
作为本申请实施例的一种实施方式,所述频率控制字依据所述波形参数生成模块1的输出频率、所述数据位宽以及所述第一时钟信息确定。波形参数生成模块1的输出频率、数据位宽、第一时钟信息的关系如下:
As an implementation method of the embodiment of the present application, the frequency control word is determined according to the output frequency of the waveform parameter generation module 1, the data bit width and the first clock information. The relationship among the output frequency, data bit width and the first clock information of the waveform parameter generation module 1 is as follows:
As an implementation method of the embodiment of the present application, the frequency control word is determined according to the output frequency of the waveform parameter generation module 1, the data bit width and the first clock information. The relationship among the output frequency, data bit width and the first clock information of the waveform parameter generation module 1 is as follows:
其中,F为频率控制字,fo为波形参数生成模块1的输出频率、N为相位累加器单元11的数据位宽、fc为第一时钟信息。相位累加器单元11的工作时钟频率根据数模转换模块2的采样率以及波形参数生成模块1的数量确定,数据位宽N根据中频信号的精度确定,第一时钟信息fc可以预设,结合上述公式,可以发现,根据需要的输出频率fo即可以确定相位累加器单元11在进行累加计算时的频率控制字。通过灵活调节频率控制字,可以调节波形参数生成模块1的输出频率,用于匹配不同频率的中频信号的需求。Among them, F is the frequency control word, fo is the output frequency of the waveform parameter generation module 1, N is the data bit width of the phase accumulator unit 11, and fc is the first clock information. The working clock frequency of the phase accumulator unit 11 is determined according to the sampling rate of the digital-to-analog conversion module 2 and the number of waveform parameter generation modules 1, the data bit width N is determined according to the accuracy of the intermediate frequency signal, and the first clock information fc can be preset. Combined with the above formula, it can be found that the frequency control word of the phase accumulator unit 11 when performing the accumulation calculation can be determined according to the required output frequency fo. By flexibly adjusting the frequency control word, the output frequency of the waveform parameter generation module 1 can be adjusted to match the needs of intermediate frequency signals of different frequencies.
例如,期望输出频率fo为300MHz,通过计算F=232*300/400=3221225472;假如fo为600MHz,通过计算F=232*300/400=6442450944>232,此时频率控制字远大于相位累加器单元11的数据位宽的最大值,此时频率控制字F=(232*600/400)%232=2147483648,也可以期望输出的频率fo对波形参数生成模块1的工作时钟取模后再按上述公式计算:F=(232*(600%400)/400)=232*200/400=2147483648。存储器单元12输出波形数据的频率由频率控制字决定,通过调节频率控制字就可以控制相位累加器单元11累加一圈的时间,进而控制存储器单元12输出一个完整波形的时间,也就是频率的倒数。结合发现,根据需要输出的频率fo即可以确定相位累加器单元11在累加计算时的频率控制字,通
过灵活调节频率控制字,可以调节波形参数生成模块1输出波形参数的频率,用于匹配不同频率的中频信号的需要。For example, the expected output frequency fo is 300MHz, by calculating F=2 32 *300/400=3221225472; if fo is 600MHz, by calculating F=2 32 *300/400=6442450944>2 32 , at this time the frequency control word is much larger than the maximum value of the data bit width of the phase accumulator unit 11, at this time the frequency control word F=(2 32 *600/400)%2 32 =2147483648, it is also possible to calculate the output frequency fo by taking the modulus of the working clock of the waveform parameter generating module 1 according to the above formula: F=(2 32 *(600%400)/400)=2 32 *200/400=2147483648. The frequency of the waveform data output by the memory unit 12 is determined by the frequency control word. By adjusting the frequency control word, the time for the phase accumulator unit 11 to accumulate one circle can be controlled, thereby controlling the time for the memory unit 12 to output a complete waveform, that is, the inverse of the frequency. It is found that the frequency control word of the phase accumulator unit 11 during the accumulation calculation can be determined according to the frequency fo output as required. By flexibly adjusting the frequency control word, the frequency of the waveform parameter output by the waveform parameter generating module 1 can be adjusted to match the needs of intermediate frequency signals of different frequencies.
作为本申请实施例的一种实施方式,各波形参数生成模块1的之间的预设相位差的计算如下:
As an implementation method of the embodiment of the present application, the preset phase difference between each waveform parameter generating module 1 is calculated as follows:
As an implementation method of the embodiment of the present application, the preset phase difference between each waveform parameter generating module 1 is calculated as follows:
假如输出频率fo为300MHz,各波形参数生成模块1之间的预设相位差Ph=232*300/1200=1073741824。其中fo为输出频率、N为相位累加器单元11的位宽、fd为数模转换模块2的工作时钟(采样率)、Ph为各波形数据生成模块之间的预设相位差,其中,波形参数生成模块1的个数等于(fd/fc),因此,可以确定每个波形参数生成模块1的工作时钟fc等于数模转换模块2的工作时钟fd除以波形参数生成模块1的个数。Assuming the output frequency fo is 300MHz, the preset phase difference Ph between each waveform parameter generating module 1 is 2 32 *300/1200=1073741824. Wherein fo is the output frequency, N is the bit width of the phase accumulator unit 11, fd is the working clock (sampling rate) of the digital-to-analog conversion module 2, and Ph is the preset phase difference between each waveform data generating module. The number of waveform parameter generating modules 1 is equal to (fd/fc). Therefore, it can be determined that the working clock fc of each waveform parameter generating module 1 is equal to the working clock fd of the digital-to-analog conversion module 2 divided by the number of waveform parameter generating modules 1.
结合所述描述的频率控制字和预设相位差与波形参数生成模块1的输出频率的对应关系,可以通过灵活调节频率控制字和预设相位差,调节波形参数生成模块1输出波形参数的频率,用于匹配不同频率的中频信号的需要。此外,灵活调节频率控制字和预设相位差还可以提高数模转换模块2输出的中频信号的精度。In combination with the correspondence between the frequency control word and the preset phase difference and the output frequency of the waveform parameter generating module 1, the frequency of the waveform parameter output by the waveform parameter generating module 1 can be adjusted by flexibly adjusting the frequency control word and the preset phase difference to match the needs of intermediate frequency signals of different frequencies. In addition, the accuracy of the intermediate frequency signal output by the digital-to-analog conversion module 2 can also be improved by flexibly adjusting the frequency control word and the preset phase difference.
作为本申请实施例的一种实施方式,所述相位累加器单元11和所述存储器单元12的工作时钟与所述数模转换模块2的工作时钟同源。其中,相位累加器单元11和所述存储器单元12的工作时钟频率与数模转换模块2的工作时钟频率存在倍数关系,具体倍数根据波形参数生成模块1的数量确定。数模转换模块2时工作时需要提供时钟信号,通常由时钟源提供,此外,相位累加器单元11、存储器单元12在工作时也需要提供时钟信号,采用同一时钟源提供的时钟信号工作,确保相位累加器单元11、存储器单元12、数模转换模块2的工作时钟同步,进而确保输出至数模转换模块2的波形参数的准确以及数模转换模块2输出的中频信号的精度。As an implementation method of the embodiment of the present application, the working clocks of the phase accumulator unit 11 and the memory unit 12 are co-sourced with the working clock of the digital-to-analog conversion module 2. Among them, the working clock frequencies of the phase accumulator unit 11 and the memory unit 12 are multiples of the working clock frequency of the digital-to-analog conversion module 2, and the specific multiples are determined according to the number of waveform parameter generation modules 1. The digital-to-analog conversion module 2 needs to provide a clock signal when working, which is usually provided by a clock source. In addition, the phase accumulator unit 11 and the memory unit 12 also need to provide a clock signal when working, and work with the clock signal provided by the same clock source to ensure that the working clocks of the phase accumulator unit 11, the memory unit 12, and the digital-to-analog conversion module 2 are synchronized, thereby ensuring the accuracy of the waveform parameters output to the digital-to-analog conversion module 2 and the accuracy of the intermediate frequency signal output by the digital-to-analog conversion module 2.
作为本申请实施例的一种实施方式,所述波形参数生成模块1、所述数据处理模块3均为FPGA内的功能模块。在本实施例中,波形参数生成模块1、数据处理模块3均为FPGA内设置的功能模块,其中,波形参数生成模块1可以包括DDS,存储器单元12采用RAM或者ROM存储器。在FPGA内设置功能模块,并灵活定义各功能模块的参数,用于满足各种中频信号对应的波形参数需求。As an implementation method of the embodiment of the present application, the waveform parameter generation module 1 and the data processing module 3 are both functional modules in the FPGA. In this embodiment, the waveform parameter generation module 1 and the data processing module 3 are both functional modules set in the FPGA, wherein the waveform parameter generation module 1 may include a DDS, and the memory unit 12 uses a RAM or ROM memory. Functional modules are set in the FPGA, and the parameters of each functional module are flexibly defined to meet the waveform parameter requirements corresponding to various intermediate frequency signals.
此外,在FPGA内设置功能模块时,一个所述FPGA内包括多个所述波形参数生成模块1和至少一个所述数据处理模块3;多个所述波形参数生成模块1对应一个所述数据处理模块3。其中,根据中频信号的频率参数需求,在FPGA内设置对应数量的波形参数生成模块1输出波形参数、以及一个数据处理模块3对各波形参数进行拼接和格式转换处理,并将处理后的波形参数传输至数模转换模块2。在FPGA内部通过对波形参数生成模块1和数据处理模块3进行多次例化通信连接多个数模转换模块2,输出多个中频信号的波形参数,满足量子处理器上多个量子位的驱动需求。需要说明的是,在FPGA内设置波形参数生成模块1的数量、工作时钟频率、数据位宽,需要结合FPGA的内存和资源设置。In addition, when setting the functional modules in the FPGA, one FPGA includes multiple waveform parameter generation modules 1 and at least one data processing module 3; multiple waveform parameter generation modules 1 correspond to one data processing module 3. According to the frequency parameter requirements of the intermediate frequency signal, a corresponding number of waveform parameter generation modules 1 are set in the FPGA to output waveform parameters, and a data processing module 3 is used to splice and convert the format of each waveform parameter, and the processed waveform parameters are transmitted to the digital-to-analog conversion module 2. Multiple digital-to-analog conversion modules 2 are connected by instantiating the waveform parameter generation module 1 and the data processing module 3 multiple times inside the FPGA, and the waveform parameters of multiple intermediate frequency signals are output to meet the driving requirements of multiple quantum bits on the quantum processor. It should be noted that the number of waveform parameter generation modules 1, the working clock frequency, and the data bit width set in the FPGA need to be combined with the memory and resource settings of the FPGA.
在具体应用时,中频信号混频处理后用于对量子处理器进行读取,所述数模转换模块2的采样率至少包括1GS/s,所述波形参数生成模块1的数量至少包括2个。中频信号混频处理后用于对量子处理器进行操控,所述数模转换模块2的采样率至少包括3GS/s,所述波形参数生成模块1的数量至少包括6个。并行的波形参数生成模块1的数量越多,越能降低单个波形参数生成模块1的工作时钟频率,满足FPGA内部逻辑时序的需求。在量子处理器运行量子计算时,操控信号的精度直接影响量子处理器上施加的逻辑门的保真度,对中频信号的分辨率要求极高,数模转换模块2的采样率设置为3GS/s,对应的FPGA内的波形参数生成模块1的数量至少包括6个,即每个波形参数生成模块1的工作时钟频率至少为500MHz。在本实施例中,数模转换模块2的采样率设置为
3.2GS/s,波形参数生成模块1的数量设置为8个,每个波形参数生成模块1的工作时钟频率为400MHz-1000MHz。In specific applications, the intermediate frequency signal is used to read the quantum processor after mixing processing, the sampling rate of the digital-to-analog conversion module 2 includes at least 1GS/s, and the number of the waveform parameter generation modules 1 includes at least 2. The intermediate frequency signal is used to control the quantum processor after mixing processing, the sampling rate of the digital-to-analog conversion module 2 includes at least 3GS/s, and the number of the waveform parameter generation modules 1 includes at least 6. The more the number of parallel waveform parameter generation modules 1 is, the lower the working clock frequency of a single waveform parameter generation module 1 can be, and the requirements of the internal logic timing of the FPGA can be met. When the quantum processor runs quantum computing, the accuracy of the control signal directly affects the fidelity of the logic gates applied to the quantum processor, and the resolution requirements of the intermediate frequency signal are extremely high. The sampling rate of the digital-to-analog conversion module 2 is set to 3GS/s, and the number of the corresponding waveform parameter generation modules 1 in the FPGA includes at least 6, that is, the working clock frequency of each waveform parameter generation module 1 is at least 500MHz. In this embodiment, the sampling rate of the digital-to-analog conversion module 2 is set to 3.2GS/s, the number of waveform parameter generation modules 1 is set to 8, and the working clock frequency of each waveform parameter generation module 1 is 400MHz-1000MHz.
此外,对于读取信号的要求相较于操控信号而言低一些,采用1GS/s以上的即可,本实施例中采样率优选1.2GS/s,波形参数生成模块1的数量设置为4个,每个波形参数生成模块1的工作时钟频率至少为300MHz。采用合适数量的波形参数生成模块1,避免波形参数生成模块1的工作时钟频率过高不能满足FPGA内部逻辑时序的要求,提高信噪比的同时降低资源消耗,确保FPGA的性能。In addition, the requirements for the read signal are lower than those for the control signal, and a sampling rate of 1GS/s or more can be used. In this embodiment, the sampling rate is preferably 1.2GS/s, and the number of waveform parameter generation modules 1 is set to 4, and the working clock frequency of each waveform parameter generation module 1 is at least 300MHz. Using an appropriate number of waveform parameter generation modules 1 can avoid the working clock frequency of the waveform parameter generation module 1 being too high to meet the requirements of the internal logic timing of the FPGA, improve the signal-to-noise ratio, reduce resource consumption, and ensure the performance of the FPGA.
结合附图1-附图3所示,作为本申请实施例的一种实施方式,所述预设相位差为所述波形参数生成模块1的数量的导数。例如,波形参数生成模块1的数量为3个,则各波形参数生成模块1输出的波形参数之间的预设相位差为1/3,确保在第一时钟信息更新时,各波形参数生成模块1输出的波形参数之间相位差一致且分辨率一致,确保传输至数模转换模块2的波形参数覆盖中频信号的幅值,幅值在周期内均匀分布,提高中频信号的精度和分辨率。As shown in Figures 1 to 3, as an implementation method of the present application, the preset phase difference is a derivative of the number of the waveform parameter generation modules 1. For example, if the number of waveform parameter generation modules 1 is 3, the preset phase difference between the waveform parameters output by each waveform parameter generation module 1 is 1/3, ensuring that when the first clock information is updated, the phase difference and resolution between the waveform parameters output by each waveform parameter generation module 1 are consistent, ensuring that the waveform parameters transmitted to the digital-to-analog conversion module 2 cover the amplitude of the intermediate frequency signal, and the amplitude is evenly distributed within the period, thereby improving the accuracy and resolution of the intermediate frequency signal.
在一些实施例中,为使得输出的中频信号的频率和分辨率满足条件,对应的DAC的采样率也需要满足一定条件,具体可以是,FPGA中用于运行Cordic算法的功能模块的工作时钟频率需要与DAC的采样率相匹配。然而,在相关技术中,FPGA内仅存在单个运行Cordic算法的功能模块,为使输出的数字信号达到精度条件,该模块需要执行多次迭代运算,导致输出时延较大且消耗较多运算资源。此外,受FPGA的工作时钟频率限制,该模块在高时钟频率下运行输出的数字信号难以实现较为准确的逻辑时序。In some embodiments, in order to make the frequency and resolution of the output intermediate frequency signal meet the conditions, the sampling rate of the corresponding DAC also needs to meet certain conditions. Specifically, the working clock frequency of the functional module used to run the Cordic algorithm in the FPGA needs to match the sampling rate of the DAC. However, in the related art, there is only a single functional module running the Cordic algorithm in the FPGA. In order to make the output digital signal meet the accuracy conditions, the module needs to perform multiple iterative operations, resulting in a large output delay and consuming more computing resources. In addition, due to the limitation of the working clock frequency of the FPGA, it is difficult for the module to achieve a more accurate logic timing when running the output digital signal at a high clock frequency.
因此,有必要提供一种信号发生装置,可以通过多个信号参数生成模块分别基于Cordic算法根据输入的相位控制信息生成初级信号参数,并通过向不同信号参数生成模块输入符合指定规则的相位控制信息,使得多个信号参数生成模块输出的初级信号参数之间的相位差为指定相位差的整数倍,通过对多个信号参数生成模块输出的初级信号参数进行拼接以形成与目标中频信号的周期对应的目标信号参数,再通过数模转换模块根据目标信号参数生成目标中频信号,从而在输出的中频信号的精度满足条件的情况下,降低单个信号参数生成模块的工作频率,实现较为准确的逻辑时序。Therefore, it is necessary to provide a signal generating device, which can generate primary signal parameters according to the input phase control information based on the Cordic algorithm through multiple signal parameter generating modules, and by inputting phase control information that complies with specified rules into different signal parameter generating modules, the phase difference between the primary signal parameters output by the multiple signal parameter generating modules is an integer multiple of the specified phase difference, and the primary signal parameters output by the multiple signal parameter generating modules are spliced to form a target signal parameter corresponding to the period of the target intermediate frequency signal, and then the target intermediate frequency signal is generated according to the target signal parameter through the digital-to-analog conversion module, so that when the accuracy of the output intermediate frequency signal meets the conditions, the operating frequency of a single signal parameter generating module is reduced to achieve more accurate logic timing.
请参阅图4。本申请实施例提供的信号发生装置还可以包括多个信号参数生成模块4。Please refer to Fig. 4. The signal generating device provided in the embodiment of the present application may further include a plurality of signal parameter generating modules 4.
在本实施方式中,多个信号参数生成模块4用于分别基于Cordic算法根据输入的相位控制信息生成初级信号参数;其中,不同信号参数生成模块输入的相位控制信息符合指定规则,使得多个信号参数生成模块输出的初级信号参数之间的相位差为指定相位差的整数倍。In this embodiment, multiple signal parameter generating modules 4 are used to generate primary signal parameters based on the Cordic algorithm according to the input phase control information; wherein the phase control information input by different signal parameter generating modules conforms to the specified rules, so that the phase difference between the primary signal parameters output by the multiple signal parameter generating modules is an integer multiple of the specified phase difference.
在本实施方式中,相位控制信息可以用于表示初始向量在每个工作时钟时刻所需迭代旋转的角度。具体的,例如,对于第一信号参数生成模块,相位控制信息可以为单次旋转角度。对于除第一信号参数生成模块以外的其他信号参数生成模块,相位控制信息可以为单次旋转角度与指定角度值的整数倍之和。In this embodiment, the phase control information can be used to indicate the angle at which the initial vector needs to be iteratively rotated at each working clock moment. Specifically, for example, for the first signal parameter generating module, the phase control information can be a single rotation angle. For other signal parameter generating modules except the first signal parameter generating module, the phase control information can be the sum of a single rotation angle and an integer multiple of a specified angle value.
在本实施方式中,初级信号参数可以用于表示初始向量经多次旋转形成的多个向量的坐标参数。具体的,初级信号参数包括的坐标参数的数量可以由单次旋转角度确定。In this embodiment, the primary signal parameters can be used to represent the coordinate parameters of multiple vectors formed by multiple rotations of the initial vector. Specifically, the number of coordinate parameters included in the primary signal parameters can be determined by a single rotation angle.
在本实施方式中,信号参数生成模块4可以在二维直角坐标系中使用Cordic算法。信号参数生成模块4基于Cordic算法,根据输入的相位控制信息生成初级信号参数的具体过程如下。In this embodiment, the signal parameter generation module 4 can use the Cordic algorithm in a two-dimensional rectangular coordinate system. The specific process of the signal parameter generation module 4 generating primary signal parameters based on the Cordic algorithm according to the input phase control information is as follows.
请参阅图5。在本实施方式中,二维坐标系中存在第一初始向量(x0,y0),该第一初始向量位于X轴上且x0>0,y0=0。在一些实施方式中,第一初始向量可以与X轴正向具有夹角β(图2中未示出),则x0>0,y0>0。Please refer to Figure 5. In this embodiment, there is a first initial vector ( x0 , y0 ) in the two-dimensional coordinate system, the first initial vector is located on the X axis and x0 >0, y0 =0. In some embodiments, the first initial vector may have an angle β with the positive direction of the X axis (not shown in Figure 2), then x0 >0, y0 >0.
向第一信号参数生成模块输入第一相位控制信息Ph1,具体的,第一相位控制信息Ph1可以包括向量单次旋转角度α,则将第一初始向量沿逆时针方向旋转α角度可以得到
第一向量(x′0,y′0)。参见公式1。第一向量的坐标参数(x′0,y′0)可以通过第一初始向量的坐标(x0,y0)和单次旋转角度α表示。
The first phase control information Ph1 is input to the first signal parameter generating module. Specifically, the first phase control information Ph1 may include a single rotation angle α of the vector. Then, the first initial vector is rotated counterclockwise by an angle α to obtain First vector (x′ 0 , y′ 0 ). See Formula 1. The coordinate parameters of the first vector (x′ 0 , y′ 0 ) can be expressed by the coordinates of the first initial vector (x 0 , y 0 ) and a single rotation angle α.
The first phase control information Ph1 is input to the first signal parameter generating module. Specifically, the first phase control information Ph1 may include a single rotation angle α of the vector. Then, the first initial vector is rotated counterclockwise by an angle α to obtain First vector (x′ 0 , y′ 0 ). See Formula 1. The coordinate parameters of the first vector (x′ 0 , y′ 0 ) can be expressed by the coordinates of the first initial vector (x 0 , y 0 ) and a single rotation angle α.
将第一向量沿逆时针方向旋转α角度可以得到第二向量,以此类推,沿逆时针方向以α角度迭代旋转第一初始向量一周,可以得到多个向量以及对应的多个坐标参数,将多个坐标参数作为第一初级信号参数。具体的,例如,α为1°,则迭代旋转第一初始向量一周可以得到360个坐标参数。α为2°,则迭代旋转第一初始向量一周可以得到180个坐标参数。The second vector can be obtained by rotating the first vector counterclockwise by an angle of α. Similarly, the first initial vector can be iteratively rotated counterclockwise by an angle of α to obtain multiple vectors and corresponding multiple coordinate parameters, and the multiple coordinate parameters are used as the first primary signal parameters. Specifically, for example, if α is 1°, 360 coordinate parameters can be obtained by iteratively rotating the first initial vector. If α is 2°, 180 coordinate parameters can be obtained by iteratively rotating the first initial vector.
向第二信号参数生成模块输入第二相位控制信息Ph2,具体的,第二相位控制信息Ph2可以包括单次旋转角度α和指定角度值θ。第二信号参数生成模块将第一初始向量沿逆时针方向旋转角度θ得到第二初始向量(x1,y1),重复上述过程迭代旋转第二初始向量一周,可以得到第二初级信号参数。第二相位控制信息中的单次旋转角度α和第一相位控制信息中的单次旋转角度α取值相同。第二初级信号参数与第一初级信号参数之间的相位差为角度θ对应的相位差。The second phase control information Ph2 is input to the second signal parameter generation module. Specifically, the second phase control information Ph2 may include a single rotation angle α and a specified angle value θ. The second signal parameter generation module rotates the first initial vector counterclockwise by an angle θ to obtain a second initial vector (x 1 , y 1 ). The second primary signal parameter can be obtained by repeating the above process to iteratively rotate the second initial vector for one circle. The single rotation angle α in the second phase control information and the single rotation angle α in the first phase control information have the same value. The phase difference between the second primary signal parameter and the first primary signal parameter is the phase difference corresponding to the angle θ.
在本实施方式中,单个信号参数生成模块4在生成初级信号参数后,可以将初级信号参数直接发送给数模转换模块。在一些实施方式中,单个信号参数生成模块4在生成初级信号参数后,可以将初级信号参数暂存在寄存器中,在多个信号参数生成模块4生成的初级信号参数形成与目标中频信号的至少一个周期对应的目标信号参数的情况下,多个信号参数生成模块4将生成的多个初级信号参数共同发送给数模转换模块。In this embodiment, after generating the primary signal parameters, the single signal parameter generating module 4 can directly send the primary signal parameters to the digital-to-analog conversion module. In some embodiments, after generating the primary signal parameters, the single signal parameter generating module 4 can temporarily store the primary signal parameters in a register, and when the primary signal parameters generated by the multiple signal parameter generating modules 4 form target signal parameters corresponding to at least one cycle of the target intermediate frequency signal, the multiple signal parameter generating modules 4 send the generated multiple primary signal parameters to the digital-to-analog conversion module together.
在本实施方式中,多个信号参数生成模块4的工作时钟频率fd可以由同一时钟源提供,以实现多个信号参数生成模块4的工作时钟同步。In this implementation, the working clock frequencies fd of the multiple signal parameter generating modules 4 may be provided by the same clock source to achieve working clock synchronization of the multiple signal parameter generating modules 4 .
在本实施方式中,数模转换模块2可以用于根据按照指定相位差排列的多个初级信号参数形成的目标信号参数,生成目标中频信号。具体的,数模转换模块可以在接收到多个信号参数生成模块4发送的多个初级信号参数后,按照指定相位差确定多个初级信号参数的输出次序,并按照输出次序以及指定相位差对多个初级信号参数进行排列以形成目标信号参数,使得目标信号参数中包含的坐标参数的数量与数模转换模块的需要满足的采样率条件相匹配,再根据目标信号参数生成目标中频信号。In this embodiment, the digital-to-analog conversion module 2 can be used to generate a target intermediate frequency signal according to a target signal parameter formed by a plurality of primary signal parameters arranged according to a specified phase difference. Specifically, after receiving a plurality of primary signal parameters sent by a plurality of signal parameter generation modules 4, the digital-to-analog conversion module can determine the output order of the plurality of primary signal parameters according to the specified phase difference, and arrange the plurality of primary signal parameters according to the output order and the specified phase difference to form a target signal parameter, so that the number of coordinate parameters contained in the target signal parameter matches the sampling rate condition that the digital-to-analog conversion module needs to meet, and then generate a target intermediate frequency signal according to the target signal parameter.
在本实施方式中,数模转换模块2可以根据由多个初级信号参数形成的目标信号参数生成目标中频信号,实现了数模转换模块2在准确的逻辑时序下输出满足精度条件的目标中频信号。In this embodiment, the digital-to-analog conversion module 2 can generate a target intermediate frequency signal according to target signal parameters formed by multiple primary signal parameters, so that the digital-to-analog conversion module 2 outputs a target intermediate frequency signal that meets accuracy conditions under accurate logical timing.
在一些实施方式中,所述目标中频信号的频率与量子处理器的操控信号和/或读取信号的频率具有第一关联关系;其中,所述第一关联关系用于表征在所述操控信号和/或读取信号的频率满足所述量子处理器的精度条件的情况下,所述目标中频信号的频率满足的第一频率条件。In some embodiments, the frequency of the target intermediate frequency signal has a first correlation with the frequency of the manipulation signal and/or the read signal of the quantum processor; wherein the first correlation is used to characterize a first frequency condition satisfied by the frequency of the target intermediate frequency signal when the frequency of the manipulation signal and/or the read signal satisfies the accuracy condition of the quantum processor.
在执行量子计算的运算过程时,量子处理器的工作频率通常在6GHz-8GHz之间,为实现对量子比特状态的操控和对经量子门操作后的量子比特状态的读取,混频处理后的操控信号和读取信号需要接近量子处理器的工作频率。在操控信号和/或读取信号的频率达到GHz级别的情况下,目标中频信号的频率需要满足的第一频率条件可以为频率在200MHz-500MHz范围内,且目标中频信号的分辨率不小于1KHz。When executing the quantum computing operation process, the operating frequency of the quantum processor is usually between 6GHz and 8GHz. In order to realize the manipulation of the quantum bit state and the reading of the quantum bit state after the quantum gate operation, the manipulation signal and the reading signal after the mixing process need to be close to the operating frequency of the quantum processor. When the frequency of the manipulation signal and/or the reading signal reaches the GHz level, the first frequency condition that the frequency of the target intermediate frequency signal needs to meet can be that the frequency is within the range of 200MHz-500MHz, and the resolution of the target intermediate frequency signal is not less than 1KHz.
在本实施方式中,由于目标中频信号的频率与操控信号和/或读取信号的频率之间满足第一关联关系,使得经目标中频信号混频获得的操控信号和/或读取信号能够满足量子处理器的精度条件。In this embodiment, since the frequency of the target intermediate frequency signal satisfies the first correlation relationship with the frequency of the manipulation signal and/or the read signal, the manipulation signal and/or the read signal obtained by mixing the target intermediate frequency signal can meet the accuracy condition of the quantum processor.
在一些实施方式中,所述信号参数生成模块4的数量与所述目标中频信号的频率具有第二关联关系;其中,所述第二关联关系用于表征在所述目标中频信号的频率满足所述第一频率条件的情况下,所述信号参数生成模块4的数量满足的数量条件。
In some embodiments, the number of the signal parameter generating modules 4 has a second correlation relationship with the frequency of the target intermediate frequency signal; wherein the second correlation relationship is used to characterize the quantity condition satisfied by the number of the signal parameter generating modules 4 when the frequency of the target intermediate frequency signal satisfies the first frequency condition.
在本实施方式中,通过DAC的采样率实现信号参数生成模块4的数量与目标中频信号的频率的关联。根据奈奎斯特(Nyquist)采样定理,为使得采样后的数字信号能够保留采样前原始信号的信息,采样率为输出信号频率的2倍。但受限于镜频抑制滤波器的有限的带外抑制特性,一般取最高输出信号频率为采样率的0.45倍。例如,在DAC输出的目标中频信号的频率为200MHz-500MHz的情况下,DAC的采样率不低于1GS/s。In this embodiment, the number of signal parameter generation modules 4 is associated with the frequency of the target intermediate frequency signal through the sampling rate of the DAC. According to the Nyquist sampling theorem, in order to enable the sampled digital signal to retain the information of the original signal before sampling, the sampling rate is twice the output signal frequency. However, due to the limited out-of-band suppression characteristics of the image rejection filter, the maximum output signal frequency is generally taken as 0.45 times the sampling rate. For example, when the frequency of the target intermediate frequency signal output by the DAC is 200MHz-500MHz, the sampling rate of the DAC is not less than 1GS/s.
在本实施方式中,信号参数生成模块4的数量根据DAC的采样率和单个信号参数生成模块4的工作时钟频率确定。单个信号参数生成模块4的工作时钟频率可以为预设值。具体的,例如,目标中频信号的频率为500MHz,数模转换模块的采样率为1.2GS/s。在单个信号参数生成模块4的工作时钟频率为400MHz的情况下,信号参数生成模块4的数量为3个;在单个信号参数生成模块4的工作时钟频率为300MHz的情况下,信号参数生成模块4的数量为4个。信号参数生成模块4的数量越多,单个信号参数生成模块4的工作时钟频率越低,由于单个信号参数生成模块4的工作时钟频率受FPGA工作频率的限制,较低的工作时钟频率可以使得信号参数生成模块4在较为准确的逻辑时序下工作。本说明书实施方式对信号参数生成模块4的数量不作具体限制。In this embodiment, the number of signal parameter generating modules 4 is determined according to the sampling rate of the DAC and the working clock frequency of a single signal parameter generating module 4. The working clock frequency of a single signal parameter generating module 4 can be a preset value. Specifically, for example, the frequency of the target intermediate frequency signal is 500MHz, and the sampling rate of the digital-to-analog conversion module is 1.2GS/s. When the working clock frequency of a single signal parameter generating module 4 is 400MHz, the number of signal parameter generating modules 4 is 3; when the working clock frequency of a single signal parameter generating module 4 is 300MHz, the number of signal parameter generating modules 4 is 4. The more the number of signal parameter generating modules 4, the lower the working clock frequency of a single signal parameter generating module 4. Since the working clock frequency of a single signal parameter generating module 4 is limited by the working frequency of the FPGA, a lower working clock frequency can enable the signal parameter generating module 4 to work under a more accurate logic timing. The embodiment of this specification does not specifically limit the number of signal parameter generating modules 4.
因此,可以根据目标中频信号的频率确定输出该频率的目标中频信号的DAC的采样率,再根据DAC的采样率和单个信号参数生成模块4的工作时钟频率确定信号参数生成模块4的数量,以实现多个信号参数生成模块4均在较为准确的逻辑时序下工作。Therefore, the sampling rate of the DAC that outputs the target intermediate frequency signal of the target intermediate frequency signal can be determined according to the frequency of the target intermediate frequency signal, and then the number of signal parameter generating modules 4 can be determined according to the sampling rate of the DAC and the working clock frequency of a single signal parameter generating module 4, so as to ensure that multiple signal parameter generating modules 4 operate under relatively accurate logical timing.
在一些实施方式中,所述相位控制信息依据所述信号参数生成模块4的数量以及所述信号参数生成模块4的工作时钟频率、输出频率和数据位宽确定。In some implementations, the phase control information is determined according to the number of the signal parameter generating modules 4 and the working clock frequency, output frequency and data bit width of the signal parameter generating modules 4 .
在本实施方式中,信号参数生成模块4的输出频率可以用于表示单位时间内单个信号参数生成模块4输出的初级信号参数包括的坐标参数的数量。信号参数生成模块4的输出频率可以通过调节频率控制字获取。具体的,频率控制字可以为信号参数生成模块4在每个工作时钟输出的坐标参数对应的向量相对于前一坐标参数对应的向量在二维直角坐标系内的旋转角度。例如,请参见图5,频率控制字可以为向量(x′0,y′0)相对于向量(x0,y0)的旋转角度α。In this embodiment, the output frequency of the signal parameter generating module 4 can be used to represent the number of coordinate parameters included in the primary signal parameters output by a single signal parameter generating module 4 per unit time. The output frequency of the signal parameter generating module 4 can be obtained by adjusting the frequency control word. Specifically, the frequency control word can be the rotation angle of the vector corresponding to the coordinate parameter output by the signal parameter generating module 4 at each working clock relative to the vector corresponding to the previous coordinate parameter in the two-dimensional rectangular coordinate system. For example, referring to FIG. 5, the frequency control word can be the rotation angle α of the vector (x′ 0 , y′ 0 ) relative to the vector (x 0 , y 0 ).
由于目标中频信号的频率可以在200MHz-500MHz范围内变化,通过改变频率控制字,可以调节单个信号参数生成模块4的输出频率,以匹配不同频率的中频信号。Since the frequency of the target intermediate frequency signal can vary within the range of 200 MHz-500 MHz, the output frequency of the single signal parameter generating module 4 can be adjusted by changing the frequency control word to match intermediate frequency signals of different frequencies.
在本实施方式中,信号参数生成模块4的数据位宽可以用于表示信号参数生成模块4一次传输的数据宽度。信号参数生成模块4的数据位宽可以根据中频信号的分辨率确定。In this embodiment, the data bit width of the signal parameter generating module 4 can be used to represent the data width transmitted once by the signal parameter generating module 4. The data bit width of the signal parameter generating module 4 can be determined according to the resolution of the intermediate frequency signal.
请参见公式2。在本实施方式中,可以根据信号参数生成模块4的工作时钟频率、输出频率和数据位宽确定。
Please refer to Formula 2. In this implementation, it can be determined according to the working clock frequency, output frequency and data bit width of the signal parameter generation module 4 .
Please refer to Formula 2. In this implementation, it can be determined according to the working clock frequency, output frequency and data bit width of the signal parameter generation module 4 .
其中,F为频率控制字,PW为信号参数生成模块4的数据位宽,fo为信号参数生成模块4的输出频率,fd为信号参数生成模块4的工作时钟频率。其中,PW的最高位为符号位,次高两位为整数位。Among them, F is the frequency control word, PW is the data bit width of the signal parameter generation module 4, fo is the output frequency of the signal parameter generation module 4, and fd is the working clock frequency of the signal parameter generation module 4. Among them, the highest bit of PW is the sign bit, and the next highest two bits are integer bits.
在本实施方式中,相位控制信息可以包括频率控制字和指定相位差的整数倍。具体的,请参见图5,指定相位差可以为向量(x1,y1)相对于向量(x0,y0)的旋转角度θ。请参见公式3,指定相位差可以根据信号参数生成模块4的工作时钟频率、输出频率和数据位宽以及信号参数生成模块4的数量确定。
In this embodiment, the phase control information may include a frequency control word and an integer multiple of a specified phase difference. Specifically, referring to FIG5 , the specified phase difference may be a rotation angle θ of the vector (x 1 , y 1 ) relative to the vector (x 0 , y 0 ). Referring to Formula 3, the specified phase difference may be determined according to the operating clock frequency, output frequency and data bit width of the signal parameter generating module 4 and the number of the signal parameter generating modules 4 .
In this embodiment, the phase control information may include a frequency control word and an integer multiple of a specified phase difference. Specifically, referring to FIG5 , the specified phase difference may be a rotation angle θ of the vector (x 1 , y 1 ) relative to the vector (x 0 , y 0 ). Referring to Formula 3, the specified phase difference may be determined according to the operating clock frequency, output frequency and data bit width of the signal parameter generating module 4 and the number of the signal parameter generating modules 4 .
其中,ΔPh为指定相位差,PW为信号参数生成模块4的数据位宽,fo为信号参数生成模块4的输出频率,fd为信号参数生成模块4的工作时钟频率,N为信号参数生成模块4的数量。其中,PW的最高位为符号位,次高两位为整数位。
Wherein, ΔPh is the specified phase difference, PW is the data bit width of the signal parameter generation module 4, fo is the output frequency of the signal parameter generation module 4, fd is the working clock frequency of the signal parameter generation module 4, and N is the number of the signal parameter generation modules 4. Wherein, the highest bit of PW is the sign bit, and the next highest two bits are integer bits.
通过调整相位控制信息中的频率控制字和指定相位差,可以调节多个信号参数生成模块4的输出频率,以匹配不同频率的中频信号。By adjusting the frequency control word and the specified phase difference in the phase control information, the output frequencies of the multiple signal parameter generating modules 4 can be adjusted to match intermediate frequency signals of different frequencies.
在一些实施方式中,所述指定规则可以包括相邻信号参数生成模块4输入的相位控制信息的差值为指定相位差。In some implementations, the designated rule may include that the difference between the phase control information input by the adjacent signal parameter generation module 4 is a designated phase difference.
请参阅图5。在本实施方式中,指定相位差可以为向量(x1,y1)相对于向量(x0,y0)的旋转角度θ以及向量(x2,y2)相对于向量(x1,y1)的旋转角度θ。Please refer to Fig. 5. In this embodiment, the specified phase difference may be a rotation angle θ of the vector ( x1 , y1 ) relative to the vector ( x0 , y0 ) and a rotation angle θ of the vector ( x2 , y2 ) relative to the vector ( x1 , y1 ).
通过向相邻的信号参数生成模块4输入差值为指定相位差的相位控制信息,可以实现多个信号参数生成模块4输出的初级信号参数之间的相位差为指定相位差的整数倍。By inputting phase control information whose difference is a specified phase difference into adjacent signal parameter generating modules 4, it can be achieved that the phase difference between the primary signal parameters output by multiple signal parameter generating modules 4 is an integer multiple of the specified phase difference.
在一些实施方式中,包括多个信号参数生成模块的信号发生装置也可以包括去前文所述的数据处理模块3,数据处理模块3可以用于对多个所述初级信号参数进行数据处理以获取与所述目标中频信号的至少一个周期对应的目标信号参数。In some embodiments, the signal generating device including multiple signal parameter generating modules may also include the data processing module 3 mentioned above, and the data processing module 3 can be used to perform data processing on the multiple primary signal parameters to obtain target signal parameters corresponding to at least one period of the target intermediate frequency signal.
请参阅图6。在本实施方式中,信号参数生成模块4在生成初级信号参数后,可以将初级信号参数发送给数据处理模块3。数据处理模块3在接收到多个初级信号参数后,可以根据进行数字信号与模拟信号转换的数据格式和数据位宽要求,对初级信号参数包括的多个二维直角坐标系中的坐标参数进行数据处理。具体的,根据公式1可知,由坐标参数可以得到坐标参数对应的向量相对于初始向量的旋转角度的余弦值和正切值,但FPGA无法直接计算正弦值、余弦值和正切值。Please refer to Figure 6. In this embodiment, after generating the primary signal parameters, the signal parameter generation module 4 can send the primary signal parameters to the data processing module 3. After receiving the multiple primary signal parameters, the data processing module 3 can perform data processing on the coordinate parameters in the multiple two-dimensional rectangular coordinate systems included in the primary signal parameters according to the data format and data bit width requirements for converting digital signals to analog signals. Specifically, according to Formula 1, the cosine value and tangent value of the rotation angle of the vector corresponding to the coordinate parameters relative to the initial vector can be obtained from the coordinate parameters, but the FPGA cannot directly calculate the sine value, cosine value and tangent value.
请参见公式4与表1。表1示出了在tanθi=2-i的情况下,i取0,1,…,6等值时,θi,tanθi,cosθi的对应值。数据处理模块可以先对正弦值、余弦值和正切值进行数据转换,以实现通过移位和加减表示坐标参数对应的向量相对于初始向量的旋转角度。Please refer to Formula 4 and Table 1. Table 1 shows the corresponding values of θ i , tanθ i , and cosθ i when tanθ i = 2 -i and i takes values of 0, 1, ..., 6, etc. The data processing module can first perform data conversion on the sine value, cosine value, and tangent value to achieve the rotation angle of the vector corresponding to the coordinate parameter relative to the initial vector by shifting and adding and subtracting.
当旋转角度θ满足时,θ可以以公式5的形式表达,其中,si∈{-1,1}。When the rotation angle θ satisfies When , θ can be expressed in the form of Formula 5, where s i ∈{-1,1}.
表1
Table 1
Table 1
θi=arctan2-i 公式4
θ i = arctan2 -i Formula 4
θ i = arctan2 -i Formula 4
请参见公式6,第k次迭代旋转初始向量得到的向量(xk,yk)的坐标参数为:
Referring to Formula 6, the coordinate parameters of the vector (x k , y k ) obtained by rotating the initial vector for the kth iteration are:
Referring to Formula 6, the coordinate parameters of the vector (x k , y k ) obtained by rotating the initial vector for the kth iteration are:
数据处理模块3可以按照指定相位差确定多个初级信号参数的输出次序。具体的,数据处理模块3可以以第一信号参数生成模块生成的第一初级信号参数为基准,比较多个初级信号参数与第一初级信号参数的相位差与指定相位差的倍数关系,基于倍数关系确定多个初级信号参数的输出次序。例如,可以按照倍数递增的规律确定初级信号参数的输出次序,倍数越小的初级信号参数的输出次序越靠前;也可以按照倍数递减的规律确定初级信号参数的输出次序,倍数越小的初级信号参数的输出次序越靠后。The data processing module 3 can determine the output order of multiple primary signal parameters according to the specified phase difference. Specifically, the data processing module 3 can use the first primary signal parameter generated by the first signal parameter generating module as a reference, compare the multiple relationship between the phase difference between the multiple primary signal parameters and the first primary signal parameter and the specified phase difference, and determine the output order of the multiple primary signal parameters based on the multiple relationship. For example, the output order of the primary signal parameters can be determined according to the rule of increasing multiples, and the smaller the multiple, the higher the output order of the primary signal parameters; the output order of the primary signal parameters can also be determined according to the rule of decreasing multiples, and the smaller the multiple, the lower the output order of the primary signal parameters.
在确定多个初级信号参数的输出次序之后,数据处理模块3可以根据指定相位差和输出次序,对多个初级信号参数包括的多个坐标参数进行拼接和数据格式转换,以获得
与目标中频信号的至少一个周期对应的目标信号参数,并将目标信号参数发送给数模转换模块2。After determining the output order of the multiple primary signal parameters, the data processing module 3 can perform splicing and data format conversion on the multiple coordinate parameters included in the multiple primary signal parameters according to the specified phase difference and output order to obtain A target signal parameter corresponding to at least one period of the target intermediate frequency signal is obtained, and the target signal parameter is sent to the digital-to-analog conversion module 2.
在本实施方式中,多个信号参数生成模块4分别将其生成的初级信号参数发送给同一个数据处理模块3。该数据处理模块3在对多个初级信号参数进行数据转换处理后,将形成的目标信号参数发送给数模转换模块2。In this embodiment, the plurality of signal parameter generating modules 4 respectively send the generated primary signal parameters to the same data processing module 3. The data processing module 3 sends the generated target signal parameters to the digital-to-analog conversion module 2 after performing data conversion processing on the plurality of primary signal parameters.
在一些实施方式中,多个信号参数生成模块4可以将其生成的初级信号参数分别发送给多个数据处理模块3。具体的,例如,可以是每个信号参数生成模块4将初级信号参数发送给与其一一对应的数据处理模块3,也可以是每两个信号参数生成模块4将初级信号参数发送给同一个数据处理模块3。本说明书实施方式对数据处理模块3的数量不作具体限制。In some implementations, multiple signal parameter generation modules 4 may send the primary signal parameters generated by them to multiple data processing modules 3. Specifically, for example, each signal parameter generation module 4 may send the primary signal parameters to the data processing module 3 corresponding thereto, or every two signal parameter generation modules 4 may send the primary signal parameters to the same data processing module 3. The implementations of this specification do not specifically limit the number of data processing modules 3.
在一些实施方式中,多个数据处理模块3可以分别用于对初级信号参数中包括的坐标参数进行不同数据处理。具体的,例如,单个数据处理模块3可以用于对初级信号参数中包括的坐标参数进行初步数据处理,转换为符合数模转换模块2格式要求的坐标参数,再按照指定相位差和输出次序对多个初级信号参数中符合数模转换模块2格式要求的坐标参数进行拼接,以形成目标信号参数,再将目标信号参数发送给数模转换模块2。本说明书实施方式对单个数据处理模块3的功能不作具体限制。In some embodiments, multiple data processing modules 3 can be used to perform different data processing on the coordinate parameters included in the primary signal parameters. Specifically, for example, a single data processing module 3 can be used to perform preliminary data processing on the coordinate parameters included in the primary signal parameters, convert them into coordinate parameters that meet the format requirements of the digital-to-analog conversion module 2, and then splice the coordinate parameters that meet the format requirements of the digital-to-analog conversion module 2 in multiple primary signal parameters according to the specified phase difference and output order to form target signal parameters, and then send the target signal parameters to the digital-to-analog conversion module 2. The embodiments of this specification do not specifically limit the functions of a single data processing module 3.
在信号参数生成模块4生成的初级信号参数被传输至数模转换模块2之前,通过数据处理模块3对初级信号参数进行数据处理,使得数模转换模块2接收到的目标信号参数符合数模转换模块2的数据位宽和数据格式要求,提高了数模转换模块2的转换效率。Before the primary signal parameters generated by the signal parameter generation module 4 are transmitted to the digital-to-analog conversion module 2, the primary signal parameters are processed by the data processing module 3, so that the target signal parameters received by the digital-to-analog conversion module 2 meet the data bit width and data format requirements of the digital-to-analog conversion module 2, thereby improving the conversion efficiency of the digital-to-analog conversion module 2.
在一些实施方式中,可以将信号参数生成模块4和数据处理模块3作为一个模块组,在FPGA内部对模块组进行多次例化,以形成多个模块组,每个模块组连接一个数模转换模块2以输出多个中频信号,满足量子处理器上多位量子比特的操控需求。In some embodiments, the signal parameter generation module 4 and the data processing module 3 can be taken as a module group, and the module group can be instantiated multiple times inside the FPGA to form multiple module groups. Each module group is connected to a digital-to-analog conversion module 2 to output multiple intermediate frequency signals to meet the control requirements of multi-bit quantum bits on the quantum processor.
在一些实施方式中,信号发生装置还包括与所述信号参数生成模块4具有指定对应关系的相位累加器单元11。在一些实施例中,相位累加器单元11可以简称为累加器。累加器用于依据所述信号参数生成模块4的工作时钟频率对所述相位控制信息进行累加,并将累加后的相位控制信息发送至所述信号参数生成模块4。In some embodiments, the signal generating device further includes a phase accumulator unit 11 having a specified corresponding relationship with the signal parameter generating module 4. In some embodiments, the phase accumulator unit 11 can be simply referred to as an accumulator. The accumulator is used to accumulate the phase control information according to the working clock frequency of the signal parameter generating module 4, and send the accumulated phase control information to the signal parameter generating module 4.
请参阅图7。在本实施方式中,指定对应关系可以为一一对应,即,每个信号参数生成模块4可以具有一个对应的相位累加器单元11。Please refer to FIG7 . In this embodiment, the designated corresponding relationship may be a one-to-one correspondence, that is, each signal parameter generating module 4 may have a corresponding phase accumulator unit 11 .
在本实施方式中,相位累加器单元11用于依据所述信号参数生成模块4的工作时钟频率对所述相位控制信息进行累加,并将累加后的相位控制信息发送至所述信号参数生成模块4,可以包括:相位累加器单元11可以在每个工作时钟内,以前一次相位控制信息为基础累加一次频率控制字至相位控制信息,再将累加后的相位控制信息发送给信号参数生成模块4,以用于控制信号参数生成模块4在每个工作时钟时刻根据累加后的相位控制信息改变输出。具体的,工作时钟时刻可以根据工作时钟频率确定。例如,工作时钟频率为400MHz,工作时钟为工作时钟频率的倒数,即2.5ns。以0时刻为初始工作时钟时刻,每间隔2.5ns的时刻均为工作时钟时刻。In this embodiment, the phase accumulator unit 11 is used to accumulate the phase control information according to the working clock frequency of the signal parameter generating module 4, and send the accumulated phase control information to the signal parameter generating module 4, which may include: the phase accumulator unit 11 can accumulate a frequency control word to the phase control information based on the previous phase control information in each working clock, and then send the accumulated phase control information to the signal parameter generating module 4, so as to control the signal parameter generating module 4 to change the output according to the accumulated phase control information at each working clock moment. Specifically, the working clock moment can be determined according to the working clock frequency. For example, the working clock frequency is 400MHz, and the working clock is the reciprocal of the working clock frequency, that is, 2.5ns. Take time 0 as the initial working clock moment, and every moment of 2.5ns is the working clock moment.
请参阅图5。以第一信号参数生成模块为例,相位控制信息包括频率控制字。在二维直角坐标系内,向量(x0,y0)对应初始工作时钟时刻,初始相位控制信息为旋转角度α,则在2.5ns时刻时,向量(x0,y0)沿逆时针方向旋转角度α,得到向量(x′0,y′0),第一信号参数生成模块输出向量(x′0,y′0)的坐标参数。相位累加器单元11可以在每个工作时钟内,在前一次相位控制信息的基础上累加一次旋转角度α,即在2.5ns时刻至5ns时刻内,相位累加器单元11在初始相位控制信息的基础上累加一次旋转角度α得到第一相位控制信息,并将第一相位控制信息发送给第一信号参数生成模块,以在5ns时刻,控制向量(x′0,y′0)沿逆时针方向再旋转角度α得到向量(x″0,y″0),第
一信号参数生成模块输出向量(x″0,y″0)的坐标参数。以此类推,直至向量(x0,y0)旋转一周,第一信号参数生成模块输出的坐标参数的数量为360°/α。Please refer to Figure 5. Taking the first signal parameter generation module as an example, the phase control information includes a frequency control word. In a two-dimensional rectangular coordinate system, the vector (x 0 , y 0 ) corresponds to the initial working clock moment, and the initial phase control information is a rotation angle α. Then, at the time of 2.5ns, the vector (x 0 , y 0 ) rotates counterclockwise by an angle α to obtain a vector (x′ 0 , y′ 0 ). The first signal parameter generation module outputs the coordinate parameters of the vector (x′ 0 , y′ 0 ). The phase accumulator unit 11 can accumulate a rotation angle α on the basis of the previous phase control information within each working clock, that is, within the period from 2.5ns to 5ns, the phase accumulator unit 11 accumulates a rotation angle α on the basis of the initial phase control information to obtain the first phase control information, and sends the first phase control information to the first signal parameter generating module, so that at the time of 5ns, the control vector (x′ 0 , y′ 0 ) is rotated again in the counterclockwise direction by an angle α to obtain the vector (x″ 0 , y″ 0 ). A signal parameter generation module outputs the coordinate parameters of the vector (x" 0 , y" 0 ). This is deduced in this way, until the vector (x 0 , y 0 ) rotates one circle, the number of coordinate parameters output by the first signal parameter generation module is 360°/α.
通过相位累加器单元11不断改变输入信号参数生成模块4的相位控制信息,以实现信号参数生成模块4根据接收到的相位控制信息生成初级信号参数,简化了信号参数生成模块4生成初级信号参数的过程,减少了信号参数生成模块4的输出时延。The phase control information of the input signal parameter generating module 4 is continuously changed through the phase accumulator unit 11, so that the signal parameter generating module 4 generates primary signal parameters according to the received phase control information, which simplifies the process of the signal parameter generating module 4 generating primary signal parameters and reduces the output delay of the signal parameter generating module 4.
在一些实施方式中,所述相位累加器单元11和所述信号参数生成模块4的工作时钟与所述数模转换模块的工作时钟同源,以实现信号参数生成模块4与对应的相位累加器单元11工作时钟同步,以及多个信号参数生成模块4和对应的多个相位累加器单元11与数模转换模块的工作时钟同步。In some embodiments, the working clocks of the phase accumulator unit 11 and the signal parameter generating module 4 are the same as the working clock of the digital-to-analog conversion module, so as to achieve working clock synchronization of the signal parameter generating module 4 and the corresponding phase accumulator unit 11, as well as working clock synchronization of multiple signal parameter generating modules 4 and the corresponding multiple phase accumulator units 11 and the digital-to-analog conversion module.
基于同一申请构思,如图8所示,本申请实施例提供一种量子控制系统,包括任一项上述的信号发生装置、微波源、以及信号混频装置,所述信号混频装置用于对所述信号发生装置输出的中频信号以及所述微波源输出的微波信号进行混频处理并输出操控信号和/或读取信号。Based on the same application concept, as shown in Figure 8, an embodiment of the present application provides a quantum control system, including any of the above-mentioned signal generating devices, microwave sources, and signal mixing devices, wherein the signal mixing device is used to mix the intermediate frequency signal output by the signal generating device and the microwave signal output by the microwave source and output a control signal and/or a reading signal.
基于同一申请构思,本申请实施例提供一种量子计算机,包括上述的量子控制系统及量子处理器,所述量子控制系统输出用于控制所述量子处理器执行运算的操控信号、以及对所述量子处理器的运算结果进行测量的读取信号。Based on the same application concept, an embodiment of the present application provides a quantum computer, including the above-mentioned quantum control system and quantum processor, wherein the quantum control system outputs a control signal for controlling the quantum processor to perform operations, and a read signal for measuring the operation results of the quantum processor.
以上依据图式所示的实施例详细说明了本申请的构造、特征及作用效果,以上所述仅为本申请的较佳实施例,但本申请不以图面所示限定实施范围,凡是依照本申请的构想所作的改变,或修改为等同变化的等效实施例,仍未超出说明书与图示所涵盖的精神时,均应在本申请的保护范围内。
The above describes in detail the structure, features and effects of the present application based on the embodiments shown in the drawings. The above is only a preferred embodiment of the present application, but the present application does not limit the scope of implementation to what is shown in the drawings. Any changes made in accordance with the concept of the present application, or modifications to equivalent embodiments with equivalent changes, which still do not exceed the spirit covered by the description and drawings, should be within the protection scope of the present application.
Claims (20)
- 一种信号发生装置,其特征在于,用于输出携带量子态编码信息的中频信号,所述信号发生装置包括若干个波形参数生成模块和数模转换模块;A signal generating device, characterized in that it is used to output an intermediate frequency signal carrying quantum state encoding information, and the signal generating device includes a plurality of waveform parameter generating modules and a digital-to-analog conversion module;所述波形参数生成模块依据第一时钟信息和频率控制字输出所述中频信号的波形参数;其中,各所述波形参数生成模块输出的波形参数之间具有预设相位差,所述预设相位差用于控制所述波形参数按照相位次序输出;The waveform parameter generation module outputs the waveform parameters of the intermediate frequency signal according to the first clock information and the frequency control word; wherein the waveform parameters output by each of the waveform parameter generation modules have a preset phase difference, and the preset phase difference is used to control the waveform parameters to be output in phase order;所述数模转换模块依据各所述波形参数生成模块输出的波形参数输出对应的中频信号;The digital-to-analog conversion module outputs a corresponding intermediate frequency signal according to the waveform parameters output by each of the waveform parameter generation modules;其中,所述预设相位差依据各所述波形参数生成模块的第一时钟信息及输出所述波形参数的输出频率确定。The preset phase difference is determined according to the first clock information of each waveform parameter generating module and the output frequency of outputting the waveform parameter.
- 根据权利要求1所述的信号发生装置,其特征在于,还包括数据处理模块,所述数据处理模块对各所述波形参数生成模块输出的波形参数按照输出位序进行拼接,并将拼接后的波形参数发送至所述数模转换模块。The signal generating device according to claim 1 is characterized in that it also includes a data processing module, which splices the waveform parameters output by each of the waveform parameter generating modules according to the output bit sequence, and sends the spliced waveform parameters to the digital-to-analog conversion module.
- 根据权利要求2所述的信号发生装置,其特征在于,所述波形参数生成模块包括相位累加器单元和存储器单元;The signal generating device according to claim 2, characterized in that the waveform parameter generating module comprises a phase accumulator unit and a memory unit;所述相位累加器单元用于依据所述第一时钟信息将所述频率控制字与当前相位值累加,并将累加后的相位值与相位控制字相加得到的相位数据发送至所述存储器单元;The phase accumulator unit is used to accumulate the frequency control word and the current phase value according to the first clock information, and send the phase data obtained by adding the accumulated phase value and the phase control word to the memory unit;所述存储器单元用于依据地址存储所述波形参数,并根据所述相位数据输出对应地址的波形参数至所述数据处理模块。The memory unit is used to store the waveform parameters according to the address, and output the waveform parameters corresponding to the address to the data processing module according to the phase data.
- 根据权利要求3所述的信号发生装置,其特征在于,所述相位累加器单元的数据位宽包括32位。The signal generating device according to claim 3 is characterized in that the data bit width of the phase accumulator unit includes 32 bits.
- 根据权利要求4所述的信号发生装置,其特征在于,所述频率控制字依据所述波形参数生成模块的输出频率、所述数据位宽以及所述第一时钟信息确定。The signal generating device according to claim 4 is characterized in that the frequency control word is determined according to the output frequency of the waveform parameter generating module, the data bit width and the first clock information.
- 根据权利要求4所述的信号发生装置,其特征在于,所述预设相位差确定为:
The signal generating device according to claim 4, characterized in that the preset phase difference is determined as:
其中,Ph为所述预设相位差,所述N为所述相位累加器单元的数据位宽,fd为所述第一时钟信息,fo为所述波形参数生成模块的输出频率。Among them, Ph is the preset phase difference, N is the data bit width of the phase accumulator unit, fd is the first clock information, and fo is the output frequency of the waveform parameter generation module. - 根据权利要求3所述的信号发生装置,其特征在于,所述相位累加器单元和所述存储器单元的工作时钟与所述数模转换模块的工作时钟同源。The signal generating device according to claim 3 is characterized in that the working clocks of the phase accumulator unit and the memory unit are co-sourced with the working clock of the digital-to-analog conversion module.
- 根据权利要求2所述的信号发生装置,其特征在于,所述波形参数生成模块、所述数据处理模块均为FPGA内的功能模块。The signal generating device according to claim 2 is characterized in that the waveform parameter generating module and the data processing module are both functional modules within the FPGA.
- 根据权利要求8所述的信号发生装置,其特征在于,一个所述FPGA内包括多个所述波形参数生成模块和至少一个所述数据处理模块。The signal generating device according to claim 8 is characterized in that one of the FPGAs includes a plurality of the waveform parameter generating modules and at least one of the data processing modules.
- 根据权利要求1所述的信号发生装置,其特征在于,所述数模转换模块的采样率至少包括1GS/s,所述波形参数生成模块的数量至少包括2个。The signal generating device according to claim 1 is characterized in that the sampling rate of the digital-to-analog conversion module is at least 1 GS/s, and the number of the waveform parameter generation modules is at least 2.
- 根据权利要求1所述的信号发生装置,其特征在于,所述数模转换模块的采样率至少包括3GS/s,所述波形参数生成模块的数量至少包括6个。The signal generating device according to claim 1 is characterized in that the sampling rate of the digital-to-analog conversion module is at least 3GS/s, and the number of the waveform parameter generation modules is at least 6.
- 根据权利要求1所述的信号发生装置,其特征在于,所述波形参数生成模块包括相位累加器单元,所述信号发生装置还包括:The signal generating device according to claim 1, characterized in that the waveform parameter generating module comprises a phase accumulator unit, and the signal generating device further comprises:多个信号参数生成模块,用于分别基于Cordic算法根据输入的相位控制信息生成初级信号参数;其中,不同信号参数生成模块输入的相位控制信息符合指定规则,使得多个信号参数生成模块输出的初级信号参数之间的相位差为指定相位差的整数倍;Multiple signal parameter generation modules, used to generate primary signal parameters according to input phase control information based on Cordic algorithm respectively; wherein the phase control information input by different signal parameter generation modules conforms to a specified rule, so that the phase difference between the primary signal parameters output by the multiple signal parameter generation modules is an integer multiple of the specified phase difference;所述数模转换模块还用于根据按照指定相位差排列的多个初级信号参数形成的目标信号参数,以生成所述中频信号; The digital-to-analog conversion module is also used to generate the intermediate frequency signal according to the target signal parameters formed by the multiple primary signal parameters arranged according to the specified phase difference;其中,所述相位累加器单元与所述信号参数生成模块具有指定对应关系,所述相位累加器单元用于依据所述信号参数生成模块的工作时钟频率对所述相位控制信息进行累加,并将累加后的相位控制信息发送至所述信号参数生成模块。Among them, the phase accumulator unit has a specified corresponding relationship with the signal parameter generation module, and the phase accumulator unit is used to accumulate the phase control information according to the working clock frequency of the signal parameter generation module, and send the accumulated phase control information to the signal parameter generation module.
- 根据权利要求12所述的信号发生装置,其特征在于,所述中频信号的频率与量子处理器的操控信号和/或读取信号的频率具有第一关联关系;其中,所述第一关联关系用于表征在所述操控信号和/或读取信号的频率满足所述量子处理器的精度条件的情况下,所述中频信号的频率满足的第一频率条件。The signal generating device according to claim 12 is characterized in that the frequency of the intermediate frequency signal has a first correlation with the frequency of the control signal and/or the read signal of the quantum processor; wherein the first correlation is used to characterize the first frequency condition satisfied by the frequency of the intermediate frequency signal when the frequency of the control signal and/or the read signal satisfies the accuracy condition of the quantum processor.
- 根据权利要求13所述的信号发生装置,其特征在于,所述信号参数生成模块的数量与所述中频信号的频率具有第二关联关系;其中,所述第二关联关系用于表征在所述中频信号的频率满足所述第一频率条件的情况下,所述信号参数生成模块的数量满足的数量条件。The signal generating device according to claim 13 is characterized in that the number of the signal parameter generating modules has a second correlation relationship with the frequency of the intermediate frequency signal; wherein the second correlation relationship is used to characterize the quantity condition satisfied by the number of the signal parameter generating modules when the frequency of the intermediate frequency signal satisfies the first frequency condition.
- 根据权利要求12所述的信号发生装置,其特征在于,所述相位控制信息依据所述信号参数生成模块的数量以及所述信号参数生成模块的工作时钟频率、输出频率和数据位宽确定。The signal generating device according to claim 12 is characterized in that the phase control information is determined according to the number of the signal parameter generating modules and the working clock frequency, output frequency and data bit width of the signal parameter generating modules.
- 根据权利要求15所述的信号发生装置,其特征在于,所述指定规则包括相邻信号参数生成模块输入的相位控制信息的差值为指定相位差。The signal generating device according to claim 15 is characterized in that the specified rule includes the difference between the phase control information input by adjacent signal parameter generation modules being the specified phase difference.
- 根据权利要求12所述的信号发生装置,其特征在于,还包括数据处理模块,用于对多个所述初级信号参数进行数据处理以获取与所述中频信号的至少一个周期对应的目标信号参数。The signal generating device according to claim 12 is characterized in that it also includes a data processing module for performing data processing on a plurality of the primary signal parameters to obtain a target signal parameter corresponding to at least one period of the intermediate frequency signal.
- 根据权利要求12所述的信号发生装置,其特征在于,所述信号参数生成模块的工作时钟与所述数模转换模块的工作时钟同源。The signal generating device according to claim 12 is characterized in that a working clock of the signal parameter generating module is co-sourced with a working clock of the digital-to-analog conversion module.
- 一种量子控制系统,其特征在于,包括权利要求1-18任一项所述的信号发生装置、微波源、以及信号混频装置,所述信号混频装置用于对所述信号发生装置输出的中频信号以及所述微波源输出的微波信号进行混频处理并输出操控信号和/或读取信号。A quantum control system, characterized in that it comprises the signal generating device, microwave source, and signal mixing device as described in any one of claims 1 to 18, wherein the signal mixing device is used to mix the intermediate frequency signal output by the signal generating device and the microwave signal output by the microwave source and output a control signal and/or a read signal.
- 一种量子计算机,其特征在于,包括权利要求19所述的量子控制系统及量子处理器,所述量子控制系统输出用于控制所述量子处理器执行运算的操控信号、以及对所述量子处理器的运算结果进行测量的读取信号。 A quantum computer, characterized in that it includes the quantum control system and quantum processor described in claim 19, wherein the quantum control system outputs a control signal for controlling the quantum processor to perform operations, and a read signal for measuring the operation results of the quantum processor.
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